35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
4.9 KiB
Protectli Vault FW2B and FW4B
This page describes how to run coreboot on the Protectli FW2B and Protectli FW4B.
Required proprietary blobs
To build a minimal working coreboot image some blobs are required (assuming only the BIOS region is being modified).
+-----------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+=================+=================================+=====================+
| FSP | Intel Firmware Support Package | Required |
+-----------------+---------------------------------+---------------------+
| microcode | CPU microcode | Required |
+-----------------+---------------------------------+---------------------+
| vgabios | VGA Option ROM | Optional |
+-----------------+---------------------------------+---------------------+
FSP is automatically added by coreboot build system into the image) from the
3rdparty/fsp submodule.
microcode updates are automatically included into the coreboot image by build
system from the 3rdparty/intel-microcode submodule.
VGA Option ROM is not required to boot, but if one needs graphics in pre-OS stage, it should be included.
Flashing coreboot
Internal programming
The main SPI flash can be accessed using flashrom.
External programming
The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. This chip is located on the bottom side of the case (the radiator side). One has to remove all screws (in order): 4 top cover screws, 4 side cover screws (one side is enough), 4 mainboard screws, 3 CPU screws (under the DIMM). Lift up the mainboard and turn around it. The flash chip is near the mainboard edge close to the Ethernet Controllers. Use a clip (or solder the wires) to program the chip. Watch out on the voltage, the SPI operates at 1.8V! Specifically, it's a Macronix MX25U6435F (1.8V) - datasheet.
Known issues
- After flashing with external programmer the board will not boot if flashed the BIOS region only. For some reason it is required to flash whole image along with TXE region.
- USB 3.0 ports get detected very late in SeaBIOS, it needs huge timeout values in order to get the devices detected.
Untested
Not all mainboard's peripherals and functions were tested because of lack of the cables or not being populated on the board case.
- internal USB 2.0 header
Working
-
USB 3.0 front ports (SeaBIOS and Linux)
-
4 Ethernet ports (2 Ethernet ports on FW2B)
-
2 HDMI ports with VGA Option ROM
-
2 HDMI ports with libgfxinit
-
flashrom
-
PCIe WiFi
-
SATA and mSATA
-
Super I/O serial port 0 (RS232 via front RJ45 connector)
-
SMBus (reading SPD from DIMMs)
-
initialization with Braswell FSP
-
SeaBIOS payload (version rel-1.13.0)
-
booting Debian, Ubuntu, FreeBSD
Not working
- mPCIe debug card connected to mSATA (mSATA slot has LPC signals routed, however for some reason the debug card is not powered)
Technology
The mainboard has two variants: FW2B and FW4B. They have different Braswell SoC. The FW2B replaces 2 out of 4 Ethernet Controllers with 4 USB ports connected via FE1.1 USB 2.0 hub.
- FW2B:
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3060 |
+------------------+--------------------------------------------------+
| PCH | Braswell |
+------------------+--------------------------------------------------+
| Super I/O | ITE IT8613E |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Trusted Execution Engine |
+------------------+--------------------------------------------------+
- FW4B:
+------------------+--------------------------------------------------+
| CPU | Intel Celeron J3160 |
+------------------+--------------------------------------------------+
| PCH | Braswell |
+------------------+--------------------------------------------------+
| Super I/O | ITE IT8613E |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Trusted Execution Engine |
+------------------+--------------------------------------------------+
