9fee35c6c4
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <PlatformMemoryConfiguration.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 4)
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},
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// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 5)
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},
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// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 6)
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},
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// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 7)
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},
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// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
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HotplugDisabled,
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PcieGen2,
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PcieGen2,
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AspmL0sL1, 0)
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}
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = NULL,
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};
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->GnbConfig.PsppPolicy = 0;
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}
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/*----------------------------------------------------------------------------------------
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* CUSTOMER OVERIDES MEMORY TABLE
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*----------------------------------------------------------------------------------------
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*/
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
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// APU soldered down memory uses memory CLK0 and CLK1 on CS0
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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// APU soldered down memory requires different seeds
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#define WLSEED 0x08
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#define RXSEED 0x40
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WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
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HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
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PSO_END
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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