AGESA: Split long lines in OemCustomize.c

Change-Id: I907f55622e6aaba401471239f706ab24cd26319f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

src/mainboard/amd/inagua/OemCustomize.c

@@ -23,25 +23,41 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 4)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 6)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 7)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/amd/parmer/OemCustomize.c

@@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 
@@ -131,7 +159,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
 		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 	},
 };

src/mainboard/amd/persimmon/OemCustomize.c

@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/amd/south_station/OemCustomize.c

@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 4)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 5)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 6)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 7)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/amd/thatcher/OemCustomize.c

@@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 4, PCI Device Number 4, LAN */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 

src/mainboard/amd/torpedo/OemCustomize.c

@@ -22,37 +22,61 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, BIT2)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, BIT3)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	}
 };
 

src/mainboard/amd/union_station/OemCustomize.c

@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 4)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 5)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 6)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 7)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/asrock/e350m1/OemCustomize.c

@@ -23,13 +23,21 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/asus/f2a85-m/OemCustomize.c

@@ -69,19 +69,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 

src/mainboard/elmex/pcm205400/OemCustomize.c

@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 46)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/gizmosphere/gizmo/OemCustomize.c

@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 4)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 5)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 6)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 7)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c

@@ -70,48 +70,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 
@@ -132,7 +160,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
 		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 	},
 };

src/mainboard/lenovo/g505s/OemCustomize.c

@@ -70,48 +70,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 
 	/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 
@@ -132,7 +160,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
 		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 	},
 };

src/mainboard/lippert/frontrunner-af/OemCustomize.c

@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/lippert/toucan-af/OemCustomize.c

@@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };
 

src/mainboard/msi/ms7721/OemCustomize.c

@@ -71,31 +71,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
 	},
 	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
 	},
 };
 

src/mainboard/pcengines/apu1/OemCustomize.c

@@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 4)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 5)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 6)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 7)
 	},
 	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGen2,
+				PcieGen2,
+				AspmL0sL1, 0)
 	}
 };