21bc2ca5d5
This implementation is the same for all SoC that select SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR CPU support code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/amd_pci_mmconf.h>
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#include <amdblocks/cpu.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/x86/tsc.h>
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#include <soc/southbridge.h>
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#include <soc/psp_transfer.h>
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#include <stdint.h>
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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early_cache_setup();
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write_resume_eip();
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enable_pci_mmconf();
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/*
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* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
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* to get micro-seconds granularity.
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*/
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base_timestamp /= tsc_freq_mhz();
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if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
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boot_with_psp_timestamp(base_timestamp);
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/*
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* if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or
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* previous step did nothing, proceed with normal bootblock main.
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*/
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bootblock_main_with_basetime(base_timestamp);
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}
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void bootblock_soc_early_init(void)
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{
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fch_pre_init();
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}
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void bootblock_soc_init(void)
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{
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
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verify_psp_transfer_buf();
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show_psp_transfer_info();
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}
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fch_early_init();
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}
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