e14e66bc0c
Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/espi.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/pmlib.h>
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#include <amdblocks/smbus.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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#include <soc/uart.h>
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#include "chip.h"
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/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
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static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
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I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
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I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
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I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
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I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
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};
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static void lpc_configure_decodes(void)
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{
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if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
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lpc_enable_port80();
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}
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static void reset_i2c_peripherals(void)
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{
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const struct soc_amd_cezanne_config *cfg = config_of_soc();
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struct soc_i2c_peripheral_reset_info reset_info;
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reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
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reset_info.i2c_scl = i2c_scl_pins;
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reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
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sb_reset_i2c_peripherals(&reset_info);
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}
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/* Before console init */
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void fch_pre_init(void)
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{
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
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lpc_early_init();
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/* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI
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interface hasn't already been set up in verstage on PSP */
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
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configure_espi_with_mb_hook();
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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lpc_configure_decodes();
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fch_spi_early_init();
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fch_smbus_init();
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fch_enable_cf9_io();
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fch_enable_legacy_io();
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fch_disable_legacy_dma_io();
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enable_aoac_devices();
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/*
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* On reset Range_0 defaults to enabled. We want to start with a clean
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* slate to not have things unexpectedly enabled.
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*/
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clear_uart_legacy_config();
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if (CONFIG(AMD_SOC_CONSOLE_UART))
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set_uart_config(CONFIG_UART_FOR_CONSOLE);
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/* disable the keyboard reset function before mainboard GPIO setup */
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if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
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fch_disable_kb_rst();
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}
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/* After console init */
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void fch_early_init(void)
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{
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reset_i2c_peripherals();
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pm_set_power_failure_state();
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fch_print_pmxc0_status();
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i2c_soc_early_init();
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show_spi_speeds_and_modes();
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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}
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