b77eec82f3
Add support for BDC detection, based on the schematics for each board. Support for boards without schematics needs further testing. Needs test on all boards. Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
257 lines
6.6 KiB
Plaintext
257 lines
6.6 KiB
Plaintext
chip northbridge/intel/gm45
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gfx.use_spread_spectrum_clock" = "1"
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device cpu_cluster 0 on
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chip cpu/intel/socket_mPGA478MN
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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# Enable Super LFM
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register "slfm" = "1"
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# Enable C5, C6
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register "c5" = "1"
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register "c6" = "1"
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0 on
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device pci 00.0 on
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subsystemid 0x17aa 0x20e0
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end # host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on # VGA
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subsystemid 0x17aa 0x20e4
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ioapic_irq 2 INTA 0x10
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end
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device pci 02.1 on
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subsystemid 0x17aa 0x20e4
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end # Display
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device pci 03.0 on
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subsystemid 0x17aa 0x20e6
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end # ME
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device pci 03.1 off end # ME
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device pci 03.2 off end # ME
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device pci 03.3 off end # ME
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chip southbridge/intel/i82801ix
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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register "gpi8_routing" = "2"
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register "gpe0_en" = "0x01000000"
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register "gpi1_routing" = "2"
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# Set AHCI mode, enable ports 1 and 2.
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register "sata_port_map" = "0x03"
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register "sata_clock_request" = "0"
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register "sata_traffic_monitor" = "0"
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# Set c-state support
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register "c4onc3_enable" = "1"
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register "c5_enable" = "1"
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register "c6_enable" = "1"
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# Set thermal throttling to 75%.
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register "throttle_duty" = "THTL_75_0"
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# Enable PCIe ports 1,2,4 as slots (Mini * PCIe).
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register "pcie_slot_implemented" = "0xb"
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# Set power limits to 10 * 10^0 watts.
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# Maybe we should set less for Mini PCIe.
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register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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chip drivers/generic/ioapic
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register "have_isa_interrupts" = "1"
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register "irq_on_fsb" = "1"
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register "enable_virtual_wire" = "1"
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register "base" = "(void *)0xfec00000"
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device ioapic 2 on end
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end
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device pci 19.0 on end # LAN
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device pci 1a.0 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTA 0x10
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end
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device pci 1a.1 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTB 0x11
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end
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device pci 1a.2 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTC 0x12
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end
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device pci 1a.7 on # EHCI
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subsystemid 0x17aa 0x20f1
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ioapic_irq 2 INTC 0x12
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end
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device pci 1b.0 on # HD Audio
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subsystemid 0x17aa 0x20f2
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ioapic_irq 2 INTA 0x10
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x17aa 0x20f3 # WWAN
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ioapic_irq 2 INTA 0x10
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end
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device pci 1c.1 on
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subsystemid 0x17aa 0x20f3 # WLAN
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end # PCIe Port #2
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device pci 1c.2 on
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subsystemid 0x17aa 0x20f3 # UWB
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end # PCIe Port #3
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device pci 1c.3 on
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subsystemid 0x17aa 0x20f3 # Expresscard
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end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTA 0x10
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end
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device pci 1d.1 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTB 0x11
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end
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device pci 1d.2 on # UHCI
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subsystemid 0x17aa 0x20f0
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ioapic_irq 2 INTC 0x12
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end
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device pci 1d.7 on # EHCI
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subsystemid 0x17aa 0x20f1
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ioapic_irq 2 INTA 0x10
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end
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device pci 1e.0 on # PCI
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subsystemid 0x17aa 0x20f4
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end
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device pci 1f.0 on # LPC bridge
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subsystemid 0x17aa 0x20f5
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa6"
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register "config1" = "0x04"
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register "config2" = "0xa0"
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register "config3" = "0x01"
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register "beepmask0" = "0xfe"
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register "beepmask1" = "0x96"
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register "has_power_management_beeps" = "1"
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register "has_uwb" = "1"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xf4"
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register "event5_enable" = "0x3c"
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register "event6_enable" = "0x80"
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x01"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0xff"
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register "eventb_enable" = "0xff"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "has_bdc_detection" = "1"
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register "bdc_gpio_num" = "48"
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register "bdc_gpio_lvl" = "0"
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end
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chip superio/nsc/pc87382
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device pnp 164e.2 off end # IR
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device pnp 164e.3 off end # Serial Port
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device pnp 164e.7 on # GPIO
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io 0x60 = 0x1680
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end
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device pnp 164e.19 on # DLPC
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io 0x60 = 0x164c
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end
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end
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chip superio/nsc/pc87384
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x3bc
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irq 0x70 = 7
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end
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device pnp 2e.2 off end # Serial Port / IR
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device pnp 2e.3 on # Serial Port
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.7 on # GPIO
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io 0x60 = 0x1620
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end
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end
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chip drivers/lenovo/hybrid_graphics
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device pnp ff.f on end # dummy
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register "detect_gpio" = "21"
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register "has_panel_hybrid_gpio" = "1"
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register "panel_hybrid_gpio" = "22"
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register "panel_integrated_lvl" = "0"
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register "has_backlight_gpio" = "1"
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register "backlight_gpio" = "19"
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register "backlight_integrated_lvl" = "0"
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register "has_dgpu_power_gpio" = "1"
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register "dgpu_power_gpio" = "49"
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register "dgpu_power_off_lvl" = "0"
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register "has_thinker1" = "0"
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end
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end
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device pci 1f.2 on # SATA/IDE 1
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subsystemid 0x17aa 0x20f8
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ioapic_irq 2 INTB 0x11
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end
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device pci 1f.3 on # SMBus
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subsystemid 0x17aa 0x20f9
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ioapic_irq 2 INTC 0x12
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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device i2c 5c on end
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device i2c 5d on end
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device i2c 5e on end
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device i2c 5f on end
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end
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end
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device pci 1f.5 off end # SATA/IDE 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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