200f7b7ee1
Older parts do not have the menvcfg csr. Provide a Kconfig variable, default y, to enable it. Check the variable in the payload code, when coreboot SBI is used, and print out if it is enabled. The SiFive FU540 and FU740 do not support this register; set the variable to n for those parts. Add constants for this new CSR. Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
123 lines
2.4 KiB
Plaintext
123 lines
2.4 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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config ARCH_RISCV_RV64
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bool
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select ARCH_RISCV
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config ARCH_RISCV_RV32
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bool
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select ARCH_RISCV
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config ARCH_RISCV
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bool
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select ARCH_SUPPORTS_CLANG
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if ARCH_RISCV
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config RISCV_ARCH
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string
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config RISCV_ABI
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string
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config RISCV_CODEMODEL
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string
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config ARCH_RISCV_M_DISABLED
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bool
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config ARCH_RISCV_M
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# Whether a SOC implements M mode.
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# M mode is the most privileged mode, it is
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# the equivalent in some ways of x86 SMM mode
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# save that in M mode it is impossible to turn
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# on paging.
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# While the spec requires it, there is at least
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# one implementation that will not have it due
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# to security concerns.
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bool
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default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED
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default n
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config ARCH_RISCV_S
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# S (supervisor) mode is for kernels. It is optional.
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bool
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default n
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config RISCV_HAS_OPENSBI
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def_bool n
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config RISCV_OPENSBI
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bool "Use OpenSBI to hand over control to payload"
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depends on ARCH_RISCV_M && ARCH_RISCV_S
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depends on RISCV_HAS_OPENSBI
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default n
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help
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Load OpenSBI after payload has been loaded and use it to
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provide the SBI and to handover control to payload.
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config OPENSBI_PLATFORM
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string
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depends on RISCV_HAS_OPENSBI
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help
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The OpenSBI platform to build for.
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config OPENSBI_TEXT_START
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hex
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depends on RISCV_HAS_OPENSBI
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help
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The linking address used to build opensbi.
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config OPENSBI_FW_DYNAMIC_BOOT_HART
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int
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default RISCV_WORKING_HARTID
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help
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This specifies the hart that OpenSBI will use to boot the payload. If set to
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value -1, OpenSBI will use a 'lottery' scheme to figure it out itself.
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This hart must be able to execute in the Supervisor priviledged mode, since
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that is the mode usually used for the payload. If the hart does not support
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Supervisor mode OpenSBI will again look for a hart that does support it.
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config ARCH_RISCV_U
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# U (user) mode is for programs.
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bool
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default n
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config ARCH_RISCV_PMP
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bool
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default n
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config ARCH_BOOTBLOCK_RISCV
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bool
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default n
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config ARCH_VERSTAGE_RISCV
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bool
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default n
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config ARCH_ROMSTAGE_RISCV
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bool
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default n
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config ARCH_RAMSTAGE_RISCV
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bool
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default n
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config RISCV_USE_ARCH_TIMER
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bool
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default n
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config RISCV_WORKING_HARTID
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int
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# Newer SoC have the menvconfig register.
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# Very few SOC do not have this.
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# Older SoC, such as the SiFive FU[57]40, that
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# do not have this register, should set this
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# to n.
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config RISCV_SOC_HAS_MENVCFG
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bool
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default y
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endif # if ARCH_RISCV
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