Uwe Hermann bc359473e2 Minor tweaks in the 440BX RAM init code (trivial). ...

Still hardcoded for Tyan S1846.

This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2007-06-07 22:16:30 +00:00

..

chip.h

Initial Intel 440BX RAM initialization framework.

2007-04-01 17:24:03 +00:00

Config.lb

Initial Intel 440BX RAM initialization framework.

2007-04-01 17:24:03 +00:00

debug.c

- Add support _framework_ for the Asus p2b.

2006-07-29 17:40:36 +00:00

i440bx.h

Add convenience macros PAM0..PAM6 (trivial).

2006-11-30 21:26:45 +00:00

northbridge.c

Various 440BX and Tyan S1846 related minor changes and fixes (trivial):

2007-05-27 23:31:31 +00:00

northbridge.h

Initial Intel 440BX RAM initialization framework.

2007-04-01 17:24:03 +00:00

raminit.c

Minor tweaks in the 440BX RAM init code (trivial).

2007-06-07 22:16:30 +00:00

raminit.h

Initial Intel 440BX RAM initialization framework.

2007-04-01 17:24:03 +00:00