bc359473e2
Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
561 lines
17 KiB
C
561 lines
17 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "i440bx.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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/* Uncomment this to enable debugging output. */
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#define DEBUG_RAM_SETUP 1
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/* Debugging macros. */
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#if defined(DEBUG_RAM_SETUP)
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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#define DUMPNORTH()
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#endif
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/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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/* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
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* defined in DRAMC[2:0].
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*
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* [0] == Normal 15.625 us -> 15.6 us
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* [1] == Reduced(.25X) 3.9 us -> 7.8 ns
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* [2] == Reduced(.5X) 7.8 us -> 7.8 us
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* [3] == Extended(2x) 31.3 us -> 31.2 us
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* [4] == Extended(4x) 62.5 us -> 62.4 us
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* [5] == Extended(8x) 125 us -> 124.8 us
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*/
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static const uint32_t refresh_rate_map[] = {
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1, 5, 5, 2, 3, 4
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};
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/* Table format: register, bitmask, value. */
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static const long register_values[] = {
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/* NBXCFG - NBX Configuration Register
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* 0x50 - 0x53
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*
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* [31:24] SDRAM Row Without ECC
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* 0 = ECC components are populated in this row
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* 1 = ECC components are not populated in this row
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* [23:19] Reserved
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* [18:18] Host Bus Fast Data Ready Enable (HBFDRE)
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* Assertion of DRAM data on host bus occurs...
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* 0 = ...one clock after sampling snoop results (default)
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* 1 = ...on the same clock the snoop result is being sampled
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* (this mode is faster by one clock cycle)
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* [17:17] ECC - EDO static Drive mode
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* 0 = Normal mode (default)
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* 1 = ECC signals are always driven
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* [16:16] IDSEL_REDIRECT
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* 0 = IDSEL1 is allocated to this bridge (default)
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* 1 = IDSEL7 is allocated to this bridge
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* [15:15] WSC# Handshake Disable
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* 1 = Uni-processor mode
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* 0 = Dual-processor mode with external IOAPIC (default)
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* [14:14] Intel Reserved
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* [13:12] Host/DRAM Frequency
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* 00 = 100 MHz
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* 01 = Reserved
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* 10 = 66 MHz
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* 11 = Reserved
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* [11:11] AGP to PCI Access Enable
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* 1 = Enable
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* 0 = Disable
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* [10:10] PCI Agent to Aperture Access Disable
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* 1 = Disable
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* 0 = Enable (default)
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* [09:09] Aperture Access Global Enable
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* 1 = Enable
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* 0 = Disable
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* [08:07] DRAM Data Integrity Mode (DDIM)
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* 00 = Non-ECC
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* 01 = EC-only
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* 10 = ECC Mode
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* 11 = ECC Mode with hardware scrubbing enabled
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* [06:06] ECC Diagnostic Mode Enable (EDME)
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* 1 = Enable
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* 0 = Normal operation mode (default)
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* [05:05] MDA Present (MDAP)
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* Works in conjunction with the VGA_EN bit.
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* VGA_EN MDAP
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* 0 x All VGA cycles are sent to PCI
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* 1 0 All VGA cycles are sent to AGP
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* 1 1 All VGA cycles are sent to AGP, except for
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* cycles in the MDA range.
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* [04:04] Reserved
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* [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO)
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* 1 = Enable
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* 0 = Disable
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* [02:02] In-Order Queue Depth (IOQD)
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* 1 = In-order queue = maximum
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* 0 = A7# is sampled asserted (i.e., 0)
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* [01:00] Reserved
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*/
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// TODO
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NBXCFG + 0, 0x00, 0x0c,
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// NBXCFG + 1, 0x00, 0xa0,
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NBXCFG + 1, 0x00, 0x80,
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NBXCFG + 2, 0x00, 0x00,
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NBXCFG + 3, 0x00, 0xff,
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/* DRAMC - DRAM Control Register
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* 0x57
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*
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* [7:6] Reserved
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* [5:5] Module Mode Configuration (MMCONFIG)
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* TODO
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* [4:3] DRAM Type (DT)
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* 00 = EDO
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* 01 = SDRAM
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* 10 = Registered SDRAM
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* 11 = Reserved
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* Note: EDO, SDRAM and Registered SDRAM cannot be mixed.
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* [2:0] DRAM Refresh Rate (DRR)
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* 000 = Refresh disabled
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* 001 = 15.6 us
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* 010 = 31.2 us
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* 011 = 62.4 us
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* 100 = 124.8 us
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* 101 = 249.6 us
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* 110 = Reserved
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* 111 = Reserved
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*/
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/* Choose SDRAM (not registered), and disable refresh for now. */
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DRAMC, 0x00, 0x08,
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/*
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* PAM[6:0] - Programmable Attribute Map Registers
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* 0x59 - 0x5f
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*
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* 0x59 [3:0] Reserved
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* 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
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* 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS
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* 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS
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* 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS
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* 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS
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* 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS
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* 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
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* 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
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* 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
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* 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension
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* 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension
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* 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension
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* 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension
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*
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* Bit assignment:
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* 00 = DRAM Disabled (all access goes to memory mapped I/O space)
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* 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space)
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* 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
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* 11 = Read/Write (all access goes to DRAM)
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*/
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// TODO
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PAM0, 0x00, 0x00,
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PAM1, 0x00, 0x00,
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PAM2, 0x00, 0x00,
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PAM3, 0x00, 0x00,
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PAM4, 0x00, 0x00,
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PAM5, 0x00, 0x00,
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PAM6, 0x00, 0x00,
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/* DRB[0:7] - DRAM Row Boundary Registers
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* 0x60 - 0x67
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*
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* An array of 8 byte registers, which hold the ending memory address
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* assigned to each pair of DIMMs, in 8MB granularity.
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*
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* 0x60 DRB0 = Total memory in row0 (in 8 MB)
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* 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
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* 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB)
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* 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB)
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* 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB)
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* 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB)
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* 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
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* 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
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*/
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/* Set the DRBs to zero for now, this will be fixed later. */
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DRB0, 0x00, 0x00,
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DRB1, 0x00, 0x00,
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DRB2, 0x00, 0x00,
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DRB3, 0x00, 0x00,
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DRB4, 0x00, 0x00,
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DRB5, 0x00, 0x00,
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DRB6, 0x00, 0x00,
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DRB7, 0x00, 0x00,
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/* FDHC - Fixed DRAM Hole Control Register
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* 0x68
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*
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* Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB.
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*
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* [7:6] Hole Enable (HEN)
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* 00 = None
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* 01 = 512 KB - 640 KB (128 KB)
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* 10 = 15 MB - 16 MB (1 MB)
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* 11 = Reserved
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* [5:0] Reserved
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*/
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/* No memory holes. */
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FDHC, 0x00, 0x00,
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/* RPS - SDRAM Row Page Size Register
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* 0x74 - 0x75
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*
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* Sets the row page size for SDRAM. For EDO memory, the page
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* size is fixed at 2 KB.
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*
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* [15:0] Page Size (PS)
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* TODO
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*/
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// TODO
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RPS + 0, 0x00, 0x00,
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RPS + 1, 0x00, 0x00,
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/* SDRAMC - SDRAM Control Register
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* 0x76 - 0x77
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*
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* [15:10] Reserved
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* [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
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* 00 = Illegal
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* 01 = Add a clock delay to the lead-off clock count
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* 10 = Illegal
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* 11 = Illegal
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* [07:05] SDRAM Mode Select (SMS)
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* 000 = Normal SDRAM Operation (default)
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* 001 = NOP Command Enable
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* 010 = All Banks Precharge Enable
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* 011 = Mode Register Set Enable
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* 100 = CBR Enable
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* 101 = Reserved
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* 110 = Reserved
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* 111 = Reserved
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* [04:04] SDRAMPWR
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* 0 = 3 DIMM configuration
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* 1 = 4 DIMM configuration
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* [03:03] Leadoff Command Timing (LCT)
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* 0 = 4 CS# Clock
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* 1 = 3 CS# Clock
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* [02:02] CAS# Latency (CL)
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* 0 = 3 DCLK CAS# latency
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* 1 = 2 DCLK CAS# latency
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* [01:01] SDRAM RAS# to CAS# Delay (SRCD)
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* 0 = 3 clocks between a row activate and a read or write cmd.
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* 1 = 2 clocks between a row activate and a read or write cmd.
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* [00:00] SDRAM RAS# Precharge (SRP)
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* 0 = 3 clocks of RAS# precharge
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* 1 = 2 clocks of RAS# precharge
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*/
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SDRAMC + 0, 0x00, 0x00,
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SDRAMC + 0, 0x00, 0x00,
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/* PGPOL - Paging Policy Register
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* 0x78 - 0x79
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*
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* [15:08] Banks per Row (BPR)
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* TODO
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* 0 = 2 banks
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* 1 = 4 banks
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* [07:05] Reserved
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* [04:04] Intel Reserved
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* [03:00] DRAM Idle Timer (DIT)
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* 0000 = 0 clocks
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* 0001 = 2 clocks
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* 0010 = 4 clocks
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* 0011 = 8 clocks
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* 0100 = 10 clocks
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* 0101 = 12 clocks
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* 0110 = 16 clocks
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* 0111 = 32 clocks
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* 1xxx = Infinite (pages are not closed for idle condition)
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*/
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// TODO
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PGPOL + 0, 0x00, 0x00,
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PGPOL + 1, 0x00, 0xff,
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/* PMCR - Power Management Control Register
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* 0x7a
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*
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* [07:07] Power Down SDRAM Enable (PDSE)
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* 1 = Enable
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* 0 = Disable
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* [06:06] ACPI Control Register Enable (SCRE)
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* 1 = Enable
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* 0 = Disable (default)
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* [05:05] Suspend Refresh Type (SRT)
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* 1 = Self refresh mode
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* 0 = CBR fresh mode
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* [04:04] Normal Refresh Enable (NREF_EN)
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* 1 = Enable
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* 0 = Disable
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* [03:03] Quick Start Mode (QSTART)
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* 1 = Quick start mode for the processor is enabled
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* [02:02] Gated Clock Enable (GCLKEN)
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* 1 = Enable
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* 0 = Disable
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* [01:01] AGP Disable (AGP_DIS)
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* 1 = Disable
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* 0 = Enable
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* [00:00] CPU reset without PCIRST enable (CRst_En)
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* 1 = Enable
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* 0 = Disable
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*/
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/* Enable normal refresh and the gated clock. */
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// TODO: Only do this later?
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// PMCR, 0x00, 0x14,
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// PMCR, 0x00, 0x10,
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PMCR, 0x00, 0x00,
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};
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/*-----------------------------------------------------------------------------
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SDRAM configuration functions.
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-----------------------------------------------------------------------------*/
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/**
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* Send the specified RAM command to all DIMMs.
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*
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* @param Memory controller
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* @param TODO
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* @param TODO
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*/
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static void do_ram_command(const struct mem_controller *ctrl,
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uint32_t command, uint32_t addr_offset)
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{
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int i;
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uint16_t reg;
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/* TODO: Support for multiple DIMMs. */
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/* Configure the RAM command. */
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reg = pci_read_config16(ctrl->d0, SDRAMC);
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reg &= 0xff1f; /* Clear bits 7-5. */
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reg |= (uint16_t) (command << 5);
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pci_write_config16(ctrl->d0, SDRAMC, reg);
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/* RAM_COMMAND_NORMAL affects only the memory controller and
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doesn't need to be "sent" to the DIMMs. */
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/* if (command == RAM_COMMAND_NORMAL) return; */
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG_HEX16(reg);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
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PRINT_DEBUG("\r\n");
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/* Read from (DIMM start address + addr_offset). */
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read32(0 + addr_offset); // FIXME
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}
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/*-----------------------------------------------------------------------------
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DIMM-independant configuration functions.
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-----------------------------------------------------------------------------*/
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/**
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* TODO.
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*
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* @param Memory controller
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*/
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static void spd_enable_refresh(const struct mem_controller *ctrl)
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{
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int i, value;
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uint8_t reg;
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reg = pci_read_config8(ctrl->d0, DRAMC);
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for (i = 0; i < DIMM_SOCKETS; i++) {
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value = spd_read_byte(ctrl->channel0[i], SPD_REFRESH);
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if (value < 0)
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continue;
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reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
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PRINT_DEBUG(" Enabling refresh (DRAMC = 0x");
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PRINT_DEBUG_HEX8(reg);
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PRINT_DEBUG(") for DIMM ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\r\n");
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}
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pci_write_config8(ctrl->d0, DRAMC, reg);
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}
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/*-----------------------------------------------------------------------------
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Public interface.
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-----------------------------------------------------------------------------*/
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/**
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* TODO.
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*
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* @param Memory controller
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*/
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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int i, max;
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uint8_t reg;
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PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
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DUMPNORTH();
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max = sizeof(register_values) / sizeof(register_values[0]);
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/* Set registers as specified in the register_values[] array. */
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for (i = 0; i < max; i += 3) {
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reg = pci_read_config8(ctrl->d0, register_values[i]);
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reg &= register_values[i + 1];
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reg |= register_values[i + 2] & ~(register_values[i + 1]);
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pci_write_config8(ctrl->d0, register_values[i], reg);
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PRINT_DEBUG(" Set register 0x");
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PRINT_DEBUG_HEX8(register_values[i]);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX8(reg);
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PRINT_DEBUG("\r\n");
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}
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}
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/**
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* TODO.
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*
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* @param Memory controller
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* TODO: Don't hardcode the values here, get info via SPD. */
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/* Map all legacy regions to RAM (read/write). This is required if
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* you want to use the RAM area from 768 KB - 1 MB. If the PAM
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* registers are not set here appropriately, the RAM in that region
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* will not be accessible, thus a RAM check of it will also fail.
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*/
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pci_write_config8(ctrl->d0, PAM0, 0x30);
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pci_write_config8(ctrl->d0, PAM1, 0x33);
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pci_write_config8(ctrl->d0, PAM2, 0x33);
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pci_write_config8(ctrl->d0, PAM3, 0x33);
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pci_write_config8(ctrl->d0, PAM4, 0x33);
|
|
pci_write_config8(ctrl->d0, PAM5, 0x33);
|
|
pci_write_config8(ctrl->d0, PAM6, 0x33);
|
|
|
|
/* TODO: Set DRB0-DRB7. */
|
|
/* Currently this is hardcoded to one 64 MB DIMM in slot 0. */
|
|
pci_write_config8(ctrl->d0, DRB0, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB1, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB2, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB3, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB4, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB5, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB6, 0x08);
|
|
pci_write_config8(ctrl->d0, DRB7, 0x08);
|
|
|
|
/* TODO: Set DRAMC. Don't enable refresh for now. */
|
|
pci_write_config8(ctrl->d0, DRAMC, 0x08);
|
|
|
|
/* TODO: Set RPS. */
|
|
pci_write_config16(ctrl->d0, RPS, 0x0001);
|
|
|
|
/* TODO: Set SDRAMC. */
|
|
// pci_write_config16(ctrl->d0, SDRAMC, 0x010f); // FIXME?
|
|
pci_write_config16(ctrl->d0, SDRAMC, 0x0003); // FIXME?
|
|
|
|
/* TODO: Set PGPOL. */
|
|
// pci_write_config16(ctrl->d0, PGPOL, 0x0107);
|
|
pci_write_config16(ctrl->d0, PGPOL, 0x0123);
|
|
|
|
/* TODO: Set NBXCFG. */
|
|
// pci_write_config32(ctrl->d0, NBXCFG, 0x0100220c); // FIXME?
|
|
pci_write_config32(ctrl->d0, NBXCFG, 0xff00800c);
|
|
|
|
/* TODO: Set PMCR? */
|
|
// pci_write_config8(ctrl->d0, PMCR, 0x14);
|
|
pci_write_config8(ctrl->d0, PMCR, 0x10);
|
|
|
|
/* TODO? */
|
|
pci_write_config8(ctrl->d0, MLT, 0x40);
|
|
pci_write_config8(ctrl->d0, DRAMT, 0x03);
|
|
pci_write_config8(ctrl->d0, MBSC, 0x03);
|
|
pci_write_config8(ctrl->d0, SCRR, 0x38);
|
|
}
|
|
|
|
/**
|
|
* Enable SDRAM.
|
|
*
|
|
* @param Number of controllers
|
|
* @param Memory controller
|
|
*/
|
|
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|
{
|
|
int i;
|
|
|
|
/* 0. Wait until power/voltages and clocks are stable (200us). */
|
|
udelay(200);
|
|
|
|
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
|
|
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
|
|
do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
|
|
udelay(200);
|
|
|
|
/* 2. Precharge all. Wait tRP. */
|
|
PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
|
|
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
|
|
udelay(1);
|
|
|
|
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
|
|
PRINT_DEBUG("RAM Enable 3: CBR\r\n");
|
|
for (i = 0; i < 8; i++) {
|
|
do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
|
|
udelay(1);
|
|
}
|
|
|
|
/* 4. Mode register set. Wait two memory cycles. */
|
|
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
|
|
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
|
|
udelay(2);
|
|
|
|
/* 5. Normal operation. */
|
|
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
|
|
do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
|
|
udelay(1);
|
|
|
|
/* 6. Finally enable refresh. */
|
|
PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
|
|
// pci_write_config8(ctrl->d0, PMCR, 0x10);
|
|
spd_enable_refresh(ctrl);
|
|
udelay(1);
|
|
|
|
PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
|
|
DUMPNORTH();
|
|
}
|