bf0902eb83
The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11054 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
109 lines
3.1 KiB
C
109 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp_util.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_bus_default_ops,
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};
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static struct device_operations cpu_bus_ops = {
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.init = &soc_init_cpus,
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};
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static void soc_enable(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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/* Handle PCH device enable */
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if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
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(dev->ops == NULL || dev->ops->enable == NULL)) {
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pch_enable_dev(dev);
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}
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}
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}
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struct chip_operations soc_intel_skylake_ops = {
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CHIP_NAME("Intel Skylake")
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.enable_dev = &soc_enable,
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.init = &soc_init_pre_device,
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};
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/* UPD parameters to be initialized before SiliconInit */
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void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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const struct device *dev;
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const struct soc_intel_skylake_config *config;
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/* Set the parameters for SiliconInit */
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dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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params->Device4Enable = config->Device4Enable;
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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SILICON_INIT_UPD *params)
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{
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/* Display the parameters for SiliconInit */
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printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
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soc_display_upd_value("GpioTablePtr", 4,
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(uint32_t)original->GpioTablePtr,
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(uint32_t)params->GpioTablePtr);
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soc_display_upd_value("Device4Enable", 1,
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original->Device4Enable,
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params->Device4Enable);
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}
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device)
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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else
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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(device << 16) | vendor);
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}
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struct pci_operations soc_pci_ops = {
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.set_subsystem = &pci_set_subsystem
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};
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