35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
3.5 KiB
NPCD378
This page describes the Nuvoton SuperIO chip that can be found on various HP mainboards.
As no datasheet is available most of the functions have been reverse engineered and might be inaccurate or wrong.
LDNs
+-------+---------------------------+
| LDN # | Function |
+=======+===========================+
| 0 | FDC |
+-------+---------------------------+
| 1 | Parallel Port |
+-------+---------------------------+
| 2 | Com1 |
+-------+---------------------------+
| 3 | Com2 / IR |
+-------+---------------------------+
| 4 | LED and PWR button CTRL |
+-------+---------------------------+
| 5 | PS/2 AUX |
+-------+---------------------------+
| 6 | PS/2 KB |
+-------+---------------------------+
| 7 | WDT1 |
+-------+---------------------------+
| 8 | HWM |
+-------+---------------------------+
| 0xf | GPIO |
+-------+---------------------------+
| 0x15 | I2C ? |
+-------+---------------------------+
| 0x1e | SUSPEND CTL ? |
+-------+---------------------------+
| 0x1c | GPIO ? |
+-------+---------------------------+
LDN0
Follows Nuvoton's default FDC register set. See NCT6102D for more details.
LDN1
Follows Nuvoton's default LPT register set. See NCT6102D for more details.
LDN2
Follows Nuvoton's default COM1 register set. See NCT6102D for more details.
LDN3
Follows Nuvoton's default COM2 register set. See NCT6102D for more details.
LDN4
On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.
It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle and power button behaviour on normal / during S3 resume.
LDN5
A custom PS/2 AUX port.
LDN6
Follows Nuvoton's default KBC register set. See NCT6102D for more details.
LDN7
Looks like a WDT.
LDN8
Custom HWM space. It exposes 256 byte of IO config space. See HWM for more details.
HWM
Register
The registers are accessible via IO space and are located at LDN8's IOBASE.
+---------------+-----------------------+
| IOBASE offset | Register |
+---------------+-----------------------+
| 0x4 | Host Write CTRL |
+---------------+-----------------------+
| 0x10 - 0xfe | HWM Page # |
+---------------+-----------------------+
| 0xff | Page index select |
+---------------+-----------------------+
Host Write CTRL
Bit 0 must be cleared prior to writing any of the HWM register and it must be set after writing to HWM register to signal the SuperIO that data has changed. Reading register is possible at any time and doesn't need special locking.
HWM Page
The SuperIO exposes 16 different pages. Nearly all registers are unknown.
Page 1
+---------------+-----------------------+
| IOBASE offset | Register |
+---------------+-----------------------+
| 0x98 | PSU fan PWM |
+---------------+-----------------------+
Page index
The 4 LSB of the page index register selects which HWM page is active. A write takes effect immediately.