c7cb5e434b
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register format and thus mainboards using using these platforms have similar gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so that it other chipsets added to autoport can use it. This was originally written by Iru Cai in his Haswell autoport patch in CB:30890; I have simply split out the code to a separate commit as it is a separate logical change. TEST=Generated output is identical before and after this patch when run against logs from a Dell Latitude E6430 Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
324 lines
10 KiB
Go
324 lines
10 KiB
Go
package main
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import "fmt"
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type bd82x6x struct {
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variant string
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node *DevTreeNode
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}
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func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool {
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portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
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if !ok {
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return false
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}
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return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
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}
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func ich9GetFlashSize(ctx Context) {
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inteltool := ctx.InfoSource.GetInteltool()
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switch (inteltool.RCBA[0x3410] >> 10) & 3 {
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/* SPI. All boards I've seen with sandy/ivy use SPI. */
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case 3:
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ROMProtocol = "SPI"
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highflkb := uint32(0)
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for reg := uint16(0); reg < 5; reg++ {
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fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff
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flkb := (fl + 1) << 2
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if flkb > highflkb {
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highflkb = flkb
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}
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}
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ROMSizeKB = int(highflkb)
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/* Shared with ME. Flashrom is unable to handle it. */
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FlashROMSupport = "n"
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}
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}
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func (b bd82x6x) GetGPIOHeader() string {
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return "southbridge/intel/bd82x6x/pch.h"
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}
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func (b bd82x6x) EnableGPE(in int) {
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b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
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}
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func (b bd82x6x) EncodeGPE(in int) int {
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return in + 0x10
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}
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func (b bd82x6x) DecodeGPE(in int) int {
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return in - 0x10
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}
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func (b bd82x6x) NeedRouteGPIOManually() {
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b.node.Comment += ", FIXME: set gpiX_routing for EC support"
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}
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func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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SouthBridge = &b
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inteltool := ctx.InfoSource.GetInteltool()
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GPIO(ctx, inteltool)
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KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
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KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
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KconfigInt["USBDEBUG_HCD_INDEX"] = 2
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KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
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dmi := ctx.InfoSource.GetDMI()
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if dmi.Vendor == "LENOVO" {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
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} else {
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KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
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}
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KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
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ich9GetFlashSize(ctx)
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DSDTDefines = append(DSDTDefines,
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DSDTDefine{
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Key: "BRIGHTNESS_UP",
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Value: "\\_SB.PCI0.GFX0.INCB",
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},
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DSDTDefine{
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Key: "BRIGHTNESS_DOWN",
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Value: "\\_SB.PCI0.GFX0.DECB",
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})
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FADT := ctx.InfoSource.GetACPI()["FACP"]
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pcieHotplugMap := "{ "
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for port := 0; port < 7; port++ {
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if b.IsPCIeHotplug(ctx, port) {
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pcieHotplugMap += "1, "
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} else {
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pcieHotplugMap += "0, "
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}
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}
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if b.IsPCIeHotplug(ctx, 7) {
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pcieHotplugMap += "1 }"
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} else {
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pcieHotplugMap += "0 }"
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}
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cur := DevTreeNode{
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Chip: "southbridge/intel/bd82x6x",
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Comment: "Intel Series 6 Cougar Point PCH",
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Registers: map[string]string{
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"sata_interface_speed_support": "0x3",
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"gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
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"gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
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"gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
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"gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
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"pcie_port_coalesce": "1",
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"pcie_hotplug_map": pcieHotplugMap,
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"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
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"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
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"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
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"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"},
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},
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}
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b.node = &cur
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xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}]
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if ok {
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cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
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cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
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cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
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}
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PutPCIChip(addr, cur)
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PutPCIDevParent(addr, "", "lpc")
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/platform.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
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})
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "southbridge/intel/common/acpi/sleepstates.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "southbridge/intel/bd82x6x/acpi/pch.asl",
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})
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AddBootBlockFile("early_init.c", "")
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AddROMStageFile("early_init.c", "")
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sb := Create(ctx, "early_init.c")
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defer sb.Close()
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Add_gpl(sb)
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sb.WriteString(`#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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`)
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usbPortConfig := "{\n"
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currentMap := map[uint32]int{
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0x20000153: 0,
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0x20000f57: 1,
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0x2000055b: 2,
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0x20000f51: 3,
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0x2000094a: 4,
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0x2000035f: 5,
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0x20000f53: 6,
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0x20000f5b: 7,
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0x20000553: 9,
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}
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for port := uint(0); port < 14; port++ {
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var pinmask uint32
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OCPin := -1
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if port < 8 {
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pinmask = inteltool.RCBA[0x35a0]
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} else {
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pinmask = inteltool.RCBA[0x35a4]
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}
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for pin := uint(0); pin < 4; pin++ {
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if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 {
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OCPin = int(pin)
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if port >= 8 {
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OCPin += 4
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}
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}
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}
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current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]]
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if !ok {
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usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, 0x%x, %d},\n",
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((inteltool.RCBA[0x359c]>>port)&1)^1,
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inteltool.RCBA[uint16(0x3500+4*port)] & 0xfff,
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OCPin)
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} else {
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usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, %d, %d},\n",
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((inteltool.RCBA[0x359c]>>port)&1)^1,
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current,
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OCPin)
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}
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}
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usbPortConfig += "\t\t\t}"
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cur.Registers["usb_port_config"] = usbPortConfig
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sb.WriteString(`
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void bootblock_mainboard_early_init(void)
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{
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`)
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RestorePCI16Simple(sb, addr, 0x82)
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RestorePCI16Simple(sb, addr, 0x80)
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sb.WriteString("}\n")
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gnvs := Create(ctx, "acpi_tables.c")
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defer gnvs.Close()
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Add_gpl(gnvs)
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gnvs.WriteString(`#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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/* FIXME: check this function. */
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* The lid is open by default. */
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gnvs->lids = 1;
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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`)
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}
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func init() {
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/* BD82X6X LPC */
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for id := 0x1c40; id <= 0x1c5f; id++ {
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RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"})
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}
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/* C216 LPC */
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for id := 0x1e41; id <= 0x1e5f; id++ {
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RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"})
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}
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/* PCIe bridge */
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for _, id := range []uint16{
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0x1c10, 0x1c12, 0x1c14, 0x1c16,
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0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
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0x1e10, 0x1e12, 0x1e14, 0x1e16,
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0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
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0x1e25, 0x244e, 0x2448,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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/* SMBus controller */
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RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
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RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
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/* SATA */
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for _, id := range []uint16{
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0x1c00, 0x1c01, 0x1c02, 0x1c03,
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0x1e00, 0x1e01, 0x1e02, 0x1e03,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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/* EHCI */
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for _, id := range []uint16{
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0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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/* XHCI */
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RegisterPCI(0x8086, 0x1e31, GenericPCI{})
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/* ME and children */
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for _, id := range []uint16{
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0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d,
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0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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/* Ethernet */
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RegisterPCI(0x8086, 0x1502, GenericPCI{})
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RegisterPCI(0x8086, 0x1503, GenericPCI{})
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}
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