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system76-coreboot/src
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Maxim Polyakov c8b7215639 mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD 
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h,
use FSP_M_CONFIG structure fields to configure UPD options for FSP-M
in romstage instead of raw offsets.

Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:23:27 +00:00
..
acpi
src/acpi: Add missing <{stdbool,stdint}.h>
2020-07-29 09:37:10 +00:00
arch
mb/emulation/qemu-armv7: Fix board
2020-08-03 05:11:17 +00:00
commonlib
src: Remove unused 'include <stdint.h>
2020-07-14 16:11:10 +00:00
console
console: Update for vboot before bootblock
2020-06-15 22:07:12 +00:00
cpu
cpu/intel/haswell: add Crystal Well CPU IDs
2020-08-03 05:16:29 +00:00
device
Change all assert(0) to BUG()
2020-08-03 05:15:15 +00:00
drivers
drivers/amd/i2s_machine_dev: return if scope is NULL
2020-08-03 05:08:39 +00:00
ec
ec/lenovo/h8: Align macro values in one column
2020-07-26 21:40:00 +00:00
include
assert.h: Try to evaluate assertions at compile time
2020-08-03 05:15:59 +00:00
lib
lib/string: Add standard strstr() function
2020-08-03 05:12:23 +00:00
mainboard
mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD
2020-08-03 05:23:27 +00:00
northbridge
nb/intel/haswell: Add Crystal Well PCI IDs
2020-08-03 05:16:41 +00:00
security
security/intel/txt: Add Intel TXT support
2020-07-31 16:02:54 +00:00
soc
src/soc/intel/jasperlake: Update SD card ACPI device
2020-08-03 05:20:52 +00:00
southbridge
Change all assert(0) to BUG()
2020-08-03 05:15:15 +00:00
superio
superio/common: Avoid NULL pointer dereference
2020-07-24 21:21:09 +00:00
vendorcode
vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
2020-08-02 16:45:22 +00:00
Kconfig
arch/x86: Remove RELOCATABLE_RAMSTAGE
2020-07-06 06:17:47 +00:00