The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
		
			
				
	
	
		
			82 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Groff
		
	
	
	
	
	
			
		
		
	
	
			82 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			Groff
		
	
	
	
	
	
| .TH INTELTOOL 8
 | |
| .SH NAME
 | |
| inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
 | |
| .SH SYNOPSIS
 | |
| .B inteltool \fR[\fB\-vh?gGrpmedPMaAsfS\fR]
 | |
| .SH DESCRIPTION
 | |
| .B inteltool
 | |
| is a handy little tool for dumping the configuration space of Intel(R)
 | |
| CPUs, northbridges and southbridges.
 | |
| .sp
 | |
| This tool has been developed for the coreboot project (see
 | |
| .B https://coreboot.org
 | |
| for details on coreboot).
 | |
| .SH OPTIONS
 | |
| .TP
 | |
| .B "\-h, \-\-help"
 | |
| Show a help text and exit.
 | |
| .TP
 | |
| .B "\-v, \-\-version"
 | |
| Show version information and exit.
 | |
| .TP
 | |
| .B "\-a, \-\-all"
 | |
| Dump all known information listed below.
 | |
| .TP
 | |
| .B "\-g, \-\-gpio"
 | |
| Dump I/O Controller Hub (ICH) southbridge GPIO registers.
 | |
| .TP
 | |
| .B "\-G, \-\-gpio-diffs"
 | |
| Show only GPIO register differences from hardware defaults.
 | |
| .TP
 | |
| .B "\-r, \-\-rcba"
 | |
| Dump I/O Controller Hub (ICH) southbridge RCBA registers.
 | |
| .TP
 | |
| .B "\-s, \-\-spi"
 | |
| Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
 | |
| .TP
 | |
| .B "\-f, \-\-gfx"
 | |
| .RB "Dump graphics registers. " \
 | |
| "Due to unknown reasons this might lock up some systems after a few seconds."
 | |
| .TP
 | |
| .B "\-p, \-\-pmbase"
 | |
| Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
 | |
| .TP
 | |
| .B "\-m, \-\-mchbar"
 | |
| Dump Intel(R) northbridge MCHBAR registers.
 | |
| .TP
 | |
| .BR "\-S" " \fIfile\fR, " "\-\-spd=" "\fIfile\fR"
 | |
| Dump the memory registers as above and store the current timing settings
 | |
| into \fIfile\fR.
 | |
| .TP
 | |
| .B "\-e, \-\-epbar"
 | |
| Dump Intel(R) northbridge EPBAR registers.
 | |
| .TP
 | |
| .B "\-d, \-\-dmibar"
 | |
| Dump Intel(R) northbridge DMIBAR registers.
 | |
| .TP
 | |
| .B "\-P, \-\-pciexbar"
 | |
| Dump Intel(R) northbridge PCIEXBAR registers.
 | |
| .TP
 | |
| .B "\-M, \-\-msrs"
 | |
| Dump Intel(R) CPU MSRs.
 | |
| .TP
 | |
| .B "\-A, \-\-ambs"
 | |
| Dump Advanced Memory Buffer (AMB) registers.
 | |
| .SH BUGS
 | |
| Please report any bugs on the coreboot mailing list
 | |
| .RB "(" https://coreboot.org/Mailinglist ")."
 | |
| .SH LICENCE
 | |
| .B inteltool
 | |
| is covered by the GNU General Public License (GPL), version 2.
 | |
| .SH COPYRIGHT
 | |
| Copyright (C) 2008 coresystems GmbH
 | |
| .SH AUTHORS
 | |
| Stefan Reinauer <stepan@coresystems.de>
 | |
| .PP
 | |
| This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
 | |
| It is licensed under the terms of the GNU GPL (version 2).
 | |
| .sp
 | |
| Intel(R) is a registered trademark of Intel Corporation. Other product
 | |
| and/or company names mentioned herein may be trademarks or registered
 | |
| trademarks of their respective owners.
 |