ce4c9ec4f6
Cannonlake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
107 lines
2.5 KiB
Plaintext
107 lines
2.5 KiB
Plaintext
config SOC_INTEL_CANNONLAKE
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bool
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help
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Intel Cannonlake support
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if SOC_INTEL_CANNONLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select HAVE_HARD_RESET
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select HAVE_INTEL_FIRMWARE
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select HAVE_MONOTONIC_TIMER
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select INTEL_CAR_NEM_ENHANCED
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select PLATFORM_USES_FSP2_0
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select RELOCATABLE_RAMSTAGE
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CSE
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMBUS
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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select SOC_INTEL_COMMON_RESET
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select UDELAY_TSC
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config UART_DEBUG
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bool "Enable UART debug port."
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default y
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select CONSOLE_SERIAL
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART
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select DRIVERS_UART_8250IO
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config UART_FOR_CONSOLE
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int "Index for LPSS UART port to use for console"
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default 2 if DRIVERS_UART_8250MEM
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help
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Index for LPSS UART port to use for console:
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0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config CPU_BCLK_MHZ
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int
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default 100
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 3
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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endif
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