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soc/intel/cannonlake: Add Kconfig option to select UART index

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Cannonlake SOC has two possible ways to make serial
console functional.

1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.

This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

PCI based LPSS UART2 is by default enabled for Chrome Design.

Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-08-14 13:23:54 +05:30 committed by Martin Roth
parent 19a7adeffe
commit ce4c9ec4f6
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/cannonlake/Kconfig
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@ -56,6 +56,13 @@ config UART_DEBUG
select DRIVERS_UART
select DRIVERS_UART_8250IO
config UART_FOR_CONSOLE
int "Index for LPSS UART port to use for console"
default 2 if DRIVERS_UART_8250MEM
help
Index for LPSS UART port to use for console:
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
config DCACHE_RAM_BASE
default 0xfef00000