35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
135 lines
4.7 KiB
Markdown
135 lines
4.7 KiB
Markdown
# ASRock H110M-DVS
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This page describes how to run coreboot on the [ASRock H110M-DVS].
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## Required proprietary blobs
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Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset.
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Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md)
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(intel FSP 2.0) to initialize this generation silicon. Please see this
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[document](../../soc/intel/code_development_model/code_development_model.md).
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FSP Information:
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```{eval-rst}
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+-----------------------------+-------------------+-------------------+
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| FSP Project Name | Directory | Specification |
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+-----------------------------+-------------------+-------------------+
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| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
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| processors and chipsets | | |
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| (formerly Kaby Lake) | | |
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+-----------------------------+-------------------+-------------------+
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```
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## Building coreboot
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The following steps set the default parameters for this board to build a
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fully working image:
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```bash
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make distclean
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touch .config
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./util/scripts/config --enable VENDOR_ASROCK
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./util/scripts/config --enable BOARD_ASROCK_H110M_DVS
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./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx"
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make olddefconfig
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```
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However, it is strongly advised to use `make menuconfig` afterwards
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(or instead), so that you can see all of the settings.
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Use the following command to disable the serial console if debugging
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output is not required:
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```bash
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./util/scripts/config --disable CONSOLE_SERIAL
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```
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However, a more flexible method is to change the console log level from
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within an OS using `util/nvramtool`, or with the `nvramcui` payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. By default, only
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the BIOS region of the flash is writable. If you wish to change any
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other region, such as the Management Engine or firmware descriptor, then
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an external programmer is required (unless you find a clever way around
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the flash protection). More information about this [here](../../tutorial/flashing_firmware/index.md).
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### External programming
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The flash chip is a 8 MiB socketed DIP-8 chip. Specifically, it's a
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Macronix MX25L6473E, whose datasheet can be found [here][MX25L6473E].
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The chip is located to the bottom right-hand side of the board. For
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a precise location, refer to section 1.3 (Motherboard Layout) of the
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[H110M-DVS manual], where the chip is labelled "64Mb BIOS". Take note of
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the chip's orientation, remove it from its socket, and flash it with
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an external programmer. For reference, the notch in the chip should be
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facing towards the bottom of the board.
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## Known issues
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- The VGA port doesn't work. Discrete graphic card is used as primary
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device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not
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set). Dynamic switching between iGPU and PEG is not yet supported.
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- SuperIO GPIO pin is used to reset Realtek chip. However, since the
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Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network
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chip is in a reset state all the time.
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## Untested
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- parallel port
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- PS/2 keyboard
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- PS/2 mouse
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- EHCI debug
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- TPM
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- infrared module
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- chassis intrusion header
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- chassis speaker header
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## Working
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- integrated graphics init with libgfxinit (see [Known issues](#known-issues))
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- PCIe x1
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- PEG x16 Gen3
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- SATA
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- USB
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- serial port
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- onboard audio
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- using `me_cleaner`
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- using `flashrom`
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## TODO
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- NCT6791D GPIOs
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- onboard network (see [Known issues](#known-issues))
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- S3 suspend/resume
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- Wake-on-LAN
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- hardware monitor
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## Technology
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```{eval-rst}
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+------------------+--------------------------------------------------+
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| CPU | Intel Skylake/Kaby Lake (LGA1151) |
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+------------------+--------------------------------------------------+
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| PCH | Intel Sunrise Point H110 |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6791D |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
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[MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
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