41ba11229a
Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which lets us specify coreboot's EL upon entry. Based on that, we access the appropriate ELx registers. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74798 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
148 lines
4.0 KiB
ArmAsm
148 lines
4.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Optimized assembly for low-level CPU operations on ARM64 processors.
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*/
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#include <arch/asm.h>
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#include <arch/cache.h>
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.macro dcache_apply_all crm
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dsb sy
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mrs x0, clidr_el1 // read CLIDR
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and w3, w0, #0x07000000 // narrow to LoC
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lsr w3, w3, #23 // left align LoC (low 4 bits)
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cbz w3, 5f //done
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mov w10, #0 // w10 = 2 * cache level
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mov w8, #1 // w8 = constant 0b1
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1: //next_level
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add w2, w10, w10, lsr #1 // calculate 3 * cache level
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lsr w1, w0, w2 // extract 3-bit cache type for this level
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and w1, w1, #0x7 // w1 = cache type
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cmp w1, #2 // is it data or i&d?
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b.lt 4f //skip
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msr csselr_el1, x10 // select current cache level
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isb // sync change of csselr
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mrs x1, ccsidr_el1 // w1 = read ccsidr
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and w2, w1, #7 // w2 = log2(linelen_bytes) - 4
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add w2, w2, #4 // w2 = log2(linelen_bytes)
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ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also
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// max way number)
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clz w5, w4 // w5 = 32 - log2(ways)
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// (bit position of way in DC)
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lsl w9, w4, w5 // w9 = max way number
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// (aligned for DC)
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lsl w16, w8, w5 // w16 = amount to decrement (way
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// number per iteration)
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2: //next_way
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ubfx w7, w1, #13, #15 // w7 = max set #, right aligned
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lsl w7, w7, w2 // w7 = max set #, DC aligned
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lsl w17, w8, w2 // w17 = amount to decrement (set
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// number per iteration)
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3: //next_set
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orr w11, w10, w9 // w11 = combine way # & cache #
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orr w11, w11, w7 // ... and set #
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dc \crm, x11 // clean and/or invalidate line
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subs w7, w7, w17 // decrement set number
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b.ge 3b //next_set
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subs x9, x9, x16 // decrement way number
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b.ge 2b //next_way
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4: //skip
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add w10, w10, #2 // increment 2 *cache level
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cmp w3, w10 // Went beyond LoC?
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b.gt 1b //next_level
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5: //done
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dsb sy
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isb
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ret
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.endm
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=isw
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=csw
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=cisw
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ENDPROC(dcache_clean_invalidate_all)
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/* This must be implemented in assembly to ensure there are no accesses to
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memory (e.g. the stack) in between disabling and flushing the cache. */
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ENTRY(mmu_disable)
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str x30, [sp, #-0x8]
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mrs x0, CURRENT_EL(sctlr)
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mov x1, #~(SCTLR_C | SCTLR_M)
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and x0, x0, x1
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msr CURRENT_EL(sctlr), x0
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isb
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bl dcache_clean_invalidate_all
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ldr x30, [sp, #-0x8]
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ret
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ENDPROC(mmu_disable)
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/*
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* Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a
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* known state regarding caches/SCTLR/SCR/PSTATE. Completely invalidates
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* icache/dcache, disables MMU and dcache (if active), and enables unaligned
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* accesses, icache. Seeds stack and initializes SP_EL0. Clobbers R22 and R23.
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*/
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ENTRY(arm64_init_cpu)
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/* Initialize PSTATE (mask all exceptions, select SP_EL0). */
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msr SPSel, #0
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msr DAIFSet, #0xf
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/* TODO: This is where we'd put non-boot CPUs into WFI if needed. */
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/* x22: SCTLR, return address: x23 (callee-saved by subroutine) */
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mov x23, x30
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mrs x22, CURRENT_EL(sctlr)
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/* Activate ICache already for speed during cache flush below. */
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orr x22, x22, #SCTLR_I
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msr CURRENT_EL(sctlr), x22
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isb
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/* Invalidate dcache */
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bl dcache_invalidate_all
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/* Reinitialize SCTLR from scratch to known-good state.
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This may disable MMU or DCache. */
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ldr w22, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA)
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msr CURRENT_EL(sctlr), x22
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#if CONFIG_ARM64_CURRENT_EL == EL3
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/* Initialize SCR to unmask all interrupts (so that if we get a spurious
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IRQ/SError we'll see it when it happens, not hang in BL31). This will
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only have an effect after we DAIFClr in exception_init(). */
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mov x22, #SCR_RES1 | SCR_IRQ | SCR_FIQ | SCR_EA
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msr scr_el3, x22
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#endif
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/* Invalidate icache and TLB for good measure */
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ic iallu
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tlbi alle3
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dsb sy
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isb
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/* Initialize stack with sentinel value to later check overflow. */
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ldr x2, =0xdeadbeefdeadbeef
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ldr x0, =_stack
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ldr x1, =_estack
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1:
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stp x2, x2, [x0], #16
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cmp x0, x1
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bne 1b
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/* Leave a line of beef dead for easier visibility in stack dumps. */
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sub sp, x0, #16
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ret x23
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ENDPROC(arm64_init_cpu)
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