Only thing not decoded now are the PCH straps
ifdtool -d path/to/image.bin
File path/to/image.bin is 4096 bytes
Found Flash Descriptor signature at 0x00000010
FLMAP0:    0x02040003
  NR:      2
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x12100206
  ISL:     0x12
  FPSBA:   0x100
  NM:      2
  FMBA:    0x60
FLMAP2:    0x00210120
  PSL:     0x2101
  FMSBA:   0x200
FLUMAP1:   0x000004df
  Intel ME VSCC Table Length (VTL):        4
  Intel ME VSCC Table Base Address (VTBA): 0x000df0
ME VSCC table:
  JID0:  0x001740ef
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x40
    SPI Componend Vendor ID:            0xef
  VSCC0: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB
  JID1:  0x001720c2
    SPI Componend Device ID 1:          0x17
    SPI Componend Device ID 0:          0x20
    SPI Componend Vendor ID:            0xc2
  VSCC1: 0x20052005
    Lower Erase Opcode:                 0x20
    Lower Write Enable on Write Status: 0x50
    Lower Write Status Required:        No
    Lower Write Granularity:            64 bytes
    Lower Block / Sector Erase Size:    4KB
    Upper Erase Opcode:                 0x20
    Upper Write Enable on Write Status: 0x50
    Upper Write Status Required:        No
    Upper Write Granularity:            64 bytes
    Upper Block / Sector Erase Size:    4KB
OEM Section:
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Found Region Section
FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1:    0x07ff0180
  Flash Region 1 (BIOS): 00180000 - 007fffff
FLREG2:    0x017f0001
  Flash Region 2 (Intel ME): 00001000 - 0017ffff
FLREG3:    0x00001fff
  Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
FLREG4:    0x00001fff
  Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section
FLCOMP     0x64900024
  Dual Output Fast Read Support:       supported
  Read ID/Read Status Clock Frequency: 50MHz
  Write/Erase Clock Frequency:         50MHz
  Fast Read Clock Frequency:           50MHz
  Fast Read Support:                   supported
  Read Clock Frequency:                20MHz
  Component 2 Density:                 8MB
  Component 1 Density:                 8MB
FLILL      0x000060c7
  Invalid Instruction 3: 0x00
  Invalid Instruction 2: 0x00
  Invalid Instruction 1: 0x60
  Invalid Instruction 0: 0xc7
FLPB       0x00000000
  Flash Partition Boundary Address: 0x000000
Found PCH Strap Section
PCHSTRP0:  0x0820d602
PCHSTRP1:  0x0000010f
PCHSTRP2:  0x00560000
PCHSTRP3:  0x00000000
PCHSTRP4:  0x00c8e000
PCHSTRP5:  0x00000000
PCHSTRP6:  0x00000000
PCHSTRP7:  0xc0001ae0
PCHSTRP8:  0x00000000
PCHSTRP9:  0x30000580
PCHSTRP10: 0x00410044
PCHSTRP11: 0x99000097
PCHSTRP12: 0x00000000
PCHSTRP13: 0x00000000
PCHSTRP14: 0x00000000
PCHSTRP15: 0x0000033e
PCHSTRP16: 0x00000000
PCHSTRP17: 0x00000002
Found Master Section
FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000
FLMSTR2:   0x0c0d0000 (Intel ME)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      enabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      enabled
  Requester ID:                      0x0000
FLMSTR3:   0x08080118 (GbE)
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           enabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: disabled
  Flash Descriptor Write Access:     disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            enabled
  Intel ME Region Read Access:       disabled
  Host CPU/BIOS Region Read Access:  disabled
  Flash Descriptor Read Access:      disabled
  Requester ID:                      0x0118
Found Processor Strap Section
????:      0x00000000
????:      0xffffffff
????:      0xffffffff
????:      0xffffffff
Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1756
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
		
	
		
			
				
	
	
		
			112 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			112 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * ifdtool - dump Intel Firmware Descriptor information
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|  *
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|  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; version 2 of the License.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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|  */
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| 
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| #include <stdint.h>
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| #define IFDTOOL_VERSION "1.1"
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| 
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| enum spi_frequency {
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| 	SPI_FREQUENCY_20MHZ = 0,
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| 	SPI_FREQUENCY_33MHZ = 1,
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| 	SPI_FREQUENCY_50MHZ = 4,
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| };
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| 
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| enum component_density {
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| 	COMPONENT_DENSITY_512KB = 0,
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| 	COMPONENT_DENSITY_1MB   = 1,
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| 	COMPONENT_DENSITY_2MB   = 2,
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| 	COMPONENT_DENSITY_4MB   = 3,
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| 	COMPONENT_DENSITY_8MB   = 4,
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| 	COMPONENT_DENSITY_16MB  = 5,
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| };
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| 
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| // flash descriptor
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| typedef struct {
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| 	uint32_t flvalsig;
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| 	uint32_t flmap0;
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| 	uint32_t flmap1;
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| 	uint32_t flmap2;
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| 	uint8_t  reserved[0xefc - 0x20];
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| 	uint32_t flumap1;
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| } __attribute__((packed)) fdbar_t;
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| 
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| // regions
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| typedef struct {
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| 	uint32_t flreg0;
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| 	uint32_t flreg1;
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| 	uint32_t flreg2;
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| 	uint32_t flreg3;
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| 	uint32_t flreg4;
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| } __attribute__((packed)) frba_t;
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| 
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| // component section
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| typedef struct {
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| 	uint32_t flcomp;
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| 	uint32_t flill;
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| 	uint32_t flpb;
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| } __attribute__((packed)) fcba_t;
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| 
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| // pch strap
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| typedef struct {
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| 	uint32_t pchstrp0;
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| 	uint32_t pchstrp1;
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| 	uint32_t pchstrp2;
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| 	uint32_t pchstrp3;
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| 	uint32_t pchstrp4;
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| 	uint32_t pchstrp5;
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| 	uint32_t pchstrp6;
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| 	uint32_t pchstrp7;
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| 	uint32_t pchstrp8;
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| 	uint32_t pchstrp9;
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| 	uint32_t pchstrp10;
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| 	uint32_t pchstrp11;
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| 	uint32_t pchstrp12;
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| 	uint32_t pchstrp13;
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| 	uint32_t pchstrp14;
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| 	uint32_t pchstrp15;
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| 	uint32_t pchstrp16;
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| 	uint32_t pchstrp17;
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| } __attribute__((packed)) fpsba_t;
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| 
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| // master
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| typedef struct {
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| 	uint32_t flmstr1;
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| 	uint32_t flmstr2;
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| 	uint32_t flmstr3;
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| } __attribute__((packed)) fmba_t;
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| 
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| // processor strap
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| typedef struct {
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| 	uint32_t data[8];
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| } __attribute__((packed)) fmsba_t;
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| 
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| // ME VSCC
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| typedef struct {
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| 	uint32_t jid;
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| 	uint32_t vscc;
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| } vscc_t;
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| 
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| typedef struct {
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| 	// Actual number of entries specified in vtl
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| 	vscc_t entry[8];
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| } vtba_t;
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| 
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| typedef struct {
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| 	int base, limit, size;
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| } region_t;
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