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We have been trying to avoid reassigning previously used USB addresses to different devices since CL:197420, because some devices seem to take issue with that. Unfortunately, that patch doesn't affect XHCI: those controllers insist on chosing addresses on their own. The only way to prevent them from reusing a previously assigned address is to not disable that slot at all. This patch implements address reuse avoidance on XHCI by not disabling slots when a device is detatched (which may occur both on physical detachment or if we simply couldn't find a driver for that device). Instead, we just release as many resources as we can for detached devices (by dropping all endpoint contexts) and defer the final cleanup until the point where the controller actually runs out of resources (a point that we probably don't often reach in most firmware scenarios). BRANCH=none BUG=chrome-os-partner:42181 TEST=Booted an Oak plugged into a Servo without having a driver for the SMSC network chip, observed that it could still enumerate the next device afterwards. Kept unplugging/replugging stuff until the cleanup triggered and made sure the controller still worked after that. Also played around a bit on a Falco without issues. Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284175 Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10957 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.