35599f9a66
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.
For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:
* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:
```{toctree}
:maxdepth: 1
Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```
Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.
The toctrees were converted to the MyST syntax using the following
command and Python script:
`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`
```
import re
import sys
in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
with open(sys.argv[1], "w") as f:
for line in lines:
match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
if match is not None:
if not in_list:
in_list = True
f.write("```{toctree}\n")
f.write(":maxdepth: 1\n\n")
f.write(match.group(1) + " <" + match.group(2) + ">\n")
else:
if in_list:
f.write("```\n")
f.write(line)
in_list = False
if in_list:
f.write("```\n")
```
While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.
This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.
Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.
These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`
Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.
From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.
TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.
[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html
Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2.7 KiB
Cavium CN81xx documentation
Reference code
The Cavium reference code is called `BDK`_ (board development kit) and is part
of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot.
SOC code
The SOC folder contains functions for:
- TWSI
- UART
- TIMER
- SPI
- MMU
- DRAM
- CLOCK
- GPIO
- Secondary CPUs
- PCI
All other hardware is initialized by the BDK code, which is invoked from ramstage.
Notes about the hardware
Cavium SoC do not have embedded SRAM. The BOOTROM setups the L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed location. It then jumps to the firmware.
For more details have a look at `Cavium CN8XXX Bootflow`_.
CAR setup
For Cache-as-RAM we only need to lock the cachelines which are used by bootblock or romstage until DRAM has been set up. At the end of romstage the cachelines are unlocked and the contents are flushed to DRAM. Locked cachelines are never evicted.
The CAR setup is done in bootblock_custom.S and thus doesn't use the common
aarch64 bootblock.S code.
DRAM setup
The DRAM setup is done by the `BDK`_.
PCI setup
The PCI setup is done using the MMCONF mechanism. Besides configuring device visibility (secure/unsecure) the MSI-X interrupts needs to be configured.
Devicetree patching
The Linux devicetree needs to be patched, depending on the available hardware and their configuration. Some values depends on fuses, some on user selectable configuration.
The following SoC specific fixes are made:
- Fix SCLK
- Fix UUA refclock
- Remove unused PEM entries
- Remove unused QLM entries
- Set local MAC address
CN81xx quirks
The CN81xx needs some quirks that are not documented or hidden in the code.
Violation of PCI spec
Problem:
- The PCI device 01:01.0 is disabled, but a multifunction device.
- The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot PCI allocator.
Solution:
The PCI Bus 0 and 1 are scanned manually in SOC's PCI code.
Crash accessing SLI memory
Problem:
The SLI memory region decodes to attached PCIe devices. Accessing the memory region results in 'Data Abort Exception' if the link of the PCIe device never had been enabled.
Solution:
Enable the PCIe link at least once. (You can disabling the link and the SLI memory reads as 0xffffffff.)
RNG Data Abort Exception
Problem:
'Data Abort Exception' on accessing the enabled RNG.
Solution:
Read the BDK_RNM_CTL_STATUS register at least once after writing it.
.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
.. _Cavium CN8XXX Bootflow: ../bootflow.html
.. _BDK: ../../../vendorcode/cavium/bdk.html