8c986ab263
* Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
20 lines
766 B
Markdown
20 lines
766 B
Markdown
# Cavium bootflow
|
|
|
|
The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller.
|
|
It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get
|
|
the position of the bootstage in flash. It then loads 192KiB from flash into
|
|
L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as
|
|
the signature of the bootstage isn't verified.
|
|
The **BOOTROM** can do AES decryption for obfuscation or verify the signature
|
|
of the bootstage. Both features aren't used and won't be described any further.
|
|
|
|
* The typical position of bootstage in flash is at address **0x20000**.
|
|
* The entry point in physical DRAM is at address **0x100000**.
|
|
|
|
## Layout
|
|
|
|
![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow]
|
|
|
|
[cavium_bootflow]: cavium_bootflow.png
|
|
|