system76-coreboot

Files

Sumeet Pawnikar 810527a4ea soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix

Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.

Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2019-07-31 04:27:48 +00:00

amd

soc/amd/picasso: Remove dead SPD size Kconfig symbol

2019-07-21 17:31:01 +00:00

cavium

arch/non-x86: Flip HAVE_MONOTONIC_TIMER default

2019-07-09 13:07:38 +00:00

imgtec

arch/non-x86: Flip HAVE_MONOTONIC_TIMER default

2019-07-09 13:07:38 +00:00

intel

soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix