ffa710b9dd
The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.