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Vlv2TbltDevicePkg/PlatformDxe: Remove the unused variables

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Fix the following errors from gcc:

Vlv2TbltDevicePkg/PlatformDxe/Platform.c: In function ?InitPciDevPME?:
Vlv2TbltDevicePkg/PlatformDxe/Platform.c:516:26: error: variable ?Status? set but not used [-Werror=unused-but-set-variable]

Vlv2TbltDevicePkg/PlatformDxe/Platform.c: In function ?InitThermalZone?:
Vlv2TbltDevicePkg/PlatformDxe/Platform.c:575:26: error: variable ?Status? set but not used [-Werror=unused-but-set-variable]

Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c: In function ?InitializeSubsystemIds?:
Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c:111:10: error: variable ?SubsystemAudioVidDid? set but not used [-Werror=unused-but-set-variable]

Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c: In function ?InitBadBars?:
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c:115:40: error: variable ?PciIoDevice? set but not used [-Werror=unused-but-set-variable]
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c:114:39: error: variable ?Status? set but not used [-Werror=unused-but-set-variable]

Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c: In function ?ProgramPciLatency?:
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c:320:39: error: variable ?Status? set but not used [-Werror=unused-but-set-variable]

Cc: David Wei <david.wei@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: David Wei <david.wei@intel.com>
This commit is contained in:
Gary Lin
2016-07-29 11:25:34 +08:00
committed by david wei
parent 5c3bd3500f
commit 076d0d64aa
3 changed files with 122 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
View File

@@ -99,10 +99,8 @@ InitializeSubsystemIds (
the Subsystem Vendor and Device IDs.
@retval Returns VOID
**/
InitializeSubsystemIds (
VOID
InitializeSubsystemIds (
)

212
Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
View File

@@ -102,8 +102,6 @@ InitBadBars(
return EFI_SUCCESS;
}
VOID
VOID
InitBadBars(
@@ -112,8 +110,6 @@ InitBadBars(
IN UINT16 DeviceId
)
{
PCI_IO_DEVICE *PciIoDevice;
UINT64 BaseAddress = 0;
UINT64 BaseAddress = 0;
UINT64 TempBaseAddress = 0;
@@ -124,31 +120,31 @@ InitBadBars(
UINTN MemSizeBits;
switch ( VendorId) {
case ATI_VENDOR_ID:
//
// ATI fix-ups. At this time all ATI cards in BadDeviceTable
// have same problem in that OPROM BAR needs to be increased.
//
Bar = 0x30 ;
//
case ATI_VENDOR_ID:
//
// ATI fix-ups. At this time all ATI cards in BadDeviceTable
// have same problem in that OPROM BAR needs to be increased.
//
Bar = 0x30 ;
//
// Get original BAR address
//
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &BaseAddress
);
//
// Find BAR size
//
TempBaseAddress = 0xffffffff;
Status = PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
Bar,
1,
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &BaseAddress
);
//
// Find BAR size
//
TempBaseAddress = 0xffffffff;
PciIo->Pci.Write (
PciIo,
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &TempBaseAddress
);
PciIo->Pci.Read (
@@ -159,32 +155,32 @@ InitBadBars(
(VOID *) &TempBaseAddress
);
TempBaseAddress &= 0xfffffffe;
MemSize = 1;
while ((TempBaseAddress & 0x01) == 0) {
TempBaseAddress = TempBaseAddress >> 1;
MemSize = MemSize << 1;
MemSize = 1;
while ((TempBaseAddress & 0x01) == 0) {
TempBaseAddress = TempBaseAddress >> 1;
MemSize = MemSize << 1;
}
//
// Free up allocated memory memory and re-allocate with increased size.
//
gDS->FreeMemorySpace (
BaseAddress,
MemSize
);
//
// Force new alignment
//
MemSize = 0x8000000;
MemSizeBits = 28;
Status = gDS->AllocateMemorySpace (
EfiGcdAllocateAnySearchBottomUp,
EfiGcdMemoryTypeMemoryMappedIo,
MemSizeBits, // Alignment
MemSize,
&BaseAddress,
mImageHandle,
BaseAddress,
MemSize
);
//
// Force new alignment
//
MemSize = 0x8000000;
MemSizeBits = 28;
gDS->AllocateMemorySpace (
EfiGcdAllocateAnySearchBottomUp,
EfiGcdMemoryTypeMemoryMappedIo,
MemSizeBits, // Alignment
MemSize,
&BaseAddress,
mImageHandle,
NULL
);
PciIo->Pci.Write (
@@ -195,22 +191,22 @@ InitBadBars(
(VOID *) &BaseAddress
);
break;
case NCR_VENDOR_ID:
#define MIN_NCR_IO_SIZE 0x800
#define NCR_GRAN 11 // 2**11 = 0x800
//
// NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
//
break;
case NCR_VENDOR_ID:
#define MIN_NCR_IO_SIZE 0x800
#define NCR_GRAN 11 // 2**11 = 0x800
//
// NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
//
for (Bar = 0x10; Bar < 0x28; Bar+= 4) {
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &BaseAddress
);
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &BaseAddress
);
if (BaseAddress && 0x01) {
TempBaseAddress = 0xffffffff;
PciIo->Pci.Write (
@@ -218,28 +214,28 @@ InitBadBars(
EfiPciIoWidthUint32,
Bar,
1,
(VOID *) &TempBaseAddress
);
TempBaseAddress &= 0xfffffffc;
IoSize = 1;
(VOID *) &TempBaseAddress
);
TempBaseAddress &= 0xfffffffc;
IoSize = 1;
while ((TempBaseAddress & 0x01) == 0) {
TempBaseAddress = TempBaseAddress >> 1;
IoSize = IoSize << 1;
}
if (IoSize < MIN_NCR_IO_SIZE) {
Status = gDS->FreeIoSpace (
BaseAddress,
IoSize
);
TempBaseAddress = TempBaseAddress >> 1;
IoSize = IoSize << 1;
}
if (IoSize < MIN_NCR_IO_SIZE) {
gDS->FreeIoSpace (
BaseAddress,
IoSize
);
gDS->AllocateIoSpace (
EfiGcdAllocateAnySearchTopDown,
EfiGcdIoTypeIo,
NCR_GRAN, // Alignment
MIN_NCR_IO_SIZE,
&BaseAddress,
mImageHandle,
NULL
EfiGcdAllocateAnySearchTopDown,
EfiGcdIoTypeIo,
NCR_GRAN, // Alignment
MIN_NCR_IO_SIZE,
&BaseAddress,
mImageHandle,
NULL
);
TempBaseAddress = BaseAddress + 1;
PciIo->Pci.Write (
@@ -255,13 +251,13 @@ InitBadBars(
break;
case INTEL_VENDOR_ID:
if (DeviceId == INTEL_82573E_IDER) {
//
// Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not
// support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable
// them all for Control Blocks and Bus mastering ops as well as Secondary IDE
// Controller.
case INTEL_VENDOR_ID:
if (DeviceId == INTEL_82573E_IDER) {
//
// Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not
// support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable
// them all for Control Blocks and Bus mastering ops as well as Secondary IDE
// Controller.
// All Tekoa A2 or earlier step chips for now.
//
PciIo->Pci.Read (
@@ -269,13 +265,13 @@ InitBadBars(
EfiPciIoWidthUint8,
PCI_REVISION_ID_OFFSET,
1,
&RevId
);
if (RevId <= 0x02) {
for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
//
// Maybe want to clean this up a bit later but for now just clear out the secondary
// Bars don't worry aboyut freeing up thge allocs.
&RevId
);
if (RevId <= 0x02) {
for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
//
// Maybe want to clean this up a bit later but for now just clear out the secondary
// Bars don't worry aboyut freeing up thge allocs.
//
TempBaseAddress = 0x0;
PciIo->Pci.Write (
@@ -286,13 +282,13 @@ InitBadBars(
(VOID *) &TempBaseAddress
);
} // end for
}
else
{
//
//Tekoa A3 or above:
//Clear bus master base address (PCI register 0x20)
//since Tekoa does not fully support IDE Bus Mastering
}
else
{
//
//Tekoa A3 or above:
//Clear bus master base address (PCI register 0x20)
//since Tekoa does not fully support IDE Bus Mastering
//
TempBaseAddress = 0x0;
PciIo->Pci.Write (
@@ -308,19 +304,17 @@ ProgramPciLatency(
default:
break;
}
return;
}
return;
}
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
EFI_STATUS Status;
//
// Program Master Latency Timer
VOID
ProgramPciLatency(
IN EFI_PCI_IO_PROTOCOL *PciIo
)
{
//
// Program Master Latency Timer
//
if (mSystemConfiguration.PciLatency != 0) {
PciIo->Pci.Write (

40
Vlv2TbltDevicePkg/PlatformDxe/Platform.c
View File

@@ -513,16 +513,15 @@ InitPciDevPME (
)
{
UINTN VarSize;
EFI_STATUS Status;
VarSize = sizeof(SYSTEM_CONFIGURATION);
Status = gRT->GetVariable(
NORMAL_SETUP_NAME,
&gEfiNormalSetupGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
gRT->GetVariable(
NORMAL_SETUP_NAME,
&gEfiNormalSetupGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
//
//Program HDA PME_EN
@@ -572,21 +571,20 @@ InitThermalZone (
)
{
UINTN VarSize;
EFI_STATUS Status;
EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
VarSize = sizeof(SYSTEM_CONFIGURATION);
Status = gRT->GetVariable(
NORMAL_SETUP_NAME,
&gEfiNormalSetupGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
Status = gBS->LocateProtocol (
&gEfiGlobalNvsAreaProtocolGuid,
NULL,
(void **)&GlobalNvsArea
);
gRT->GetVariable(
NORMAL_SETUP_NAME,
&gEfiNormalSetupGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
gBS->LocateProtocol (
&gEfiGlobalNvsAreaProtocolGuid,
NULL,
(void **)&GlobalNvsArea
);
GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
}