ArmPlatformPkg: Introduce Primary core macros
On MpCore system, the primary core can now be any core of the system. To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask' and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'. These PCDs by default use the ClusterId and CoreId to identify the core. And the primary core is defined as the ClusetrId=0 and CoreId=0. The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId), GET_CORE_POS(MpId), PRIMARY_CORE_ID. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -32,7 +32,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN CoreId
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IN UINTN MpId
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)
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{
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// Function pointer to Secondary Core entry point
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@@ -45,7 +45,7 @@ SecondaryMain (
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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secondary_start = (VOID (*)())secondary_entry_addr;
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@@ -21,7 +21,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN CoreId
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IN UINTN MpId
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)
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{
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ASSERT(FALSE);
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@@ -36,7 +36,7 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
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VOID
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CEntryPoint (
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IN UINTN CoreId,
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IN UINTN MpId,
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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@@ -62,7 +62,7 @@ CEntryPoint (
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//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
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//If not primary Jump to Secondary Main
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if(0 == CoreId) {
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if (IS_PRIMARY_CORE(MpId)) {
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// Initialize the Debug Agent for Source Level Debugging
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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@@ -70,7 +70,7 @@ CEntryPoint (
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// Goto primary Main.
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PrimaryMain (PeiCoreEntryPoint);
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} else {
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SecondaryMain (CoreId);
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SecondaryMain (MpId);
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}
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// PEI Core should always load and never return
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@@ -57,7 +57,7 @@ PrimaryMain (
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN CoreId
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IN UINTN MpId
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);
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#endif
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@@ -19,19 +19,18 @@
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.text
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.align 3
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#global symbols referenced by this module
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GCC_ASM_IMPORT(CEntryPoint)
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GCC_ASM_IMPORT(ArmReadMpidr)
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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StartupAddr: .word CEntryPoint
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#make _ModuleEntryPoint as global
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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# Identify CPU ID
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mrc p15, 0, r0, c0, c0, 5
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and r0, #0xf
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bl ASM_PFX(ArmReadMpidr)
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// Get ID of this CPU in Multicore system
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LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
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and r0, r0, r1
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_SetupStack:
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# Setup Stack for the 4 CPU cores
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@@ -19,6 +19,7 @@
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmReadMpidr
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EXPORT _ModuleEntryPoint
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PRESERVE8
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@@ -28,8 +29,10 @@ StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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// Identify CPU ID
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mrc p15, 0, r0, c0, c0, 5
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and r0, #0xf
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bl ArmReadMpidr
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// Get ID of this CPU in Multicore system
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LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
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and r0, r0, r1
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_SetupStack
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// Setup Stack for the 4 CPU cores
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@@ -62,7 +65,7 @@ _PrepareArguments
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ldr r2, StartupAddr
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// jump to PrePeiCore C code
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// r0 = core_id
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// r0 = mp_id
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// r1 = pei_core_address
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blx r2
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@@ -58,6 +58,9 @@
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress
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gArmTokenSpaceGuid.PcdNormalFvSize
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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