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ArmLib/ArmV7: Add ISB to ArmEnableVFP

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ArmEnableVFP could crash on an out-of-order CPU. Adding an instruction barrier after writing to CPACR cures the problem.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13134 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
2012-03-26 11:01:21 +00:00
parent eac42a514b
commit 18029bb911
4 changed files with 4 additions and 0 deletions
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ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
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@@ -88,6 +88,7 @@ ASM_PFX(CPSRRead):
ASM_PFX(ArmWriteCPACR):
mcr p15, 0, r0, c1, c0, 2
isb
bx lr
ASM_PFX(ArmWriteAuxCr):