ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11735 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -15,7 +15,7 @@
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/ArmLib.h>
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#include <Library/L2X0CacheLib.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/PcdLib.h>
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#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)
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@@ -25,6 +25,10 @@
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VOID
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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)
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{
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@@ -66,9 +70,9 @@ L2x0CacheInit (
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Aux |= L2x0_AUXCTRL_AW_AWCACHE;
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// Use default Size
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Data = L2x0ReadReg(L2X0_AUXCTRL);
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Aux |= Data & (0x7 << 17);
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Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;
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// Use default associativity
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Aux |= Data & (0x1 << 16);
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Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;
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// Enabled I & D Prefetch
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Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
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@@ -88,29 +92,16 @@ L2x0CacheInit (
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L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
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}
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if (Revision >= 4) {
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// Tag RAM Latency register
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// - Use default latency
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// Data RAM Latency Control register
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// - Use default latency
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} else if (Revision >= 2) {
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L2x0WriteReg(L230_TAG_LATENCY,
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(L2_TAG_ACCESS_LATENCY << 8)
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| (L2_TAG_ACCESS_LATENCY << 4)
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| L2_TAG_SETUP_LATENCY
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);
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L2x0WriteReg(L230_DATA_LATENCY,
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(L2_DATA_ACCESS_LATENCY << 8)
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| (L2_DATA_ACCESS_LATENCY << 4)
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| L2_DATA_SETUP_LATENCY
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);
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} else {
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Aux |= (L2_TAG_ACCESS_LATENCY << 6)
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| (L2_DATA_ACCESS_LATENCY << 3)
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| L2_DATA_ACCESS_LATENCY;
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}
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if (Revision >= 2) {
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L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);
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L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);
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} else {
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// PL310 old style latency is not supported yet
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ASSERT(0);
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}
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// Set the platform specific values
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Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;
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// Write Auxiliary value
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L2x0WriteReg(L2X0_AUXCTRL, Aux);
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