OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (skeleton)
Introduce the Q35SmramAtDefaultSmbaseInitialization() function for detecting the "SMRAM at default SMBASE" feature. For now, the function is only a skeleton, so that we can gradually build upon the result while the result is hard-coded as FALSE. The actual detection will occur in a later patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-6-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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mergify[bot]
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e0ed7a9b15
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73974f809c
@@ -43,6 +43,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize;
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STATIC UINT16 mQ35TsegMbytes;
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STATIC UINT16 mQ35TsegMbytes;
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BOOLEAN mQ35SmramAtDefaultSmbase;
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UINT32 mQemuUc32Base;
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UINT32 mQemuUc32Base;
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VOID
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VOID
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@@ -90,6 +92,22 @@ Q35TsegMbytesInitialization (
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}
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}
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VOID
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Q35SmramAtDefaultSmbaseInitialization (
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VOID
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)
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{
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RETURN_STATUS PcdStatus;
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ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
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mQ35SmramAtDefaultSmbase = FALSE;
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PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,
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mQ35SmramAtDefaultSmbase);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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VOID
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VOID
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QemuUc32BaseInitialization (
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QemuUc32BaseInitialization (
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VOID
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VOID
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@@ -792,6 +792,7 @@ InitializePlatform (
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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if (FeaturePcdGet (PcdSmmSmramRequire)) {
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Q35BoardVerification ();
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Q35BoardVerification ();
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Q35TsegMbytesInitialization ();
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Q35TsegMbytesInitialization ();
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Q35SmramAtDefaultSmbaseInitialization ();
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}
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}
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PublishPeiMemory ();
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PublishPeiMemory ();
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@@ -52,6 +52,11 @@ Q35TsegMbytesInitialization (
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VOID
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VOID
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);
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);
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VOID
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Q35SmramAtDefaultSmbaseInitialization (
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VOID
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);
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EFI_STATUS
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EFI_STATUS
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PublishPeiMemory (
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PublishPeiMemory (
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VOID
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VOID
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@@ -119,6 +124,8 @@ extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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extern UINT16 mHostBridgeDevId;
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extern BOOLEAN mQ35SmramAtDefaultSmbase;
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extern UINT32 mQemuUc32Base;
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extern UINT32 mQemuUc32Base;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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#endif // _PLATFORM_PEI_H_INCLUDED_
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@@ -84,6 +84,7 @@
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
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gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
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gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
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gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase
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gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
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gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
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