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This revision can only work with Intel(c) UDK Debugger Tool version 1.2 or greater. Detailed change log is as below:

Browse Source 
1. Define the transfer protocol revision mechanism. Increase the revision number to 0.2 and inform user to use the latest one when the HOST software is too old.
   New HOST software will implement logic to handle all other revision mismatch cases.
2. Define new debug message packet to print the debug agent trace information by debug port channel.
3. Add check sum mechanism in the communication protocol between TARGET/HOST.
4. Introduced one "try" mechanism to avoid Debug Agent crashed by some invalid HOST command.
5. Enable the late-attach feature: Change the break in from "!" to "\xFC". Add a new short symbol "\xFA" for attach and a new debug command for detach.
6. Support Terminal work on debug port by install EFI Serial IO protocol upon Debug Communication Library.
7. Enable CPUID feature.
8. Enable the hardware data breakpoint.
9. add handshake to improve usb debug cable identify stability issue.
10.Refine all the communication protocol packet to improve extensibility and debugging performance.
  a. Use 64bit for IO port address.
  b. Add additional Width field to READ_MEMORY/WRITE_MEMORY.
  c. Add SEARCH_SIGNATURE support to speed the symbol finding for late attach.
  d. Remove READ_GROUP register.
  e. Add READ_ALL_REGISTERS support (WinDbg always requests to read all registers).
11.Move AcquireDebugPortControl () in advance to fix resource collision on IpiSentByApFlag.
12.Fix IO break point does not work issue in PEI phase.
13.Avoid BSP/APs collision when they met break point at the same time.
14.Solve a bug of calculating debug handle in sec phase.
15.Use mailbox content at Dxe phase but not clear it and reinitialize again.
16.Fix FP/MMX/XMM/IO/MSR access issue in both Gdb and WinDbg.

Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13437 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff
2012-06-11 02:15:11 +00:00
parent 44538ba5aa
commit 93c0bdec28
32 changed files with 2653 additions and 2524 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1280
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
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214
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
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@ -31,6 +31,7 @@
#include <Library/LocalApicLib.h>
#include <Library/DebugLib.h>
#include <Library/TimerLib.h>
#include <Library/PrintLib.h>
#include <TransferProtocol.h>
#include <ImageDebugSupport.h>
@ -39,9 +40,6 @@
#include "DebugTimer.h"
#include "ArchDebugSupport.h"
#define DEBUG_AGENT_REVISION ((0 << 16) | 01)
#define DEBUG_AGENT_CAPABILITIES 0
#define DEBUG_INT1_VECTOR 1
#define DEBUG_INT3_VECTOR 3
#define DEBUG_TIMER_VECTOR 32
@ -55,19 +53,46 @@ extern UINTN Exception0Handle;
extern UINTN TimerInterruptHandle;
extern UINT16 ExceptionStubHeaderSize;
typedef union {
struct {
UINT32 HostPresent : 1;
UINT32 BreakOnNextSmi : 1;
UINT32 Reserved : 30;
} Bits;
UINT32 Uint32;
} DEBUG_AGENT_FLAG;
//
// CPU exception information issued by debug agent
//
typedef struct {
//
// This field is used to save CPU content before executing HOST command
//
BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
//
// This filed returens the exception information issued by HOST command
//
DEBUG_DATA_RESPONSE_GET_EXCEPTION ExceptionContent;
} DEBUG_AGENT_EXCEPTION_BUFFER;
#pragma pack(1)
typedef struct {
//
// Lower 32 bits to store the status of DebugAgent
//
UINT32 HostAttached : 1; // 1: HOST is attached
UINT32 AgentInProgress : 1; // 1: Debug Agent is communicating with HOST
UINT32 MemoryReady : 1; // 1: Memory is ready
UINT32 SteppingFlag : 1; // 1: Agent is running stepping command
UINT32 Reserved1 : 28;
//
// Higher 32bits to control the behavior of DebugAgent
//
UINT32 BreakOnNextSmi : 1; // 1: Break on next SMI
UINT32 PrintErrorLevel : 8; // Bitmask of print error level for debug message
UINT32 Reserved2 : 23;
} DEBUG_AGENT_FLAG;
typedef struct {
DEBUG_AGENT_FLAG DebugFlag;
UINT64 DebugPortHandle;
//
// Pointer to DEBUG_AGENT_EXCEPTION_BUFFER
//
UINT64 ExceptionBufferPointer;
} DEBUG_AGENT_MAILBOX;
#pragma pack()
@ -115,31 +140,11 @@ InitializeDebugIdt (
VOID
);
/**
Write specified register into save CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range
@param[in] Width Data width to read.
@param[in] RegisterBuffer Pointer to input buffer with data.
**/
VOID
ArchWriteRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 Width,
IN UINT8 *RegisterBuffer
);
/**
Read register value from saved CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range
@param[in] Width Data width to read.
@return The address of register value.
@ -149,14 +154,12 @@ UINT8 *
ArchReadRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 *Width
);
/**
Send packet with response data to HOST.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Data Pointer to response data buffer.
@param[in] DataSize Size of response data in byte.
@ -166,121 +169,19 @@ ArchReadRegisterBuffer (
**/
RETURN_STATUS
SendDataResponsePacket (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 *Data,
IN UINT16 DataSize
);
/**
Read segment selector by register index.
Check if HOST is attached based on Mailbox.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterIndex Register Index.
@return Value of segment selector.
**/
UINT64
ReadRegisterSelectorByIndex (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 RegisterIndex
);
/**
Read group register of common registers.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroup Pointer to Group registers.
**/
VOID
ReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
);
/**
Read group register of Segment Base.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegBase Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegBase (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
);
/**
Read gourp register of Segment Limit.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegLim Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegLim (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
);
/**
Read group register by group index.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] GroupIndex Group Index.
@retval RETURN_SUCCESS Read successfully.
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
**/
RETURN_STATUS
ArchReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 GroupIndex
);
/**
Send acknowledge packet to HOST.
@param AckCommand Type of Acknowledge packet.
**/
VOID
SendAckPacket (
IN UINT8 AckCommand
);
/**
Receive acknowledge packet OK from HOST in specified time.
@param[in] Timeout Time out value to wait for acknowlege from HOST.
The unit is microsecond.
@param[out] BreakReceived If BreakReceived is not NULL,
TRUE is retured if break-in symbol received.
FALSE is retured if break-in symbol not received.
@retval RETRUEN_SUCCESS Succeed to receive acknowlege packet from HOST,
the type of acknowlege packet saved in Ack.
@retval RETURN_TIMEOUT Specified timeout value was up.
**/
RETURN_STATUS
WaitForAckPacketOK (
IN UINTN Timeout,
OUT BOOLEAN *BreakReceived OPTIONAL
);
/**
Check if HOST is connected based on Mailbox.
@retval TRUE HOST is connected.
@retval FALSE HOST is not connected.
@retval TRUE HOST is attached.
@retval FALSE HOST is not attached.
**/
BOOLEAN
IsHostConnected (
IsHostAttached (
VOID
);
@ -306,5 +207,40 @@ GetDebugPortHandle (
VOID
);
/**
Read the Attach/Break-in symbols from the debug port.
@param[in] Handle Pointer to Debug Port handle.
@param[out] BreakSymbol Returned break symbol.
@retval EFI_SUCCESS Read the symbol in BreakSymbol.
@retval EFI_NOT_FOUND No read the break symbol.
**/
EFI_STATUS
DebugReadBreakSymbol (
IN DEBUG_PORT_HANDLE Handle,
OUT UINT8 *BreakSymbol
);
/**
Prints a debug message to the debug port if the specified error level is enabled.
If any bit in ErrorLevel is also set in Mainbox, then print the message specified
by Format and the associated variable argument list to the debug port.
@param[in] ErrorLevel The error level of the debug message.
@param[in] Format Format string for the debug message to print.
@param[in] ... Variable argument list whose contents are accessed
based on the format string specified by Format.
**/
VOID
EFIAPI
DebugAgentMsgPrint (
IN UINT8 ErrorLevel,
IN CHAR8 *Format,
...
);
#endif

44
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
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@ -1,7 +1,7 @@
/** @file
Multi-Processor support functions implementation.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -101,7 +101,7 @@ HaltOtherProcessors (
IN UINT32 CurrentProcessorIndex
)
{
DebugAgentMsgPrint (DEBUG_AGENT_INFO, "processor[%x]:Try to halt other processors.\n", CurrentProcessorIndex);
if (!IsBsp (CurrentProcessorIndex)) {
SetIpiSentByApFlag (TRUE);;
}
@ -305,7 +305,7 @@ SetDebugViewPoint (
}
/**
Initialize debug timer.
Set the IPI send by BPS/AP flag.
@param[in] IpiSentByApFlag TRUE means this IPI is sent by AP.
FALSE means this IPI is sent by BSP.
@ -324,7 +324,7 @@ SetIpiSentByApFlag (
}
/**
Check if any processor breaks.
Check the next pending breaking CPU.
@retval others There is at least one processor broken, the minimum
index number of Processor returned.
@ -332,7 +332,7 @@ SetIpiSentByApFlag (
**/
UINT32
FindCpuNotRunning (
FindNextPendingBreakCpu (
VOID
)
{
@ -368,3 +368,37 @@ IsAllCpuRunning (
return TRUE;
}
/**
Check if the current processor is the first breaking processor.
If yes, halt other processors.
@param[in] ProcessorIndex Processor index value.
@return TRUE This processor is the first breaking processor.
@return FALSE This processor is not the first breaking processor.
**/
BOOLEAN
IsFirstBreakProcessor (
IN UINT32 ProcessorIndex
)
{
if (MultiProcessorDebugSupport) {
if (mDebugMpContext.BreakAtCpuIndex != (UINT32) -1) {
//
// The current processor is not the first breaking one.
//
SetCpuBreakFlagByIndex (ProcessorIndex, TRUE);
return FALSE;
} else {
//
// If no any processor breaks, try to halt other processors
//
HaltOtherProcessors (ProcessorIndex);
return TRUE;
}
}
return TRUE;
}

26
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.h
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@ -1,7 +1,7 @@
/** @file
Header file for Multi-Processor support.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -32,7 +32,7 @@ typedef struct {
UINT32 BreakAtCpuIndex; ///< Processor index value of the current breaking CPU
UINT32 DebugTimerInitCount; ///< Record BSP's init timer count
BOOLEAN IpiSentByAp; ///< TRUR: IPI is sent by AP. TALSE: IPI is sent by BSP
BOOLEAN RunCommandSet; ///< TRUE: RUN commmand is not executed. FALSE : RUN command is executed.
BOOLEAN RunCommandSet; ///< TRUE: RUN commmand is executing. FALSE : RUN command has been executed.
} DEBUG_MP_CONTEXT;
extern CONST BOOLEAN MultiProcessorDebugSupport;
@ -181,7 +181,7 @@ SetDebugViewPoint (
);
/**
Initialize debug timer.
Set the IPI send by BPS/AP flag.
@param[in] IpiSentByApFlag TRUE means this IPI is sent by AP.
FALSE means this IPI is sent by BSP.
@ -193,7 +193,7 @@ SetIpiSentByApFlag (
);
/**
Check if any processor breaks.
Check the next pending breaking CPU.
@retval others There is at least one processor broken, the minimum
index number of Processor returned.
@ -201,7 +201,7 @@ SetIpiSentByApFlag (
**/
UINT32
FindCpuNotRunning (
FindNextPendingBreakCpu (
VOID
);
@ -217,5 +217,21 @@ IsAllCpuRunning (
VOID
);
/**
Check if the current processor is the first breaking processor.
If yes, halt other processors.
@param[in] ProcessorIndex Processor index value.
@return TRUE This processor is the first breaking processor.
@return FALSE This processor is not the first breaking processor.
**/
BOOLEAN
IsFirstBreakProcessor (
IN UINT32 ProcessorIndex
);
#endif

195
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ArchDebugSupport.c
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@ -1,7 +1,7 @@
/** @file
Public include file for Debug Port Library.
Supporting functions for IA32 architecture.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -14,188 +14,6 @@
#include "DebugAgent.h"
/**
Read the offset of FP / MMX / XMM registers by register index.
@param[in] Index Register index.
@param[out] Width Register width returned.
@return Offset in register address range.
**/
UINT16
ArchReadFxStatOffset (
IN UINT8 Index,
OUT UINT8 *Width
)
{
if (Index < SOFT_DEBUGGER_REGISTER_ST0) {
switch (Index) {
case SOFT_DEBUGGER_REGISTER_FP_FCW:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fcw);
case SOFT_DEBUGGER_REGISTER_FP_FSW:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Fsw);
case SOFT_DEBUGGER_REGISTER_FP_FTW:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ftw);
case SOFT_DEBUGGER_REGISTER_FP_OPCODE:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Opcode);
case SOFT_DEBUGGER_REGISTER_FP_EIP:
*Width = (UINT8) sizeof (UINTN);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Eip);
case SOFT_DEBUGGER_REGISTER_FP_CS:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Cs);
case SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET:
*Width = (UINT8) sizeof (UINTN);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, DataOffset);
case SOFT_DEBUGGER_REGISTER_FP_DS:
*Width = (UINT8) sizeof (UINT16);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Ds);
case SOFT_DEBUGGER_REGISTER_FP_MXCSR:
*Width = (UINT8) sizeof (UINTN);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr);
case SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK:
*Width = (UINT8) sizeof (UINTN);
return (UINT16)OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, Mxcsr_Mask);
}
}
if (Index < SOFT_DEBUGGER_REGISTER_XMM0) {
*Width = 10;
} else if (Index < SOFT_DEBUGGER_REGISTER_MM0 ) {
*Width = 16;
} else {
*Width = 8;
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
}
return (UINT16)(OFFSET_OF(DEBUG_DATA_IA32_FX_SAVE_STATE, St0Mm0) + (Index - SOFT_DEBUGGER_REGISTER_ST0) * 16);
}
/**
Write specified register into save CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range.
@param[in] Width Data width to read.
@param[in] RegisterBuffer Pointer to input buffer with data.
**/
VOID
ArchWriteRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 Width,
IN UINT8 *RegisterBuffer
)
{
UINT8 *Buffer;
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
} else {
//
// If it is MMX register, adjust its index position
//
if (Index >= SOFT_DEBUGGER_REGISTER_MM0) {
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
}
//
// FPU/MMX/XMM registers
//
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, &Width);
}
CopyMem (Buffer + Offset, RegisterBuffer, Width);
}
/**
Read register value from saved CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range
@param[in] Width Data width to read.
@return The address of register value.
**/
UINT8 *
ArchReadRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 *Width
)
{
UINT8 *Buffer;
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_IA32_FX_SAVE_STATE) + Index * 4;
if (*Width == 0) {
*Width = (UINT8) sizeof (UINTN);
}
} else {
//
// FPU/MMX/XMM registers
//
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, Width);
}
return Buffer;
}
/**
Read group register of common registers.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroup Pointer to Group registers.
**/
VOID
ReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
)
{
RegisterGroup->Cs = (UINT16) CpuContext->Cs;
RegisterGroup->Ds = (UINT16) CpuContext->Ds;
RegisterGroup->Es = (UINT16) CpuContext->Es;
RegisterGroup->Fs = (UINT16) CpuContext->Fs;
RegisterGroup->Gs = (UINT16) CpuContext->Gs;
RegisterGroup->Ss = (UINT16) CpuContext->Ss;
RegisterGroup->Eflags = CpuContext->Eflags;
RegisterGroup->Ebp = CpuContext->Ebp;
RegisterGroup->Eip = CpuContext->Eip;
RegisterGroup->Esp = CpuContext->Esp;
RegisterGroup->Eax = CpuContext->Eax;
RegisterGroup->Ebx = CpuContext->Ebx;
RegisterGroup->Ecx = CpuContext->Ecx;
RegisterGroup->Edx = CpuContext->Edx;
RegisterGroup->Esi = CpuContext->Esi;
RegisterGroup->Edi = CpuContext->Edi;
RegisterGroup->Dr0 = CpuContext->Dr0;
RegisterGroup->Dr1 = CpuContext->Dr1;
RegisterGroup->Dr2 = CpuContext->Dr2;
RegisterGroup->Dr3 = CpuContext->Dr3;
RegisterGroup->Dr6 = CpuContext->Dr6;
RegisterGroup->Dr7 = CpuContext->Dr7;
}
/**
Initialize IDT entries to support source level debug.
@ -237,6 +55,11 @@ InitializeDebugIdt (
InterruptHandler = (UINTN) &TimerInterruptHandle;
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
IdtEntry[Index].Bits.Selector = CodeSegment;
IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
//
// Set DE flag in CR4 to enable IO breakpoint
//
AsmWriteCr4 (AsmReadCr4 () | BIT3);
}

10
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ArchDebugSupport.h
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@ -1,7 +1,7 @@
/** @file
IA32 specific defintions for debug agent library instance.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -15,17 +15,13 @@
#ifndef _ARCH_DEBUG_SUPPORT_H_
#define _ARCH_DEBUG_SUPPORT_H_
#include "ArchRegisters.h"
#include "ProcessorContext.h"
#include "TransferProtocol.h"
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP;
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM;
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE;
#define DEBUG_SW_BREAKPOINT_SYMBOL 0xcc
#define DEBUG_ARCH_SYMBOL DEBUG_DATA_BREAK_CPU_ARCH_IA32
typedef DEBUG_DATA_IA32_FX_SAVE_STATE DEBUG_DATA_FX_SAVE_STATE;
typedef DEBUG_DATA_IA32_SYSTEM_CONTEXT DEBUG_CPU_CONTEXT;
#endif

210
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ArchReadGroupRegister.c
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@ -1,210 +0,0 @@
/** @file
IA32 Group registers read support functions.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "DebugAgent.h"
/**
Read group register of Segment Base.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegBase Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegBase (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINTN Index;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Index = CpuContext->Cs / 8;
RegisterGroupSegBase->CsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Ss / 8;
RegisterGroupSegBase->SsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Gs / 8;
RegisterGroupSegBase->GsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Fs / 8;
RegisterGroupSegBase->FsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Es / 8;
RegisterGroupSegBase->EsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Ds / 8;
RegisterGroupSegBase->DsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
RegisterGroupSegBase->LdtBas = 0;
RegisterGroupSegBase->TssBas = 0;
}
/**
Read gourp register of Segment Limit.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegLim Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegLim (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINTN Index;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Index = CpuContext->Cs / 8;
RegisterGroupSegLim->CsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->CsLim = (RegisterGroupSegLim->CsLim << 12) | 0xfff;
}
Index = CpuContext->Ss / 8;
RegisterGroupSegLim->SsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->SsLim = (RegisterGroupSegLim->SsLim << 12) | 0xfff;
}
Index = CpuContext->Gs / 8;
RegisterGroupSegLim->GsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->GsLim = (RegisterGroupSegLim->GsLim << 12) | 0xfff;
}
Index = CpuContext->Fs / 8;
RegisterGroupSegLim->FsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->FsLim = (RegisterGroupSegLim->FsLim << 12) | 0xfff;
}
Index = CpuContext->Es / 8;
RegisterGroupSegLim->EsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->EsLim = (RegisterGroupSegLim->EsLim << 12) | 0xfff;
}
Index = CpuContext->Ds / 8;
RegisterGroupSegLim->DsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->DsLim = (RegisterGroupSegLim->DsLim << 12) | 0xfff;
}
RegisterGroupSegLim->LdtLim = 0xffff;
RegisterGroupSegLim->TssLim = 0xffff;
}
/**
Read group register by group index.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] GroupIndex Group Index.
@retval RETURN_SUCCESS Read successfully.
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
**/
RETURN_STATUS
ArchReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 GroupIndex
)
{
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP RegisterGroup;
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM RegisterGroupSegLim;
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE RegisterGroupSegBase;
switch (GroupIndex) {
case SOFT_DEBUGGER_REGISTER_GROUP_GPDRS32:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_LIMITS32:
ReadRegisterGroupSegLim (CpuContext, &RegisterGroupSegLim);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupSegLim, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES32:
ReadRegisterGroupSegBase (CpuContext, &RegisterGroupSegBase);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupSegBase, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE));
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Read segment selector by register index.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterIndex Register Index.
@return Value of segment selector.
**/
UINT64
ReadRegisterSelectorByIndex (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 RegisterIndex
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINT16 Selector;
UINT32 Data32;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Selector = 0;
switch (RegisterIndex) {
case SOFT_DEBUGGER_REGISTER_CSAS:
Selector = (UINT16) CpuContext->Cs;
break;
case SOFT_DEBUGGER_REGISTER_SSAS:
Selector = (UINT16) CpuContext->Ss;
break;
case SOFT_DEBUGGER_REGISTER_GSAS:
Selector = (UINT16) CpuContext->Gs;
break;
case SOFT_DEBUGGER_REGISTER_FSAS:
Selector = (UINT16) CpuContext->Fs;
break;
case SOFT_DEBUGGER_REGISTER_ESAS:
Selector = (UINT16) CpuContext->Es;
break;
case SOFT_DEBUGGER_REGISTER_DSAS:
Selector = (UINT16) CpuContext->Ds;
case SOFT_DEBUGGER_REGISTER_LDTAS:
case SOFT_DEBUGGER_REGISTER_TSSAS:
return 0x00820000;
break;
}
Data32 = (UINT32) RShiftU64 (Ia32Gdt[Selector / 8].Uint64, 24);
return (Data32 & (UINT32)(~0xff)) | Selector;
}

160
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/ArchRegisters.h
View File

@ -1,160 +0,0 @@
/** @file
IA32 register defintions needed by debug transfer protocol.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ARCH_REGISTERS_H_
#define _ARCH_REGISTERS_H_
#pragma pack(1)
///
/// FXSAVE_STATE
/// FP / MMX / XMM registers (see fxrstor instruction definition)
///
typedef struct {
UINT16 Fcw;
UINT16 Fsw;
UINT16 Ftw;
UINT16 Opcode;
UINT32 Eip;
UINT16 Cs;
UINT16 Reserved1;
UINT32 DataOffset;
UINT16 Ds;
UINT8 Reserved2[2];
UINT32 Mxcsr;
UINT32 Mxcsr_Mask;
UINT8 St0Mm0[10];
UINT8 Reserved3[6];
UINT8 St1Mm1[10];
UINT8 Reserved4[6];
UINT8 St2Mm2[10];
UINT8 Reserved5[6];
UINT8 St3Mm3[10];
UINT8 Reserved6[6];
UINT8 St4Mm4[10];
UINT8 Reserved7[6];
UINT8 St5Mm5[10];
UINT8 Reserved8[6];
UINT8 St6Mm6[10];
UINT8 Reserved9[6];
UINT8 St7Mm7[10];
UINT8 Reserved10[6];
UINT8 Xmm0[16];
UINT8 Xmm1[16];
UINT8 Xmm2[16];
UINT8 Xmm3[16];
UINT8 Xmm4[16];
UINT8 Xmm5[16];
UINT8 Xmm6[16];
UINT8 Xmm7[16];
UINT8 Reserved11[14 * 16];
} DEBUG_DATA_IA32_FX_SAVE_STATE;
///
/// IA-32 processor context definition
///
typedef struct {
DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;
UINT32 Dr0;
UINT32 Dr1;
UINT32 Dr2;
UINT32 Dr3;
UINT32 Dr6;
UINT32 Dr7;
UINT32 Eflags;
UINT32 Ldtr;
UINT32 Tr;
UINT32 Gdtr[2];
UINT32 Idtr[2];
UINT32 Eip;
UINT32 Gs;
UINT32 Fs;
UINT32 Es;
UINT32 Ds;
UINT32 Cs;
UINT32 Ss;
UINT32 Cr0;
UINT32 Cr1; ///< Reserved
UINT32 Cr2;
UINT32 Cr3;
UINT32 Cr4;
UINT32 Edi;
UINT32 Esi;
UINT32 Ebp;
UINT32 Esp;
UINT32 Edx;
UINT32 Ecx;
UINT32 Ebx;
UINT32 Eax;
} DEBUG_DATA_IA32_SYSTEM_CONTEXT;
///
/// IA32 GROUP register
///
typedef struct {
UINT16 Cs;
UINT16 Ds;
UINT16 Es;
UINT16 Fs;
UINT16 Gs;
UINT16 Ss;
UINT32 Eflags;
UINT32 Ebp;
UINT32 Eip;
UINT32 Esp;
UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
UINT32 Esi;
UINT32 Edi;
UINT32 Dr0;
UINT32 Dr1;
UINT32 Dr2;
UINT32 Dr3;
UINT32 Dr6;
UINT32 Dr7;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;
///
/// IA32 Segment Limit GROUP register
///
typedef struct {
UINT32 CsLim;
UINT32 SsLim;
UINT32 GsLim;
UINT32 FsLim;
UINT32 EsLim;
UINT32 DsLim;
UINT32 LdtLim;
UINT32 TssLim;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;
///
/// IA32 Segment Base GROUP register
///
typedef struct {
UINT32 CsBas;
UINT32 SsBas;
UINT32 GsBas;
UINT32 FsBas;
UINT32 EsBas;
UINT32 DsBas;
UINT32 LdtBas;
UINT32 TssBas;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;
#pragma pack()
#endif

8
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.S
View File

@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -281,6 +281,9 @@ NoExtrPush:
movl %esp,%edi
.byte 0x0f, 0xae, 0x07 # fxsave [edi]
## save the exception data
pushl 8(%esp)
## Clear Direction Flag
cld
@ -290,6 +293,9 @@ NoExtrPush:
call ASM_PFX(InterruptProcess)
addl $8,%esp
## skip the exception data
addl $4,%esp
## FX_SAVE_STATE_IA32 FxSaveState;
movl %esp,%esi
.byte 0x0f, 0xae, 0x0e # fxrstor [esi]

8
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.asm
View File

@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -283,6 +283,9 @@ NoExtrPush:
mov edi, esp
db 0fh, 0aeh, 00000111y ;fxsave [edi]
;; save the exception data
push dword ptr [ebp + 8]
;; Clear Direction Flag
cld
@ -292,6 +295,9 @@ NoExtrPush:
call InterruptProcess
add esp, 8
; skip the exception data
add esp, 4
;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
db 0fh, 0aeh, 00001110y ; fxrstor [esi]

202
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/ArchDebugSupport.c
View File

@ -1,7 +1,7 @@
/** @file
Supporting functions for x64 architecture.
Supporting functions for X64 architecture.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -14,199 +14,6 @@
#include "DebugAgent.h"
/**
Read the offset of FP / MMX / XMM registers by register index.
@param[in] Index Register index.
@param[out] Width Register width returned.
@return Offset in register address range.
**/
UINT16
ArchReadFxStatOffset (
IN UINT8 Index,
OUT UINT8 *Width
)
{
if (Index < SOFT_DEBUGGER_REGISTER_ST0) {
switch (Index) {
case SOFT_DEBUGGER_REGISTER_FP_FCW:
*Width = (UINT8) sizeof (UINT16);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Fcw);
case SOFT_DEBUGGER_REGISTER_FP_FSW:
*Width = (UINT8) sizeof (UINT16);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Fsw);
case SOFT_DEBUGGER_REGISTER_FP_FTW:
*Width = (UINT8) sizeof (UINT16);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Ftw);
case SOFT_DEBUGGER_REGISTER_FP_OPCODE:
*Width = (UINT8) sizeof (UINT16);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Opcode);
case SOFT_DEBUGGER_REGISTER_FP_EIP:
*Width = (UINT8) sizeof (UINTN);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Rip);
case SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET:
*Width = (UINT8) sizeof (UINTN);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, DataOffset);
case SOFT_DEBUGGER_REGISTER_FP_MXCSR:
*Width = (UINT8) sizeof (UINT32);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Mxcsr);
case SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK:
*Width = (UINT8) sizeof (UINT32);
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, Mxcsr_Mask);
default:
return (UINT16) (-1);
}
}
if (Index < SOFT_DEBUGGER_REGISTER_XMM0) {
*Width = 10;
} else if (Index < SOFT_DEBUGGER_REGISTER_MM0 ) {
*Width = 16;
} else {
*Width = 8;
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
}
return OFFSET_OF(DEBUG_DATA_X64_FX_SAVE_STATE, St0Mm0) + (Index - SOFT_DEBUGGER_REGISTER_ST0) * 16;
}
/**
Write specified register into save CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range
@param[in] Width Data width to read.
@param[in] RegisterBuffer Pointer to input buffer with data.
**/
VOID
ArchWriteRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 Width,
IN UINT8 *RegisterBuffer
)
{
UINT8 *Buffer;
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_X64_FX_SAVE_STATE) + Index * 8;
} else {
//
// If it is MMX register, adjust its index position
//
if (Index >= SOFT_DEBUGGER_REGISTER_MM0) {
Index -= SOFT_DEBUGGER_REGISTER_MM0 - SOFT_DEBUGGER_REGISTER_ST0;
}
//
// FPU/MMX/XMM registers
//
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, &Width);
}
CopyMem (Buffer + Offset, RegisterBuffer, Width);
}
/**
Read register value from saved CPU context.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] Index Register index value.
@param[in] Offset Offset in register address range
@param[in] Width Data width to read.
@return The address of register value.
**/
UINT8 *
ArchReadRegisterBuffer (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 Index,
IN UINT8 Offset,
IN UINT8 *Width
)
{
UINT8 *Buffer;
if (Index < SOFT_DEBUGGER_REGISTER_FP_BASE) {
Buffer = (UINT8 *) CpuContext + sizeof (DEBUG_DATA_X64_FX_SAVE_STATE) + Index * 8;
if (*Width == 0) {
*Width = (UINT8) sizeof (UINTN);
}
} else {
//
// FPU/MMX/XMM registers
//
Buffer = (UINT8 *) CpuContext + ArchReadFxStatOffset (Index, Width);
}
return Buffer;
}
/**
Read group register of common registers.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroup Pointer to Group registers.
**/
VOID
ReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP *RegisterGroup
)
{
RegisterGroup->Cs = (UINT16) CpuContext->Cs;
RegisterGroup->Ds = (UINT16) CpuContext->Ds;
RegisterGroup->Es = (UINT16) CpuContext->Es;
RegisterGroup->Fs = (UINT16) CpuContext->Fs;
RegisterGroup->Gs = (UINT16) CpuContext->Gs;
RegisterGroup->Ss = (UINT16) CpuContext->Ss;
RegisterGroup->Eflags = (UINT32) CpuContext->Eflags;
RegisterGroup->Rbp = CpuContext->Rbp;
RegisterGroup->Eip = CpuContext->Eip;
RegisterGroup->Rsp = CpuContext->Rsp;
RegisterGroup->Eax = CpuContext->Rax;
RegisterGroup->Rbx = CpuContext->Rbx;
RegisterGroup->Rcx = CpuContext->Rcx;
RegisterGroup->Rdx = CpuContext->Rdx;
RegisterGroup->Rsi = CpuContext->Rsi;
RegisterGroup->Rdi = CpuContext->Rdi;
RegisterGroup->R8 = CpuContext->R8;
RegisterGroup->R9 = CpuContext->R9;
RegisterGroup->R10 = CpuContext->R10;
RegisterGroup->R11 = CpuContext->R11;
RegisterGroup->R12 = CpuContext->R12;
RegisterGroup->R13 = CpuContext->R13;
RegisterGroup->R14 = CpuContext->R14;
RegisterGroup->R15 = CpuContext->R15;
RegisterGroup->Dr0 = CpuContext->Dr0;
RegisterGroup->Dr1 = CpuContext->Dr1;
RegisterGroup->Dr2 = CpuContext->Dr2;
RegisterGroup->Dr3 = CpuContext->Dr3;
RegisterGroup->Dr6 = CpuContext->Dr6;
RegisterGroup->Dr7 = CpuContext->Dr7;
RegisterGroup->Cr0 = CpuContext->Cr0;
RegisterGroup->Cr2 = CpuContext->Cr2;
RegisterGroup->Cr3 = CpuContext->Cr3;
RegisterGroup->Cr4 = CpuContext->Cr4;
RegisterGroup->Cr8 = CpuContext->Cr8;
CopyMem ((UINT8 *) &RegisterGroup->Xmm0[0], (UINT8 *) &CpuContext->FxSaveState.Xmm0[0], 16 * 10);
}
/**
Initialize IDT entries to support source level debug.
@ -252,4 +59,9 @@ InitializeDebugIdt (
IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
//
// Set DE flag in CR4 to enable IO breakpoint
//
AsmWriteCr4 (AsmReadCr4 () | BIT3);
}

10
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/ArchDebugSupport.h
View File

@ -1,7 +1,7 @@
/** @file
X64 specific defintions for debug agent library instance.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -15,17 +15,13 @@
#ifndef _ARCH_DEBUG_SUPPORT_H_
#define _ARCH_DEBUG_SUPPORT_H_
#include "ArchRegisters.h"
#include "ProcessorContext.h"
#include "TransferProtocol.h"
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP;
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM;
typedef DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64 DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE;
#define DEBUG_SW_BREAKPOINT_SYMBOL 0xcc
#define DEBUG_ARCH_SYMBOL DEBUG_DATA_BREAK_CPU_ARCH_X64
typedef DEBUG_DATA_X64_FX_SAVE_STATE DEBUG_DATA_FX_SAVE_STATE;
typedef DEBUG_DATA_X64_SYSTEM_CONTEXT DEBUG_CPU_CONTEXT;
#endif

259
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/ArchReadGroupRegister.c
View File

@ -1,259 +0,0 @@
/** @file
x64 Group registers read support functions.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "DebugAgent.h"
/**
Read segment selector by register index.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterIndex Register Index.
@return Value of segment selector.
**/
UINT64
ReadRegisterSelectorByIndex (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 RegisterIndex
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINT16 Selector;
UINT32 Data32;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Selector = 0;
switch (RegisterIndex) {
case SOFT_DEBUGGER_REGISTER_CSAS:
Selector = (UINT16) CpuContext->Cs;
break;
case SOFT_DEBUGGER_REGISTER_SSAS:
Selector = (UINT16) CpuContext->Ss;
break;
case SOFT_DEBUGGER_REGISTER_GSAS:
Selector = (UINT16) CpuContext->Gs;
break;
case SOFT_DEBUGGER_REGISTER_FSAS:
Selector = (UINT16) CpuContext->Fs;
break;
case SOFT_DEBUGGER_REGISTER_ESAS:
Selector = (UINT16) CpuContext->Es;
break;
case SOFT_DEBUGGER_REGISTER_DSAS:
Selector = (UINT16) CpuContext->Ds;
case SOFT_DEBUGGER_REGISTER_LDTAS:
case SOFT_DEBUGGER_REGISTER_TSSAS:
return 0x00820000;
break;
}
Data32 = (UINT32) RShiftU64 (Ia32Gdt[Selector / 8].Uint64, 24);
return (Data32 & (UINT32)(~0xff)) | Selector;
}
/**
Read group register of Segment Base.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegBase Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegBase (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *RegisterGroupSegBase
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINTN Index;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Index = CpuContext->Cs / 8;
RegisterGroupSegBase->CsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Ss / 8;
RegisterGroupSegBase->SsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Gs / 8;
RegisterGroupSegBase->GsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Fs / 8;
RegisterGroupSegBase->FsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Es / 8;
RegisterGroupSegBase->EsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
Index = CpuContext->Ds / 8;
RegisterGroupSegBase->DsBas = (Ia32Gdt[Index].Bits.BaseLow) + (Ia32Gdt[Index].Bits.BaseMid << 16) + (Ia32Gdt[Index].Bits.BaseMid << 24);
RegisterGroupSegBase->LdtBas = 0;
RegisterGroupSegBase->TssBas = 0;
}
/**
Read group register of Segment Limit.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] RegisterGroupSegLim Pointer to Group registers.
**/
VOID
ReadRegisterGroupSegLim (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *RegisterGroupSegLim
)
{
IA32_DESCRIPTOR *Ia32Descriptor;
IA32_GDT *Ia32Gdt;
UINTN Index;
Ia32Descriptor = (IA32_DESCRIPTOR *) CpuContext->Gdtr;
Ia32Gdt = (IA32_GDT *) (Ia32Descriptor->Base);
Index = CpuContext->Cs / 8;
RegisterGroupSegLim->CsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->CsLim = (RegisterGroupSegLim->CsLim << 12) | 0xfff;
}
Index = CpuContext->Ss / 8;
RegisterGroupSegLim->SsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->SsLim = (RegisterGroupSegLim->SsLim << 12) | 0xfff;
}
Index = CpuContext->Gs / 8;
RegisterGroupSegLim->GsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->GsLim = (RegisterGroupSegLim->GsLim << 12) | 0xfff;
}
Index = CpuContext->Fs / 8;
RegisterGroupSegLim->FsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->FsLim = (RegisterGroupSegLim->FsLim << 12) | 0xfff;
}
Index = CpuContext->Es / 8;
RegisterGroupSegLim->EsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->EsLim = (RegisterGroupSegLim->EsLim << 12) | 0xfff;
}
Index = CpuContext->Ds / 8;
RegisterGroupSegLim->DsLim = Ia32Gdt[Index].Bits.LimitLow + (Ia32Gdt[Index].Bits.LimitHigh << 16);
if (Ia32Gdt[Index].Bits.Granularity == 1) {
RegisterGroupSegLim->DsLim = (RegisterGroupSegLim->DsLim << 12) | 0xfff;
}
RegisterGroupSegLim->LdtLim = 0xffff;
RegisterGroupSegLim->TssLim = 0xffff;
}
/**
Read group register by group index.
@param[in] CpuContext Pointer to saved CPU context.
@param[in] GroupIndex Group Index.
@retval RETURN_SUCCESS Read successfully.
@retval RETURN_NOT_SUPPORTED Group index cannot be supported.
**/
RETURN_STATUS
ArchReadRegisterGroup (
IN DEBUG_CPU_CONTEXT *CpuContext,
IN UINT8 GroupIndex
)
{
UINTN DataN;
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP RegisterGroup;
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM RegisterGroupBasLim;
DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64 RegisterGroupBases64;
switch (GroupIndex) {
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BAS_LIM64:
DataN = (UINTN) (CpuContext->Idtr[0] & 0xffff);
RegisterGroupBasLim.IdtLim = DataN;
DataN = (UINTN) (CpuContext->Gdtr[0] & 0xffff);
RegisterGroupBasLim.GdtLim = DataN;
DataN = (UINTN) RShiftU64 (CpuContext->Idtr[0], 16);
DataN |= (UINTN) LShiftU64 (CpuContext->Idtr[1], sizeof (UINTN) * 8 - 16);
RegisterGroupBasLim.IdtBas = DataN;
DataN = (UINTN) RShiftU64 (CpuContext->Gdtr[0], 16);
DataN |= (UINTN) LShiftU64 (CpuContext->Gdtr[1], sizeof (UINTN) * 8 - 16);
RegisterGroupBasLim.GdtBas = DataN;
ReadRegisterGroupSegLim (CpuContext, (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM *) &RegisterGroupBasLim.CsLim);
ReadRegisterGroupSegBase (CpuContext, (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE *) &RegisterGroupBasLim.CsBas);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupBasLim, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_GP2_64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Eflags, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_GP64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Eax, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_DR64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr0, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_SEGMENT_BASES64:
RegisterGroupBases64.Ldtr = (UINT16) CpuContext->Ldtr;
RegisterGroupBases64.Tr = (UINT16) CpuContext->Tr;
RegisterGroupBases64.Csas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_CSAS);
RegisterGroupBases64.Ssas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_SSAS);
RegisterGroupBases64.Gsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_GSAS);
RegisterGroupBases64.Fsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_FSAS);
RegisterGroupBases64.Esas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_ESAS);
RegisterGroupBases64.Dsas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_DSAS);
RegisterGroupBases64.Ldtas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_LDTAS);
RegisterGroupBases64.Tssas = ReadRegisterSelectorByIndex (CpuContext, SOFT_DEBUGGER_REGISTER_TSSAS);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroupBases64, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_CR64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr7 + 8, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR));
break;
case SOFT_DEBUGGER_REGISTER_GROUP_XMM64:
ReadRegisterGroup (CpuContext, &RegisterGroup);
SendDataResponsePacket (CpuContext, (UINT8 *) &RegisterGroup.Dr7 + 8 * 6, (UINT16) sizeof (DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM));
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}

332
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/ArchRegisters.h
View File

@ -1,332 +0,0 @@
/** @file
X64 register defintions needed by debug transfer protocol.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ARCH_REGISTERS_H_
#define _ARCH_REGISTERS_H_
#pragma pack(1)
///
/// FXSAVE_STATE (promoted operation)
/// FP / MMX / XMM registers (see fxrstor instruction definition)
///
typedef struct {
UINT16 Fcw;
UINT16 Fsw;
UINT16 Ftw;
UINT16 Opcode;
UINT64 Rip;
UINT64 DataOffset;
UINT32 Mxcsr;
UINT32 Mxcsr_Mask;
UINT8 St0Mm0[10];
UINT8 Reserved2[6];
UINT8 St1Mm1[10];
UINT8 Reserved3[6];
UINT8 St2Mm2[10];
UINT8 Reserved4[6];
UINT8 St3Mm3[10];
UINT8 Reserved5[6];
UINT8 St4Mm4[10];
UINT8 Reserved6[6];
UINT8 St5Mm5[10];
UINT8 Reserved7[6];
UINT8 St6Mm6[10];
UINT8 Reserved8[6];
UINT8 St7Mm7[10];
UINT8 Reserved9[6];
UINT8 Xmm0[16];
UINT8 Xmm1[16];
UINT8 Xmm2[16];
UINT8 Xmm3[16];
UINT8 Xmm4[16];
UINT8 Xmm5[16];
UINT8 Xmm6[16];
UINT8 Xmm7[16];
UINT8 Xmm8[16];
UINT8 Xmm9[16];
UINT8 Xmm10[16];
UINT8 Xmm11[16];
UINT8 Xmm12[16];
UINT8 Xmm13[16];
UINT8 Xmm14[16];
UINT8 Xmm15[16];
UINT8 Reserved11[6 * 16];
} DEBUG_DATA_X64_FX_SAVE_STATE;
///
/// x64 processor context definition
///
typedef struct {
DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState;
UINT64 Dr0;
UINT64 Dr1;
UINT64 Dr2;
UINT64 Dr3;
UINT64 Dr6;
UINT64 Dr7;
UINT64 Eflags;
UINT64 Ldtr;
UINT64 Tr;
UINT64 Gdtr[2];
UINT64 Idtr[2];
UINT64 Eip;
UINT64 Gs;
UINT64 Fs;
UINT64 Es;
UINT64 Ds;
UINT64 Cs;
UINT64 Ss;
UINT64 Cr0;
UINT64 Cr1; /* Reserved */
UINT64 Cr2;
UINT64 Cr3;
UINT64 Cr4;
UINT64 Rdi;
UINT64 Rsi;
UINT64 Rbp;
UINT64 Rsp;
UINT64 Rdx;
UINT64 Rcx;
UINT64 Rbx;
UINT64 Rax;
UINT64 Cr8;
UINT64 R8;
UINT64 R9;
UINT64 R10;
UINT64 R11;
UINT64 R12;
UINT64 R13;
UINT64 R14;
UINT64 R15;
} DEBUG_DATA_X64_SYSTEM_CONTEXT;
///
/// x64 GROUP register
///
typedef struct {
UINT16 Cs;
UINT16 Ds;
UINT16 Es;
UINT16 Fs;
UINT16 Gs;
UINT16 Ss;
UINT32 Eflags;
UINT64 Rbp;
UINT64 Eip;
UINT64 Rsp;
UINT64 Eax;
UINT64 Rbx;
UINT64 Rcx;
UINT64 Rdx;
UINT64 Rsi;
UINT64 Rdi;
UINT64 R8;
UINT64 R9;
UINT64 R10;
UINT64 R11;
UINT64 R12;
UINT64 R13;
UINT64 R14;
UINT64 R15;
UINT64 Dr0;
UINT64 Dr1;
UINT64 Dr2;
UINT64 Dr3;
UINT64 Dr6;
UINT64 Dr7;
UINT64 Cr0;
UINT64 Cr2;
UINT64 Cr3;
UINT64 Cr4;
UINT64 Cr8;
UINT8 Xmm0[16];
UINT8 Xmm1[16];
UINT8 Xmm2[16];
UINT8 Xmm3[16];
UINT8 Xmm4[16];
UINT8 Xmm5[16];
UINT8 Xmm6[16];
UINT8 Xmm7[16];
UINT8 Xmm8[16];
UINT8 Xmm9[16];
UINT8 Xmm10[16];
UINT8 Xmm11[16];
UINT8 Xmm12[16];
UINT8 Xmm13[16];
UINT8 Xmm14[16];
UINT8 Xmm15[16];
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_X64;
///
/// x64 Segment Limit GROUP register
///
typedef struct {
UINT64 CsLim;
UINT64 SsLim;
UINT64 GsLim;
UINT64 FsLim;
UINT64 EsLim;
UINT64 DsLim;
UINT64 LdtLim;
UINT64 TssLim;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_X64;
///
/// x64 Segment Base GROUP register
///
typedef struct {
UINT64 CsBas;
UINT64 SsBas;
UINT64 GsBas;
UINT64 FsBas;
UINT64 EsBas;
UINT64 DsBas;
UINT64 LdtBas;
UINT64 TssBas;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_X64;
///
/// x64 Segment Base/Limit GROUP register
///
typedef struct {
UINT64 IdtBas;
UINT64 IdtLim;
UINT64 GdtBas;
UINT64 GdtLim;
UINT64 CsLim;
UINT64 SsLim;
UINT64 GsLim;
UINT64 FsLim;
UINT64 EsLim;
UINT64 DsLim;
UINT64 LdtLim;
UINT64 TssLim;
UINT64 CsBas;
UINT64 SsBas;
UINT64 GsBas;
UINT64 FsBas;
UINT64 EsBas;
UINT64 DsBas;
UINT64 LdtBas;
UINT64 TssBas;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BAS_LIM;
///
/// x64 register GROUP register
///
typedef struct {
UINT32 Eflags;
UINT64 Rbp;
UINT64 Eip;
UINT64 Rsp;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP2;
///
/// x64 general register GROUP register
///
typedef struct {
UINT64 Eax;
UINT64 Rbx;
UINT64 Rcx;
UINT64 Rdx;
UINT64 Rsi;
UINT64 Rdi;
UINT64 R8;
UINT64 R9;
UINT64 R10;
UINT64 R11;
UINT64 R12;
UINT64 R13;
UINT64 R14;
UINT64 R15;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_GP;
///
/// x64 Segment GROUP register
///
typedef struct {
UINT16 Cs;
UINT16 Ds;
UINT16 Es;
UINT16 Fs;
UINT16 Gs;
UINT16 Ss;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT;
///
/// x64 Debug Register GROUP register
///
typedef struct {
UINT64 Dr0;
UINT64 Dr1;
UINT64 Dr2;
UINT64 Dr3;
UINT64 Dr6;
UINT64 Dr7;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_DR;
///
/// x64 Control Register GROUP register
///
typedef struct {
UINT64 Cr0;
UINT64 Cr2;
UINT64 Cr3;
UINT64 Cr4;
UINT64 Cr8;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_CR;
///
/// x64 XMM Register GROUP register
///
typedef struct {
UINT8 Xmm0[16];
UINT8 Xmm1[16];
UINT8 Xmm2[16];
UINT8 Xmm3[16];
UINT8 Xmm4[16];
UINT8 Xmm5[16];
UINT8 Xmm6[16];
UINT8 Xmm7[16];
UINT8 Xmm8[16];
UINT8 Xmm9[16];
UINT8 Xmm10[16];
UINT8 Xmm11[16];
UINT8 Xmm12[16];
UINT8 Xmm13[16];
UINT8 Xmm14[16];
UINT8 Xmm15[16];
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_XMM;
///
/// x64 Segment Base GROUP register
///
typedef struct {
UINT16 Ldtr;
UINT16 Tr;
UINT64 Csas;
UINT64 Ssas;
UINT64 Gsas;
UINT64 Fsas;
UINT64 Esas;
UINT64 Dsas;
UINT64 Ldtas;
UINT64 Tssas;
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGMENT_BASES_X64;
#pragma pack()
#endif

12
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.S
View File

@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -302,6 +302,9 @@ NoExtrPush:
movq %rsp, %rdi
.byte 0x0f, 0xae, 0b00000111
## save the exception data;
pushq 16(%rbp)
## Clear Direction Flag
cld
@ -313,9 +316,12 @@ NoExtrPush:
# Per X64 calling convention, allocate maximum parameter stack space
# and make sure RSP is 16-byte aligned
#
subq $(4 * 8), %rsp
subq $(32 + 8), %rsp
call ASM_PFX(InterruptProcess)
addq $(4 * 8), %rsp
addq $(32 + 8), %rsp
## skip the exception data;
addq $8, %rsp
## FX_SAVE_STATE_X64 FxSaveState;

18
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.asm
View File

@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -263,9 +263,12 @@ NoExtrPush:
push rax
sub rsp, 512
mov rdi, rsp
mov rdi, rsp
db 0fh, 0aeh, 00000111y ;fxsave [rdi]
;; save the exception data
push qword ptr [rbp + 16]
;; Clear Direction Flag
cld
@ -273,9 +276,16 @@ NoExtrPush:
mov rdx, rsp ; Structure
mov r15, rcx ; save vector in r15
sub rsp, 32
;
; Per X64 calling convention, allocate maximum parameter stack space
; and make sure RSP is 16-byte aligned
;
sub rsp, 32 + 8
call InterruptProcess
add rsp, 32
add rsp, 32 + 8
;; skip the exception data
add rsp, 8
mov rsi, rsp
db 0fh, 0aeh, 00001110y ; fxrstor [rsi]