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ArmPlatformPkg: Tidy Lcd code: Coding standard

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There is no functional modification in this change
As preparation for further work, the formatting is corrected to meet
the EDKII coding standard.
Of specific note, some invalid include guards were fixed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Girish Pathak
2017-09-26 21:15:11 +01:00
committed by Leif Lindholm
parent e10c79145e
commit b1b69d2606
6 changed files with 208 additions and 176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c
View File

@@ -1,6 +1,6 @@
/** @file PL111Lcd.c
/** @file
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -19,13 +19,10 @@
#include "PL111Lcd.h"
/**********************************************************************
*
* This file contains all the bits of the PL111 that are
* platform independent.
*
**********************************************************************/
/** This file contains all the bits of the PL111 that are
platform independent.
**/
EFI_STATUS
LcdIdentify (
VOID
@@ -54,11 +51,11 @@ LcdInitialize (
)
{
// Define start of the VRAM. This never changes for any graphics mode
MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);
MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);
MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
// Disable all interrupts from the PL111
MmioWrite32(PL111_REG_LCD_IMSC, 0);
MmioWrite32 (PL111_REG_LCD_IMSC, 0);
return EFI_SUCCESS;
}
@@ -81,37 +78,54 @@ LcdSetMode (
LCD_BPP LcdBpp;
// Set the video mode timings and other relevant information
Status = LcdPlatformGetTimings (ModeNumber,
&HRes,&HSync,&HBackPorch,&HFrontPorch,
&VRes,&VSync,&VBackPorch,&VFrontPorch);
Status = LcdPlatformGetTimings (
ModeNumber,
&HRes,
&HSync,
&HBackPorch,
&HFrontPorch,
&VRes,
&VSync,
&VBackPorch,
&VFrontPorch
);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR( Status )) {
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR( Status )) {
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
// Disable the CLCD_LcdEn bit
LcdControl = MmioRead32( PL111_REG_LCD_CONTROL);
MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1);
LcdControl = MmioRead32 (PL111_REG_LCD_CONTROL);
MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1);
// Set Timings
MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes));
MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes));
MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes));
MmioWrite32 (
PL111_REG_LCD_TIMING_0,
HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes)
);
MmioWrite32 (
PL111_REG_LCD_TIMING_1,
VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes)
);
MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes));
MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
// PL111_REG_LCD_CONTROL
LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |
PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
// Turn on power to the LCD Panel
LcdControl |= PL111_CTRL_LCD_PWR;
MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
return EFI_SUCCESS;
}