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Add IntelFsp2Pkg and IntelFsp2WrapperPkg.

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Add FSP2.0 support.
This series of patch is to support FSP2.0 specification at
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf

Some major updates include:
1) One FSP binary is separated to multiple components:
FSP-T, FSP-M, FSP-S, and optional FSP-O.
Each component has its own configuration data region.
2) All FSP-APIs use same UPD format - FSP_UPD_HEADER.
3) Add EnumInitPhaseEndOfFirmware notifyphase.
4) FSP1.1/FSP1.0 compatibility is NOT maintained.
5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg,
to indicate that it is for FspWrapper only.

IntelFspPkg and IntelFspWrapperPkg will be deprecated.
The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg
and IntelFsp2WrapperPkg.
The old platform can still use IntelFspPkg and IntelFspWrapperPkg
for compatibility consideration.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
This commit is contained in:
Jiewen Yao
2016-05-13 13:00:53 +08:00
parent c9802c4564
commit cf1d454983
118 changed files with 15633 additions and 0 deletions
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76
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm Normal file
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;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
SECTION .text
;
; Following functions will be provided in C
;
extern ASM_PFX(Loader2PeiSwitchStack)
extern ASM_PFX(FspApiCallingCheck)
;
; Following functions will be provided in ASM
;
extern ASM_PFX(FspApiCommonContinue)
extern ASM_PFX(AsmGetFspInfoHeader)
;----------------------------------------------------------------------------
; FspApiCommon API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
global ASM_PFX(FspApiCommon)
ASM_PFX(FspApiCommon):
;
; EAX holds the API index
;
;
; Stack must be ready
;
push eax
add esp, 4
cmp eax, dword [esp - 4]
jz FspApiCommon1
mov eax, 080000003h
jmp exit
FspApiCommon1:
;
; Verify the calling condition
;
pushad
push DWORD [esp + (4 * 8 + 4)] ; push ApiParam
push eax ; push ApiIdx
call ASM_PFX(FspApiCallingCheck)
add esp, 8
cmp eax, 0
jz FspApiCommon2
mov dword [esp + (4 * 7)], eax
popad
exit:
ret
FspApiCommon2:
popad
cmp eax, 3 ; FspMemoryInit API
jz FspApiCommon3
call ASM_PFX(AsmGetFspInfoHeader)
jmp ASM_PFX(Loader2PeiSwitchStack)
FspApiCommon3:
jmp ASM_PFX(FspApiCommonContinue)

202
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm Normal file
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;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
SECTION .text
;
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
struc FSPM_UPD_COMMON
; FSP_UPD_HEADER {
.FspUpdHeader: resd 8
; }
; FSPM_ARCH_UPD {
.Revision: resb 1
.Reserved: resb 3
.NvsBufferPtr: resd 1
.StackBase: resd 1
.StackSize: resd 1
.BootLoaderTolumSize: resd 1
.BootMode: resd 1
.Reserved1: resb 8
; }
.size:
endstruc
;
; Following functions will be provided in C
;
extern ASM_PFX(SecStartup)
extern ASM_PFX(FspApiCommon)
;
; Following functions will be provided in PlatformSecLib
;
extern ASM_PFX(AsmGetFspBaseAddress)
extern ASM_PFX(AsmGetFspInfoHeader)
API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
FSP_HEADER_CFGREG_OFFSET EQU 24h
;----------------------------------------------------------------------------
; FspMemoryInit API
;
; This FSP API is called after TempRamInit and initializes the memory.
;
;----------------------------------------------------------------------------
global ASM_PFX(FspMemoryInitApi)
ASM_PFX(FspMemoryInitApi):
mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; TempRamExitApi API
;
; This API tears down temporary RAM
;
;----------------------------------------------------------------------------
global ASM_PFX(TempRamExitApi)
ASM_PFX(TempRamExitApi):
mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; FspApiCommonContinue API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
global ASM_PFX(FspApiCommonContinue)
ASM_PFX(FspApiCommonContinue):
;
; EAX holds the API index
;
;
; FspMemoryInit API setup the initial stack frame
;
;
; Place holder to store the FspInfoHeader pointer
;
push eax
;
; Update the FspInfoHeader pointer
;
push eax
call ASM_PFX(AsmGetFspInfoHeader)
mov [esp + 4], eax
pop eax
;
; Create a Task Frame in the stack for the Boot Loader
;
pushfd ; 2 pushf for 4 byte alignment
cli
pushad
; Reserve 8 bytes for IDT save/restore
sub esp, 8
sidt [esp]
; Get Stackbase and StackSize from FSPM_UPD Param
mov edx, [esp + API_PARAM1_OFFSET]
cmp edx, 0
jnz FspStackSetup
; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null
push eax
call ASM_PFX(AsmGetFspInfoHeader)
mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET]
add edx, [eax + FSP_HEADER_CFGREG_OFFSET]
pop eax
FspStackSetup:
mov edi, [edx + FSPM_UPD_COMMON.StackBase]
mov ecx, [edx + FSPM_UPD_COMMON.StackSize]
add edi, ecx
;
; Setup new FSP stack
;
xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size
mov ebx, esp ; Put Stack base + Stack size in ebx
;
; Pass the API Idx to SecStartup
;
push eax
;
; Pass the BootLoader stack to SecStartup
;
push edi
;
; Pass entry point of the PEI core
;
call ASM_PFX(AsmGetFspBaseAddress)
mov edi, eax
call ASM_PFX(AsmGetPeiCoreOffset)
add edi, eax
push edi
;
; Pass BFV into the PEI Core
; It uses relative address to calucate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
; they are different. The code below can handle both cases.
;
call ASM_PFX(AsmGetFspBaseAddress)
push eax
;
; Pass stack base and size into the PEI Core
;
sub ebx, ecx ; Stack base + Stack size - Stack size
push ebx
push ecx
;
; Pass Control into the PEI Core
;
call ASM_PFX(SecStartup)
add esp, 4
exit:
ret
global ASM_PFX(FspPeiCoreEntryOff)
ASM_PFX(FspPeiCoreEntryOff):
;
; This value will be pached by the build script
;
DD 0x12345678
global ASM_PFX(AsmGetPeiCoreOffset)
ASM_PFX(AsmGetPeiCoreOffset):
mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)]
ret
;----------------------------------------------------------------------------
; Module Entrypoint API
;----------------------------------------------------------------------------
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
jmp $

62
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryS.nasm Normal file
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;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
SECTION .text
;
; Following functions will be provided in C
;
extern ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; NotifyPhase API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
global ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi):
mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; FspSiliconInit API
;
; This FSP API initializes the CPU and the chipset including the IO
; controllers in the chipset to enable normal operation of these devices.
;
;----------------------------------------------------------------------------
global ASM_PFX(FspSiliconInitApi)
ASM_PFX(FspSiliconInitApi):
mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; FspApiCommonContinue API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
global ASM_PFX(FspApiCommonContinue)
ASM_PFX(FspApiCommonContinue):
jmp $
ret
;----------------------------------------------------------------------------
; Module Entrypoint API
;----------------------------------------------------------------------------
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
jmp $

469
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm Normal file
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;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
SECTION .text
%include "SaveRestoreSseNasm.inc"
%include "MicrocodeLoadNasm.inc"
;
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
;
; Following functions will be provided in PlatformSecLib
;
extern ASM_PFX(AsmGetFspBaseAddress)
extern ASM_PFX(AsmGetFspInfoHeader)
;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation
extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation
extern ASM_PFX(SecCarInit)
;
; Define the data length that we saved on the stack top
;
DATA_LEN_OF_PER0 EQU 18h
DATA_LEN_OF_MCUD EQU 18h
DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
;
; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid
; build error. This needs to be fixed later on.
;
struc MicrocodeHdr
.MicrocodeHdrVersion: resd 1
.MicrocodeHdrRevision: resd 1
.MicrocodeHdrDate: resd 1
.MicrocodeHdrProcessor: resd 1
.MicrocodeHdrChecksum: resd 1
.MicrocodeHdrLoader: resd 1
.MicrocodeHdrFlags: resd 1
.MicrocodeHdrDataSize: resd 1
.MicrocodeHdrTotalSize: resd 1
.MicrocodeHdrRsvd: resd 3
.size:
endstruc
struc ExtSigHdr
.ExtSigHdrCount: resd 1
.ExtSigHdrChecksum: resd 1
.ExtSigHdrRsvd: resd 3
.size:
endstruc
struc ExtSig
.ExtSigProcessor: resd 1
.ExtSigFlags: resd 1
.ExtSigChecksum: resd 1
.size:
endstruc
struc LoadMicrocodeParams
; FSP_UPD_HEADER {
.FspUpdHeader: resd 8
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd 1
.MicrocodeCodeSize: resd 1
.CodeRegionBase: resd 1
.CodeRegionSize: resd 1
; }
.size:
endstruc
;
; Define SSE macros
;
;
;args 1: ReturnAddress 2:MmxRegister
;
%macro LOAD_MMX_EXT 2
mov esi, %1
movd %2, esi ; save ReturnAddress into MMX
%endmacro
;
;args 1: RoutineLabel 2:MmxRegister
;
%macro CALL_MMX_EXT 2
mov esi, %%ReturnAddress
movd %2, esi ; save ReturnAddress into MMX
jmp %1
%%ReturnAddress:
%endmacro
;
;arg 1:MmxRegister
;
%macro RET_ESI_EXT 1
movd esi, %1 ; move ReturnAddress from MMX to ESI
jmp esi
%endmacro
;
;arg 1:RoutineLabel
;
%macro CALL_MMX 1
CALL_MMX_EXT %1, mm7
%endmacro
%macro RET_ESI 0
RET_ESI_EXT mm7
%endmacro
;
; @todo: The strong/weak implementation does not work.
; This needs to be reviewed later.
;
;------------------------------------------------------------------------------
;
;;global ASM_PFX(SecPlatformInitDefault)
;ASM_PFX(SecPlatformInitDefault):
; ; Inputs:
; ; mm7 -> Return address
; ; Outputs:
; ; eax -> 0 - Successful, Non-zero - Failed.
; ; Register Usage:
; ; eax is cleared and ebp is used for return address.
; ; All others reserved.
;
; ; Save return address to EBP
; movd ebp, mm7
;
; xor eax, eax
;Exit1:
; jmp ebp
;------------------------------------------------------------------------------
global ASM_PFX(LoadMicrocodeDefault)
ASM_PFX(LoadMicrocodeDefault):
; Inputs:
; esp -> LoadMicrocodeParams pointer
; Register Usage:
; esp Preserved
; All others destroyed
; Assumptions:
; No memory available, stack is hard-coded and used for return address
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
;
;
; Save return address to EBP
movd ebp, mm7
cmp esp, 0
jz ParamError
mov eax, dword [esp + 4] ; Parameter pointer
cmp eax, 0
jz ParamError
mov esp, eax
mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
cmp esi, 0
jnz CheckMainHeader
ParamError:
mov eax, 080000002h
jmp Exit2
CheckMainHeader:
; Get processor signature and platform ID from the installed processor
; and save into registers for later use
; ebx = processor signature
; edx = platform ID
mov eax, 1
cpuid
mov ebx, eax
mov ecx, MSR_IA32_PLATFORM_ID
rdmsr
mov ecx, edx
shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits
and ecx, 7h ; platform id at bit[52..50]
mov edx, 1
shl edx, cl
; Current register usage
; esp -> stack with parameters
; esi -> microcode update to check
; ebx = processor signature
; edx = platform ID
; Check for valid microcode header
; Minimal test checking for header version and loader version as 1
mov eax, dword 1
cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax
jne AdvanceFixedSize
cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax
jne AdvanceFixedSize
; Check if signature and plaform ID match
cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]
jne LoadMicrocodeDefault1
test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]
jnz LoadCheck ; Jif signature and platform ID match
LoadMicrocodeDefault1:
; Check if extended header exists
; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
xor eax, eax
cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
je NextMicrocode
cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax
je NextMicrocode
; Then verify total size - sizeof header > data size
mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
sub ecx, MicrocodeHdr.size
cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
jng NextMicrocode ; Jif extended header does not exist
; Set edi -> extended header
mov edi, esi
add edi, MicrocodeHdr.size
add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]
; Get count of extended structures
mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]
; Move pointer to first signature structure
add edi, ExtSigHdr.size
CheckExtSig:
; Check if extended signature and platform ID match
cmp dword [edi + ExtSig.ExtSigProcessor], ebx
jne LoadMicrocodeDefault2
test dword [edi + ExtSig.ExtSigFlags], edx
jnz LoadCheck ; Jif signature and platform ID match
LoadMicrocodeDefault2:
; Check if any more extended signatures exist
add edi, ExtSig.size
loop CheckExtSig
NextMicrocode:
; Advance just after end of this microcode
xor eax, eax
cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax
je LoadMicrocodeDefault3
add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]
jmp CheckAddress
LoadMicrocodeDefault3:
add esi, dword 2048
jmp CheckAddress
AdvanceFixedSize:
; Advance by 4X dwords
add esi, dword 1024
CheckAddress:
; Is valid Microcode start point ?
cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
jz Done
; Is automatic size detection ?
mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
cmp eax, 0ffffffffh
jz LoadMicrocodeDefault4
; Address >= microcode region address + microcode region size?
add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]
cmp esi, eax
jae Done ;Jif address is outside of microcode region
jmp CheckMainHeader
LoadMicrocodeDefault4:
LoadCheck:
; Get the revision of the current microcode update loaded
mov ecx, MSR_IA32_BIOS_SIGN_ID
xor eax, eax ; Clear EAX
xor edx, edx ; Clear EDX
wrmsr ; Load 0 to MSR at 8Bh
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
rdmsr ; Get current microcode signature
; Verify this microcode update is not already loaded
cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
je Continue
LoadMicrocode:
; EAX contains the linear address of the start of the Update Data
; EDX contains zero
; ECX contains 79h (IA32_BIOS_UPDT_TRIG)
; Start microcode load with wrmsr
mov eax, esi
add eax, MicrocodeHdr.size
xor edx, edx
mov ecx, MSR_IA32_BIOS_UPDT_TRIG
wrmsr
mov eax, 1
cpuid
Continue:
jmp NextMicrocode
Done:
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
rdmsr ; Get current microcode signature
xor eax, eax
cmp edx, 0
jnz Exit2
mov eax, 08000000Eh
Exit2:
jmp ebp
global ASM_PFX(EstablishStackFsp)
ASM_PFX(EstablishStackFsp):
;
; Save parameter pointer in edx
;
mov edx, dword [esp + 4]
;
; Enable FSP STACK
;
mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
push dword [edx + 2Ch] ; Code size sizeof(FSPT_UPD_COMMON) + 12
push dword [edx + 28h] ; Code base sizeof(FSPT_UPD_COMMON) + 8
push dword [edx + 24h] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
push dword [edx + 20h] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
;
; Save API entry/exit timestamp into stack
;
push DATA_LEN_OF_PER0 ; Size of the data region
push 30524550h ; Signature of the data region 'PER0'
rdtsc
push edx
push eax
LOAD_EDX
push edx
LOAD_EAX
push eax
;
; Terminator for the data on stack
;
push 0
;
; Set ECX/EDX to the BootLoader temporary memory range
;
mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
mov edx, ecx
add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]
cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.
jb EstablishStackFspSuccess
mov eax, 80000003h ;EFI_UNSUPPORTED
jmp EstablishStackFspExit
EstablishStackFspSuccess:
xor eax, eax
EstablishStackFspExit:
RET_ESI
;----------------------------------------------------------------------------
; TempRamInit API
;
; This FSP API will load the microcode update, enable code caching for the
; region specified by the boot loader and also setup a temporary stack to be
; used till main memory is initialized.
;
;----------------------------------------------------------------------------
global ASM_PFX(TempRamInitApi)
ASM_PFX(TempRamInitApi):
;
; Ensure SSE is enabled
;
ENABLE_SSE
;
; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
;
SAVE_REGS
;
; Save timestamp into XMM6
;
rdtsc
SAVE_EAX
SAVE_EDX
;
; Check Parameter
;
mov eax, dword [esp + 4]
cmp eax, 0
mov eax, 80000002h
jz TempRamInitExit
;
; Sec Platform Init
;
CALL_MMX ASM_PFX(SecPlatformInit)
cmp eax, 0
jnz TempRamInitExit
; Load microcode
LOAD_ESP
CALL_MMX ASM_PFX(LoadMicrocodeDefault)
SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_ESP
CALL_MMX ASM_PFX(SecCarInit)
cmp eax, 0
jnz TempRamInitExit
LOAD_ESP
CALL_MMX ASM_PFX(EstablishStackFsp)
cmp eax, 0
jnz TempRamInitExit
LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
TempRamInitExit:
mov bl, al ; save al data in bl
mov al, 07Fh ; API exit postcode 7f
out 080h, al
mov al, bl ; restore al data from bl
;
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
;
LOAD_REGS
ret
;----------------------------------------------------------------------------
; Module Entrypoint API
;----------------------------------------------------------------------------
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
jmp $

35
IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm Normal file
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;; @file
; Provide FSP helper function.
;
; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
SECTION .text
global ASM_PFX(FspInfoHeaderRelativeOff)
ASM_PFX(FspInfoHeaderRelativeOff):
;
; This value will be pached by the build script
;
DD 0x12345678
global ASM_PFX(AsmGetFspBaseAddress)
ASM_PFX(AsmGetFspBaseAddress):
mov eax, ASM_PFX(AsmGetFspInfoHeader)
sub eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)]
add eax, 0x1C
mov eax, dword [eax]
ret
global ASM_PFX(AsmGetFspInfoHeader)
ASM_PFX(AsmGetFspInfoHeader):
mov eax, ASM_PFX(AsmGetFspInfoHeader)
sub eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)]
ret

78
IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Abstract:
;
;------------------------------------------------------------------------------
SECTION .data
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
ASM_PFX(mFpuControlWord):
dw 0x027F
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
ASM_PFX(mMmxControlWord):
dd 0x01F80
SECTION .text
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
global ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
push ebx
;
; Initialize floating point units
;
finit
fldcw [ASM_PFX(mFpuControlWord)]
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
cpuid
bt edx, 25
jnc Done
;
; Set OSFXSR bit 9 in CR4
;
mov eax, cr4
or eax, BIT9
mov cr4, eax
;
; The processor should support SSE instruction and we can use
; ldmxcsr instruction
;
ldmxcsr [ASM_PFX(mMmxControlWord)]
Done:
pop ebx
ret

16
IntelFsp2Pkg/FspSecCore/Ia32/MicrocodeLoadNasm.inc Normal file
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;; @file
;
;@copyright
; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;;
MSR_IA32_PLATFORM_ID equ 000000017h
MSR_IA32_BIOS_UPDT_TRIG equ 000000079h
MSR_IA32_BIOS_SIGN_ID equ 00000008bh

187
IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Abstract:
;
; Provide macro for register save/restore using SSE registers
;
;------------------------------------------------------------------------------
;
; Define SSE instruction set
;
%ifdef USE_SSE41_FLAG
;
; Define SSE macros using SSE 4.1 instructions
; args 1:XMM, 2:IDX, 3:REG
%macro SXMMN 3
pinsrd %1, %3, (%2 & 3)
%endmacro
;
;args 1:XMM, 2:REG, 3:IDX
;
%macro LXMMN 3
pextrd %2, %1, (%3 & 3)
%endmacro
%else
;
; Define SSE macros using SSE 2 instructions
; args 1:XMM, 2:IDX, 3:REG
%macro SXMMN 3
pinsrw %1, %3, (%2 & 3) * 2
ror %3, 16
pinsrw %1, %3, (%2 & 3) * 2 + 1
rol %3, 16
%endmacro
;
;args 1:XMM, 2:REG, 3:IDX
;
%macro LXMMN 3
pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)
movd %2, %1
pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
%endmacro
%endif
;
; XMM7 to save/restore EBP, EBX, ESI, EDI
;
%macro SAVE_REGS 0
SXMMN xmm7, 0, ebp
SXMMN xmm7, 1, ebx
SXMMN xmm7, 2, esi
SXMMN xmm7, 3, edi
SAVE_ESP
%endmacro
%macro LOAD_REGS 0
LXMMN xmm7, ebp, 0
LXMMN xmm7, ebx, 1
LXMMN xmm7, esi, 2
LXMMN xmm7, edi, 3
LOAD_ESP
%endmacro
;
; XMM6 to save/restore EAX, EDX, ECX, ESP
;
%macro LOAD_EAX 0
LXMMN xmm6, eax, 1
%endmacro
%macro SAVE_EAX 0
SXMMN xmm6, 1, eax
%endmacro
%macro LOAD_EDX 0
LXMMN xmm6, edx, 2
%endmacro
%macro SAVE_EDX 0
SXMMN xmm6, 2, edx
%endmacro
%macro SAVE_ECX 0
SXMMN xmm6, 3, ecx
%endmacro
%macro LOAD_ECX 0
LXMMN xmm6, ecx, 3
%endmacro
%macro SAVE_ESP 0
SXMMN xmm6, 0, esp
%endmacro
%macro LOAD_ESP 0
movd esp, xmm6
%endmacro
;
; XMM5 for calling stack
; arg 1:Entry
%macro CALL_XMM 1
mov esi, %%ReturnAddress
pslldq xmm5, 4
%ifdef USE_SSE41_FLAG
pinsrd xmm5, esi, 0
%else
pinsrw xmm5, esi, 0
ror esi, 16
pinsrw xmm5, esi, 1
%endif
mov esi, %1
jmp esi
%%ReturnAddress:
%endmacro
%macro RET_XMM 0
movd esi, xmm5
psrldq xmm5, 4
jmp esi
%endmacro
%macro ENABLE_SSE 0
;
; Initialize floating point units
;
jmp NextAddress
align 4
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
FpuControlWord DW 027Fh
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
MmxControlWord DD 01F80h
SseError:
;
; Processor has to support SSE
;
jmp SseError
NextAddress:
finit
fldcw [FpuControlWord]
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
cpuid
bt edx, 25
jnc SseError
%ifdef USE_SSE41_FLAG
;
; SSE 4.1 support
;
bt ecx, 19
jnc SseError
%endif
;
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
;
mov eax, cr4
or eax, 00000600h
mov cr4, eax
;
; The processor should support SSE instruction and we can use
; ldmxcsr instruction
;
ldmxcsr [MmxControlWord]
%endmacro

78
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Abstract:
;
; Switch the stack from temporary memory to permanent memory.
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; SecSwitchStack (
; UINT32 TemporaryMemoryBase,
; UINT32 PermenentMemoryBase
; );
;------------------------------------------------------------------------------
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
; Save three register: eax, ebx, ecx
;
push eax
push ebx
push ecx
push edx
;
; !!CAUTION!! this function address's is pushed into stack after
; migration of whole temporary memory, so need save it to permanent
; memory at first!
;
mov ebx, [esp + 20] ; Save the first parameter
mov ecx, [esp + 24] ; Save the second parameter
;
; Save this function's return address into permanent memory at first.
; Then, Fixup the esp point to permanent memory
;
mov eax, esp
sub eax, ebx
add eax, ecx
mov edx, dword [esp] ; copy pushed register's value to permanent memory
mov dword [eax], edx
mov edx, dword [esp + 4]
mov dword [eax + 4], edx
mov edx, dword [esp + 8]
mov dword [eax + 8], edx
mov edx, dword [esp + 12]
mov dword [eax + 12], edx
mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
mov dword [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permanent memory
;
; Fixup the ebp point to permenent memory
;
mov eax, ebp
sub eax, ebx
add eax, ecx
mov ebp, eax ; From now, ebp is pointed to permanent memory
pop edx
pop ecx
pop ebx
pop eax
ret