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UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/

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The patch moves all files under UefiCpuPkg/Include/Register/ to
MdePkg/Include/Register using following detailed approaches:
1. Move UefiCpuPkg/Include/Register/Amd/ to
   MdePkg/Include/Register/Amd folder.
2. Move remaining in UefiCpuPkg/Include/Register/ to
   MdePkg/Include/Register/Intel folder.
3. Create wrapper header files under UefiCpuPkg/Include/Register/
   to include the accordingly files in MdePkg/Include/Register/Intel.
   This is to avoid build break because code in other repos like
   edk2-platform includes the file from UefiCpuPkg.

The wrapper header files will be removed after all consumers code
is updated.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ni, Ray
2019-08-01 17:58:30 +08:00
committed by Eric Dong
parent b3527dedc3
commit e057908f8d
39 changed files with 8194 additions and 8119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

784
MdePkg/Include/Register/Intel/Msr/AtomMsr.h Normal file
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/** @file
MSR Definitions for the Intel(R) Atom(TM) Processor Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __ATOM_MSR_H__
#define __ATOM_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Atom(TM) Processor Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x1C || \
DisplayModel == 0x26 || \
DisplayModel == 0x27 || \
DisplayModel == 0x35 || \
DisplayModel == 0x36 \
) \
)
/**
Shared. Model Specific Platform ID (R).
@param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PLATFORM_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
@endcode
@note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
**/
#define MSR_ATOM_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:8;
///
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
///
UINT32 MaximumQualifiedRatio:5;
UINT32 Reserved2:19;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PLATFORM_ID_REGISTER;
/**
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
processor features; (R) indicates current processor configuration.
@param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 AERR_DriveEnable:1;
///
/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
/// Disabled Always 0.
///
UINT32 BERR_Enable:1;
UINT32 Reserved2:1;
UINT32 Reserved3:1;
///
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
///
UINT32 BINIT_DriverEnable:1;
UINT32 Reserved4:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 AERR_ObservationEnabled:1;
UINT32 Reserved5:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved6:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
///
UINT32 ResetVector:1;
UINT32 Reserved7:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
///
UINT32 APICClusterID:2;
UINT32 Reserved8:2;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
///
UINT32 IntegerBusFrequencyRatio:5;
UINT32 Reserved9:5;
UINT32 Reserved10:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_EBL_CR_POWERON_REGISTER;
/**
Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The From_IP part of the
stack contains pointers to the source instruction . See also: - Last Branch
Record Stack TOS at 1C9H - Section 17.5.
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
/// @}
/**
Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The To_IP part of the
stack contains pointers to the destination instruction.
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
@{
**/
#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
/// @}
/**
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
bus clock speed for processors based on Intel Atom microarchitecture:.
@param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_FSB_FREQ_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
@endcode
@note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
**/
#define MSR_ATOM_FSB_FREQ 0x000000CD
/**
MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 2:0] - Scalable Bus Speed
///
/// Atom Processor Family
/// ---------------------
/// 111B: 083 MHz (FSB 333)
/// 101B: 100 MHz (FSB 400)
/// 001B: 133 MHz (FSB 533)
/// 011B: 167 MHz (FSB 667)
///
/// 133.33 MHz should be utilized if performing calculation with
/// System Bus Speed when encoding is 001B.
/// 166.67 MHz should be utilized if performing calculation with
/// System Bus Speed when
/// encoding is 011B.
///
UINT32 ScalableBusSpeed:3;
UINT32 Reserved1:29;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_FSB_FREQ_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:7;
///
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved2:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved3:8;
UINT32 Reserved4:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_BBL_CR_CTL3_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_PERF_STATUS (0x00000198)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PERF_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
@endcode
@note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
**/
#define MSR_ATOM_PERF_STATUS 0x00000198
/**
MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] Current Performance State Value.
///
UINT32 CurrentPerformanceStateValue:16;
UINT32 Reserved1:16;
UINT32 Reserved2:8;
///
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
/// configured for the processor.
///
UINT32 MaximumBusRatio:5;
UINT32 Reserved3:19;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PERF_STATUS_REGISTER;
/**
Shared.
@param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_ATOM_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_THERM2_CTL_REGISTER;
/**
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
UINT32 Reserved4:1;
///
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
/// the processor to indicate a pending break event within the processor 0
/// = Indicates compatible FERR# signaling behavior This bit must be set
/// to 1 to support XAPIC interrupt model usage.
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 2-2.
///
UINT32 PEBS:1;
///
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
/// thermal sensor indicates that the die temperature is at the
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
/// TM2 will reduce the bus to core ratio and voltage according to the
/// value last written to MSR_THERM2_CTL bits 15:0.
/// When this bit is clear (0, default), the processor does not change
/// the VID signals or the bus to core ratio when the processor enters a
/// thermally managed state. The BIOS must enable this feature if the
/// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
/// not set, this feature is not supported and BIOS must not alter the
/// contents of the TM2 bit location. The processor is operating out of
/// specification if both this bit and the TM1 bit are set to 0.
///
UINT32 TM2:1;
UINT32 Reserved5:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved6:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
///
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
/// (R/WO) When set, this bit causes the following bits to become
/// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
/// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
/// be set before an Enhanced Intel SpeedStep Technology transition is
/// requested. This bit is cleared on reset.
///
UINT32 EISTLock:1;
UINT32 Reserved8:1;
///
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved9:8;
UINT32 Reserved10:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
/**
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
that points to the MSR containing the most recent branch record. See
MSR_LASTBRANCH_0_FROM_IP (at 40H).
@param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
/**
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
@param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
@endcode
@note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_ATOM_LER_FROM_LIP 0x000001DD
/**
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
to the target of the last branch instruction that the processor executed
prior to the last exception that was generated or the last interrupt that
was handled.
@param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
@endcode
@note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_ATOM_LER_TO_LIP 0x000001DE
/**
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
@endcode
@note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
#define MSR_ATOM_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
///
UINT32 Enable:1;
UINT32 Reserved1:31;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_ATOM_PEBS_ENABLE_REGISTER;
/**
Package. Package C2 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C2 Residency Counter. (R/O) Time that this
package is in processor-specific C2 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
/**
Package. Package C4 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C4 Residency Counter. (R/O) Time that this
package is in processor-specific C4 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
/**
Package. Package C6 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C6 Residency Counter. (R/O) Time that this
package is in processor-specific C6 states since last reset. Counts at 1 Mhz
frequency.
@param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
@endcode
@note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
**/
#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
#endif

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/** @file
MSR Definitions for Intel processors based on the Broadwell microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __BROADWELL_MSR_H__
#define __BROADWELL_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Broadwell microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x3D || \
DisplayModel == 0x47 || \
DisplayModel == 0x4F || \
DisplayModel == 0x56 \
) \
)
/**
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Ovf_PMC0.
///
UINT32 Ovf_PMC0:1;
///
/// [Bit 1] Ovf_PMC1.
///
UINT32 Ovf_PMC1:1;
///
/// [Bit 2] Ovf_PMC2.
///
UINT32 Ovf_PMC2:1;
///
/// [Bit 3] Ovf_PMC3.
///
UINT32 Ovf_PMC3:1;
UINT32 Reserved1:28;
///
/// [Bit 32] Ovf_FixedCtr0.
///
UINT32 Ovf_FixedCtr0:1;
///
/// [Bit 33] Ovf_FixedCtr1.
///
UINT32 Ovf_FixedCtr1:1;
///
/// [Bit 34] Ovf_FixedCtr2.
///
UINT32 Ovf_FixedCtr2:1;
UINT32 Reserved2:20;
///
/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
/// Addresses (ToPA).".
///
UINT32 Trace_ToPA_PMI:1;
UINT32 Reserved3:5;
///
/// [Bit 61] Ovf_Uncore.
///
UINT32 Ovf_Uncore:1;
///
/// [Bit 62] Ovf_BufDSSAVE.
///
UINT32 OvfBuf:1;
///
/// [Bit 63] CondChgd.
///
UINT32 CondChgd:1;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
@endcode
@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
/// processor-specific C-state code name (consuming the least power) for
/// the package. The default is set as factory-configured package C-state
/// limit. The following C-state code name encodings are supported: 0000b:
/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
///
UINT32 Limit:4;
UINT32 Reserved1:6;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
UINT32 IO_MWAIT:1;
UINT32 Reserved2:4;
///
/// [Bit 15] CFG Lock (R/WO).
///
UINT32 CFGLock:1;
UINT32 Reserved3:9;
///
/// [Bit 25] C3 State Auto Demotion Enable (R/W).
///
UINT32 C3AutoDemotion:1;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W).
///
UINT32 C1AutoDemotion:1;
///
/// [Bit 27] Enable C3 Undemotion (R/W).
///
UINT32 C3Undemotion:1;
///
/// [Bit 28] Enable C1 Undemotion (R/W).
///
UINT32 C1Undemotion:1;
///
/// [Bit 29] Enable Package C-State Auto-demotion (R/W).
///
UINT32 CStateAutoDemotion:1;
///
/// [Bit 30] Enable Package C-State Undemotion (R/W).
///
UINT32 CStateUndemotion:1;
UINT32 Reserved4:1;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
@endcode
@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum
frequency that hardware will select.
@param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
UINT32 MAX_RATIO:7;
UINT32 Reserved2:1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
UINT32 MIN_RATIO:7;
UINT32 Reserved3:17;
UINT32 Reserved4:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
@endcode
@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639
#endif

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/** @file
MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __GOLDMONT_PLUS_MSR_H__
#define __GOLDMONT_PLUS_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel Atom processors based on the Goldmont plus microarchitecture?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x7A \
) \
)
/**
Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
Sampling (PEBS).".
@param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
@endcode
**/
#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC0.
///
UINT32 Fix_Me_1:1;
///
/// [Bit 1] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC1.
///
UINT32 Fix_Me_2:1;
///
/// [Bit 2] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC2.
///
UINT32 Fix_Me_3:1;
///
/// [Bit 3] Enable PEBS trigger and recording for the programmed event
/// (precise or otherwise) on IA32_PMC3.
///
UINT32 Fix_Me_4:1;
UINT32 Reserved1:28;
///
/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
///
UINT32 Fix_Me_5:1;
///
/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
///
UINT32 Fix_Me_6:1;
///
/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
///
UINT32 Fix_Me_7:1;
UINT32 Reserved2:29;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
/**
Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
the first entry of the 32-entry LBR stack. The From_IP part of the stack
contains pointers to the source instruction. See also: - Last Branch Record
Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and
.. Exception Recording for Processors based on Goldmont Plus
Microarchitecture.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F
/**
Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
the first entry of the 32-entry LBR stack. The To_IP part of the stack
contains pointers to the Destination instruction. See also: - Section 17.7,
"Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
based on Goldmont Plus Microarchitecture.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF
/**
Core. Last Branch Record N Additional Information (R/W) One of the three
MSRs that make up the first entry of the 32-entry LBR stack. This part of
the stack contains flag and elapsed cycle information. See also: - Last
Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".
@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
@endcode
**/
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF
#endif

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/** @file
MSR Definitions for Pentium M Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __PENTIUM_M_MSR_H__
#define __PENTIUM_M_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Pentium M Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0D \
) \
)
/**
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
/**
Processor Hard Power-On Configuration (R/W) Enables and disables processor
features. (R) Indicates current processor configuration.
@param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:1;
///
/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
/// Pentium M processor.
///
UINT32 DataErrorCheckingEnable:1;
///
/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 ResponseErrorCheckingEnable:1;
///
/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 MCERR_DriveEnable:1;
///
/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
UINT32 AddressParityEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
/// the Pentium M processor.
///
UINT32 BINIT_DriverEnable:1;
///
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 OutputTriStateEnable:1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
UINT32 ExecuteBIST:1;
///
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 MCERR_ObservationEnabled:1;
UINT32 Reserved3:1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
UINT32 BINIT_ObservationEnabled:1;
UINT32 Reserved4:1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
/// Always 0 on the Pentium M processor.
///
UINT32 ResetVector:1;
UINT32 Reserved5:1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
/// processor.
///
UINT32 APICClusterID:2;
///
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
/// 0 on the Pentium M processor.
///
UINT32 SystemBusFrequency:1;
UINT32 Reserved6:1;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
/// M processor.
///
UINT32 SymmetricArbitrationID:2;
///
/// [Bits 26:22] Clock Frequency Ratio (R/O).
///
UINT32 ClockFrequencyRatio:5;
UINT32 Reserved7:5;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
/**
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
@{
**/
#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
/// @}
/**
Reserved.
@param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
/**
@param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
UINT32 L2HardwareEnabled:1;
UINT32 Reserved1:4;
///
/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
/// cache data bus. ECC is always generated on write cycles. 1. = Disabled
/// (default) 2. = Enabled For the Pentium M processor, ECC checking on
/// the cache data bus is always enabled.
///
UINT32 ECCCheckEnable:1;
UINT32 Reserved2:2;
///
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
UINT32 L2Enabled:1;
UINT32 Reserved3:14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
UINT32 L2NotPresent:1;
UINT32 Reserved4:8;
UINT32 Reserved5:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
/**
@param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
/// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
///
UINT32 TM_SELECT:1;
UINT32 Reserved2:15;
UINT32 Reserved3:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
/**
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
<b>Example usage</b>
@code
MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1:3;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
/// Intel Thermal Monitor feature. This allows processor clocks to be
/// automatically modulated based on the processor's thermal sensor
/// operation. 0 = Disabled (default). The automatic thermal control
/// circuit enable bit determines if the thermal control circuit (TCC)
/// will be activated when the processor's internal thermal sensor
/// determines the processor is about to exceed its maximum operating
/// temperature. When the TCC is activated and TM1 is enabled, the
/// processors clocks will be forced to a 50% duty cycle. BIOS must enable
/// this feature. The bit should not be confused with the on-demand
/// thermal control circuit enable bit.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:2;
///
/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
/// processor to indicate a pending break event within the processor 0 =
/// Indicates compatible FERR# signaling behavior This bit must be set to
/// 1 to support XAPIC interrupt model usage.
/// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported
///
UINT32 FERR:1;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO)
/// 1 = Processor doesn't support branch trace storage (BTS)
/// 0 = BTS is supported
///
UINT32 BTS:1;
///
/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
/// Processor does not support processor event based sampling (PEBS); 0 =
/// PEBS is supported. The Pentium M processor does not support PEBS.
///
UINT32 PEBS:1;
UINT32 Reserved5:3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
/// processor, this bit may be configured to be read-only.
///
UINT32 EIST:1;
UINT32 Reserved6:6;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. The default is processor
/// specific.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
/**
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
to the MSR containing the most recent branch record. See also: -
MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
and Exception Recording (Pentium M Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
@endcode
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
/**
Debug Control (R/W) Controls how several debug features are used. Bit
definitions are discussed in the referenced section. See Section 17.15,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
@endcode
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
**/
#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
/**
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
@endcode
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
/**
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
@endcode
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
**/
#define MSR_PENTIUM_M_MC3_CTL 0x00000410
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
**/
#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in the processor, all
reads and writes to this MSR will cause a general-protection exception.
@param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
@endcode
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
#endif

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/** @file
MSR Definitions for Pentium Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __PENTIUM_MSR_H__
#define __PENTIUM_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Pentium Processors?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x05 && \
( \
DisplayModel == 0x01 || \
DisplayModel == 0x02 || \
DisplayModel == 0x04 \
) \
)
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
@endcode
@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
/**
See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
@endcode
@note MSR_PENTIUM_TSC is defined as TSC in SDM.
**/
#define MSR_PENTIUM_TSC 0x00000010
/**
See Section 18.6.9.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
@endcode
@note MSR_PENTIUM_CESR is defined as CESR in SDM.
**/
#define MSR_PENTIUM_CESR 0x00000011
/**
Section 18.6.9.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
@endcode
@note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
@{
**/
#define MSR_PENTIUM_CTR0 0x00000012
#define MSR_PENTIUM_CTR1 0x00000013
/// @}
#endif

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/** @file
MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __XEON_5600_MSR_H__
#define __XEON_5600_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor Series 5600?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x25 || \
DisplayModel == 0x2C \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
@endcode
@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
UINT32 Maximum1C:8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
UINT32 Maximum2C:8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
UINT32 Maximum3C:8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
UINT32 Maximum4C:8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
UINT32 Maximum5C:8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
UINT32 Maximum6C:8;
UINT32 Reserved:16;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
/**
Package. See Table 2-2.
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
@endcode
@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0
#endif

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/** @file
MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __XEON_E7_MSR_H__
#define __XEON_E7_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor E7 Family?
@param DisplayFamily Display Family ID
@param DisplayModel Display Model ID
@retval TRUE Yes, it is.
@retval FALSE No, it isn't.
**/
#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x2F \
) \
)
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
<b>Example usage</b>
@code
MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
@endcode
@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
/// MSR, the configuration of AES instruction set availability is as
/// follows: 11b: AES instructions are not available until next RESET.
/// otherwise, AES instructions are available. Note, AES instruction set
/// is not available if read is unsuccessful. If the configuration is not
/// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
UINT32 AESConfiguration:2;
UINT32 Reserved1:30;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
/**
Thread. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
@endcode
@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
/**
Package. Reserved Attempt to read/write will cause #UD.
@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
@endcode
@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
/**
Package. Uncore C-box 8 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
/**
Package. Uncore C-box 8 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
/**
Package. Uncore C-box 8 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
/**
Package. Uncore C-box 8 perfmon event select MSR.
@param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
/// @}
/**
Package. Uncore C-box 8 perfmon counter MSR.
@param ECX MSR_XEON_E7_C8_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
/// @}
/**
Package. Uncore C-box 9 perfmon local box control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
/**
Package. Uncore C-box 9 perfmon local box status MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
/**
Package. Uncore C-box 9 perfmon local box overflow control MSR.
@param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
**/
#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
/**
Package. Uncore C-box 9 perfmon event select MSR.
@param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
/// @}
/**
Package. Uncore C-box 9 perfmon counter MSR.
@param ECX MSR_XEON_E7_C9_PMON_CTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
@endcode
@note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
@{
**/
#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB
/// @}
#endif

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MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h Normal file
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