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UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/

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The patch moves all files under UefiCpuPkg/Include/Register/ to
MdePkg/Include/Register using following detailed approaches:
1. Move UefiCpuPkg/Include/Register/Amd/ to
   MdePkg/Include/Register/Amd folder.
2. Move remaining in UefiCpuPkg/Include/Register/ to
   MdePkg/Include/Register/Intel folder.
3. Create wrapper header files under UefiCpuPkg/Include/Register/
   to include the accordingly files in MdePkg/Include/Register/Intel.
   This is to avoid build break because code in other repos like
   edk2-platform includes the file from UefiCpuPkg.

The wrapper header files will be removed after all consumers code
is updated.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ni, Ray
2019-08-01 17:58:30 +08:00
committed by Eric Dong
parent b3527dedc3
commit e057908f8d
39 changed files with 8194 additions and 8119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

0
UefiCpuPkg/Include/Register/Amd/Cpuid.h → MdePkg/Include/Register/Amd/Cpuid.h
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0
UefiCpuPkg/Include/Register/Amd/Fam17Msr.h → MdePkg/Include/Register/Amd/Fam17Msr.h
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4
UefiCpuPkg/Include/Register/Amd/Msr.h → MdePkg/Include/Register/Amd/Msr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
Copyright (c) 2017 - 2019, Advanced Micro Devices. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -17,7 +17,7 @@
#ifndef __AMD_MSR_H__
#define __AMD_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
#include <Register/Amd/Fam17Msr.h>
#endif

6572
MdePkg/Include/Register/Intel/ArchitecturalMsr.h Normal file
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File diff suppressed because it is too large Load Diff

183
MdePkg/Include/Register/Intel/LocalApic.h Normal file
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@ -0,0 +1,183 @@
/** @file
IA32 Local APIC Definitions.
Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __INTEL_LOCAL_APIC_H__
#define __INTEL_LOCAL_APIC_H__
//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
#define XAPIC_VERSION_OFFSET 0x30
#define XAPIC_EOI_OFFSET 0x0b0
#define XAPIC_ICR_DFR_OFFSET 0x0e0
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
#define XAPIC_ICR_LOW_OFFSET 0x300
#define XAPIC_ICR_HIGH_OFFSET 0x310
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
#define X2APIC_MSR_BASE_ADDRESS 0x800
#define X2APIC_MSR_ICR_ADDRESS 0x830
#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define LOCAL_APIC_DELIVERY_MODE_SMI 2
#define LOCAL_APIC_DELIVERY_MODE_NMI 4
#define LOCAL_APIC_DELIVERY_MODE_INIT 5
#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
//
// Local APIC Version Register.
//
typedef union {
struct {
UINT32 Version:8; ///< The version numbers of the local APIC.
UINT32 Reserved0:8; ///< Reserved.
UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
UINT32 Reserved1:7; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_VERSION;
//
// Low half of Interrupt Command Register (ICR).
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 Reserved0:1; ///< Reserved.
UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
UINT32 Reserved1:2; ///< Reserved.
UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
UINT32 Reserved2:12; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_ICR_LOW;
//
// High half of Interrupt Command Register (ICR)
//
typedef union {
struct {
UINT32 Reserved0:24; ///< Reserved.
UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
} Bits;
UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
} LOCAL_APIC_ICR_HIGH;
//
// Spurious-Interrupt Vector Register (SVR)
//
typedef union {
struct {
UINT32 SpuriousVector:8; ///< Spurious Vector.
UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
UINT32 Reserved0:2; ///< Reserved.
UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
UINT32 Reserved1:19; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_SVR;
//
// Divide Configuration Register (DCR)
//
typedef union {
struct {
UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
UINT32 Reserved0:1; ///< Always 0.
UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
UINT32 Reserved1:28; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_DCR;
//
// LVT Timer Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 Reserved0:4; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 Reserved1:3; ///< Reserved.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
UINT32 Reserved2:14; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_TIMER;
//
// LVT LINT0/LINT1 Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:1; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
UINT32 TriggerMode:1; ///< 0:edge, 1:level.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 Reserved1:15; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_LINT;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Reserved0:2; ///< Reserved
UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
UINT32 Reserved1:8; ///< Reserved.
UINT32 DestinationId:8; ///< Specifies the Destination ID.
UINT32 BaseAddress:12; ///< Must be 0FEEH
} Bits;
UINT32 Uint32;
} LOCAL_APIC_MSI_ADDRESS;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:3; ///< Reserved.
UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
UINT32 Reserved1:16; ///< Reserved.
UINT32 Reserved2:32; ///< Reserved.
} Bits;
UINT64 Uint64;
} LOCAL_APIC_MSI_DATA;
#endif

194
MdePkg/Include/Register/Intel/Microcode.h Normal file
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@ -0,0 +1,194 @@
/** @file
Microcode Definitions.
Microcode Definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3A, Section 9.11 Microcode Definitions
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
**/
#ifndef __INTEL_MICROCODE_H__
#define __INTEL_MICROCODE_H__
///
/// CPU Microcode Date in BCD format
///
typedef union {
struct {
UINT32 Year:16;
UINT32 Day:8;
UINT32 Month:8;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_DATE;
///
/// CPU Microcode Processor Signature format
///
typedef union {
struct {
UINT32 Stepping:4;
UINT32 Model:4;
UINT32 Family:4;
UINT32 Type:2;
UINT32 Reserved1:2;
UINT32 ExtendedModel:4;
UINT32 ExtendedFamily:8;
UINT32 Reserved2:4;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_PROCESSOR_SIGNATURE;
#pragma pack (1)
///
/// Microcode Update Format definition
///
typedef struct {
///
/// Version number of the update header
///
UINT32 HeaderVersion;
///
/// Unique version number for the update, the basis for the update
/// signature provided by the processor to indicate the current update
/// functioning within the processor. Used by the BIOS to authenticate
/// the update and verify that the processor loads successfully. The
/// value in this field cannot be used for processor stepping identification
/// alone. This is a signed 32-bit number.
///
UINT32 UpdateRevision;
///
/// Date of the update creation in binary format: mmddyyyy (e.g.
/// 07/18/98 is 07181998H).
///
CPU_MICROCODE_DATE Date;
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Checksum of Update Data and Header. Used to verify the integrity of
/// the update header and data. Checksum is correct when the
/// summation of all the DWORDs (including the extended Processor
/// Signature Table) that comprise the microcode update result in
/// 00000000H.
///
UINT32 Checksum;
///
/// Version number of the loader program needed to correctly load this
/// update. The initial version is 00000001H
///
UINT32 LoaderRevision;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlags;
///
/// Specifies the size of the encrypted data in bytes, and must be a
/// multiple of DWORDs. If this value is 00000000H, then the microcode
/// update encrypted data is 2000 bytes (or 500 DWORDs).
///
UINT32 DataSize;
///
/// Specifies the total size of the microcode update in bytes. It is the
/// summation of the header size, the encrypted data size and the size of
/// the optional extended signature table. This value is always a multiple
/// of 1024.
///
UINT32 TotalSize;
///
/// Reserved fields for future expansion.
///
UINT8 Reserved[12];
} CPU_MICROCODE_HEADER;
///
/// Extended Signature Table Header Field Definitions
///
typedef struct {
///
/// Specifies the number of extended signature structures (Processor
/// Signature[n], processor flags[n] and checksum[n]) that exist in this
/// microcode update
///
UINT32 ExtendedSignatureCount;
///
/// Checksum of update extended processor signature table. Used to
/// verify the integrity of the extended processor signature table.
/// Checksum is correct when the summation of the DWORDs that
/// comprise the extended processor signature table results in
/// 00000000H.
///
UINT32 ExtendedChecksum;
///
/// Reserved fields.
///
UINT8 Reserved[12];
} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
///
/// Extended Signature Table Field Definitions
///
typedef struct {
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlag;
///
/// Used by utility software to decompose a microcode update into
/// multiple microcode updates where each of the new updates is
/// constructed without the optional Extended Processor Signature
/// Table.
/// To calculate the Checksum, substitute the Primary Processor
/// Signature entry and the Processor Flags entry with the
/// corresponding Extended Patch entry. Delete the Extended Processor
/// Signature Table entries. The Checksum is correct when the
/// summation of all DWORDs that comprise the created Extended
/// Processor Patch results in 00000000H.
///
UINT32 Checksum;
} CPU_MICROCODE_EXTENDED_TABLE;
#pragma pack ()
#endif

44
MdePkg/Include/Register/Intel/Msr.h Normal file
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@ -0,0 +1,44 @@
/** @file
MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 ~ 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __INTEL_MSR_H__
#define __INTEL_MSR_H__
#include <Register/Intel/ArchitecturalMsr.h>
#include <Register/Intel/Msr/Core2Msr.h>
#include <Register/Intel/Msr/AtomMsr.h>
#include <Register/Intel/Msr/SilvermontMsr.h>
#include <Register/Intel/Msr/GoldmontMsr.h>
#include <Register/Intel/Msr/GoldmontPlusMsr.h>
#include <Register/Intel/Msr/NehalemMsr.h>
#include <Register/Intel/Msr/Xeon5600Msr.h>
#include <Register/Intel/Msr/XeonE7Msr.h>
#include <Register/Intel/Msr/SandyBridgeMsr.h>
#include <Register/Intel/Msr/IvyBridgeMsr.h>
#include <Register/Intel/Msr/HaswellMsr.h>
#include <Register/Intel/Msr/HaswellEMsr.h>
#include <Register/Intel/Msr/BroadwellMsr.h>
#include <Register/Intel/Msr/XeonDMsr.h>
#include <Register/Intel/Msr/SkylakeMsr.h>
#include <Register/Intel/Msr/XeonPhiMsr.h>
#include <Register/Intel/Msr/Pentium4Msr.h>
#include <Register/Intel/Msr/CoreMsr.h>
#include <Register/Intel/Msr/PentiumMMsr.h>
#include <Register/Intel/Msr/P6Msr.h>
#include <Register/Intel/Msr/PentiumMsr.h>
#endif

4
UefiCpuPkg/Include/Register/Msr/AtomMsr.h → MdePkg/Include/Register/Intel/Msr/AtomMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __ATOM_MSR_H__
#define __ATOM_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Atom(TM) Processor Family?

4
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h → MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __BROADWELL_MSR_H__
#define __BROADWELL_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Broadwell microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/Core2Msr.h → MdePkg/Include/Register/Intel/Msr/Core2Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __CORE2_MSR_H__
#define __CORE2_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Core(TM) 2 Processor Family?

4
UefiCpuPkg/Include/Register/Msr/CoreMsr.h → MdePkg/Include/Register/Intel/Msr/CoreMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __CORE_MSR_H__
#define __CORE_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel Core Solo and Intel Core Duo Processors?

4
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h → MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __GOLDMONT_MSR_H__
#define __GOLDMONT_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel Atom processors based on the Goldmont microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h → MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h
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@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __GOLDMONT_PLUS_MSR_H__
#define __GOLDMONT_PLUS_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel Atom processors based on the Goldmont plus microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h → MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __HASWELL_E_MSR_H__
#define __HASWELL_E_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Haswell-E microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h → MdePkg/Include/Register/Intel/Msr/HaswellMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __HASWELL_MSR_H__
#define __HASWELL_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Haswell microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h → MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __IVY_BRIDGE_MSR_H__
#define __IVY_BRIDGE_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Ivy Bridge microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h → MdePkg/Include/Register/Intel/Msr/NehalemMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __NEHALEM_MSR_H__
#define __NEHALEM_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Nehalem microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/P6Msr.h → MdePkg/Include/Register/Intel/Msr/P6Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __P6_MSR_H__
#define __P6_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is P6 Family Processors?

4
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h → MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __PENTIUM_4_MSR_H__
#define __PENTIUM_4_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Pentium(R) 4 Processors?

4
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h → MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __PENTIUM_M_MSR_H__
#define __PENTIUM_M_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Pentium M Processors?

4
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h → MdePkg/Include/Register/Intel/Msr/PentiumMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __PENTIUM_MSR_H__
#define __PENTIUM_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Pentium Processors?

4
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h → MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __SANDY_BRIDGE_MSR_H__
#define __SANDY_BRIDGE_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Sandy Bridge microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h → MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __SILVERMONT_MSR_H__
#define __SILVERMONT_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Silvermont microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h → MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __SKYLAKE_MSR_H__
#define __SKYLAKE_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel processors based on the Skylake microarchitecture?

4
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h → MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __XEON_5600_MSR_H__
#define __XEON_5600_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor Series 5600?

4
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h → MdePkg/Include/Register/Intel/Msr/XeonDMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __XEON_D_MSR_H__
#define __XEON_D_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor D product Family?

4
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h → MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __XEON_E7_MSR_H__
#define __XEON_E7_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Processor E7 Family?

4
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h → MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -18,7 +18,7 @@
#ifndef __XEON_PHI_MSR_H__
#define __XEON_PHI_MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Intel/ArchitecturalMsr.h>
/**
Is Intel(R) Xeon(R) Phi(TM) processor Family?

184
MdePkg/Include/Register/Intel/SmramSaveStateMap.h Normal file
View File

@ -0,0 +1,184 @@
/** @file
SMRAM Save State Map Definitions.
SMRAM Save State Map definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3C, Section 34.4 SMRAM
Volume 3C, Section 34.5 SMI Handler Execution Environment
Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __INTEL_SMRAM_SAVE_STATE_MAP_H__
#define __INTEL_SMRAM_SAVE_STATE_MAP_H__
///
/// Default SMBASE address
///
#define SMM_DEFAULT_SMBASE 0x30000
///
/// Offset of SMM handler from SMBASE
///
#define SMM_HANDLER_OFFSET 0x8000
///
/// Offset of SMRAM Save State Map from SMBASE
///
#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00
#pragma pack (1)
///
/// 32-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved[0x200]; // 7c00h
// Padded an extra 0x200 bytes so 32-bit and 64-bit
// SMRAM Save State Maps are the same size
UINT8 Reserved1[0xf8]; // 7e00h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved2[0x9C]; // 7f08h
UINT32 IOMemAddr; // 7fa0h
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS; // 7fach
UINT32 _SS; // 7fb0h
UINT32 _DS; // 7fb4h
UINT32 _FS; // 7fb8h
UINT32 _GS; // 7fbch
UINT32 Reserved3; // 7fc0h
UINT32 _TR; // 7fc4h
UINT32 _DR7; // 7fc8h
UINT32 _DR6; // 7fcch
UINT32 _EAX; // 7fd0h
UINT32 _ECX; // 7fd4h
UINT32 _EDX; // 7fd8h
UINT32 _EBX; // 7fdch
UINT32 _ESP; // 7fe0h
UINT32 _EBP; // 7fe4h
UINT32 _ESI; // 7fe8h
UINT32 _EDI; // 7fech
UINT32 _EIP; // 7ff0h
UINT32 _EFLAGS; // 7ff4h
UINT32 _CR3; // 7ff8h
UINT32 _CR0; // 7ffch
} SMRAM_SAVE_STATE_MAP32;
///
/// 64-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved1[0x1d0]; // 7c00h
UINT32 GdtBaseHiDword; // 7dd0h
UINT32 LdtBaseHiDword; // 7dd4h
UINT32 IdtBaseHiDword; // 7dd8h
UINT8 Reserved2[0xc]; // 7ddch
UINT64 IO_EIP; // 7de8h
UINT8 Reserved3[0x50]; // 7df0h
UINT32 _CR4; // 7e40h
UINT8 Reserved4[0x48]; // 7e44h
UINT32 GdtBaseLoDword; // 7e8ch
UINT32 Reserved5; // 7e90h
UINT32 IdtBaseLoDword; // 7e94h
UINT32 Reserved6; // 7e98h
UINT32 LdtBaseLoDword; // 7e9ch
UINT8 Reserved7[0x38]; // 7ea0h
UINT64 EptVmxControl; // 7ed8h
UINT32 EnEptVmxControl; // 7ee0h
UINT8 Reserved8[0x14]; // 7ee4h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved9[0x18]; // 7f04h
UINT64 _R15; // 7f1ch
UINT64 _R14;
UINT64 _R13;
UINT64 _R12;
UINT64 _R11;
UINT64 _R10;
UINT64 _R9;
UINT64 _R8;
UINT64 _RAX; // 7f5ch
UINT64 _RCX;
UINT64 _RDX;
UINT64 _RBX;
UINT64 _RSP;
UINT64 _RBP;
UINT64 _RSI;
UINT64 _RDI;
UINT64 IOMemAddr; // 7f9ch
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS;
UINT32 _SS;
UINT32 _DS;
UINT32 _FS;
UINT32 _GS;
UINT32 _LDTR; // 7fc0h
UINT32 _TR;
UINT64 _DR7; // 7fc8h
UINT64 _DR6;
UINT64 _RIP; // 7fd8h
UINT64 IA32_EFER; // 7fe0h
UINT64 _RFLAGS; // 7fe8h
UINT64 _CR3; // 7ff0h
UINT64 _CR0; // 7ff8h
} SMRAM_SAVE_STATE_MAP64;
///
/// Union of 32-bit and 64-bit SMRAM Save State Maps
///
typedef union {
SMRAM_SAVE_STATE_MAP32 x86;
SMRAM_SAVE_STATE_MAP64 x64;
} SMRAM_SAVE_STATE_MAP;
///
/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
///
#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004
///
/// SMRAM Save State Map IOMisc I/O Length Values
///
#define SMM_IO_LENGTH_BYTE 0x01
#define SMM_IO_LENGTH_WORD 0x02
#define SMM_IO_LENGTH_DWORD 0x04
///
/// SMRAM Save State Map IOMisc I/O Instruction Type Values
///
#define SMM_IO_TYPE_IN_IMMEDIATE 0x9
#define SMM_IO_TYPE_IN_DX 0x1
#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8
#define SMM_IO_TYPE_OUT_DX 0x0
#define SMM_IO_TYPE_INS 0x3
#define SMM_IO_TYPE_OUTS 0x2
#define SMM_IO_TYPE_REP_INS 0x7
#define SMM_IO_TYPE_REP_OUTS 0x6
///
/// SMRAM Save State Map IOMisc structure
///
typedef union {
struct {
UINT32 SmiFlag:1;
UINT32 Length:3;
UINT32 Type:4;
UINT32 Reserved1:8;
UINT32 Port:16;
} Bits;
UINT32 Uint32;
} SMRAM_SAVE_STATE_IOMISC;
#pragma pack ()
#endif

948
MdePkg/Include/Register/Intel/StmApi.h Normal file
View File

@ -0,0 +1,948 @@
/** @file
STM API definition
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _INTEL_STM_API_H_
#define _INTEL_STM_API_H_
#include <Register/Intel/StmStatusCode.h>
#include <Register/Intel/StmResourceDescriptor.h>
#include <Register/Intel/ArchitecturalMsr.h>
#pragma pack (1)
/**
STM Header Structures
**/
typedef struct {
UINT32 Intel64ModeSupported :1; ///> bitfield
UINT32 EptSupported :1; ///> bitfield
UINT32 Reserved :30; ///> must be 0
} STM_FEAT;
#define STM_SPEC_VERSION_MAJOR 1
#define STM_SPEC_VERSION_MINOR 0
typedef struct {
UINT8 StmSpecVerMajor;
UINT8 StmSpecVerMinor;
///
/// Must be zero
///
UINT16 Reserved;
UINT32 StaticImageSize;
UINT32 PerProcDynamicMemorySize;
UINT32 AdditionalDynamicMemorySize;
STM_FEAT StmFeatures;
UINT32 NumberOfRevIDs;
UINT32 StmSmmRevID[1];
///
/// The total STM_HEADER should be 4K.
///
} SOFTWARE_STM_HEADER;
typedef struct {
MSEG_HEADER HwStmHdr;
SOFTWARE_STM_HEADER SwStmHdr;
} STM_HEADER;
/**
VMCALL API Numbers
API number convention: BIOS facing VMCALL interfaces have bit 16 clear
**/
/**
StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
physical mapping of an address range into the SMM guest's virtual
memory space.
@param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)
@param EBX Low 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be 0.
@note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
are not modified by StmMapAddressRange.
@retval CF 0
No error, EAX set to STM_SUCCESS.
The memory range was mapped as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested mapping contains a protected resource.
@retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
The requested cache type could not be satisfied.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
Page count must not be zero.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmMapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_MAP_ADDRESS_RANGE 0x00000001
/**
STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 PhysicalAddress;
UINT64 VirtualAddress;
UINT32 PageCount;
UINT32 PatCacheType;
} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
@{
**/
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF
/// @}
/**
StmUnmapAddressRange enables a SMM guest to remove mappings from its page
table.
If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
control its own page tables. In this case, the STM implementation may
optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
@param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
@param EBX Low 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. The memory range was unmapped
as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmUnmapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
/**
STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 VirtualAddress;
UINT32 Length;
} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Since the normal OS environment runs with a different set of page tables than
the SMM guest, virtual mappings will certainly be different. In order to do a
guest virtual to host physical translation of an address from the normal OS
code (EIP for example), it is necessary to walk the page tables governing the
OS page mappings. Since the SMM guest has no direct access to the page tables,
it must ask the STM to do this page table walk. This is supported via the
StmAddressLookup VMCALL. All OS page table formats need to be supported,
(e.g. PAE, PSE, Intel64, EPT, etc.)
StmAddressLookup takes a CR3 value and a virtual address from the interrupted
code as input and returns the corresponding physical address. It also
optionally maps the physical address into the SMM guest's virtual address
space. This new mapping persists ONLY for the duration of the SMI and if
needed in subsequent SMIs it must be remapped. PAT cache types follow the
interrupted environment's page table.
If EPT is enabled, OS CR3 only provides guest physical address information,
but the SMM guest might also need to know the host physical address. Since
SMM does not have direct access rights to EPT (it is protected by the STM),
SMM can input InterruptedEptp to let STM help to walk through it, and output
the host physical address.
@param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)
@param EBX Low 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. PhysicalAddress contains the
host physical address determined by walking the interrupted SMM
guest's page tables. SmmGuestVirtualAddress contains the SMM
guest's virtual mapping of the requested address.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested page was a protected page.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The requested virtual address did not exist in the page given
page table.
@retval EAX #ERROR_STM_BAD_CR3
The CR3 input was invalid. CR3 values must be from one of the
interrupted guest, or from the interrupted guest of another
processor.
@retval EAX #ERROR_STM_PHYSICAL_OVER_4G
The resulting physical address is greater than 4G and no virtual
address was supplied. The STM could not determine what address
within the SMM guest's virtual address space to do the mapping.
STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
physical address determined by walking the interrupted
environment's page tables.
@retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
A specific virtual mapping was requested, but
SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
is running in 32 bit mode.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_ADDRESS_LOOKUP 0x00000003
/**
STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
**/
typedef struct {
UINT64 InterruptedGuestVirtualAddress;
UINT32 Length;
UINT64 InterruptedCr3;
UINT64 InterruptedEptp;
UINT32 MapToSmmGuest:2;
UINT32 InterruptedCr4Pae:1;
UINT32 InterruptedCr4Pse:1;
UINT32 InterruptedIa32eMode:1;
UINT32 Reserved1:27;
UINT32 Reserved2;
UINT64 PhysicalAddress;
UINT64 SmmGuestVirtualAddress;
} STM_ADDRESS_LOOKUP_DESCRIPTOR;
/**
Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
@{
**/
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3
/// @}
/**
When returning from a protection exception (see section 6.2), the SMM guest
can instruct the STM to take one of two paths. It can either request a value
be logged to the TXT.ERRORCODE register and subsequently reset the machine
(indicating it couldn't resolve the problem), or it can request that the STM
resume the SMM guest again with the specified register state.
Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
like a jump or an IRET instruction than a "call". It does not return directly
to the caller, but indirectly to a different location specified on the
caller's stack (see section 6.2) or not at all.
If the SMM guest STM protection exception handler itself causes a protection
exception (e.g. a single nested exception), or more than 100 un-nested
exceptions occur within the scope of a single SMI event, the STM must write
STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
the code requirements while still enabling a reasonable debugging capability.
@param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
@param EBX If 0, resume SMM guest using register state found on exception
stack. If in range 0x01..0x0F, EBX contains a BIOS error code
which the STM must record in the TXT.ERRORCODE register and
subsequently reset the system via TXT.CMD.SYS_RESET. The value
of the TXT.ERRORCODE register is calculated as follows:
TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
Values 0x10..0xFFFFFFFF are reserved, do not use.
**/
#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
/**
VMCALL API Numbers
API number convention: MLE facing VMCALL interfaces have bit 16 set.
The STM configuration lifecycle is as follows:
1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
setup of initial protection profile. This is done on a single CPU and
has global effect.
3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
protection profile. The protection profile is global across all CPUs.
4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
SMI events. This must be done on every logical CPU.
5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
#STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
necessary.
6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
following #STM_API_STOP VMCALL.
**/
/**
StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
should remain disabled from the invocation of GETSEC[SENTER] until they are
re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
enabled and the STM has been started and is active. Prior to invoking
StartStmVMCALL(), the MLE root should first invoke
InitializeProtectionVMCALL() followed by as many iterations of
ProtectResourceVMCALL() as necessary to establish the initial protection
profile. StartStmVmcall() must be invoked on all processor threads.
@param EAX #STM_API_START (0x00010001)
@param EDX STM configuration options. These provide the MLE with the
ability to pass configuration parameters to the STM.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been configured
and is now active and the guarding all requested resources.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. STM remains active and
guarding previously enabled resource list.
@retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
The StartStmVMCALL() was invoked from VMX root mode, but outside
of SMX. This error code indicates the STM or platform does not
support the STM outside of SMX. The SMI handler remains active
and operates in legacy mode. See Appendix C
@retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT
The CPU doesn't support the MSR bit. The STM is not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_START (BIT16 | 1)
/**
Bit values for EDX input parameter to #STM_API_START VMCALL
@{
**/
#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0
/// @}
/**
The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
normally done as part of a full teardown of the SMX environment when the
system is being shut down. At the time the call is invoked, SMI is enabled
and the STM is active. When the call returns, the STM has been stopped and
all STM context is discarded and SMI is disabled.
@param EAX #STM_API_STOP (0x00010002)
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been stopped and
is no longer processing SMI events. SMI is blocked.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_STOPPED
The STM was not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_STOP (BIT16 | 2)
/**
The ProtectResourceVMCALL() is invoked by the MLE root to request protection
of specific resources. The request is defined by a STM_RESOURCE_LIST, which
may contain more than one resource descriptor. Each resource descriptor is
processed separately by the STM. Whether or not protection for any specific
resource is granted is returned by the STM via the ReturnStatus bit in the
associated STM_RSC_DESC_HEADER.
@param EAX #STM_API_PROTECT_RESOURCE (0x00010003)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource request granted,
and clear for each resource request denied. There are no other fields
modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
contained entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has successfully
merged the entire protection request into the active protection
profile. There is therefore no need to check the ReturnStatus
bits in the STM_RESOURCE_LIST.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE
At least one of the requested resource protections intersects a
BIOS required resource. Therefore, the caller must walk through
the STM_RESOURCE_LIST to determine which of the requested
resources was not granted protection. The entire list must be
traversed since there may be multiple failures.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources was not granted protection. The entire list
must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_OUT_OF_RESOURCES
The STM has encountered an internal error and cannot complete
the request.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_PROTECT_RESOURCE (BIT16 | 3)
/**
The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
STM allow the SMI handler access to the specified resources.
@param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource processed. For
a properly formed STM_RESOURCE_LIST, this should be all resources
listed. There are no other fields modified by
UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The requested resources are
not being guarded by the STM.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources were not able to be unprotected. The entire
list must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)
/**
The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
of BIOS required resources from the STM.
@param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)
@param EBX Low 32 bits of physical address of caller allocated destination
buffer. Bits 11:0 are ignored and assumed to be zero, making the
buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated destination
buffer.
@param EDX Indicates which page of the BIOS resource list to copy into the
destination buffer. The first page is indicated by 0, the second
page by 1, etc.
@retval CF 0
No error, EAX set to STM_SUCCESS. The destination buffer
contains the BIOS required resources. If the page retrieved is
the last page, EDX will be cleared to 0. If there are more pages
to retrieve, EDX is incremented to the next page index. Calling
software should iterate on GetBiosResourcesVMCALL() until EDX is
returned cleared to 0.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The page index supplied in EDX input was out of range.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@retval EDX Page index of next page to read. A return of EDX=0 signifies
that the entire list has been read.
@note EDX is both an input and an output register.
@note All other registers unmodified.
**/
#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)
/**
The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
MLE guest (including the MLE root) from the list of protected domains.
@param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
@param EBX Low 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST.
@note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not
modified by ManageVmcsDatabaseVMCALL().
@retval CF 0
No error, EAX set to STM_SUCCESS.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_INVALID_VMCS
Indicates a request to remove a VMCS from the database was made,
but the referenced VMCS was not found in the database.
@retval EAX #ERROR_STM_VMCS_PRESENT
Indicates a request to add a VMCS to the database was made, but
the referenced VMCS was already present in the database.
@retval EAX #ERROR_INVALID_PARAMETER
Indicates non-zero reserved field.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred
@note All other registers unmodified.
**/
#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)
/**
STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
**/
typedef struct {
///
/// bits 11:0 are reserved and must be 0
///
UINT64 VmcsPhysPointer;
UINT32 DomainType :4;
UINT32 XStatePolicy :2;
UINT32 DegradationPolicy :4;
///
/// Must be 0
///
UINT32 Reserved1 :22;
UINT32 AddOrRemove;
} STM_VMCS_DATABASE_REQUEST;
/**
Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define DOMAIN_UNPROTECTED 0
#define DOMAIN_DISALLOWED_IO_OUT BIT0
#define DOMAIN_DISALLOWED_IO_IN BIT1
#define DOMAIN_INTEGRITY BIT2
#define DOMAIN_CONFIDENTIALITY BIT3
#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
/// @}
/**
Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define XSTATE_READWRITE 0x00
#define XSTATE_READONLY 0x01
#define XSTATE_SCRUB 0x03
/// @}
/**
Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define STM_VMCS_DATABASE_REQUEST_ADD 1
#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
/// @}
/**
InitializeProtectionVMCALL() prepares the STM for setup of the initial
protection profile which is subsequently communicated via one or more
invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
It is only necessary to invoke InitializeProtectionVMCALL() on one processor
thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked
or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
MLE guest.
@param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)
@retval CF 0
No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
capabilities as defined below. The STM has set up an empty
protection profile, except for the resources that it sets up to
protect itself. The STM must not allow the SMI handler to map
any pages from the MSEG Base to the top of TSEG. The STM must
also not allow SMI handler access to those MSRs which the STM
requires for its own protection.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. The STM remains active
and guarding the previously enabled resource list.
@retval EAX #ERROR_STM_UNPROTECTABLE
The STM determines that based on the platform configuration, the
STM is unable to protect itself. For example, the BIOS required
resource list contains memory pages in MSEG.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)
/**
Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
@{
**/
#define STM_RSC_BGI BIT1
#define STM_RSC_BGM BIT2
#define STM_RSC_MSR BIT3
/// @}
/**
The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
feature. It consists of several sub-functions to facilitate establishment of
the log itself, configuring what events will be logged, and functions to
start, stop, and clear the log.
@param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)
@param EBX Low 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
assumed to be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST.
@retval CF=0
No error, EAX set to STM_SUCCESS.
@retval CF=1
An error occurred, EAX holds relevant error value. See subfunction
descriptions below for details.
@note All other registers unmodified.
**/
#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)
///
/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
///
typedef struct {
UINT32 SubFunctionIndex;
union {
struct {
UINT32 PageCount;
//
// number of elements is PageCount
//
UINT64 Pages[];
} LogBuffer;
//
// bitmap of EVENT_TYPE
//
UINT32 EventEnableBitmap;
} Data;
} STM_EVENT_LOG_MANAGEMENT_REQUEST;
/**
Defines values for the SubFunctionIndex field of
#STM_EVENT_LOG_MANAGEMENT_REQUEST
@{
**/
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6
/// @}
/**
Log Entry Header
**/
typedef struct {
UINT32 EventSerialNumber;
UINT16 Type;
UINT16 Lock :1;
UINT16 Valid :1;
UINT16 ReadByMle :1;
UINT16 Wrapped :1;
UINT16 Reserved :12;
} LOG_ENTRY_HEADER;
/**
Enum values for the Type field of #LOG_ENTRY_HEADER
**/
typedef enum {
EvtLogStarted,
EvtLogStopped,
EvtLogInvalidParameterDetected,
EvtHandledProtectionException,
///
/// unhandled protection exceptions result in reset & cannot be logged
///
EvtBiosAccessToUnclaimedResource,
EvtMleResourceProtectionGranted,
EvtMleResourceProtectionDenied,
EvtMleResourceUnprotect,
EvtMleResourceUnprotectError,
EvtMleDomainTypeDegraded,
///
/// add more here
///
EvtMleMax,
///
/// Not used
///
EvtInvalid = 0xFFFFFFFF,
} EVENT_TYPE;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STARTED;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STOPPED;
typedef struct {
UINT32 VmcallApiNumber;
} ENTRY_EVT_LOG_INVALID_PARAM;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_DENIED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
typedef struct {
UINT64 VmcsPhysPointer;
UINT8 ExpectedDomainType;
UINT8 DegradedDomainType;
} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
typedef union {
ENTRY_EVT_LOG_STARTED Started;
ENTRY_EVT_LOG_STOPPED Stopped;
ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
} LOG_ENTRY_DATA;
typedef struct {
LOG_ENTRY_HEADER Hdr;
LOG_ENTRY_DATA Data;
} STM_LOG_ENTRY;
/**
Maximum STM Log Entry Size
**/
#define STM_LOG_ENTRY_SIZE 256
/**
STM Protection Exception Stack Frame Structures
**/
typedef struct {
UINT32 Rdi;
UINT32 Rsi;
UINT32 Rbp;
UINT32 Rdx;
UINT32 Rcx;
UINT32 Rbx;
UINT32 Rax;
UINT32 Cr3;
UINT32 Cr2;
UINT32 Cr0;
UINT32 VmcsExitInstructionInfo;
UINT32 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT32 ErrorCode;
UINT32 Rip;
UINT32 Cs;
UINT32 Rflags;
UINT32 Rsp;
UINT32 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
typedef struct {
UINT64 R15;
UINT64 R14;
UINT64 R13;
UINT64 R12;
UINT64 R11;
UINT64 R10;
UINT64 R9;
UINT64 R8;
UINT64 Rdi;
UINT64 Rsi;
UINT64 Rbp;
UINT64 Rdx;
UINT64 Rcx;
UINT64 Rbx;
UINT64 Rax;
UINT64 Cr8;
UINT64 Cr3;
UINT64 Cr2;
UINT64 Cr0;
UINT64 VmcsExitInstructionInfo;
UINT64 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT64 ErrorCode;
UINT64 Rip;
UINT64 Cs;
UINT64 Rflags;
UINT64 Rsp;
UINT64 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
typedef union {
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
} STM_PROTECTION_EXCEPTION_STACK_FRAME;
/**
Enum values for the ErrorCode field in
#STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
#STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
**/
typedef enum {
TxtSmmPageViolation = 1,
TxtSmmMsrViolation,
TxtSmmRegisterViolation,
TxtSmmIoViolation,
TxtSmmPciViolation
} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
/**
TXT Pocessor SMM Descriptor (PSD) structures
**/
typedef struct {
UINT64 SpeRip;
UINT64 SpeRsp;
UINT16 SpeSs;
UINT16 PageViolationException:1;
UINT16 MsrViolationException:1;
UINT16 RegisterViolationException:1;
UINT16 IoViolationException:1;
UINT16 PciViolationException:1;
UINT16 Reserved1:11;
UINT32 Reserved2;
} STM_PROTECTION_EXCEPTION_HANDLER;
typedef struct {
UINT8 ExecutionDisableOutsideSmrr:1;
UINT8 Intel64Mode:1;
UINT8 Cr4Pae : 1;
UINT8 Cr4Pse : 1;
UINT8 Reserved1 : 4;
} STM_SMM_ENTRY_STATE;
typedef struct {
UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request
UINT8 Reserved2 : 6;
} STM_SMM_RESUME_STATE;
typedef struct {
UINT8 DomainType : 4; ///> STM input to BIOS on each SMI
UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI
UINT8 EptEnabled : 1;
UINT8 Reserved3 : 1;
} STM_SMM_STATE;
#define TXT_SMM_PSD_OFFSET 0xfb00
#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
typedef struct {
UINT64 Signature;
UINT16 Size;
UINT8 SmmDescriptorVerMajor;
UINT8 SmmDescriptorVerMinor;
UINT32 LocalApicId;
STM_SMM_ENTRY_STATE SmmEntryState;
STM_SMM_RESUME_STATE SmmResumeState;
STM_SMM_STATE StmSmmState;
UINT8 Reserved4;
UINT16 SmmCs;
UINT16 SmmDs;
UINT16 SmmSs;
UINT16 SmmOtherSegment;
UINT16 SmmTr;
UINT16 Reserved5;
UINT64 SmmCr3;
UINT64 SmmStmSetupRip;
UINT64 SmmStmTeardownRip;
UINT64 SmmSmiHandlerRip;
UINT64 SmmSmiHandlerRsp;
UINT64 SmmGdtPtr;
UINT32 SmmGdtSize;
UINT32 RequiredStmSmmRevId;
STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
UINT64 Reserved6;
UINT64 BiosHwResourceRequirementsPtr;
// extend area
UINT64 AcpiRsdp;
UINT8 PhysicalAddressBits;
} TXT_PROCESSOR_SMM_DESCRIPTOR;
#pragma pack ()
#endif

6
UefiCpuPkg/Include/Register/StmResourceDescriptor.h → MdePkg/Include/Register/Intel/StmResourceDescriptor.h
View File

@ -1,7 +1,7 @@
/** @file
STM Resource Descriptor
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -9,8 +9,8 @@
**/
#ifndef _STM_RESOURCE_DESCRIPTOR_H_
#define _STM_RESOURCE_DESCRIPTOR_H_
#ifndef _INTEL_STM_RESOURCE_DESCRIPTOR_H_
#define _INTEL_STM_RESOURCE_DESCRIPTOR_H_
#pragma pack (1)

6
UefiCpuPkg/Include/Register/StmStatusCode.h → MdePkg/Include/Register/Intel/StmStatusCode.h
View File

@ -1,7 +1,7 @@
/** @file
STM Status Codes
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -9,8 +9,8 @@
**/
#ifndef _STM_STATUS_CODE_H_
#define _STM_STATUS_CODE_H_
#ifndef _INTEL_STM_STATUS_CODE_H_
#define _INTEL_STM_STATUS_CODE_H_
/**
STM Status Codes

6565
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
View File

File diff suppressed because it is too large Load Diff

5
UefiCpuPkg/Include/Register/Cpuid.h
View File

@ -3,11 +3,6 @@
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
November 2018, CPUID instruction.
**/
#ifndef __CPUID_H__

175
UefiCpuPkg/Include/Register/LocalApic.h
View File

@ -1,183 +1,14 @@
/** @file
IA32 Local APIC Definitions.
Wrapper header file to include <Register/Intel/LocalApic.h> in MdePkg.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __LOCAL_APIC_H__
#define __LOCAL_APIC_H__
//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
#define XAPIC_VERSION_OFFSET 0x30
#define XAPIC_EOI_OFFSET 0x0b0
#define XAPIC_ICR_DFR_OFFSET 0x0e0
#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
#define XAPIC_ICR_LOW_OFFSET 0x300
#define XAPIC_ICR_HIGH_OFFSET 0x310
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
#define X2APIC_MSR_BASE_ADDRESS 0x800
#define X2APIC_MSR_ICR_ADDRESS 0x830
#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
#define LOCAL_APIC_DELIVERY_MODE_SMI 2
#define LOCAL_APIC_DELIVERY_MODE_NMI 4
#define LOCAL_APIC_DELIVERY_MODE_INIT 5
#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
//
// Local APIC Version Register.
//
typedef union {
struct {
UINT32 Version:8; ///< The version numbers of the local APIC.
UINT32 Reserved0:8; ///< Reserved.
UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.
UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.
UINT32 Reserved1:7; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_VERSION;
//
// Low half of Interrupt Command Register (ICR).
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 Reserved0:1; ///< Reserved.
UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
UINT32 Reserved1:2; ///< Reserved.
UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
UINT32 Reserved2:12; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_ICR_LOW;
//
// High half of Interrupt Command Register (ICR)
//
typedef union {
struct {
UINT32 Reserved0:24; ///< Reserved.
UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
} Bits;
UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
} LOCAL_APIC_ICR_HIGH;
//
// Spurious-Interrupt Vector Register (SVR)
//
typedef union {
struct {
UINT32 SpuriousVector:8; ///< Spurious Vector.
UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
UINT32 Reserved0:2; ///< Reserved.
UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
UINT32 Reserved1:19; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_SVR;
//
// Divide Configuration Register (DCR)
//
typedef union {
struct {
UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
UINT32 Reserved0:1; ///< Always 0.
UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
UINT32 Reserved1:28; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_DCR;
//
// LVT Timer Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 Reserved0:4; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 Reserved1:3; ///< Reserved.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
UINT32 Reserved2:14; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_TIMER;
//
// LVT LINT0/LINT1 Register
//
typedef union {
struct {
UINT32 Vector:8; ///< The vector number of the interrupt being sent.
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:1; ///< Reserved.
UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
UINT32 TriggerMode:1; ///< 0:edge, 1:level.
UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
UINT32 Reserved1:15; ///< Reserved.
} Bits;
UINT32 Uint32;
} LOCAL_APIC_LVT_LINT;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Reserved0:2; ///< Reserved
UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
UINT32 Reserved1:8; ///< Reserved.
UINT32 DestinationId:8; ///< Specifies the Destination ID.
UINT32 BaseAddress:12; ///< Must be 0FEEH
} Bits;
UINT32 Uint32;
} LOCAL_APIC_MSI_ADDRESS;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:3; ///< Reserved.
UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
UINT32 Reserved1:16; ///< Reserved.
UINT32 Reserved2:32; ///< Reserved.
} Bits;
UINT64 Uint64;
} LOCAL_APIC_MSI_DATA;
#include <Register/Intel/LocalApic.h>
#endif

187
UefiCpuPkg/Include/Register/Microcode.h
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@ -1,194 +1,13 @@
/** @file
Microcode Definitions.
Wrapper header file to include <Register/Intel/Microcode.h> in MdePkg.
Microcode Definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3A, Section 9.11 Microcode Definitions
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
**/
#ifndef __MICROCODE_H__
#define __MICROCODE_H__
///
/// CPU Microcode Date in BCD format
///
typedef union {
struct {
UINT32 Year:16;
UINT32 Day:8;
UINT32 Month:8;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_DATE;
///
/// CPU Microcode Processor Signature format
///
typedef union {
struct {
UINT32 Stepping:4;
UINT32 Model:4;
UINT32 Family:4;
UINT32 Type:2;
UINT32 Reserved1:2;
UINT32 ExtendedModel:4;
UINT32 ExtendedFamily:8;
UINT32 Reserved2:4;
} Bits;
UINT32 Uint32;
} CPU_MICROCODE_PROCESSOR_SIGNATURE;
#pragma pack (1)
///
/// Microcode Update Format definition
///
typedef struct {
///
/// Version number of the update header
///
UINT32 HeaderVersion;
///
/// Unique version number for the update, the basis for the update
/// signature provided by the processor to indicate the current update
/// functioning within the processor. Used by the BIOS to authenticate
/// the update and verify that the processor loads successfully. The
/// value in this field cannot be used for processor stepping identification
/// alone. This is a signed 32-bit number.
///
UINT32 UpdateRevision;
///
/// Date of the update creation in binary format: mmddyyyy (e.g.
/// 07/18/98 is 07181998H).
///
CPU_MICROCODE_DATE Date;
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Checksum of Update Data and Header. Used to verify the integrity of
/// the update header and data. Checksum is correct when the
/// summation of all the DWORDs (including the extended Processor
/// Signature Table) that comprise the microcode update result in
/// 00000000H.
///
UINT32 Checksum;
///
/// Version number of the loader program needed to correctly load this
/// update. The initial version is 00000001H
///
UINT32 LoaderRevision;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlags;
///
/// Specifies the size of the encrypted data in bytes, and must be a
/// multiple of DWORDs. If this value is 00000000H, then the microcode
/// update encrypted data is 2000 bytes (or 500 DWORDs).
///
UINT32 DataSize;
///
/// Specifies the total size of the microcode update in bytes. It is the
/// summation of the header size, the encrypted data size and the size of
/// the optional extended signature table. This value is always a multiple
/// of 1024.
///
UINT32 TotalSize;
///
/// Reserved fields for future expansion.
///
UINT8 Reserved[12];
} CPU_MICROCODE_HEADER;
///
/// Extended Signature Table Header Field Definitions
///
typedef struct {
///
/// Specifies the number of extended signature structures (Processor
/// Signature[n], processor flags[n] and checksum[n]) that exist in this
/// microcode update
///
UINT32 ExtendedSignatureCount;
///
/// Checksum of update extended processor signature table. Used to
/// verify the integrity of the extended processor signature table.
/// Checksum is correct when the summation of the DWORDs that
/// comprise the extended processor signature table results in
/// 00000000H.
///
UINT32 ExtendedChecksum;
///
/// Reserved fields.
///
UINT8 Reserved[12];
} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
///
/// Extended Signature Table Field Definitions
///
typedef struct {
///
/// Extended family, extended model, type, family, model, and stepping
/// of processor that requires this particular update revision (e.g.,
/// 00000650H). Each microcode update is designed specifically for a
/// given extended family, extended model, type, family, model, and
/// stepping of the processor.
/// The BIOS uses the processor signature field in conjunction with the
/// CPUID instruction to determine whether or not an update is
/// appropriate to load on a processor. The information encoded within
/// this field exactly corresponds to the bit representations returned by
/// the CPUID instruction.
///
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
///
/// Platform type information is encoded in the lower 8 bits of this 4-
/// byte field. Each bit represents a particular platform type for a given
/// CPUID. The BIOS uses the processor flags field in conjunction with
/// the platform Id bits in MSR (17H) to determine whether or not an
/// update is appropriate to load on a processor. Multiple bits may be set
/// representing support for multiple platform IDs.
///
UINT32 ProcessorFlag;
///
/// Used by utility software to decompose a microcode update into
/// multiple microcode updates where each of the new updates is
/// constructed without the optional Extended Processor Signature
/// Table.
/// To calculate the Checksum, substitute the Primary Processor
/// Signature entry and the Processor Flags entry with the
/// corresponding Extended Patch entry. Delete the Extended Processor
/// Signature Table entries. The Checksum is correct when the
/// summation of all DWORDs that comprise the created Extended
/// Processor Patch results in 00000000H.
///
UINT32 Checksum;
} CPU_MICROCODE_EXTENDED_TABLE;
#pragma pack ()
#include <Register/Intel/Microcode.h>
#endif

36
UefiCpuPkg/Include/Register/Msr.h
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@ -1,44 +1,14 @@
/** @file
MSR Definitions.
Wrapper header file to include <Register/Intel/Msr.h> in MdePkg.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __MSR_H__
#define __MSR_H__
#include <Register/ArchitecturalMsr.h>
#include <Register/Msr/Core2Msr.h>
#include <Register/Msr/AtomMsr.h>
#include <Register/Msr/SilvermontMsr.h>
#include <Register/Msr/GoldmontMsr.h>
#include <Register/Msr/GoldmontPlusMsr.h>
#include <Register/Msr/NehalemMsr.h>
#include <Register/Msr/Xeon5600Msr.h>
#include <Register/Msr/XeonE7Msr.h>
#include <Register/Msr/SandyBridgeMsr.h>
#include <Register/Msr/IvyBridgeMsr.h>
#include <Register/Msr/HaswellMsr.h>
#include <Register/Msr/HaswellEMsr.h>
#include <Register/Msr/BroadwellMsr.h>
#include <Register/Msr/XeonDMsr.h>
#include <Register/Msr/SkylakeMsr.h>
#include <Register/Msr/XeonPhiMsr.h>
#include <Register/Msr/Pentium4Msr.h>
#include <Register/Msr/CoreMsr.h>
#include <Register/Msr/PentiumMMsr.h>
#include <Register/Msr/P6Msr.h>
#include <Register/Msr/PentiumMsr.h>
#include <Register/Intel/Msr.h>
#endif

179
UefiCpuPkg/Include/Register/SmramSaveStateMap.h
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@ -1,184 +1,13 @@
/** @file
SMRAM Save State Map Definitions.
SMRAM Save State Map definitions based on contents of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
Volume 3C, Section 34.4 SMRAM
Volume 3C, Section 34.5 SMI Handler Execution Environment
Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
Wrapper header file to include <Register/Intel/SmramSaveStateMap.h> in MdePkg.
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __SMRAM_SAVE_STATE_MAP_H__
#define __SMRAM_SAVE_STATE_MAP_H__
///
/// Default SMBASE address
///
#define SMM_DEFAULT_SMBASE 0x30000
///
/// Offset of SMM handler from SMBASE
///
#define SMM_HANDLER_OFFSET 0x8000
///
/// Offset of SMRAM Save State Map from SMBASE
///
#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00
#pragma pack (1)
///
/// 32-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved[0x200]; // 7c00h
// Padded an extra 0x200 bytes so 32-bit and 64-bit
// SMRAM Save State Maps are the same size
UINT8 Reserved1[0xf8]; // 7e00h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved2[0x9C]; // 7f08h
UINT32 IOMemAddr; // 7fa0h
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS; // 7fach
UINT32 _SS; // 7fb0h
UINT32 _DS; // 7fb4h
UINT32 _FS; // 7fb8h
UINT32 _GS; // 7fbch
UINT32 Reserved3; // 7fc0h
UINT32 _TR; // 7fc4h
UINT32 _DR7; // 7fc8h
UINT32 _DR6; // 7fcch
UINT32 _EAX; // 7fd0h
UINT32 _ECX; // 7fd4h
UINT32 _EDX; // 7fd8h
UINT32 _EBX; // 7fdch
UINT32 _ESP; // 7fe0h
UINT32 _EBP; // 7fe4h
UINT32 _ESI; // 7fe8h
UINT32 _EDI; // 7fech
UINT32 _EIP; // 7ff0h
UINT32 _EFLAGS; // 7ff4h
UINT32 _CR3; // 7ff8h
UINT32 _CR0; // 7ffch
} SMRAM_SAVE_STATE_MAP32;
///
/// 64-bit SMRAM Save State Map
///
typedef struct {
UINT8 Reserved1[0x1d0]; // 7c00h
UINT32 GdtBaseHiDword; // 7dd0h
UINT32 LdtBaseHiDword; // 7dd4h
UINT32 IdtBaseHiDword; // 7dd8h
UINT8 Reserved2[0xc]; // 7ddch
UINT64 IO_EIP; // 7de8h
UINT8 Reserved3[0x50]; // 7df0h
UINT32 _CR4; // 7e40h
UINT8 Reserved4[0x48]; // 7e44h
UINT32 GdtBaseLoDword; // 7e8ch
UINT32 Reserved5; // 7e90h
UINT32 IdtBaseLoDword; // 7e94h
UINT32 Reserved6; // 7e98h
UINT32 LdtBaseLoDword; // 7e9ch
UINT8 Reserved7[0x38]; // 7ea0h
UINT64 EptVmxControl; // 7ed8h
UINT32 EnEptVmxControl; // 7ee0h
UINT8 Reserved8[0x14]; // 7ee4h
UINT32 SMBASE; // 7ef8h
UINT32 SMMRevId; // 7efch
UINT16 IORestart; // 7f00h
UINT16 AutoHALTRestart; // 7f02h
UINT8 Reserved9[0x18]; // 7f04h
UINT64 _R15; // 7f1ch
UINT64 _R14;
UINT64 _R13;
UINT64 _R12;
UINT64 _R11;
UINT64 _R10;
UINT64 _R9;
UINT64 _R8;
UINT64 _RAX; // 7f5ch
UINT64 _RCX;
UINT64 _RDX;
UINT64 _RBX;
UINT64 _RSP;
UINT64 _RBP;
UINT64 _RSI;
UINT64 _RDI;
UINT64 IOMemAddr; // 7f9ch
UINT32 IOMisc; // 7fa4h
UINT32 _ES; // 7fa8h
UINT32 _CS;
UINT32 _SS;
UINT32 _DS;
UINT32 _FS;
UINT32 _GS;
UINT32 _LDTR; // 7fc0h
UINT32 _TR;
UINT64 _DR7; // 7fc8h
UINT64 _DR6;
UINT64 _RIP; // 7fd8h
UINT64 IA32_EFER; // 7fe0h
UINT64 _RFLAGS; // 7fe8h
UINT64 _CR3; // 7ff0h
UINT64 _CR0; // 7ff8h
} SMRAM_SAVE_STATE_MAP64;
///
/// Union of 32-bit and 64-bit SMRAM Save State Maps
///
typedef union {
SMRAM_SAVE_STATE_MAP32 x86;
SMRAM_SAVE_STATE_MAP64 x64;
} SMRAM_SAVE_STATE_MAP;
///
/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
///
#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004
///
/// SMRAM Save State Map IOMisc I/O Length Values
///
#define SMM_IO_LENGTH_BYTE 0x01
#define SMM_IO_LENGTH_WORD 0x02
#define SMM_IO_LENGTH_DWORD 0x04
///
/// SMRAM Save State Map IOMisc I/O Instruction Type Values
///
#define SMM_IO_TYPE_IN_IMMEDIATE 0x9
#define SMM_IO_TYPE_IN_DX 0x1
#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8
#define SMM_IO_TYPE_OUT_DX 0x0
#define SMM_IO_TYPE_INS 0x3
#define SMM_IO_TYPE_OUTS 0x2
#define SMM_IO_TYPE_REP_INS 0x7
#define SMM_IO_TYPE_REP_OUTS 0x6
///
/// SMRAM Save State Map IOMisc structure
///
typedef union {
struct {
UINT32 SmiFlag:1;
UINT32 Length:3;
UINT32 Type:4;
UINT32 Reserved1:8;
UINT32 Port:16;
} Bits;
UINT32 Uint32;
} SMRAM_SAVE_STATE_IOMISC;
#pragma pack ()
#include <Register/Intel/SmramSaveStateMap.h>
#endif

941
UefiCpuPkg/Include/Register/StmApi.h
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@ -1,948 +1,13 @@
/** @file
STM API definition
Wrapper header file to include <Register/Intel/StmApi.h> in MdePkg.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00
**/
#ifndef _STM_API_H_
#define _STM_API_H_
#include <Register/StmStatusCode.h>
#include <Register/StmResourceDescriptor.h>
#include <Register/ArchitecturalMsr.h>
#pragma pack (1)
/**
STM Header Structures
**/
typedef struct {
UINT32 Intel64ModeSupported :1; ///> bitfield
UINT32 EptSupported :1; ///> bitfield
UINT32 Reserved :30; ///> must be 0
} STM_FEAT;
#define STM_SPEC_VERSION_MAJOR 1
#define STM_SPEC_VERSION_MINOR 0
typedef struct {
UINT8 StmSpecVerMajor;
UINT8 StmSpecVerMinor;
///
/// Must be zero
///
UINT16 Reserved;
UINT32 StaticImageSize;
UINT32 PerProcDynamicMemorySize;
UINT32 AdditionalDynamicMemorySize;
STM_FEAT StmFeatures;
UINT32 NumberOfRevIDs;
UINT32 StmSmmRevID[1];
///
/// The total STM_HEADER should be 4K.
///
} SOFTWARE_STM_HEADER;
typedef struct {
MSEG_HEADER HwStmHdr;
SOFTWARE_STM_HEADER SwStmHdr;
} STM_HEADER;
/**
VMCALL API Numbers
API number convention: BIOS facing VMCALL interfaces have bit 16 clear
**/
/**
StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
physical mapping of an address range into the SMM guest's virtual
memory space.
@param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)
@param EBX Low 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of physical address of caller allocated
STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be 0.
@note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
are not modified by StmMapAddressRange.
@retval CF 0
No error, EAX set to STM_SUCCESS.
The memory range was mapped as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested mapping contains a protected resource.
@retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
The requested cache type could not be satisfied.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
Page count must not be zero.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmMapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_MAP_ADDRESS_RANGE 0x00000001
/**
STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 PhysicalAddress;
UINT64 VirtualAddress;
UINT32 PageCount;
UINT32 PatCacheType;
} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
@{
**/
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07
#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF
/// @}
/**
StmUnmapAddressRange enables a SMM guest to remove mappings from its page
table.
If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
control its own page tables. In this case, the STM implementation may
optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
@param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
@param EBX Low 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. The memory range was unmapped
as requested.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED
STM supports EPT and has not implemented StmUnmapAddressRange().
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
/**
STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
**/
typedef struct {
UINT64 VirtualAddress;
UINT32 Length;
} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
/**
Since the normal OS environment runs with a different set of page tables than
the SMM guest, virtual mappings will certainly be different. In order to do a
guest virtual to host physical translation of an address from the normal OS
code (EIP for example), it is necessary to walk the page tables governing the
OS page mappings. Since the SMM guest has no direct access to the page tables,
it must ask the STM to do this page table walk. This is supported via the
StmAddressLookup VMCALL. All OS page table formats need to be supported,
(e.g. PAE, PSE, Intel64, EPT, etc.)
StmAddressLookup takes a CR3 value and a virtual address from the interrupted
code as input and returns the corresponding physical address. It also
optionally maps the physical address into the SMM guest's virtual address
space. This new mapping persists ONLY for the duration of the SMI and if
needed in subsequent SMIs it must be remapped. PAT cache types follow the
interrupted environment's page table.
If EPT is enabled, OS CR3 only provides guest physical address information,
but the SMM guest might also need to know the host physical address. Since
SMM does not have direct access rights to EPT (it is protected by the STM),
SMM can input InterruptedEptp to let STM help to walk through it, and output
the host physical address.
@param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)
@param EBX Low 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
@param ECX High 32 bits of virtual address of caller allocated
STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
clear (0), ECX must be zero.
@retval CF 0
No error, EAX set to STM_SUCCESS. PhysicalAddress contains the
host physical address determined by walking the interrupted SMM
guest's page tables. SmmGuestVirtualAddress contains the SMM
guest's virtual mapping of the requested address.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_SECURITY_VIOLATION
The requested page was a protected page.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The requested virtual address did not exist in the page given
page table.
@retval EAX #ERROR_STM_BAD_CR3
The CR3 input was invalid. CR3 values must be from one of the
interrupted guest, or from the interrupted guest of another
processor.
@retval EAX #ERROR_STM_PHYSICAL_OVER_4G
The resulting physical address is greater than 4G and no virtual
address was supplied. The STM could not determine what address
within the SMM guest's virtual address space to do the mapping.
STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
physical address determined by walking the interrupted
environment's page tables.
@retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
A specific virtual mapping was requested, but
SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
is running in 32 bit mode.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_ADDRESS_LOOKUP 0x00000003
/**
STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
**/
typedef struct {
UINT64 InterruptedGuestVirtualAddress;
UINT32 Length;
UINT64 InterruptedCr3;
UINT64 InterruptedEptp;
UINT32 MapToSmmGuest:2;
UINT32 InterruptedCr4Pae:1;
UINT32 InterruptedCr4Pse:1;
UINT32 InterruptedIa32eMode:1;
UINT32 Reserved1:27;
UINT32 Reserved2;
UINT64 PhysicalAddress;
UINT64 SmmGuestVirtualAddress;
} STM_ADDRESS_LOOKUP_DESCRIPTOR;
/**
Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
@{
**/
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3
/// @}
/**
When returning from a protection exception (see section 6.2), the SMM guest
can instruct the STM to take one of two paths. It can either request a value
be logged to the TXT.ERRORCODE register and subsequently reset the machine
(indicating it couldn't resolve the problem), or it can request that the STM
resume the SMM guest again with the specified register state.
Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
like a jump or an IRET instruction than a "call". It does not return directly
to the caller, but indirectly to a different location specified on the
caller's stack (see section 6.2) or not at all.
If the SMM guest STM protection exception handler itself causes a protection
exception (e.g. a single nested exception), or more than 100 un-nested
exceptions occur within the scope of a single SMI event, the STM must write
STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
the code requirements while still enabling a reasonable debugging capability.
@param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
@param EBX If 0, resume SMM guest using register state found on exception
stack. If in range 0x01..0x0F, EBX contains a BIOS error code
which the STM must record in the TXT.ERRORCODE register and
subsequently reset the system via TXT.CMD.SYS_RESET. The value
of the TXT.ERRORCODE register is calculated as follows:
TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
Values 0x10..0xFFFFFFFF are reserved, do not use.
**/
#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
/**
VMCALL API Numbers
API number convention: MLE facing VMCALL interfaces have bit 16 set.
The STM configuration lifecycle is as follows:
1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
setup of initial protection profile. This is done on a single CPU and
has global effect.
3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
protection profile. The protection profile is global across all CPUs.
4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
SMI events. This must be done on every logical CPU.
5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
#STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
necessary.
6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
following #STM_API_STOP VMCALL.
**/
/**
StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
should remain disabled from the invocation of GETSEC[SENTER] until they are
re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
enabled and the STM has been started and is active. Prior to invoking
StartStmVMCALL(), the MLE root should first invoke
InitializeProtectionVMCALL() followed by as many iterations of
ProtectResourceVMCALL() as necessary to establish the initial protection
profile. StartStmVmcall() must be invoked on all processor threads.
@param EAX #STM_API_START (0x00010001)
@param EDX STM configuration options. These provide the MLE with the
ability to pass configuration parameters to the STM.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been configured
and is now active and the guarding all requested resources.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. STM remains active and
guarding previously enabled resource list.
@retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
The StartStmVMCALL() was invoked from VMX root mode, but outside
of SMX. This error code indicates the STM or platform does not
support the STM outside of SMX. The SMI handler remains active
and operates in legacy mode. See Appendix C
@retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT
The CPU doesn't support the MSR bit. The STM is not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_START (BIT16 | 1)
/**
Bit values for EDX input parameter to #STM_API_START VMCALL
@{
**/
#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0
/// @}
/**
The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
normally done as part of a full teardown of the SMX environment when the
system is being shut down. At the time the call is invoked, SMI is enabled
and the STM is active. When the call returns, the STM has been stopped and
all STM context is discarded and SMI is disabled.
@param EAX #STM_API_STOP (0x00010002)
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has been stopped and
is no longer processing SMI events. SMI is blocked.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_STOPPED
The STM was not active.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_STOP (BIT16 | 2)
/**
The ProtectResourceVMCALL() is invoked by the MLE root to request protection
of specific resources. The request is defined by a STM_RESOURCE_LIST, which
may contain more than one resource descriptor. Each resource descriptor is
processed separately by the STM. Whether or not protection for any specific
resource is granted is returned by the STM via the ReturnStatus bit in the
associated STM_RSC_DESC_HEADER.
@param EAX #STM_API_PROTECT_RESOURCE (0x00010003)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource request granted,
and clear for each resource request denied. There are no other fields
modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
contained entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The STM has successfully
merged the entire protection request into the active protection
profile. There is therefore no need to check the ReturnStatus
bits in the STM_RESOURCE_LIST.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE
At least one of the requested resource protections intersects a
BIOS required resource. Therefore, the caller must walk through
the STM_RESOURCE_LIST to determine which of the requested
resources was not granted protection. The entire list must be
traversed since there may be multiple failures.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources was not granted protection. The entire list
must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_OUT_OF_RESOURCES
The STM has encountered an internal error and cannot complete
the request.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_PROTECT_RESOURCE (BIT16 | 3)
/**
The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
STM allow the SMI handler access to the specified resources.
@param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)
@param EBX Low 32 bits of physical address of caller allocated
STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_RESOURCE_LIST.
@note All fields of STM_RESOURCE_LIST are inputs only, except for the
ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
return, the ReturnStatus bit is set for each resource processed. For
a properly formed STM_RESOURCE_LIST, this should be all resources
listed. There are no other fields modified by
UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
entirely within a single 4K page.
@retval CF 0
No error, EAX set to STM_SUCCESS. The requested resources are
not being guarded by the STM.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST
The resource list could not be parsed correctly, or did not
terminate before crossing a 4K page boundary. The caller must
walk through the STM_RESOURCE_LIST to determine which of the
requested resources were not able to be unprotected. The entire
list must be traversed since there may be multiple failures.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)
/**
The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
of BIOS required resources from the STM.
@param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)
@param EBX Low 32 bits of physical address of caller allocated destination
buffer. Bits 11:0 are ignored and assumed to be zero, making the
buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated destination
buffer.
@param EDX Indicates which page of the BIOS resource list to copy into the
destination buffer. The first page is indicated by 0, the second
page by 1, etc.
@retval CF 0
No error, EAX set to STM_SUCCESS. The destination buffer
contains the BIOS required resources. If the page retrieved is
the last page, EDX will be cleared to 0. If there are more pages
to retrieve, EDX is incremented to the next page index. Calling
software should iterate on GetBiosResourcesVMCALL() until EDX is
returned cleared to 0.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_PAGE_NOT_FOUND
The page index supplied in EDX input was out of range.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@retval EDX Page index of next page to read. A return of EDX=0 signifies
that the entire list has been read.
@note EDX is both an input and an output register.
@note All other registers unmodified.
**/
#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)
/**
The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
MLE guest (including the MLE root) from the list of protected domains.
@param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
@param EBX Low 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_VMCS_DATABASE_REQUEST.
@note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not
modified by ManageVmcsDatabaseVMCALL().
@retval CF 0
No error, EAX set to STM_SUCCESS.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_INVALID_VMCS
Indicates a request to remove a VMCS from the database was made,
but the referenced VMCS was not found in the database.
@retval EAX #ERROR_STM_VMCS_PRESENT
Indicates a request to add a VMCS to the database was made, but
the referenced VMCS was already present in the database.
@retval EAX #ERROR_INVALID_PARAMETER
Indicates non-zero reserved field.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred
@note All other registers unmodified.
**/
#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)
/**
STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
**/
typedef struct {
///
/// bits 11:0 are reserved and must be 0
///
UINT64 VmcsPhysPointer;
UINT32 DomainType :4;
UINT32 XStatePolicy :2;
UINT32 DegradationPolicy :4;
///
/// Must be 0
///
UINT32 Reserved1 :22;
UINT32 AddOrRemove;
} STM_VMCS_DATABASE_REQUEST;
/**
Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define DOMAIN_UNPROTECTED 0
#define DOMAIN_DISALLOWED_IO_OUT BIT0
#define DOMAIN_DISALLOWED_IO_IN BIT1
#define DOMAIN_INTEGRITY BIT2
#define DOMAIN_CONFIDENTIALITY BIT3
#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
/// @}
/**
Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define XSTATE_READWRITE 0x00
#define XSTATE_READONLY 0x01
#define XSTATE_SCRUB 0x03
/// @}
/**
Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
@{
**/
#define STM_VMCS_DATABASE_REQUEST_ADD 1
#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
/// @}
/**
InitializeProtectionVMCALL() prepares the STM for setup of the initial
protection profile which is subsequently communicated via one or more
invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
It is only necessary to invoke InitializeProtectionVMCALL() on one processor
thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked
or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
MLE guest.
@param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)
@retval CF 0
No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
capabilities as defined below. The STM has set up an empty
protection profile, except for the resources that it sets up to
protect itself. The STM must not allow the SMI handler to map
any pages from the MSEG Base to the top of TSEG. The STM must
also not allow SMI handler access to those MSRs which the STM
requires for its own protection.
@retval CF 1
An error occurred, EAX holds relevant error value.
@retval EAX #ERROR_STM_ALREADY_STARTED
The STM is already configured and active. The STM remains active
and guarding the previously enabled resource list.
@retval EAX #ERROR_STM_UNPROTECTABLE
The STM determines that based on the platform configuration, the
STM is unable to protect itself. For example, the BIOS required
resource list contains memory pages in MSEG.
@retval EAX #ERROR_STM_UNSPECIFIED
An unspecified error occurred.
@note All other registers unmodified.
**/
#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)
/**
Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
@{
**/
#define STM_RSC_BGI BIT1
#define STM_RSC_BGM BIT2
#define STM_RSC_MSR BIT3
/// @}
/**
The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
feature. It consists of several sub-functions to facilitate establishment of
the log itself, configuring what events will be logged, and functions to
start, stop, and clear the log.
@param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)
@param EBX Low 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
assumed to be zero, making the buffer 4K aligned.
@param ECX High 32 bits of physical address of caller allocated
STM_EVENT_LOG_MANAGEMENT_REQUEST.
@retval CF=0
No error, EAX set to STM_SUCCESS.
@retval CF=1
An error occurred, EAX holds relevant error value. See subfunction
descriptions below for details.
@note All other registers unmodified.
**/
#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)
///
/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
///
typedef struct {
UINT32 SubFunctionIndex;
union {
struct {
UINT32 PageCount;
//
// number of elements is PageCount
//
UINT64 Pages[];
} LogBuffer;
//
// bitmap of EVENT_TYPE
//
UINT32 EventEnableBitmap;
} Data;
} STM_EVENT_LOG_MANAGEMENT_REQUEST;
/**
Defines values for the SubFunctionIndex field of
#STM_EVENT_LOG_MANAGEMENT_REQUEST
@{
**/
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5
#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6
/// @}
/**
Log Entry Header
**/
typedef struct {
UINT32 EventSerialNumber;
UINT16 Type;
UINT16 Lock :1;
UINT16 Valid :1;
UINT16 ReadByMle :1;
UINT16 Wrapped :1;
UINT16 Reserved :12;
} LOG_ENTRY_HEADER;
/**
Enum values for the Type field of #LOG_ENTRY_HEADER
**/
typedef enum {
EvtLogStarted,
EvtLogStopped,
EvtLogInvalidParameterDetected,
EvtHandledProtectionException,
///
/// unhandled protection exceptions result in reset & cannot be logged
///
EvtBiosAccessToUnclaimedResource,
EvtMleResourceProtectionGranted,
EvtMleResourceProtectionDenied,
EvtMleResourceUnprotect,
EvtMleResourceUnprotectError,
EvtMleDomainTypeDegraded,
///
/// add more here
///
EvtMleMax,
///
/// Not used
///
EvtInvalid = 0xFFFFFFFF,
} EVENT_TYPE;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STARTED;
typedef struct {
UINT32 Reserved;
} ENTRY_EVT_LOG_STOPPED;
typedef struct {
UINT32 VmcallApiNumber;
} ENTRY_EVT_LOG_INVALID_PARAM;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_PROT_DENIED;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT;
typedef struct {
STM_RSC Resource;
} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
typedef struct {
UINT64 VmcsPhysPointer;
UINT8 ExpectedDomainType;
UINT8 DegradedDomainType;
} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
typedef union {
ENTRY_EVT_LOG_STARTED Started;
ENTRY_EVT_LOG_STOPPED Stopped;
ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
} LOG_ENTRY_DATA;
typedef struct {
LOG_ENTRY_HEADER Hdr;
LOG_ENTRY_DATA Data;
} STM_LOG_ENTRY;
/**
Maximum STM Log Entry Size
**/
#define STM_LOG_ENTRY_SIZE 256
/**
STM Protection Exception Stack Frame Structures
**/
typedef struct {
UINT32 Rdi;
UINT32 Rsi;
UINT32 Rbp;
UINT32 Rdx;
UINT32 Rcx;
UINT32 Rbx;
UINT32 Rax;
UINT32 Cr3;
UINT32 Cr2;
UINT32 Cr0;
UINT32 VmcsExitInstructionInfo;
UINT32 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT32 ErrorCode;
UINT32 Rip;
UINT32 Cs;
UINT32 Rflags;
UINT32 Rsp;
UINT32 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
typedef struct {
UINT64 R15;
UINT64 R14;
UINT64 R13;
UINT64 R12;
UINT64 R11;
UINT64 R10;
UINT64 R9;
UINT64 R8;
UINT64 Rdi;
UINT64 Rsi;
UINT64 Rbp;
UINT64 Rdx;
UINT64 Rcx;
UINT64 Rbx;
UINT64 Rax;
UINT64 Cr8;
UINT64 Cr3;
UINT64 Cr2;
UINT64 Cr0;
UINT64 VmcsExitInstructionInfo;
UINT64 VmcsExitInstructionLength;
UINT64 VmcsExitQualification;
///
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
///
UINT64 ErrorCode;
UINT64 Rip;
UINT64 Cs;
UINT64 Rflags;
UINT64 Rsp;
UINT64 Ss;
} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
typedef union {
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
} STM_PROTECTION_EXCEPTION_STACK_FRAME;
/**
Enum values for the ErrorCode field in
#STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
#STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
**/
typedef enum {
TxtSmmPageViolation = 1,
TxtSmmMsrViolation,
TxtSmmRegisterViolation,
TxtSmmIoViolation,
TxtSmmPciViolation
} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
/**
TXT Pocessor SMM Descriptor (PSD) structures
**/
typedef struct {
UINT64 SpeRip;
UINT64 SpeRsp;
UINT16 SpeSs;
UINT16 PageViolationException:1;
UINT16 MsrViolationException:1;
UINT16 RegisterViolationException:1;
UINT16 IoViolationException:1;
UINT16 PciViolationException:1;
UINT16 Reserved1:11;
UINT32 Reserved2;
} STM_PROTECTION_EXCEPTION_HANDLER;
typedef struct {
UINT8 ExecutionDisableOutsideSmrr:1;
UINT8 Intel64Mode:1;
UINT8 Cr4Pae : 1;
UINT8 Cr4Pse : 1;
UINT8 Reserved1 : 4;
} STM_SMM_ENTRY_STATE;
typedef struct {
UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request
UINT8 Reserved2 : 6;
} STM_SMM_RESUME_STATE;
typedef struct {
UINT8 DomainType : 4; ///> STM input to BIOS on each SMI
UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI
UINT8 EptEnabled : 1;
UINT8 Reserved3 : 1;
} STM_SMM_STATE;
#define TXT_SMM_PSD_OFFSET 0xfb00
#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
typedef struct {
UINT64 Signature;
UINT16 Size;
UINT8 SmmDescriptorVerMajor;
UINT8 SmmDescriptorVerMinor;
UINT32 LocalApicId;
STM_SMM_ENTRY_STATE SmmEntryState;
STM_SMM_RESUME_STATE SmmResumeState;
STM_SMM_STATE StmSmmState;
UINT8 Reserved4;
UINT16 SmmCs;
UINT16 SmmDs;
UINT16 SmmSs;
UINT16 SmmOtherSegment;
UINT16 SmmTr;
UINT16 Reserved5;
UINT64 SmmCr3;
UINT64 SmmStmSetupRip;
UINT64 SmmStmTeardownRip;
UINT64 SmmSmiHandlerRip;
UINT64 SmmSmiHandlerRsp;
UINT64 SmmGdtPtr;
UINT32 SmmGdtSize;
UINT32 RequiredStmSmmRevId;
STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
UINT64 Reserved6;
UINT64 BiosHwResourceRequirementsPtr;
// extend area
UINT64 AcpiRsdp;
UINT8 PhysicalAddressBits;
} TXT_PROCESSOR_SMM_DESCRIPTOR;
#pragma pack ()
#include <Register/Intel/StmApi.h>
#endif