sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ArmPkg: Configure TTBCR register

Browse Source 
Architecturally, the TTBCR register value is undefined at reset for
Non-Secure.
On some platforms the reset value for TTBCR is not zero and
this causes a data abort exception once the MMU is enabled.

This patch configures the TTBCR register to enable translation table
walk using TTBR0.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
This commit is contained in:
Evan Lloyd
2016-03-02 21:08:46 +00:00
committed by Leif Lindholm
parent eea222ced0
commit ff1f27c055
4 changed files with 32 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
View File

@@ -1,7 +1,7 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -23,6 +23,7 @@ GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmSetTTBCR)
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
@@ -111,6 +112,11 @@ ASM_PFX(ArmSetTTBR0):
isb
bx lr
ASM_PFX(ArmSetTTBCR):
mcr p15, 0, r0, c2, c0, 2
isb
bx lr
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)