CorebootModulePkg version is buggy and unmaintained, switching
to MdeModulePkg version fixes channel count / drive detection
issue on some KBL Chromeboxes
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
changed: buffer size from 64k to 256k
Change-Id: I7f443b9f36612f79787e1b4b1075176a91107686
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Since board names match the device, just print manufacturer
and device name without translation.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
From stepan:
"This enables eMMC booting when starting edk2
from depthcharge. Previously the driver would
bail out with an error while setting the eMMC
frequency, because depthcharge has already set
up the controller."
Also fixed detection on google/lars w/Core-i5
with upstream coreboot + Tianocore payload
Since the memory test is essentially instantanous,
remove unnecessry duplication of memory count and
static status bar for cleaner display with coreboot logo
Tianocore's PCI enumeration goes into an infinite loop, and
isn't necessary since coreboot has already handled it.
Copy and use DuetPkg's PciNoEnumeration package (which has
since been removed).
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Add function to allow enabling and disabling of the clock using the SCMI
interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that
support new API from those that just have the older protocol.
SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future
changes. It is placed after the functions that are present in the
existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to
SCMI_CLOCK_PROTOCOL so that only a single implementation of those
function are needed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Use an untyped PCD reference for PcdSerialRegisterBase, so that the
library gets built without hardcoded values, permitting modules to
override the default serial port. This allows SerialDxe to use a
different serial port from the one used for DEBUG output (which
often gets occluded due to the console driver clearing the screen).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Even though UEFI does not appear to use it, let's implement the
complete PI watchdog protocol, including handler registration,
which will be invoked before the ResetSystem() runtime service
when the watchdog timer expires.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Clean up the code, by adding missing STATIC modifiers, drop
redundant casts, and get rid of the 'success handling' anti
pattern in the entry point code.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The SP805 watchdog driver doesn't implement the PI watchdog protocol
fully, but always simply resets the system if the watchdog time runs
out.
However, the hardware does support the intended usage model, as long
as the SP805 is wired up correctly. So let's implement interrupt based
mode involving a handler that is registered by the DXE core and invoked
when the watchdog runs out. In the interrupt handler, we invoke the
notify function if one was registered, before calling the ResetSystem()
runtime service (as per the UEFI spec)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Before fixing the SP805 driver, let's clean it up a bit. No
functional changes.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Instead of #defining MAX_ALLOC_ADDRESS to MAX_ADDRESS as intended,
it is #defined to itself, causing all ARM builds to break.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The current ArmVirtMemoryInitPeiLib code splits the memory region passed
via PcdSystemMemoryBase/PcdSystemMemorySize in two if the region extends
beyond the MAX_ADDRESS limit. This was introduced for 32-bit ARM, which
may support more than 4 GB of physical address space, but cannot address
all of it via a 1:1 mapping, and a single region that is not mappable
in its entirety is unusable by the PEI core.
AArch64 is in a similar situation now: platforms may support more than
256 TB of physical address space, but only 256 TB is addressable by the
CPU, and so a memory region that extends from below this limit to above
it should be split.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
