While allocating pages aligned at an alignment higher than
4K, allocate memory taking into consideration the padding
required for that alignment. The calls to free pages takes
care of this already.
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Fix an assertion that prevented the boot menu to show up when the coreboot
string is very long.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621
According to Intel SDM as below, the BIT0 should be treated as
lock bit, and BIT1 should be treated as disable(1)/enable(0) bit.
"11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b"
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Microsoft user experience specifications recommend the boot logo is drawn 38.2%
from the top of the screen. This is also where operating systems like Fedora
expect the logo to be drawn.
Signed-off-by: James Ye <jye836@gmail.com>
No reason to hardcode the image size into the
positon calculations. Keep shift to upper 2/3
of screen.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
BMP files by tools other than MS paint can have a
variable number of padding bytes, which results in
the DataSize being less than (ImageSize - HeaderSize).
Fix the check to be less stringent.
Test: use BMP created by/saved by Photoshop
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
CorebootModulePkg version is buggy and unmaintained, switching
to MdeModulePkg version fixes channel count / drive detection
issue on some KBL Chromeboxes
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
changed: buffer size from 64k to 256k
Change-Id: I7f443b9f36612f79787e1b4b1075176a91107686
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Since board names match the device, just print manufacturer
and device name without translation.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
From stepan:
"This enables eMMC booting when starting edk2
from depthcharge. Previously the driver would
bail out with an error while setting the eMMC
frequency, because depthcharge has already set
up the controller."
Also fixed detection on google/lars w/Core-i5
with upstream coreboot + Tianocore payload
Since the memory test is essentially instantanous,
remove unnecessry duplication of memory count and
static status bar for cleaner display with coreboot logo
Tianocore's PCI enumeration goes into an infinite loop, and
isn't necessary since coreboot has already handled it.
Copy and use DuetPkg's PciNoEnumeration package (which has
since been removed).
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Add function to allow enabling and disabling of the clock using the SCMI
interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that
support new API from those that just have the older protocol.
SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future
changes. It is placed after the functions that are present in the
existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to
SCMI_CLOCK_PROTOCOL so that only a single implementation of those
function are needed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
