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213 Commits
edk2-stabl ... edk2-stabl

Author SHA1 Message Date
Andreas Sandberg
e1999b264f ArmPkg/ArmGic: Fix maximum number of interrupts in GICv3 
Bugzilla: 3415 (https://bugzilla.tianocore.org/show_bug.cgi?id=3415)

The GICv3 architecture supports up to 1020 ordinary interrupt
lines. The actual number of interrupts supported is described by the
ITLinesNumber field in the GICD_TYPER register. The total number of
implemented registers is normally calculated as
32*(ITLinesNumber+1). However, maximum value (0x1f) is a special case
since that would indicate that 1024 interrupts are implemented.

Add handling for this special case in ArmGicGetMaxNumInterrupts.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
 2021-05-27 10:08:32 +00:00
Laszlo Ersek
cfa6ffb113 MdeModulePkg/VariableLock: downgrade compatibility warnings to DEBUG_WARN 
Commit a18a9bde36 ("MdeModulePkg/Variable/RuntimeDxe: Restore Variable
Lock Protocol behavior", 2020-12-15), for bug 3111, added two such sets of
debug messages that:

(a) are relevant for developers,

(b) yet should not necessarily poke end-users, because no functionality
suffers in practice.

Both message sets are in function VariableLockRequestToLock(): the first
is a generic interface deprecation warning; the second is the
double-locking situation, which we permit for compatibility (return status
EFI_SUCCESS).

Both message sets should be emitted with the DEBUG_WARN mask, not the most
serious DEBUG_ERROR mask. On some platforms, the serial console carries
both terminal traffic, and grave (DEBUG_ERROR-only) log messages. On such
platforms, both message sets may be perceived as a nuisance by end-users,
as there is nothing they can do, and there's nothing they *should* do --
in practice, nothing malfunctions.

(Such a platform is ArmVirtQemu, built with "-D
DEBUG_PRINT_ERROR_LEVEL=0x80000000".)

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3410
Fixes: a18a9bde36
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210521204037.11980-1-lersek@redhat.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-05-23 12:06:55 +00:00
Li, Walon
1fb80369b7 MdeModulePkg/PlatformDriOverrideDxe: Fix overflow condition check 
Code mistake, VariableIndex is smaller normally than buffer+buffersize
so should not break loop.

Signed-off-by: Walon Li <walon.li@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-05-21 08:31:39 +00:00
Garrett Kirkendall
04ae17218d BaseTools: build: Set ReturnCode on POSTBUILD fail 
When build.by POSTBUILD handling section returns other than 0, set
ReturnCode to POSTBUILD_ERROR so build.py exits with return code other
than 0.

Fix for https://bugzilla.tianocore.org/show_bug.cgi?id=1977

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-05-21 06:52:36 +00:00
Sergei Dmitrouk
15ee7b7689 CryptoPkg/BaseCryptLib: Fix possible uninitialized use 
`Result` can be used uninitialized in both functions after following
either first or second `goto` statement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2021-05-19 01:39:49 +00:00
Sergei Dmitrouk
4c79f9bc20 MdeModulePkg/PciBusDxe: Fix possible uninitialized use 
If the function gets invalid value for the `ResizableBarOp` parameter
and asserts are disabled, `Bit` can be used uninitialized.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-05-19 01:39:49 +00:00
Sergei Dmitrouk
aecfbc81a9 ShellPkg/HttpDynamicCommand: Fix possible uninitialized use 
`Status` can be used uninitialized:

    /* Evaluates to FALSE */
    if (ShellGetExecutionBreakFlag ()) {
        Status = EFI_ABORTED;
        break;
    }

    /* Evaluates to FALSE */
    if (!Context->ContentDownloaded && !Context->ResponseToken.Event) {
        Status = ...;
        ASSERT_EFI_ERROR (Status);
    } else {
        ResponseMessage.Data.Response = NULL;
    }

    /* UNINITIALIZED USE */
    if (EFI_ERROR (Status)) {
        break;
    }

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-05-19 01:39:49 +00:00
Zhiguang Liu
42ec0a315b MdeModulePkg: Retrieve boot manager menu from any fv 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384

Currently, UefiBootManagerLib has the below assumption:
  Assume the BootManagerMenuFile is in the same FV as the module links to this library.
It has some limitation now, so remove the assumption.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
 2021-05-18 13:52:06 +00:00
Ray Ni
29e300ff81 UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation 
5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-05-18 08:07:57 +00:00
Loo, Tung Lun
1fbf5e30ae IntelFsp2Pkg: YAML script bug fix 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3395

This patch fixes the issue observed during
BSF file to YAML file conversion. It also
addresses the issue during multibyte array
data conversion check, for example the data
representation of 0xFFFF instead of 0xFF, 0xFF
would be thrown exception "Array size is not
proper" without this patch.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
 2021-05-18 00:46:45 +00:00
Daniel Schaefer
d2e0c473e6 BaseTools: Add DTCPP_FLAGS for GCC5 RISCV64 toolchain 
Some/all platforms are going to require EDK2 to build a device tree and
use it in the early stages of boot.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-05-17 04:22:20 +00:00
Chen, Christine
9cd854e19d BaseTools/Brotli: Fix compressed data loss issue 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2946

Currenly, when using the Brotli tool to compress data, the output
compressed binary file does not record complete compressed data
when size of input file is too large, which makes the data loss and
will trigger decompress-check issue.

The Brotli document mentioned:
The brotli tool use BrotliEncoderCompressStream method to compresses
input stream to output stream. Under some circumstances (e.g. lack of
output stream capacity) the BrotliEncoderOperation would require
several calls to BrotliEncoderCompressStream. The method must be
called again until both input stream is depleted and encoder has no
more output after the method is called.

This patch fixes this issue based on the Brotli document.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-05-17 03:45:13 +00:00
Rebecca Cran
e0cb5e1814 MdeModulePkg: Fix various typos 
Fix various typos throughout MdeModulePkg.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-05-17 02:10:31 +00:00
Lendacky, Thomas
32928415e3 UefiCpuPkg/CpuExceptionHandler: Add missing comma to exception name array 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3373

An update to expand the mExceptionNameStr array failed to add a comma
after original last entry, therefore causing the #CP name to have extra
incorrect characters and the remaining entries to be indexed incorrectly
(off by 1).

Add a comma after the "#CP" entry to resolve this issue.

Fixes: 5277540e37
Cc: Allen Wynn <Allen_Wynn@Dell.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <40e55bf6563ed8ea4962a1219efbe1ab77a56cc4.1620919615.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-05-14 11:26:17 +00:00
Sergei Dmitrouk
d82c4693f8 OvmfPkg/VirtioFsDxe: suppress incorrect gcc warnings 
`CreateDirectoryIfCreating` is used only if `PermitCreation` is set.

`NewNodeIsDirectory` might not set in case of error, but that would lead
to leaving the function before invalid use.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Message-Id: <20210511225616.5942-3-sergei@posteo.net>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-05-14 10:00:13 +00:00
Sergei Dmitrouk
eec44cdd00 ShellPkg/UefiShellCommandLib: suppress incorrect gcc warning 
`Dupes` is used only if `Duplicates != NULL` and function is left if
allocation of memory for `Dupes` fails, so it can't be used
uninitialized.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Message-Id: <20210511225616.5942-2-sergei@posteo.net>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-05-14 10:00:13 +00:00
Sachin Agrawal
22ac5cc9d9 CryptoPkg: BaseCryptLib: Add RSA PSS verify support 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3314

This patch uses Openssl's EVP API's to perform RSASSA-PSS verification
of a binary blob.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
 2021-05-14 03:35:33 +00:00
Sughosh Ganu
5531fd48de BaseTools: Add support for version 3 of FMP Image Header structure 
Add support for the ImageCapsuleSupport field, introduced in version 3
of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This
structure member is used to indicate if the corresponding payload has
support for authentication and dependency.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-05-12 01:03:53 +00:00
Lendacky, Thomas
6933c78e4d UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385

A VS2012 build fails with a cast conversion warning when the SEV-ES work
area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.

When casting from a PCD value to a pointer, the cast should first be done
to a UINTN and then to the pointer. Update the code to perform a cast to
a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Fixes: 7b7508ad78
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <c89bc819856d448360430c32cb3833a9667f987b.1620656694.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-05-11 17:45:40 +00:00
Rebecca Cran
4e5ecdbac8 SecurityPkg: Add support for RngDxe on AARCH64 
AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.

Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-05-11 16:26:05 +00:00
Rebecca Cran
9301e5644c MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions 
Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that is a part of FEAT_RNG.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-05-11 16:26:05 +00:00
Michael D Kinney
ef3840c1ff BaseTools: Fix DSC override of Guided tool 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

If the DSC file provides an override of a Guided tool path
and/or Guided tool GUID value, then make sure the one from the
DSC file is used if it is higher priority than the Guided tool
in the tools_def.txt file.  This makes the Guided tool used by
GenFds match the tool listed GuidedSectionTools.txt.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-05-10 23:28:58 +00:00
Nicola Mazzucato
375f2d8e68 ArmPkg: Update SCMI Base Protocol version to 0x20000 
The SCP-firmware has moved to full support for SCMIv2 which means that
the base protocol can be either compliant with SCMI v1 or v2.

Allow any version between SCMI v1.0 and SCMI v2.0 to be compatible
with the current implementation.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Tested-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-05-10 15:46:42 +00:00
Getnat Ejigu
f297b7f200 UnitTestFrameworkPkg: Sample unit test hangs when running in OVMF/QEMU 
Sample unit tests in UnitTestFrameworkPkg hangs when running in OVMF/QEMU
environment. Build target is X64/GCC5. Fixing this issue by adding EFIAPI
to ReportPrint() function that use VA_ARGS.

Signed-off-by: Getnat Ejigu <getnatejigu@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2021-05-04 00:51:20 +00:00
Michael D Kinney
8c8f49f0dc BaseTools: Fix New Target/ToolChain/Arch in DSC [BuildOptions] issues 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

* Save/Restore global state in GetToolChainAndFamilyFromDsc()
  This resolves an issue where the multi-arch build for
  UefiPayloadPkg would skip the autogen and build of IA32
  components.
* Expand tools wildcard.
  This resolves the issue where autogen makefile contents
  would have a BUIDLRULEFAMILY tools definitions with an
  '*' in the tool field that breaks the build from invalid
  makefile syntax.
* Build rule family higher priority than Family.
  This resolves the issue where flags were appended from
  both the BUILDRULEFAMILY and FAMILY when only
  BUILDRULEFAMILY should be appended when present.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Steven Shi <steven.shi@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Andrew Fish <afish@apple.com>
 2021-05-03 18:16:23 +00:00
Lendacky, Thomas
1e6b0394d6 OvmfPkg/Tcg2ConfigPei: Update Depex for IA32 and X64 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

The OVMF Tcg2Config PEIM adds the gOvmfTpmMmioAccessiblePpiGuid as a
Depex for IA32 and X64 builds so that the MMIO range is properly mapped
as unencrypted for an SEV-ES guest before the Tcg2Config PEIM is loaded.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <d6538e6c557173d260e272a0e5659683175e2e06.1619716333.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-30 18:35:50 +00:00
Lendacky, Thomas
8e7edbbf5d OvmfPkg/TpmMmioSevDecryptPei: Mark TPM MMIO range as unencrypted for SEV-ES 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

During PEI, the MMIO range for the TPM is marked as encrypted when running
as an SEV guest. While this isn't an issue for an SEV guest because of
the way the nested page fault is handled, it does result in an SEV-ES
guest terminating because of a mitigation check in the #VC handler to
prevent MMIO to an encrypted address. For an SEV-ES guest, this range
must be marked as unencrypted.

Create a new x86 PEIM for TPM support that will map the TPM MMIO range as
unencrypted when SEV-ES is active. The gOvmfTpmMmioAccessiblePpiGuid PPI
will be unconditionally installed before exiting. The PEIM will exit with
the EFI_ABORTED status so that the PEIM does not stay resident. This new
PEIM will depend on the installation of the permanent PEI RAM, by
PlatformPei, so that in case page table splitting is required during the
clearing of the encryption bit, the new page table(s) will be allocated
from permanent PEI RAM.

Update all OVMF Ia32 and X64 build packages to include this new PEIM.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <42794cec1f9d5bc24cbfb9dcdbe5e281ef259ef5.1619716333.git.thomas.lendacky@amd.com>
[lersek@redhat.com: refresh subject line]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-30 18:35:50 +00:00
Lendacky, Thomas
a3f12cd471 OvmfPkg: Define a new PPI GUID to signal TPM MMIO accessability 
Define a new PPI GUID that is to be used as a signal of when it is safe
to access the TPM MMIO range. This is needed so that, when SEV is active,
the MMIO range can be mapped unencrypted before it is accessed.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <03e292339273721724c8b14605cfe9d7bbe45a71.1619716333.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-30 18:35:50 +00:00
Lendacky, Thomas
cc71bd9709 OvmfPkg/VmgExitLib: Add support for new MMIO MOV opcodes 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

Enabling TPM support results in guest termination of an SEV-ES guest
because it uses MMIO opcodes that are not currently supported.

Add support for the new MMIO opcodes (0xA0 - 0xA3), MOV instructions which
use a memory offset directly encoded in the instruction. Also, add a DEBUG
statement to identify an unsupported MMIO opcode being used.

Fixes: c45f678a1e
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <2fdde57707b52ae39c49341c9d97053aaff56e4a.1619716333.git.thomas.lendacky@amd.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-30 18:35:50 +00:00
Lendacky, Thomas
75d1a7903d OvfmPkg/VmgExitLib: Properly decode MMIO MOVZX and MOVSX opcodes 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

The MOVZX and MOVSX instructions use the ModRM byte in the instruction,
but the instruction decoding support was not decoding it. This resulted
in invalid decoding and failing of the MMIO operation. Also, when
performing the zero-extend or sign-extend operation, the memory operation
should be using the size, and not the size enumeration value.

Add the ModRM byte decoding for the MOVZX and MOVSX opcodes and use the
true data size to perform the extend operations. Additionally, add a
DEBUG statement identifying the MMIO address being flagged as encrypted
during the MMIO address validation.

Fixes: c45f678a1e
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <5949d54cb2c9ab69256f67ed5654b32654c0501c.1619716333.git.thomas.lendacky@amd.com>
 2021-04-30 18:35:50 +00:00
Michael D Kinney
ab957f036f BaseTools/Source/Python: New Target/ToolChain/Arch in DSC [BuildOptions] 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

Update BaseTools to support new build targets, new tool chains,
and new architectures declared in DSC file [BuildOptions] sections.

* Do not expand * when tools_def.txt is parsed.  Only expand when
  both tools_def.txt and DSC [BuilsOptions] sections have been parsed.
  This also requires more flexible matching of tool keys that contain *
  in tool key fields.

* Pre-scan the platform DSC file for FAMILY and TOOLCHAIN declarations
  DSC in [BuildOptions] sections before the FAMILY and TOOLCHAIN need
  to be known.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-29 07:29:17 +00:00
Michael D Kinney
612edbe6cd EmulatorPkg: Temp remove IA32 GCC CI builds 
EmulatorPkg IA32 GCC builds are not working due to a failure
to install the i386 library dependencies in Ubuntu 18.04.

Temporarily disable these specific CI tests until the issue
can be resolved.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
 2021-04-29 05:38:20 +00:00
Pierre Gondois
01c0ab90be AzurePipelines: Add support for ArmPlatformPkg 
Add an entry to build the ArmPlatformPkg in the CI.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3349
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
7c4f05dc05 AzurePipelines: Add support for ArmPkg 
Add an entry to build the ArmPkg in the CI.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3348
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
ec9683ec0f .pytool: Document LicenseCheck and EccCheck 
Add an entry in the documentation for the LicenseCheck and
EccCheck plugins.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
a4cf19597f .pytool: Enable CI for ArmPlatformPkg 
Enable the CI for the ArmPlatformPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
2942cb5815 .pytool: Enable CI for ArmPkg 
Enable the CI for the ArmPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
1cb1087749 ArmPlatformPkg: Add ArmPlatformPkg.ci.yaml 
Add ArmPlatformPkg.ci.yaml to configure the CI for the
ArmPlatformPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
f11252e9fd ArmPkg: Add ArmPkg.ci.yaml 
Add ArmPkg.ci.yaml to configure the CI for the
ArmPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
b8de64bede ArmPkg: Correct small typos 
The 'cspell' CI test detected some small typos in ArmPkg.
Correct them.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
c2bd8a1a82 ArmPkg: Add OemMiscLibNull library to ArmPkg.dsc 
Add the OemMiscLibNull library to the [Components] section of
ArmPkg.dsc, allowing to complete the 'DscCompleteCheck' CI test.

According to .pytool/Readme about the 'DscCompleteCheck' test:
The test considers it an error if any INF does not appear in the
`Components` section of the package-level DSC.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
a145d5f240 ArmPkg: Re-order libraries in ArmPkg.dec 
This patch alphabetically orders libraries advertised in ArmPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
3093c95de8 ArmPkg: Document libraries in ArmPkg.dec 
This patch documents the libraries advertised in ArmPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
ecfe47968e ArmPlatformPkg: Document libraries in ArmPlatformPkg.dec 
This patch documents the libraries advertised in ArmPlatformPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
d03f71dd8b ArmPkg: Add missing library headers to ArmPkg.dec 
Some library headers are missing/incorrect in ArmPkg.dec.
This makes the 'LibraryClassCheck' CI test fail. This patch
adds/corrects them.

According to .pytool/Readme about the 'LibraryClassCheck' test:
This test scans at all library header files found in the
`Library` folders in all of the package's declared include
directories and ensures that all files have a matching
LibraryClass declaration in the DEC file for the package.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3254
Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3258
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
fd9cc2052e ArmPkg: Fix Ecc error 3002 in StandaloneMmMmuLib 
This patch fixes the following Ecc reported error:
Non-Boolean comparisons should use a compare operator
(==, !=, >, < >=, <=)

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Pierre Gondois
cc15a619a6 ArmPkg: Fix Ecc error 8003 
This patch fixes the following Ecc reported error:
The #ifndef at the start of an include file should have
one postfix underscore, and no prefix underscore character

Some include guards have been modified to match the name of the
header file. Some comments have also been added on the closing
'#endif'.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-28 12:03:51 +00:00
Rebecca Cran
5b90b8abb4 ArmPkg: Fix typo of Manufacturer in comment in SmbiosMiscDxe 
'Manufacturer' was spelled wrongly in a comment in
MiscChassisManufacturerData.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
 2021-04-27 12:46:26 +00:00
Rebecca Cran
13f32d4a64 ArmPkg: Fix calculation of offset of chassis SKU Number in SmbiosMiscDxe 
The calculation of the chassis SKU number field was being calculated
incorrectly, forgetting that there's one element already present in
the structure.
Fix the calculation and improve code readability by introducing a
SkuNumberField variable.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
 2021-04-27 12:46:26 +00:00
Rebecca Cran
bbeb1bea41 ArmPkg: Allow platforms to report their boot status via OemMiscLib call 
Add a new function to OemMiscLib to allow platforms to report their boot
status into the Type32 SMBIOS table.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
 2021-04-27 12:46:26 +00:00
Rebecca Cran
bf2b99990e ArmPkg: Allow platforms to supply more data for SMBIOS Type3 record 
Add OemMiscLib calls to allow platforms to provide the following
information about the chassis:

o Bootup state
o Power supply/supplies state
o Thermal state
o Security state
o Chassis height (in RMU)
o Number of power cords

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
 2021-04-27 12:46:26 +00:00
Michael D Kinney
8d2012035d BaseTools/GenMake: Sort generated makefile tool definitions 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3353

Sort the tool definition content of generated makefiles to help
verify that makefile contents have not changed after BaseTools
code changes.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
 2021-04-27 05:56:39 +00:00
Jiaqi Gao
5396354b86 SecurityPkg: Add constraints on PK strength 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3293

Add constraints on the key strength of enrolled platform key(PK), which
must be greater than or equal to 2048 bit. PK key strength is required
by Intel SDL and MSFT, etc. This limitation prevents user from using
weak keys as PK.

The original code to check the certificate file type is placed in a new
function CheckX509Certificate(), which checks if the X.509 certificate
meets the requirements of encode type, RSA-Key strengh, etc.

Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>
Reviewed-by: Min Xu <min.m.xu@intel.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
 2021-04-26 16:24:32 +00:00
Michael D Kinney
f2f4c6be2d BaseTools/Source/Python: Verify TAB_TOD_DEFINES_FAMILY key present 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3344

Veify that TAB_TOD_DEFINES_FAMILY key is present in ToolDef
dictionary before access.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-23 18:55:51 +00:00
Erdem Aktas
61680cac5e Maintainers.txt: Add 'Erdem Aktas' to Confidential Computing reviewers 
Add 'Erdem Aktas' as a reviewer for OvmfPkg/Confidential Computing.

Signed-off-by: Erdem Aktas <erdemaktas@google.com>
Message-Id: <a557b66c92d3e44dcd02db7ee3800d1f9fef81b4.1619102863.git.erdemaktas@google.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Min M Xu <min.m.xu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-23 11:27:59 +00:00
Shi, Steven
d3b0d007a1 BaseTools: Add double quote around CLANG_BIN path string 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3341

Current CLANG_BIN env variable is set without double quote
around the LLVM default installation path string in windows,
which causes some CI build service cannot find the LLVM path
in windows.
This patch enhance it to add double quote around it.

Signed-off-by: Steven Shi <steven.shi@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-20 10:21:17 +00:00
Jason
0bbc207275 MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309

Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
(07h) data structure.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed: Ray Ni <ray.ni@intel.com>
 2021-04-20 01:27:58 +00:00
Kun Qin
c3dcbce26f UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3300

Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm
driver will check a global variable mPhysicalAddressBits, and eventually
cap any value larger than 39 at 39.

This global variable is used in ConvertMemoryPageAttributes, which backs
SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor
that supports more than 39 bits width, trying to mark page table regions
higher than 39-bit will always return EFI_UNSUPPROTED.

This change updated the interface of SetStaticPageTable function to take
PhysicalAddressBits as an input parameter, in order to avoid changing/
accessing the global variable.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Fixes: 4eee0cc7cc
Signed-off-by: Kun Qin <kuqin12@gmail.com>
 2021-04-20 00:32:24 +00:00
Michael D Kinney
64138c95db BaseTools/Conf/tools_def.template: Remove redundant MAKE statements 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3337

Remove redundant MAKE_PATH and MAKE_FLAGS statements for
VS20xx tool chains.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
 2021-04-19 18:06:50 +00:00
Joey Gouly
8c75a07208 DynamicTablesPkg: Set the Access size for the DBG2 table 
The DBG2 table generator set the access size for the UART to
DWORD (4 bytes) by default. However, according to Section B
Generic UART, Arm Base System Architecture 1.0, Platform
Design Document, a Generic UART can have BYTE, WORD or DWORD
access sizes. To address this an AccessSize field has been
introduced in CM_ARM_SERIAL_PORT_INFO object.

This patch updates the DBG2 generator to setup the AccessSize
field in the Generic Address Structure (GAS) for the UART in
the DBG2 table with information provided by the platform.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-19 13:28:26 +00:00
Joey Gouly
a300f2a3f5 DynamicTablesPkg: Set the Access size for the SPCR table 
The SPCR table generator set the access size for the UART to
DWORD (4 bytes) by default. However, according to Section B
Generic UART, Arm Base System Architecture 1.0, Platform
Design Document, a Generic UART can have BYTE, WORD or DWORD
access sizes. To address this an AccessSize field has been
introduced in CM_ARM_SERIAL_PORT_INFO object.

This patch updates the SPCR generator to setup the AccessSize
field in the Generic Address Structure (GAS) for the UART in
the SPCR table with information provided by the platform.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-19 13:28:26 +00:00
Joey Gouly
c8cf71ec9c DynamicTablesPkg: Add access size to CM_ARM_SERIAL_PORT_INFO 
Add access size to CM_ARM_SERIAL_PORT_INFO so that this can be
passed down to the Generic Address Structure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-19 13:28:26 +00:00
Joey Gouly
10bf6c40f6 ShellPkg: Rename Address Size to Access size 
This matches the ACPI spec 6.3, table 5.1: Generic Address Structure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-19 13:28:26 +00:00
Wenyi Xie
99e7e48cc7 SecurityPkg/FvReportPei: remove redundant sizeof 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3333

In function InstallPreHashFvPpi, when calculating the size
of struct HASH_INFO, sizeof is used twice. This bug does
not lead to buffer overflow, "sizeof (HASH_INFO)" is 4,
whereas "sizeof (sizeof (HASH_INFO))" is 4 or 8.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
 2021-04-16 08:39:59 +00:00
Abner Chang
9abc447b72 RedfishPkg: Add EDK2 Redfish Foundation diagrams 
The Readme.md to delineate the EDK2 Redfish foundation driver
stack diagrams.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Fan Wang <fan.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-16 04:12:16 +00:00
Pierre Gondois
96479947bc ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_PERFORMANCE 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
063f8483b9 ArmPkg: Fix Ecc error 8005 for SCMI_CLOCK_RATE_FORMAT 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
bd8efb4f8e ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_CLOCK 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
1f93d0c5a3 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_BASE 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
84262ca3d9 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
dc6c6397b8 ArmPkg: Fix Ecc error 8005 for SCMI_STATUS 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
68c1868565 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_TYPE 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
462f95ec5b ArmPkg: Fix Ecc error 8005 for SCMI_PROTOCOL_ID 
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
2f2c0a8b9f ArmPkg: Fix Ecc error 8005/8007 in ArmDisassemblerLib 
This patch fixes the following Ecc reported error:
8005:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

8007:
There should be no use of short (single character) variable names

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
60e49aac4e ArmPkg: Fix Ecc error 7008 for OPTEE_MESSAGE_PARAM 
This patch fixes the following Ecc reported error:
Complex types should be typedef-ed

The error is due to the a nested structure declaration.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
39b3e14c99 ArmPkg: Fix Ecc error 7008 for SCMI_CLOCK_RATE 
This patch fixes the following Ecc reported error:
Complex types should be typedef-ed

The error is due to the a nested structure declaration.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
3c0c1d3fae ArmPkg: Rename include guard in ArmGicLib.h 
Edk2 coding standard states that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
f21e72135d ArmPkg: Fix Ecc error 6001 in ArmSoftFloatLib 
This patch fixes the following Ecc reported error:
All include file contents should be guarded by
a #ifndef statement.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
152015fa65 ArmPkg: Fix Ecc error 6001 in MmCommunicationDxe 
This patch fixes the following Ecc reported error:
All include file contents should be guarded by
a #ifndef statement.

This patch replaces a "#if !defined [...]" statement
by a "#ifndef [...]" statement, preventing Ecc to
throw an error.

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
74b41d5648 ArmPkg: Fix Ecc error 5003 in ArmExceptionLib 
This patch fixes the following Ecc reported error:
Function name should be left justified,
followed by the beginning of the parameter list,
with the closing parenthesis on its own line,
indented two spaces

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
22693153d1 ArmPkg: Remove ArmGic/ArmGicSecLib.c 
Commit: 142fa386eb
removes the ArmGicSecLib. The file ArmGic/ArmGicSecLib.c
was exclusively used by this library. Thus, this file should
also be removed.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
11bd8e249f ArmPkg: Fix Ecc error 10014 in SemihostLib 
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Library/SemihostLib/SemihostPrivate.h]
is existing in module
ArmPkg/Library/SemihostLib/SemihostLib.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
29bf905976 ArmPkg: Fix Ecc error 10014 in MmCommunicationDxe 
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h]
is existing in module
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
a563c84779 ArmPkg: Fix Ecc error 10014 in GenericWatchdogDxe 
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h]
is existing in module
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
d9f0b84c1d ArmPkg: Fix Ecc error 10014 in ArmScmiDxe 
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h]
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h]
are existing in module
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
but are not described in INF the file.

The patch also re-orders the files in the
[Sources.common] section.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
aec0ce7ca8 ArmPkg: Fix Ecc error 10016 in StandaloneMmMmuLib 
This patch fixes the following Ecc reported error:
Module file has FILE_GUID collision with other
module file

The two .inf files with clashing GUID are:
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf

As ArmMmuBaseLib.inf is older than ArmMmuStandaloneMmLib.inf,
it has precedence.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
d892336899 ArmPkg: Fix Ecc error 10006 in ArmPkg.dsc 
This patch fixes the following Ecc reported error:
There should be no unnecessary inclusion of library
classes in the INF file

This comes with the additional information:
The Library Class [BootLogoLib]
is not used in any platform
The Library Class [DxeServicesLib]
is not used in any platform
The Library Class [UefiBootManagerLib]
is not used in any platform
The Library Class [PeCoffExtraActionLib]
is not used in any platform

ArmPkg/ArmPkg.dsc builds the modules requiring thses libraries,
but doesn't build the required libraries. This patch adds
the missing libraries to the [LibraryClasses.common] section.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
ea61e597e1 ArmPkg: Fix Ecc error 9005 in CpuDxe 
This patch fixes the following Ecc reported error:
Only Doxygen commands '@bug', '@todo', '@example', '@file',
'@attention', '@param', '@post', '@pre', '@retval', '@return',
'@sa', '@since', '@test', '@note', '@par', '@endcode', '@code',
'@{', '@}' are allowed to mark the code

This patch removes the ":" character following the "@param"
doxygen command.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
0fc54a6a55 ArmPkg: Fix Ecc error 8001 in ArmArchTimerLib 
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used for #define
declarations

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
b9d4976998 ArmPkg: Fix Ecc error 8001 in SemihostLib 
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
a4d95d7cf9 ArmPkg: Fix Ecc error 8001 in Chipset 
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard of ArmCortexA5x.h is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:53:39 +00:00
Pierre Gondois
8948fb0974 ArmPlatformPkg: Remove package dependency in NorFlashStandaloneMm 
The DependencyCheck available in .pytool detects an unnecessary
dependency of the NorFlashStandaloneMm.inf module over the
EmbeddedPkg package.
This patch removes this dependency.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Tested-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
 2021-04-15 19:24:14 +00:00
Pierre Gondois
890e6d466c ArmPlatformPkg: Fix Ecc error 9001 
This patch fixes the following Ecc reported error:
INF/DEC/DSC/FDF file header comment should begin
with "## @file" or "# @file" at the very top file

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:24:14 +00:00
Pierre Gondois
5a5440d0dc ArmPlatformPkg: Fix Ecc error 8001 
This patch fixes the following Ecc reported error:
File header doesn't exist File header comment missing
the ""Copyright""

Even though a copyright is present in the header file,
the leading '*' char prevents the Ecc tool from detecting it.
According to the edk2 coding specifcation, section 5.2.3
"File Heading", there should not be leading '*' char.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-15 19:24:14 +00:00
Michael D Kinney
3c13938079 BaseTools/Source/Python: Remove CPU architecture assumptions 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Remove build breaks in the following tools when a check against
a fixed set of CPU architectures is made.

* Build
* GenFds
* TargetTool

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-15 15:58:44 +00:00
Michael D Kinney
251f9b3906 BaseTools/Source/C: Remove CPU architecture assumptions 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Remove build breaks in the following tools when a check against
a fixed set of CPU architectures is made.

* GenFw

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-15 15:58:44 +00:00
Michael D Kinney
d0bf83e1cc CryptoPkg/Library/Include: Allow CPU specific defines to be predefined 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Update SIXTY_FOUR_BIT and THIRTY_TWO_BIT defines in the
CryptoPkg to allow one of them to be predefined on the EDK II
build command line using /D flag or in DSC file [BuildOptions]
sections.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
 2021-04-15 15:58:44 +00:00
Michael D Kinney
db2338af0d MdePkg/Include: Allow CPU specific defines to be predefined 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assumes a fixed set of CPU architectures.

Update EFI_REMOVABLE_MEDIA_FILE_NAME to allow it to be
predefined in tools_def.txt or a DSC file [BuildOptions]
section using a *_*_*_CC_FLAGS statement.

Add support for the following two defines.  If neither are
defines, then preserve the current behavior.  If either is
defined, then compare these 16-bit values to Machine in the
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) and
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) macros.

* EFI_IMAGE_MACHINE_TYPE_VALUE
* EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-15 15:58:44 +00:00
Abner Chang
7cc8cd7b58 RedfishPkg/RestJsonStructureDxe: Fix typo in function header 
In v2, BZ reference is added.

BZ#:3030
Fix the typo [in]/[out] of parameter DestroyStructure in
function header.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
 2021-04-15 07:33:32 +00:00
Michael D Kinney
2ad22420a7 UnitTestFrameworkPkg: Use TianoCore mirror of cmocka repository 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3301

The cmocka repository https://git.cryptomilk.org/projects/cmocka.git
has gone down a few times in past year.  When it is down, it blocks
EDK II CI.  A mirror of this repository has been created in the
TianoCore organization at https://github.com/tianocore/edk2-cmocka.git
and uses a GitHub Action to auto-sync changes from
https://git.cryptomilk.org/projects/cmocka.git.

* Update .gitmodules to use https://github.com/tianocore/edk2-cmocka.git
  instead of https://git.cryptomilk.org/projects/cmocka.git.

* Update README.rst to reference the COPYING file in
  https://github.com/tianocore/edk2-cmocka.git with the cmocka license.

* Update Azure Pipelines YML files to remove a temporary workaround that
  used an alternate GitHub mirror of cmocka.  With the workaround removed,
  EDK II CI always uses the TianoCore mirror of cmocka.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-14 17:28:46 +00:00
Michael D Kinney
c055be5b82 BaseTools/PlatformAutoGen: MAKE_FLAGS and MAKE_PATH fixes 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3312

Update parsing of MAKE_FLAGS in DSC [BuildOptions] sections
to split the flags into a list to be compatible with
running the make command using Popen().  Parsing MAKE_FLAGS
from tools_def.txt already uses _SplitOption().  This change
uses the same _SplitOption() method for MAKE_FLAGS from a
DSC [BuildOptions] section.

Also update the parsing of MAKE_PATH to support MAKE_PATH
from tools_def.txt or the DSC [BuildOptions] section.  MAKE_PATH
in DSC [BuildOptions] section is higher priority than MAKE_PATH
in tools_def.txt.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-04-14 16:28:41 +00:00
Takuto Naito
037090cb7c MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchain 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325

1. AsmReadMsr64() in X64/GccInlinePriv.c
AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead
returns False. This causes build error with the CLANG toolchain.

2. AsmWriteMsr64() in X64/GccInlinePriv.c
In the case that FilterBeforeMsrWrite changes Value and returns True,
The original Value, not the changed Value, is written to the MSR.
This behavior is different from the one of AsmWriteMsr64() in
X64/WriteMsr64.c for the MSFT toolchain.

Signed-off-by: Takuto Naito <naitaku@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-14 01:50:19 +00:00
Pierre Gondois
83876950ab DynamicTablesPkg: Remove EArmObjExtendedInterruptInfo 
The EArmObjExtendedInterruptInfo doesn't exist. Remove any reference
to this enum.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-13 14:14:49 +00:00
Pierre Gondois
cc00dbcb19 DynamicTablesPkg: Re-order GicItsIdentifierArray struct 
The structure is not correctly placed in the file. Move it
so it follows the EARM_OBJECT_ID enum order.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-13 14:14:49 +00:00
Anthony PERARD
71cdb91f31 OvmfPkg/OvmfXen: Set PcdFSBClock 
Update gEfiMdePkgTokenSpaceGuid.PcdFSBClock so it can have the correct
value when SecPeiDxeTimerLibCpu start to use it for the APIC timer.

Currently, nothing appear to use the value in PcdFSBClock before
XenPlatformPei had a chance to set it even though TimerLib is included
in modules run before XenPlatformPei.

XenPlatformPei doesn't use any of the functions that would use that
value. No other modules in the PEI phase seems to use the TimerLib
before PcdFSBClock is set. There are currently two other modules in
the PEI phase that needs the TimerLib:
- S3Resume2Pei, but only because LocalApicLib needs it, but nothing is
  using the value from PcdFSBClock.
- CpuMpPei, but I believe it only runs after XenPlatformPei

Before the PEI phase, there's the SEC phase, and SecMain needs
TimerLib because of LocalApicLib. And it initialise the APIC timers
for the debug agent. But I don't think any of the DebugLib that
OvmfXen could use are actually using the *Delay functions in TimerLib,
and so would not use the value from PcdFSBClock which would be
uninitialised.

A simple runtime test showed that TimerLib doesn't use PcdFSBClock
value before it is set.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-8-anthony.perard@citrix.com>
[lersek@redhat.com: cast Freq to UINT32 for PcdSet32S(), not for ASSERT()]
 2021-04-13 11:54:58 +00:00
Anthony PERARD
c75c640512 OvmfPkg/XenPlatformPei: Calibrate APIC timer frequency 
Calculate the frequency of the APIC timer that Xen provides.

Even though the frequency is currently hard-coded, it isn't part of
the public ABI that Xen provides and thus may change at any time. OVMF
needs to determine the frequency by an other mean.

Fortunately, Xen provides a way to determines the frequency of the
TSC, so we can use TSC to calibrate the frequency of the APIC timer.
That information is found in the shared_info page which we map and
unmap once done (XenBusDxe is going to map the page somewhere else).

The shared_info page is mapped at the highest physical address allowed
as it doesn't need to be in the RAM, thus there's a call to update the
page table.

The calculated frequency is only logged in this patch, it will be used
in a following patch.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-7-anthony.perard@citrix.com>
 2021-04-13 11:54:58 +00:00
Anthony PERARD
51e0bd28bb OvmfPkg/XenPlatformPei: Map extra physical address 
Some information available in a Xen guest can be mapped anywhere in
the physical address space and they don't need to be backed by RAM.
For example, the shared info page.

While it's easier to put those pages anywhere, it is better to avoid
mapping it where the RAM is. It might split a nice 1G guest page table
into 4k pages and thus reducing performance of the guest when it
accesses its memory. Also mapping a page like the shared info page and
then unmapping it or mapping it somewhere else would leave a hole in
the RAM that the guest would propably not be able to use anymore.

So the patch introduces a new function which can be used to 1:1
mapping of guest physical memory above 4G during the PEI phase so we
can map the Xen shared pages outside of memory that can be used by
guest, and as high as possible.

Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-6-anthony.perard@citrix.com>
 2021-04-13 11:54:58 +00:00
Anthony PERARD
9d6861494a OvmfPkg/IndustryStandard: Introduce PageTable.h 
We are going to use the page table structure in yet another place,
collect the types and macro that can be used from another module
rather than making yet another copy.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <20210412133003.146438-5-anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-13 11:54:58 +00:00
Anthony PERARD
896e689841 OvmfPkg/IndustryStandard/Xen: Apply EDK2 coding style to XEN_VCPU_TIME_INFO 
We are going to use new fields from the Xen headers. Apply the EDK2
coding style so that the code that is going to use it doesn't look out
of place.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-4-anthony.perard@citrix.com>
 2021-04-13 11:54:58 +00:00
Anthony PERARD
44ad51d6b1 MdePkg: Allow PcdFSBClock to by Dynamic 
We are going to want to change the value of PcdFSBClock at run time in
OvmfXen, so move it to the PcdsDynamic section.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-3-anthony.perard@citrix.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-13 11:54:58 +00:00
Anthony PERARD
29280c7084 OvmfPkg/XenResetVector: Silent a warning from nasm 
To avoid nasm generating a warning, replace the macro by the value
expected to be stored in eax.
  Ia32/XenPVHMain.asm:76: warning: dword data exceeds bounds

Reported-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-2-anthony.perard@citrix.com>
 2021-04-13 11:54:58 +00:00
Joey Gouly
16136f218d DynamicTablesPkg: add validation for PcdNonBsaCompliant16550SerialHid 
According to ACPI 6.4, 6.1.5 _HID states:

  - A valid PNP ID must be of the form "AAA####" where A is an uppercase
    letter and # is a hex digit.
  - A valid ACPI ID must be of the form "NNNN####" where N is an uppercase
    letter or a digit ('0'-'9') and # is a hex digit.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-04-13 10:38:14 +00:00
Michael Kubacki
54211ab10f SecurityPkg/Tcg2Smm: Initialize local Status variable 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3277

Initializes the Status variable in TcgMmReadyToLock().

Fixes a Clang build failure:
Tcg2Smm.c - SecurityPkg\Tcg\Tcg2Smm\Tcg2Smm.c:254:7: error:
variable 'Status' is used uninitialized whenever 'if'
condition is false [-Werror,-Wsometimes-uninitialized]

Initializing this variable is required to address a practical
scenario in which the return value of TcgMmReadyToLock() is
undefined based on conditional evaluation in the function.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Kun Qin <kun.q@outlook.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-04-13 01:57:43 +00:00
Bret Barkelew
f8e6bcb6e7 MdeModulePkg: Initialize temp variable in VarCheckPolicyLib 
DumpVariablePolicy() will return EFI_INVALID_PARAMETER if the Buffer
pointer is NULL and the indirect Size is anything but 0. Since this
TempSize was not being initialized it is very likely that this sequence
would not return the total buffer size as expected.

Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=3310

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-13 01:24:13 +00:00
Michael D Kinney
4b59b22fed BaseTools/Conf: Fix MAKE_FLAGS typos in tools_def.template 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3313

Change MAKE_FLAG to MAKE_FLAGS to match required name from
EDK II Build Specifications for VS20xx tool chains.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
 2021-04-12 18:51:29 +00:00
Kun Qin
a7d8e28b29 UefiCpuPkg: PiSmmCpuDxeSmm: Check buffer size before accessing 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3283

Current SMM Save State routine does not check the number of bytes to be
read, when it comse to read IO_INFO, before casting the incoming buffer
to EFI_SMM_SAVE_STATE_IO_INFO. This could potentially cause memory
corruption due to extra bytes are written out of buffer boundary.

This change adds a width check before copying IoInfo into output buffer.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210406195254.1018-2-kuqin12@gmail.com>
 2021-04-12 17:23:54 +00:00
Abner Chang
2072c22a0d RedfishPkg/RedfishConfigHandler: EDKII RedfishConfigHandler Protocol 
BZ:2919

The driver is used to manage EDK2 Redfish Configuration Handler
Protocol installed by EDK2 Redfish feature drivers.
This is the EDK2 Redfish client driver written based on the EDK2
Redfish foundation to initialize EDK2 Redfish feature drivers.

EDK2 Redfish feature drivers are used to provision/consume/update
the firmware owns Redfish properties during system power on
initialization.

RedfishConfigHandlerCommon.c has the common code for the driver
instances used in different EDK2 boot phases or used by different
driver models in the future contribution.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Fan Wang <fan.wang@intel.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
 2021-04-12 07:40:31 +00:00
Abner Chang
7e7b729f6c RedfishPkg/RedfishDiscoverDxe: EFI Redfish Discover Protocol 
BZ#:2906
EDK2 EFI Redfish Discover Protocol implementation. Refer to UEFI
spec 2.9 section 31.1.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Fan Wang <fan.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
 2021-04-12 07:02:23 +00:00
Lou, Yun
5eb2de2d98 UefiCpuPkg/CpuTimerLib: Update LIBRARY_CLASS of Base instance. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2832

Update LIBRARY_CLASS of BaseCpuTimerLib to remove the usage limitation,
otherwise the Base instance cannot be used in some types of modules.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-04-12 03:20:24 +00:00
Rebecca Cran
97336fdee4 ShellPkg: Fix smbiosview system enclosure type table 
The SystemEnclosureTypeTable in QueryTable.c contained a couple
of errors: value 0x10 is "Lunch Box" not "Main Server Chassis", and
the Sub Notebook value was repeated as 0x13 when that entry is for
"SubChassis". The entries in-between needed adjusted.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
 2021-04-12 02:19:39 +00:00
Sheng, W
efa7f4df0f UefiCpuPkg/PiSmmCpuDxeSmm: Support detect SMM shadow stack overflow 
Use SMM stack guard feature to detect SMM shadow stack overflow.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3280

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Roger Feng <roger.feng@intel.com>
 2021-04-09 05:33:35 +00:00
Ray Ni
bce0328431 UefiCpuPkg/MpInitLib: Consume MicrocodeLib to remove duplicated code 
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-04-09 01:43:18 +00:00
Ray Ni
83c7f8178b UefiPayloadPkg/UefiPayloadPkg.dsc: Consume MicrocodeLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
 2021-04-09 01:43:18 +00:00
Ray Ni
030f71dfc4 OvmfPkg: Add MicrocodeLib in DSC files. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
 2021-04-09 01:43:18 +00:00
Ray Ni
1a957f17bc UefiCpuPkg: Add MicrocodeLib for loading microcode 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-04-09 01:43:18 +00:00
Jason Lou
19d5bccc76 UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2832

1. Remove PEI instance(PeiCpuTimerLib).
PeiCpuTimerLib is currently designed to save time by getting CPU TSC
frequency from Hob. BaseCpuTimerLib is designed to calculate TSC frequency
by using CPUID[15h] each time.
The time it takes to find CpuCrystalFrequencyHob (about 2000ns) is much
longer than it takes to calculate TSC frequency with CPUID[15h] (about
450ns), which means using BaseCpuTimerLib to trigger a delay is more
accurate than using PeiCpuTimerLib, recommend to use BaseCpuTimerLib
instead of PeiCpuTimerLib.

2. Remove DXE instance(DxeCpuTimerLib).
DxeCpuTimerLib is designed to calculate TSC frequency with CPUID[15h] in
its constructor function, then save it in a global variable. For this
design, once the driver containing this instance is running, this
constructor function is called, it will take extra time to calculate TSC
frequency.
The time it takes to get TSC frequency from global variable is shorter
than it takes to calculate TSC frequency with CPUID[15h], but 450ns is a
short time, the impact on the platform is very limited.
In addition, in order to simplify the code, recommend to use
BaseCpuTimerLib instead of DxeCpuTimerLib.

I did some experiments on one server platform and collected following data:
1. Average time required to find CpuCrystalFrequencyHob: about 2000 ns.
2. Average time required to find the last Hob: about 2700 ns.
2. Average time required to calculate TSC frequency: about 450 ns.

Reference code:
    //
    // Calculate average time required to find Hob.
    //
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - GetFirstGuidHob (1000 cycles)\n"));
    Ticks1 = AsmReadTsc();
    for (i = 0; i < 1000; i++) {
      GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);
    }
    Ticks2 = AsmReadTsc();

    if (GuidHob == NULL) {
      DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - CpuCrystalFrequencyHob can not be found!\n"));
    } else {
      DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - Average time required to find Hob = %d ns\n", \
          DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));
    }

    //
    // Calculate average time required to calculate CPU frequency.
    //
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - CpuidCoreClockCalculateTscFrequency (1000 cycles)\n"));
    Ticks1 = AsmReadTsc();
    for (i = 0; i < 1000; i++) {
      Freq = CpuidCoreClockCalculateTscFrequency ();
    }
    Ticks2 = AsmReadTsc();
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - Average time required to calculate TSC frequency = %d ns\n", \
        DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-04-09 01:00:22 +00:00
Dandan Bi
dc4d42302c MdePkg/Baseib: Filter/trace MSR access for IA32/X64 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-04-08 02:02:57 +00:00
Dandan Bi
38c8be123a MdePkg/IoLib: Filter/trace port IO/MMIO access 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-04-08 02:02:57 +00:00
Michael D Kinney
9c08b3e7d5 MdeModulePkg/PiDxeS3BootScriptLib: Rename mAcpiS3Enable to avoid dup symbol 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3297

Rename the global variable mAcpiS3Enable to mS3BootScriptAcpiS3Enable
to avoid duplicate symbol errors from CLANGPDB tool change when
PiDxeS3BootScriptLib from the MdeModulePkg is linked with PiSmmCpuDxeSmm
from the UefiCpuPkg.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-04-07 16:10:59 +00:00
Jiaxin Wu
4ac0296201 MdePkg/BaseLib: Add support for the XSETBV instruction 
*v2: refine the coding format.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.

Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509ab

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-06 00:43:49 +00:00
Michael D Kinney
f95cdd316c CryptoPkg: Simplify DSC by using UnitTestFrameworkPkgTarget.dsc.inc 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3288

Simplify the DSC file by using the library mappings from
UnitTestFrameworkPkgTarget.dsc.inc to build the CryptoPkg
target based unit tests that run from the UEFI Shell.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2021-04-03 01:54:22 +00:00
Michael D Kinney
8c89229885 CryptoPkg/Private/Protocol/Crypto.h: Remove duplicate function type 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3287

Remove duplicate declaration of the function prototype
EDKII_CRYPTO_RSA_GET_PUBLIC_KEY_FROM_X509.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-01 23:16:31 +00:00
Michael D Kinney
8c10a2c014 MdePkg/Include/Protocol: EFI_RESET_NOTIFICATION_PROTOCOL duplicate 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3286

Remove duplicate declaration of structure type
EFI_RESET_NOTIFICATION_PROTOCOL from ResetNotification.h.  The
forward declaration of the top of this file already declared
this type.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-01 23:16:31 +00:00
Michael D Kinney
32976569af MdePkg/Include/Protocol: EFI_HII POPUP_PROTOCOL duplicate declaration 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3285

Remove duplicate declaration of structure type
EFI_HII_POPUP_PROTOCOL from HiiPopup.h.  The forward
declaration of the top of this file already declared
this type.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-04-01 23:16:31 +00:00
Dandan Bi
62bad17dca UnitTestFrameworkPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
08c65f7c4d UefiPayloadPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
3c3a0dd9d7 UefiCpuPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
349cd45b5f StandaloneMmPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
42a492fb3e SourceLevelDebugPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
df79bfb87b SignedCapsulePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
25b77b5090 ShellPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
0d03ffc766 SecurityPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
d2263c06c9 RedfishPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
389b3b83e4 PcAtChipsetPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
d4ab7201f2 OvmfPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
d04b47962d NetworkPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
821e042f42 MdePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
e0df328f6f MdeModulePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
2b46d175cb IntelFsp2WrapperPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
2ee287b9fd IntelFsp2Pkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
8e03191dde FmpDevicePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
8cb0edc689 FatPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
991c898775 EmulatorPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
edc37612f7 EmbeddedPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
e2158c4a09 DynamicTablesPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
ae25aeaf55 CryptoPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
c8a5d99302 ArmVirtPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-31 05:47:10 +00:00
Dandan Bi
96afc54688 ArmPlatformPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
83d4afa4db ArmPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
 2021-03-31 05:47:10 +00:00
Dandan Bi
98ff7e3c63 MdePkg: Add MdeLibs.dsc.inc file to MdePkg 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc is added for some default libraries provided by MdePkg.
Platform can include MdeLibs.dsc.inc file to avoid some potential
incompatible changes to platform dsc file in future.

Only add RegisterFilterLib into it as the first version of MdeLibs.dsc.inc.
Can update and maintain MdeLibs.dsc.inc gradually later.

"MdeLibs.dsc.inc" for the [LibraryClasses*] section(s)

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-30 12:48:30 +00:00
Dandan Bi
1c11e7a214 MdePkg: Add RegisterFilterLib class and NULL instance 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

1. Add a new library class (RegisterFilterLib) to filter
and trace port IO/MMIO/MSR access.
2. Add a NULL instance (RegisterFilterLibNull) can be used
to keep current behavior.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
 2021-03-30 12:48:30 +00:00
Abner Chang
b33cf5bfcb ShellPkg/UefiHandleParsingLib: Support EFI Redfish protocols 
Add handle parsing for EFI Redfish Discover protocol.
Add handle parsing for EFI RestEx protocol.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Peter O'Hanley <peter.ohanley@hpe.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-26 02:56:22 +00:00
Abner Chang
fe66288873 MdePkg/Include: EFI Redfish Discover protocol 
Move GUID definition of EFI Redfish Discover protocol
to under MdePkg. With this we don't have dependency of
RedfishPkg in ShellPkg.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Peter O'Hanley <peter.ohanley@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-26 02:56:22 +00:00
Ankur Arora
4bf2a5b045 MdePkg: use CpuPause() in CpuDeadLoop() 
CpuPause() might allow the CPU to go into a lower power state
state while we spin.

On X86, CpuPause() executes a PAUSE instruction which the Intel
and AMD specs describe as follows:

Intel:
  "PAUSE: An additional function of the PAUSE instruction is to reduce
  the power consumed by a processor while executing a spin loop. A
  processor can execute a spin-wait loop extremely quickly, causing the
  processor to consume a lot of power while it waits for the resource it
  is spinning on to become available. Inserting a pause instruction in a
  spin-wait loop greatly reduces the processor?s power consumption."

AMD:
  "PAUSE: Improves the performance of spin loops, by providing a hint to
  the processor that the current code is in a spin loop. The processor
  may use this to optimize power consumption while in the spin loop.
  Architecturally, this instruction behaves like a NOP instruction."

On RISC-V and ARM64, CpuPause() executes a NOP, which is no worse than
the tight loop we have.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-25 03:40:17 +00:00
Ni, Ray
30691a4b40 UefiCpuPkg/SmmCommunication: Remove out-dated comments 
The comments in PiSmmCommunicationPei.c describe the whole memory
layout of the SMRAM regarding the SMM communication.

But SHA-1: 8b1d149390
PiSmmCommunicationSmm: Deprecate SMM Communication ACPI Table
removed the code that produces the ACPI Table.

This change updates the accordingly comments.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-25 02:34:29 +00:00
Liming Gao
aa75965349 MdeModulePkg: Initialize local variable value before they are used 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
This change is to fix the false compiler error on GCC49 release build.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-25 01:54:46 +00:00
Ross Burton
f037af6ecb OvmfPkg: strip build paths in release builds 
GenFw will embed a NB10 section which contains the path to the input file,
which means the output files have build paths embedded in them.  To reduce
information leakage and ensure reproducible builds, pass --zero in release
builds to remove this information.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3256
Signed-off-by: Ross Burton <ross.burton@arm.com>
Message-Id: <20210324115819.605436-1-ross.burton@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-24 22:07:32 +00:00
Liu Wei
0ecdcb6142 CryptoPkg/OpensslLib: Upgrade OpenSSL to 1.1.1j 
Update openssl from 1.1.1g to 1.1.1j. Current OpenSSL version
1.1.1g contains the vulnerabilities of CVE-2021-23841 and
CVE-2021-23840. The related vulnerable API EVP_DecryptUpdate
are used in drivers.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3266

Besides, the opensslconf.h automatically generated by process_files.pl.
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Liu Wei <weix.c.liu@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
 2021-03-23 05:37:56 +00:00
VincentX Ke
3d0df0f076 ShellPkg/Pci: Add valid check for PCI extended config space parser 
Bugzilla: 3262 (https://bugzilla.tianocore.org/show_bug.cgi?id=3262)

No need to print PCIe details while CapabilityId is 0xFFFF.
Limit the NextCapabilityOffset to PCI configuration space.

Signed-off-by: VincentX Ke <vincentx.ke@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
 2021-03-22 01:37:30 +00:00
Martin Radev
ca31888271 OvmfPkg/X86QemuLoadImageLib: Handle allocation failure for CommandLine 
The CommandLine and InitrdData may be set to NULL if the provided
size is too large. Because the zero page is mapped, this would not
cause an immediate crash but can lead to memory corruption instead.
This patch just adds validation and returns error if either allocation
has failed.

Signed-off-by: Martin Radev <martin.b.radev@gmail.com>
Message-Id: <YFPJsaGzVWQxoEU4@martin-ThinkPad-T440p>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
[lersek@redhat.com: drop unnecessary empty line from code; remove personal
 (hence likely unstable) repo reference from commit message]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-19 18:13:51 +00:00
Laszlo Ersek
eb07bfb09e Maintainers: rename the OVMF SEV subsystem to "Confidential Computing" 
The implementation of Intel TDX for OVMF has begun (TianoCore#3249).
Generalize the OVMF SEV section in "Maintainers.txt" to "Confidential
Computing". Add Jiewen Yao and Min Xu to the list of reviewers. Sort the
reviewer list alphabetically, for easier extension in the future.

After the rename, restore the alphabetical ordering between subsystem
titles in "Maintainers.txt".

TDX-related pathnames should be listed in this subsystem (with "F:"
patterns) in the future.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3249
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210310185649.19801-3-lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: James Bottomley <jejb@linux.ibm.com>
Acked-by: Min Xu <min.m.xu@intel.com>
 2021-03-18 17:12:02 +00:00
Laszlo Ersek
87a80dc4f2 Maintainers: refresh the OVMF SEV subsystem after TianoCore #2198 and #3077 
Tom added initial SEV-ES support (tracked under TianoCore#2198) in commit
range 7f7f511c5a74..7f0b28415cb4. The last commit in that range created
the "OvmfPkg: SEV-related modules" section in "Maintainers.txt".

However, we didn't list the "OvmfPkg/ResetVector" module, which had
received significant updates, enabling QEMU to learn details about the
firmware, from parsing the flash image. The SEC phase of OVMF
("OvmfPkg/Sec") gained a new responsibility as well (#VC exception
handling). List both modules now.

James introduced the remote attested / encrypted boot OVMF platform (under
TianoCore#3077) in commit range ef3e73c6a0c0..01726b6d23d4. This work
further extended "OvmfPkg/ResetVector", and added:

  OvmfPkg/AmdSev/
  OvmfPkg/Include/Guid/ConfidentialComputingSecret.h
  OvmfPkg/Library/PlatformBootManagerLibGrub/

List these too in the "OvmfPkg: SEV-related modules" section, and
designate James as a reviewer.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3077
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210310185649.19801-2-lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: James Bottomley <jejb@linux.ibm.com>
Acked-by: Min Xu <min.m.xu@intel.com>
 2021-03-18 17:12:02 +00:00
Jiaxin Wu
9fd7e88c23 MdePkg: Support standalone MM Driver Unload capability 
https://bugzilla.tianocore.org/show_bug.cgi?id=3240

This patch is to support standalone MM Driver Unload capability
by providing _DriverUnloadHandler() function.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-18 04:16:21 +00:00
Mars CC Lin
f9c53a69ed ShellPkg/SmbiosView: add more items for smbiosview -t 3 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3177
Add ContainedElementCount, ContainedElementRecordLength and
ContainedElements for smbiosview type 3.

Signed-off-by: Mars CC Lin <mars_cc_lin@phoenix.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Philippe Mathieu-Daude <philmd@redhat.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
 2021-03-18 03:10:45 +00:00
Pierre Gondois
ce6c2b0016 BaseTools/Ecc: Make Ecc only check first include guard 
The Ecc tool checks the format of the include guard. This check is
currently done on all the names following the '#ifndef' statement.
It should only be done on the first include guard.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3252
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-03-18 02:04:18 +00:00
Ray Ni
313d86c956 UefiCpuPkg/CpuDxe: Guarantee GDT is below 4GB 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3233

GDT needs to be allocated below 4GB in 64bit environment
because AP needs it for entering to protected mode.
CPU running in big real mode cannot access above 4GB GDT.

But CpuDxe driver contains below code:
  gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
  .....
  gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;

The AllocateRuntimePool() may allocate memory above 4GB.
Thus, we cannot use AllocateRuntimePool (), instead,
we should use AllocatePages() to make sure GDT is below 4GB space.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-18 01:11:23 +00:00
Ray Ni
773b0bc283 UefiCpuPkg/CpuDxe: Rename variables to follow EDKII coding standard 
The change doesn't impact any functionality.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-18 01:11:23 +00:00
Ray Ni
030ba3097a UefiCpuPkg/MpInitLib: avoid printing debug messages in AP 
MpInitLib contains a function MicrocodeDetect() which is called by
all threads as an AP procedure.
Today this function contains below code:

    if (CurrentRevision != LatestRevision) {
      AcquireSpinLock(&CpuMpData->MpLock);
      DEBUG ((
        EFI_D_ERROR,
        "Updated microcode signature [0x%08x] does not match \
        loaded microcode signature [0x%08x]\n",
        CurrentRevision, LatestRevision
        ));
      ReleaseSpinLock(&CpuMpData->MpLock);
    }

When the if-check is passed, the code may call into PEI services:
1. AcquireSpinLock
   When the PcdSpinTimeout is not 0, TimerLib
   GetPerformanceCounterProperties() is called. And some of the
   TimerLib implementations would get the information cached in
   HOB. But AP procedure cannot call PEI services to retrieve the
   HOB list.

2. DEBUG
   Certain DebugLib relies on ReportStatusCode services and the
   ReportStatusCode PPI is retrieved through the PEI services.
   DebugLibSerialPort should be used.
   But when SerialPortLib is implemented to depend on PEI services,
   even using DebugLibSerialPort can still cause AP calls PEI
   services resulting hang.

It causes a lot of debugging effort on the platform side.

There are 2 options to fix the problem:
1. make sure platform DSC chooses the proper DebugLib and set the
   PcdSpinTimeout to 0. So that AcquireSpinLock and DEBUG don't call
   PEI services.
2. remove the AcquireSpinLock and DEBUG call from the procedure.

Option #2 is preferred because it's not practical to ask every
platform DSC to be written properly.

Following option #2, there are two sub-options:
2.A. Just remove the if-check.
2.B. Capture the CurrentRevision and ExpectedRevision in the memory
     for each AP and print them together from BSP.

The patch follows option 2.B.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-17 12:39:31 +00:00
Lou, Yun
e4ff3773b7 UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Support collecting cache associative type in CpuCacheInfoLib.
This prevents the user from using additional code to obtain the
same information.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-17 11:27:39 +00:00
Chandramohan Akula
2e51b27fed MdePkg/UefiLib: Correct the arguments passed to IsLanguageSupported() 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3211

Correct the arguments passed to the IsLanguageSupported() function in
AddUnicodeString2() and LookupUnicodeString2() as expected by the function

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chandramohan Akula <chandramohan.akula@broadcom.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-17 01:42:43 +00:00
Matthew Carlson
66a31de7ee EmbeddedPkg/PrePiHobLib: replace duplicate GUID 
Currently there is a duplicate GUID shared by two INFs.
This rolls the INF for the PrePiHobLib.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2381
Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
 2021-03-16 20:41:18 +00:00
Ankur Arora
f3bdfc4186 OvmfPkg/SmmControl2Dxe: negotiate CPU hot-unplug 
Advertise OVMF support for CPU hot-unplug and negotiate it
if QEMU requests the feature.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-11-ankur.a.arora@oracle.com>
[lersek@redhat.com: preserve the empty line between the ICH9_LPC_SMI_F_*
 group of macro definitions and the SCRATCH_BUFFER type definition]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
f053288863 OvmfPkg/CpuHotplugSmm: do actual CPU hot-eject 
Add logic in EjectCpu() to do the actual the CPU ejection.

On the BSP, ejection happens by first selecting the CPU via
its QemuSelector and then sending the QEMU "eject" command.
QEMU in-turn signals the remote VCPU thread which context-switches
the CPU out of the SMI handler.

Meanwhile the CPU being ejected, waits around in its holding
area until it is context-switched out. Note that it is possible
that a slow CPU gets ejected before it reaches the wait loop.
However, this would never happen before it has executed the
"AllCpusInSync" loop in SmiRendezvous().
It can mean that an ejected CPU does not execute code after
that point but given that the CPU state will be destroyed by
QEMU, the missed cleanup is no great loss.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-10-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: unneeded inner QemuSelector declaration in EjectCpu()
 triggers VS warning #4456 (local variable shadowed); remove it]
 2021-03-16 13:21:46 +00:00
Ankur Arora
30c69d2cfa OvmfPkg/CpuHotplugSmm: add EjectCpu() 
Add EjectCpu(), which handles the CPU ejection, and provides a holding
area for said CPUs. It is called via SmmCpuFeaturesRendezvousExit(),
at the tail end of the SMI handling.

Also UnplugCpus() now stashes QEMU Selectors of CPUs which need to be
ejected in CPU_HOT_EJECT_DATA.QemuSelectorMap. This is used by
EjectCpu() to identify CPUs marked for ejection.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-9-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
af9c77e151 OvmfPkg/SmmCpuFeaturesLib: call CPU hot-eject handler 
Call the CPU hot-eject handler if one is installed. The condition for
installation is (PcdCpuMaxLogicalProcessorNumber > 1), and there's
a hot-unplug request.

The handler is called from SmmCpuFeaturesRendezvousExit(), which is
in-turn called at the tail-end of SmiRendezvous() after the BSP has
signalled an SMI exit via the "AllCpusInSync" loop.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-8-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
b6d5996706 OvmfPkg/SmmCpuFeaturesLib: init CPU ejection state 
Init CPU_HOT_EJECT_DATA, which will be used to share CPU ejection
state between SmmCpuFeaturesLib (via PiSmmCpuDxeSmm) and CpuHotPlugSmm.

The init happens via SmmCpuFeaturesSmmRelocationComplete(), and so it
will run as part of the PiSmmCpuDxeSmm entry point function,
PiCpuSmmEntry(). Once inited, CPU_HOT_EJECT_DATA is exposed via
PcdCpuHotEjectDataAddress.

The CPU hot-eject handler (CPU_HOT_EJECT_DATA->Handler) is setup when
there is an ejection request via CpuHotplugSmm.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-7-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
8ade9d425a OvmfPkg: define CPU_HOT_EJECT_DATA 
Define CPU_HOT_EJECT_DATA and add PCD PcdCpuHotEjectDataAddress, which
will be used to share CPU ejection state between OvmfPkg/CpuHotPlugSmm
and PiSmmCpuDxeSmm.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-6-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
15e6ae8ea4 OvmfPkg/CpuHotplugSmm: introduce UnplugCpus() 
Introduce UnplugCpus() which maps each APIC ID being unplugged
onto the hardware ID of the processor and informs PiSmmCpuDxeSmm
of removal by calling EFI_SMM_CPU_SERVICE_PROTOCOL.RemoveProcessor().

With this change we handle the first phase of unplug where we collect
the CPUs that need to be unplugged and mark them for removal in SMM
data structures.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-5-ankur.a.arora@oracle.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
2d92e052c3 OvmfPkg/CpuHotplugSmm: add Qemu Cpu Status helper 
Add QemuCpuhpWriteCpuStatus() which will be used to update the QEMU
CPU status register. On error, it hangs in a similar fashion as
other helper functions.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-4-ankur.a.arora@oracle.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
a752dd0746 OvmfPkg/CpuHotplugSmm: collect hot-unplug events 
Process fw_remove events in QemuCpuhpCollectApicIds(), and collect APIC IDs
and QEMU CPU Selectors for CPUs being hot-unplugged.

In addition, we now ignore CPUs which only have remove set. These
CPUs haven't been processed by OSPM yet.

This is based on the QEMU hot-unplug protocol documented here:
  https://lore.kernel.org/qemu-devel/20201204170939.1815522-3-imammedo@redhat.com/

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-3-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-16 13:21:46 +00:00
Ankur Arora
0cb242e336 OvmfPkg/CpuHotplugSmm: refactor hotplug logic 
Refactor CpuHotplugMmi() to pull out the CPU hotplug logic into
ProcessHotAddedCpus(). This is in preparation for supporting CPU
hot-unplug.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-2-ankur.a.arora@oracle.com>
 2021-03-16 13:21:46 +00:00
Abner Chang
4751a48aeb RedfishPkg/Library: RedfishLib 
EDK2 port of DMTF libredfish project. We clone the necessary files
from open source project libredfish (https://github.com/DMTF/
libredfish) tag v1.0.0 and revise it to incorporate with edk2
firmware code base.

The reason of cloning the necessary files instead of using extern
submodule of libredfish project:
libredfish as a C library which is executed under Windows and
Linux. It could be binded with other programming languages such as
java and python. The library uses curl library as the communication service with Redfish, which is not easy to be abstracted and
replaced with EFI specific protocols (e.g. EFI_REST_EX_PROTOCOL or
payload encode/decode library) and EFI data types. We had the
conversation with DMTF community and they think edk2 is a firmware
solution but not the programming language,
therefore they rejected to have edk2 as a binding to libredfish.
According to above, we decide to clone the necessary files from
libredfish modify it to incorporate with edk2.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Ting Ye <ting.ye@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Fan Wang <fan.wang@intel.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
 2021-03-11 08:44:51 +00:00
Ray Ni
54ba08c6b6 UefiCpuPkg/PiSmmCpu: Don't allocate Token for SmmStartupThisAp 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3199

When Token points to mSmmStartupThisApToken, this routine is called
from SmmStartupThisAp() in non-blocking mode due to
PcdCpuSmmBlockStartupThisAp == FALSE.

In this case, caller wants to startup AP procedure in non-blocking
mode and cannot get the completion status from the Token because there
is no way to return the Token to caller from SmmStartupThisAp().
Caller needs to use its specific way to query the completion status.

There is no need to allocate a token for such case so the 3 overheads
can be avoided:
1. Call AllocateTokenBuffer() when there is no free token.
2. Get a free token from the token buffer.
3. Call ReleaseToken() in APHandler().

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-11 01:44:51 +00:00
Michael Kubacki
edd46cd407 UefiCpuPkg/SmmCpuFeaturesLib: Add Standalone MM support 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3218

Adds an INF for StandaloneMmCpuFeaturesLib, which supports building
the SmmCpuFeaturesLib code for Standalone MM. Minimal code changes
are made to allow reuse of existing code for Standalone MM.

The original INF file names are left intact (continue to use SMM
terminology) to retain backward compatibility with platforms that
use those INFs. Similarly, the pre-existing C file names are
unchanged to be consistent with the INF file names.

Note that all references in library source files to PiSmm.h have
been changed to PiMm.h for consistency.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Message-Id: <20210217213227.1277-6-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-08 18:07:32 +00:00
Michael Kubacki
e542e05d4f UefiCpuPkg/SmmCpuFeaturesLib: Abstract PcdCpuMaxLogicalProcessorNumber 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3218

Adds a new function called GetCpuMaxLogicalProcessorNumber() to
return the number of maximum CPU logical processors (currently
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber).

This allows the the mechanism used to retrieve the CPU maximum
logical processor number to be abstracted from the logic that
needs the value.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-5-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
 2021-03-08 18:07:32 +00:00
Michael Kubacki
2002e950ea UefiCpuPkg/SmmCpuFeaturesLib: Cleanup library constructors 
There's currently two library instances:
  1. SmmCpuFeaturesLib
  2. SmmCpuFeaturesLibStm

There's two constructor functions:
  1. SmmCpuFeaturesLibConstructor()
  2. SmmCpuFeaturesLibStmConstructor()

SmmCpuFeaturesLibConstructor() is called by
SmmCpuFeaturesLibStmConstructor() since the functionality in that
function is required by both library instances.

The declaration for SmmCpuFeaturesLibConstructor() is embedded in
"SmmStm.c" instead of being declared in a header file. Further,
that constructor function is called by the STM specific constructor.

This change moves the common code to a function called
CpuFeaturesLibInitialization() which is declared in an internal
library header file "CpuFeaturesLib.h". Each constructor simply
calls this function to perform the common functionality.

Additionally, SmmCpuFeaturesLibConstructor() is moved from
SmmCpuFeaturesLibNoStm.c into a instance-specific file allowing
SmmCpuFeaturesLibNoStm.c to contain no STM implementation agnostic
to a particular library instance.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-4-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
 2021-03-08 18:07:32 +00:00
Michael Kubacki
61dc3b3399 UefiCpuPkg/SmmCpuFeaturesLib: Rename SmmCpuFeaturesLib.c 
This change renames SmmCpuFeaturesLib.c to SmmCpuFeaturesLibCommon.c
to better convey that this file contains library implementation
common to all library instances.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Message-Id: <20210217213227.1277-3-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
 2021-03-08 18:07:32 +00:00
Michael Kubacki
3e062ea498 UefiCpuPkg/SmmCpuFeaturesLib: Move multi-instance function decl to header 
FinishSmmCpuFeaturesInitializeProcessor() is a multi-instance
internal library function that is currently not declared in a
header file but embedded in "SmmCpuFeaturesLib.c".

This change cleans up the declaration moving it to a new header
file "CpuFeaturesLib.h" and removing the local declaration in
"SmmCpuFeaturesLib.c".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-2-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
[lersek@redhat.com: replace the guard macro "_CPU_FEATURES_LIB_H_" with
 "CPU_FEATURES_LIB_H_", for fixing ECC 8003, per commit 6ffbb3581a]
 2021-03-08 18:07:32 +00:00
Rebecca Cran
94fa95c874 EmbeddedPkg: Only print LibGetTime message about compile time epoch once 
The message "LibGetTime: RtcEpochSeconds non volatile variable was not
found - Using compilation time epoch." can be printed a very large
number of times, causing log files to become excessively large. This is
because the RtcEpochSeconds variable only gets set if LibSetTime is
called, for example by running 'time 12:00' in the UEFI Shell.

Avoid this by setting RtcEpochSeconds to BUILD_EPOCH (EpochSeconds)
after printing the message. It's set to a volatile variable so the
message will be displayed on future boots and not hidden.

Commit 44ae214591 reduced the verbosity of
the message to DEBUG_VERBOSE. Revert it back to DEBUG_INFO so it's more
prominent now that it doesn't get printed so frequently.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
 2021-03-08 12:28:20 +00:00
Yuwei Chen
d28a681534 BaseTools: Modify struct parser for StructPcd 
Currently the struct parser for StructPcd Generation does not
filter the types such as UINT8 which should be ignored successfully.
This patch modifies this issue.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-03-08 04:01:55 +00:00
Chen, Christine
dd6c0a0ba3 BaseTools: Adjust StructurePcd List Order. 
Currently StructurePcd.dsc have the list order issue. For a Pcd
with several elements, the list indexs are used to distinguish
these elements like this:

PcdName.name.offset_name[0]|0x0
PcdName.name.offset_name[10]|0x0
PcdName.name.offset_name[11]|0x0
...
PcdName.name.offset_name[2]|0x0
...

However, the index is not strictly sorted by decimal numerical order,
which is not user friendly. One more sort rule for index is added to
the current rules to support for decimal numerical order in this patch.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
 2021-03-08 03:14:35 +00:00
Ray Ni
8c61f1934d UefiCpuPkg/MpInitLib: Remove unused Lock from MP_CPU_EXCHANGE_INFO 
The Lock is no longer needed since "LOCK XADD" was used in
MpFuncs.nasm for ApIndex atomic increment.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-08 02:22:37 +00:00
Ray Ni
2fba7d4ee4 UefiCpuPkg/MpInitLib: Use NASM struc to avoid hardcode offset 
In Windows environment, "dumpbin /disasm" is used to verify the
disassembly before and after using NASM struc doesn't change.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2021-03-08 02:22:37 +00:00
Ray Ni
e59760f87e MdePkg/Nasm.inc: add macros for C types used in structure definition 
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
 2021-03-08 02:22:37 +00:00
Bret Barkelew
b8a92fa2fe BaseTools: Update the NASM CI dependency 
Update the external dependency (consumed by Edk2Tools) version for NASM,
as agreed in recent community meetings:
https://edk2.groups.io/g/devel/message/71289
https://edk2.groups.io/g/devel/message/71070

This is primarily used by CI builds, but may also be used by platforms.

Signed-off-by: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2021-03-08 01:33:44 +00:00
Kun Qin
59a3ccb09e SecurityPkg: Tcg2Acpi: Added unblock memory interface for NVS region 
This changes added usage of MmUnblockMemoryLib to explicitly request
allocated NVS region to be accessible from MM environment. It will bring
in compatibility with architectures that supports full memory blockage
inside MM.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB31026F3F8C3FAA39D74CE4BAF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
8802583c48 SecurityPkg: Tcg2Smm: Added support for Standalone Mm 
https://bugzilla.tianocore.org/show_bug.cgi?id=3169

This change added Standalone MM instance of Tcg2. The notify function for
Standalone MM instance is left empty.

A dependency DXE driver with a Depex of gEfiMmCommunication2ProtocolGuid
was created to indicate the readiness of Standalone MM Tcg2 driver.

Lastly, the support of CI build for Tcg2 Standalone MM module is added.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB3102C3F99CBADFCC5F8A821CF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
3c2dc30d1b SecurityPkg: Tcg2Smm: Separate Tcg2Smm into 2 modules 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3169

This change separated the original Tcg2Smm module into 2 drivers: the
SMM driver that registers callback for physical presence and memory
clear; the Tcg2Acpi driver that patches and publishes ACPI table for
runtime use.

Tcg2Smm introduced an SMI root handler to allow Tcg2Acpi to communicate
the NVS region used by Tpm.asl and exchange the registered SwSmiValue.

Lastly, Tcg2Smm driver will publish gTcg2MmSwSmiRegisteredGuid at the end
of entrypoint to ensure Tcg2Acpi to load after Tcg2Smm is ready to
communicate.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB310295CC623EF7C062844DFFF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
e2d6833c11 SecurityPkg: Tcg2Smm: Switching from gSmst to gMmst 
This change replaced gSmst with gMmst to support broader compatibility
under MM environment for Tcg2Smm driver.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB310218F28C7AAF8DB375E963F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
f463dbaded MdeModulePkg: VariableSmmRuntimeDxe: Added request unblock memory interface 
This changes added usage of MmUnblockMemoryLib to explicitly request
runtime cache regions(and its indicators) to be accessible from MM
environment when PcdEnableVariableRuntimeCache is enabled. It will bring
in compatibility with architectures that supports full memory blockage
inside MM.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Message-Id: <MWHPR06MB31026EA41F28F2CE12B68574F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
05a757c9c6 OvmfPkg: resolve MmUnblockMemoryLib (mainly for VariableSmmRuntimeDxe) 
This change added NULL MmUnblockMemoryLib instance in dsc files of
OvmfPkg to pass CI build. When SMM_REQUIRE flag is set, the library
interface is consumed by VariableSmmRuntimeDxe to better support variable
runtime cache feature.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <MWHPR06MB31028DFAB7AE46E32E5F9F86F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Kun Qin
7cda5d9e3a MdePkg: MmUnblockMemoryLib: Added definition and null instance 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3168

This interface provides an abstration layer to allow MM modules to access
requested areas that are outside of MMRAM. On MM model that blocks all
non-MMRAM accesses, areas requested through this API will be mapped or
unblocked for accessibility inside MM environment.

For MM modules that need to access regions outside of MMRAMs, the agents
that set up these regions are responsible for invoking this API in order
for these memory areas to be accessible from inside MM.

Example usages:
1. To enable runtime cache feature for variable service, Variable MM
module will need to access the allocated runtime buffer. Thus the agent
sets up these buffers, VariableSmmRuntimeDxe, will need to invoke this
API to make these regions accessible by Variable MM.
2. For TPM ACPI table to communicate to physical presence handler, the
corresponding NVS region has to be accessible from inside MM. Once the
NVS region are assigned, it needs to be unblocked thourgh this API.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Message-Id: <MWHPR06MB31028AF0D0785B93E4E7CF63F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
 2021-03-05 15:25:07 +00:00
Bandaru, Purna Chandra Rao
c5740f3606 MdeModulePkg/UfsPassThruDxe: Improve Device initialization polling Loop 
https://bugzilla.tianocore.org/show_bug.cgi?id=3217

Current Ufs Pass thru driver polls for 5us and return success even when
the timeout occurs.
There are cards that can take upto 600ms for Init and hence increased
the time out for fDeviceInit polling loop.

Signed-off-by: Bandaru <purna.chandra.rao.bandaru@intel.com>
Cc: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
 2021-03-05 08:43:23 +00:00
427 changed files with 20266 additions and 4360 deletions
Expand all files Collapse all files

3
.azurepipelines/templates/platform-build-run-steps.yml
View File

@@ -51,9 +51,6 @@ steps:
# Set default # Set default
- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}" - bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them. # Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020. # Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch) - script: git fetch origin $(System.PullRequest.targetBranch)

3
.azurepipelines/templates/pr-gate-build-job.yml
View File

@@ -21,6 +21,9 @@ jobs:
#Use matrix to speed up the build process #Use matrix to speed up the build process
strategy: strategy:
matrix: matrix:
TARGET_ARM_ARMPLATFORM:
Build.Pkgs: 'ArmPkg,ArmPlatformPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
TARGET_MDE_CPU: TARGET_MDE_CPU:
Build.Pkgs: 'MdePkg,UefiCpuPkg' Build.Pkgs: 'MdePkg,UefiCpuPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT' Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'

3
.azurepipelines/templates/pr-gate-steps.yml
View File

@@ -31,9 +31,6 @@ steps:
echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}" echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}" echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them. # Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020. # Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch) - script: git fetch origin $(System.PullRequest.targetBranch)

2
.gitmodules vendored
View File

@@ -6,7 +6,7 @@
url = https://github.com/ucb-bar/berkeley-softfloat-3.git url = https://github.com/ucb-bar/berkeley-softfloat-3.git
[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"] [submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
url = https://git.cryptomilk.org/projects/cmocka.git url = https://github.com/tianocore/edk2-cmocka.git
[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"] [submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
url = https://github.com/kkos/oniguruma url = https://github.com/kkos/oniguruma

4
.pytool/CISettings.py
View File

@@ -49,7 +49,9 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
''' return iterable of edk2 packages supported by this build. ''' return iterable of edk2 packages supported by this build.
These should be edk2 workspace relative paths ''' These should be edk2 workspace relative paths '''
return ("ArmVirtPkg", return ("ArmPkg",
"ArmPlatformPkg",
"ArmVirtPkg",
"DynamicTablesPkg", "DynamicTablesPkg",
"EmulatorPkg", "EmulatorPkg",
"MdePkg", "MdePkg",

14
.pytool/Readme.md
View File

@@ -4,8 +4,8 @@
| Package | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues | | Package | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues |
| :---- | :----- | :---- | :--- | | :---- | :----- | :---- | :--- |
| ArmPkg | | ArmPkg | | :heavy_check_mark: |
| ArmPlatformPkg | | ArmPlatformPkg | | :heavy_check_mark: |
| ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README | | ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README |
| CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode | CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
| DynamicTablesPkg | | :heavy_check_mark: | | DynamicTablesPkg | | :heavy_check_mark: |
@@ -254,6 +254,16 @@ Install
More cspell info: https://github.com/streetsidesoftware/cspell More cspell info: https://github.com/streetsidesoftware/cspell
### License Checking - LicenseCheck
Scans all new added files in a package to make sure code is contributed under
BSD-2-Clause-Patent.
### Ecc tool - EccCheck
Run the Ecc tool on the package. The Ecc tool is available in the BaseTools
package. It checks that the code complies to the EDKII coding standard.
## PyTool Scopes ## PyTool Scopes
Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning

221
ArmPkg/ArmPkg.ci.yaml Normal file
View File

@@ -0,0 +1,221 @@
## @file
# CI configuration for ArmPkg
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
## options defined .pytool/Plugin/LicenseCheck
"LicenseCheck": {
"IgnoreFiles": []
},
"EccCheck": {
## Exception sample looks like below:
## "ExceptionList": [
## "<ErrorID>", "<KeyWord>"
## ]
"ExceptionList": [
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
"Library/ArmSoftFloatLib/berkeley-softfloat-3"
]
},
## options defined .pytool/Plugin/CompilerPlugin
"CompilerPlugin": {
"DscPath": "ArmPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
"HostUnitTestCompilerPlugin": {
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/CharEncodingCheck
"CharEncodingCheck": {
"IgnoreFiles": []
},
## options defined .pytool/Plugin/DependencyCheck
"DependencyCheck": {
"AcceptableDependencies": [
"ArmPlatformPkg/ArmPlatformPkg.dec",
"ArmPkg/ArmPkg.dec",
"EmbeddedPkg/EmbeddedPkg.dec",
"MdeModulePkg/MdeModulePkg.dec",
"MdePkg/MdePkg.dec",
"ShellPkg/ShellPkg.dec"
],
# For host based unit tests
"AcceptableDependencies-HOST_APPLICATION":[
"UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
],
# For UEFI shell based apps
"AcceptableDependencies-UEFI_APPLICATION":[],
"IgnoreInf": []
},
## options defined .pytool/Plugin/DscCompleteCheck
"DscCompleteCheck": {
"IgnoreInf": [],
"DscPath": "ArmPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
"HostUnitTestDscCompleteCheck": {
"IgnoreInf": [""],
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/GuidCheck
"GuidCheck": {
"IgnoreGuidName": [],
"IgnoreGuidValue": [],
"IgnoreFoldersAndFiles": [],
"IgnoreDuplicates": [],
},
## options defined .pytool/Plugin/LibraryClassCheck
"LibraryClassCheck": {
"IgnoreHeaderFile": []
},
## options defined .pytool/Plugin/SpellCheck
"SpellCheck": {
"AuditOnly": False,
"IgnoreFiles": [
"Library/ArmSoftFloatLib/berkeley-softfloat-3/**"
], # use gitignore syntax to ignore errors
# in matching files
"ExtendWords": [
"api's",
"ackintid",
"actlr",
"aeabi",
"ashldi",
"ashrdi",
"ccidx",
"ccsidr",
"clidr",
"clrex",
"clzsi",
"cpuactlr",
"csselr",
"ctzsi",
"cygdrive",
"cygpaths",
"datas",
"dcmpeq",
"dcmpge",
"dcmpgt",
"dcmple",
"dcmplt",
"ddisable",
"divdi",
"divsi",
"dmdepkg",
"drsub",
"fcmpeq",
"fcmpge",
"fcmpgt",
"fcmple",
"fcmplt",
"ffreestanding",
"frsub",
"hisilicon",
"iccbpr",
"icciar",
"iccicr",
"icciidr",
"iccpmr",
"icdicer",
"icdicfr",
"icdictr",
"icdiser",
"icdisr",
"icdsgir",
"icenabler",
"intid",
"ipriority",
"irouter",
"isenabler",
"istatus",
"itargets",
"lable",
"ldivmod",
"ldmdb",
"ldmia",
"ldrbt",
"ldrex",
"ldrexb",
"ldrexd",
"ldrexh",
"ldrhbt",
"ldrht",
"ldrsb",
"ldrsbt",
"ldrsh",
"lshrdi",
"moddi",
"modsi",
"mpidr",
"muldi",
"mullu",
"nonshareable",
"nsacr",
"nsasedis",
"nuvia",
"oldit",
"readc",
"revsh",
"rfedb",
"sctlr",
"smccc",
"smlabb",
"smlabt",
"smlad",
"smladx",
"smlatb",
"smlatt",
"smlawb",
"smlawt",
"smlsd",
"smlsdx",
"smmla",
"smmlar",
"smmls",
"smmlsr",
"sourcery",
"srsdb",
"stmdb",
"stmia",
"strbt",
"strexb",
"strexd",
"strexh",
"strht",
"switchu",
"tpidrurw",
"ttbcr",
"typer",
"ucmpdi",
"udivdi",
"udivmoddi",
"udivsi",
"uefi's",
"uldiv",
"umoddi",
"umodsi",
"usada",
"vlpis",
"writec"
], # words to extend to the dictionary for this package
"IgnoreStandardPaths": [ # Standard Plugin defined paths that
"*.asm", "*.s" # should be ignore
],
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
}
}

65
ArmPkg/ArmPkg.dec
View File

@@ -2,7 +2,7 @@
# ARM processor package. # ARM processor package.
# #
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved. # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -27,15 +27,68 @@
Include # Root include for the package Include # Root include for the package
[LibraryClasses.common] [LibraryClasses.common]
ArmLib|Include/Library/ArmLib.h ## @libraryclass Convert Arm instructions to a human readable format.
ArmMmuLib|Include/Library/ArmMmuLib.h #
SemihostLib|Include/Library/Semihosting.h
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
## @libraryclass Provides an interface to Arm generic counters.
#
ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
## @libraryclass Provides an interface to initialize a
# Generic Interrupt Controller (GIC).
#
ArmGicArchLib|Include/Library/ArmGicArchLib.h ArmGicArchLib|Include/Library/ArmGicArchLib.h
ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
## @libraryclass Provides a Generic Interrupt Controller (GIC)
# configuration interface.
#
ArmGicLib|Include/Library/ArmGicLib.h
## @libraryclass Provides a HyperVisor Call (HVC) interface.
#
ArmHvcLib|Include/Library/ArmHvcLib.h
## @libraryclass Provides an interface to Arm registers.
#
ArmLib|Include/Library/ArmLib.h
## @libraryclass Provides a Mmu interface.
#
ArmMmuLib|Include/Library/ArmMmuLib.h
## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
# for the System Control and Management Interface (SCMI).
#
ArmMtlLib|Include/Library/ArmMtlLib.h
## @libraryclass Provides a System Monitor Call (SMC) interface.
#
ArmSmcLib|Include/Library/ArmSmcLib.h
## @libraryclass Provides a SuperVisor Call (SVC) interface.
#
ArmSvcLib|Include/Library/ArmSvcLib.h ArmSvcLib|Include/Library/ArmSvcLib.h
## @libraryclass Provides a default exception handler.
#
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
## @libraryclass Provides an interface to query miscellaneous OEM
# information.
#
OemMiscLib|Include/Library/OemMiscLib.h
## @libraryclass Provides an OpTee interface.
#
OpteeLib|Include/Library/OpteeLib.h OpteeLib|Include/Library/OpteeLib.h
## @libraryclass Provides a semihosting interface.
#
SemihostLib|Include/Library/SemihostLib.h
## @libraryclass Provides an interface for a StandaloneMm Mmu.
#
StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
[Guids.common] [Guids.common]

9
ArmPkg/ArmPkg.dsc
View File

@@ -2,7 +2,7 @@
# ARM processor package. # ARM processor package.
# #
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2018, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR> # Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation.<BR> # Copyright (c) Microsoft Corporation.<BR>
# #
@@ -32,17 +32,22 @@
[PcdsFixedAtBuild] [PcdsFixedAtBuild]
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common] [LibraryClasses.common]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
@@ -50,6 +55,7 @@
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@@ -150,6 +156,7 @@
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
[Components.AARCH64] [Components.AARCH64]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf

6
ArmPkg/Drivers/ArmGic/ArmGicDxe.h
View File

@@ -6,8 +6,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
--*/ --*/
#ifndef __ARM_GIC_DXE_H__ #ifndef ARM_GIC_DXE_H_
#define __ARM_GIC_DXE_H__ #define ARM_GIC_DXE_H_
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
@@ -76,4 +76,4 @@ GicGetDistributorIcfgBaseAndBit (
OUT UINTN *Config1Bit OUT UINTN *Config1Bit
); );
#endif #endif // ARM_GIC_DXE_H_

11
ArmPkg/Drivers/ArmGic/ArmGicLib.c
View File

@@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011-2018, ARM Limited. All rights reserved. * Copyright (c) 2011-2021, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
@@ -120,7 +120,14 @@ ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
//
// Interrupt ID 1020-1023 are reserved.
//
return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);
} }
VOID VOID

58
ArmPkg/Drivers/ArmGic/ArmGicSecLib.c
View File

@@ -1,58 +0,0 @@
/** @file
*
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
/*
* This function configures the interrupts set by the mask to be secure.
*
*/
VOID
EFIAPI
ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
)
{
UINTN Index;
UINT32 InterruptStatus;
// We must not have more interrupts defined by the mask than the number of available interrupts
ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
// Set all the interrupts defined by the mask as Secure
for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
}
}
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
{
// Turn on the GIC distributor
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
}
VOID
EFIAPI
ArmGicSetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
)
{
ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
}

2
ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
View File

@@ -121,7 +121,7 @@ GicV2GetInterruptSourceState (
@param This Instance pointer for this protocol @param This Instance pointer for this protocol
@param Source Hardware source of the interrupt @param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed. @retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_UNSUPPORTED Source interrupt is not supported @retval EFI_UNSUPPORTED Source interrupt is not supported
**/ **/

2
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
View File

@@ -115,7 +115,7 @@ GicV3GetInterruptSourceState (
@param This Instance pointer for this protocol @param This Instance pointer for this protocol
@param Source Hardware source of the interrupt @param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed. @retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_DEVICE_ERROR Hardware could not be programmed. @retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/ **/

9
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
View File

@@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2017-2018, Arm Limited. All rights reserved. # Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -18,11 +18,16 @@
ENTRY_POINT = ArmScmiDxeEntryPoint ENTRY_POINT = ArmScmiDxeEntryPoint
[Sources.common] [Sources.common]
Scmi.c ArmScmiBaseProtocolPrivate.h
ArmScmiClockProtocolPrivate.h
ArmScmiPerformanceProtocolPrivate.h
ScmiBaseProtocol.c ScmiBaseProtocol.c
Scmi.c
ScmiClockProtocol.c ScmiClockProtocol.c
ScmiDxe.c ScmiDxe.c
ScmiDxe.h
ScmiPerformanceProtocol.c ScmiPerformanceProtocol.c
ScmiPrivate.h
[Packages] [Packages]
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec

4
ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,7 +22,7 @@
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16 #define NUM_REMAIN_PERF_LEVELS_SHIFT 16
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT) #define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command. /** Return values for ScmiMessageIdPerformanceDescribeLevels command.
SCMI Spec section 4.5.2.5 SCMI Spec section 4.5.2.5
**/ **/
typedef struct { typedef struct {

10
ArmPkg/Drivers/ArmScmiDxe/Scmi.c
View File

@@ -95,7 +95,7 @@ ScmiCommandExecute (
// Fill in message header. // Fill in message header.
MessageHeader = SCMI_MESSAGE_HEADER ( MessageHeader = SCMI_MESSAGE_HEADER (
Command->MessageId, Command->MessageId,
SCMI_MESSAGE_TYPE_COMMAND, ScmiMessageTypeCommand,
Command->ProtocolId Command->ProtocolId
); );
@@ -123,7 +123,7 @@ ScmiCommandExecute (
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel); Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
if (Response->Status != SCMI_SUCCESS) { if (Response->Status != ScmiSuccess) {
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n", DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
Command->ProtocolId, Command->ProtocolId,
Command->MessageId, Command->MessageId,
@@ -195,7 +195,7 @@ ScmiGetProtocolVersion (
Status = ScmiProtocolDiscoveryCommon ( Status = ScmiProtocolDiscoveryCommon (
ProtocolId, ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_VERSION, ScmiMessageIdProtocolVersion,
(UINT32**)&ProtocolVersion (UINT32**)&ProtocolVersion
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -224,7 +224,7 @@ ScmiGetProtocolAttributes (
{ {
return ScmiProtocolDiscoveryCommon ( return ScmiProtocolDiscoveryCommon (
ProtocolId, ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES, ScmiMessageIdProtocolAttributes,
ReturnValues ReturnValues
); );
} }
@@ -246,7 +246,7 @@ ScmiGetProtocolMessageAttributes (
{ {
return ScmiProtocolDiscoveryCommon ( return ScmiProtocolDiscoveryCommon (
ProtocolId, ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES, ScmiMessageIdProtocolMessageAttributes,
ReturnValues ReturnValues
); );
} }

24
ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -34,7 +34,7 @@ BaseGetVersion (
OUT UINT32 *Version OUT UINT32 *Version
) )
{ {
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version); return ScmiGetProtocolVersion (ScmiProtocolIdBase, Version);
} }
/** Return total number of SCMI protocols supported by the SCP firmware. /** Return total number of SCMI protocols supported by the SCP firmware.
@@ -57,7 +57,7 @@ BaseGetTotalProtocols (
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *ReturnValues; UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValues); Status = ScmiGetProtocolAttributes (ScmiProtocolIdBase, &ReturnValues);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@@ -69,9 +69,9 @@ BaseGetTotalProtocols (
/** Common function which returns vendor details. /** Common function which returns vendor details.
@param[in] MessageId SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR @param[in] MessageId ScmiMessageIdBaseDiscoverVendor
OR OR
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR ScmiMessageIdBaseDiscoverSubVendor
@param[out] VendorIdentifier ASCII name of the vendor/subvendor. @param[out] VendorIdentifier ASCII name of the vendor/subvendor.
@@ -91,7 +91,7 @@ BaseDiscoverVendorDetails (
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE; Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = MessageId; Cmd.MessageId = MessageId;
PayloadLength = 0; PayloadLength = 0;
@@ -133,7 +133,7 @@ BaseDiscoverVendor (
) )
{ {
return BaseDiscoverVendorDetails ( return BaseDiscoverVendorDetails (
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR, ScmiMessageIdBaseDiscoverVendor,
VendorIdentifier VendorIdentifier
); );
} }
@@ -156,7 +156,7 @@ BaseDiscoverSubVendor (
) )
{ {
return BaseDiscoverVendorDetails ( return BaseDiscoverVendorDetails (
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR, ScmiMessageIdBaseDiscoverSubVendor,
VendorIdentifier VendorIdentifier
); );
} }
@@ -183,8 +183,8 @@ BaseDiscoverImplVersion (
SCMI_COMMAND Cmd; SCMI_COMMAND Cmd;
UINT32 PayloadLength; UINT32 PayloadLength;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE; Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION; Cmd.MessageId = ScmiMessageIdBaseDiscoverImplementationVersion;
PayloadLength = 0; PayloadLength = 0;
@@ -250,8 +250,8 @@ BaseDiscoverListProtocols (
return EFI_BUFFER_TOO_SMALL; return EFI_BUFFER_TOO_SMALL;
} }
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE; Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS; Cmd.MessageId = ScmiMessageIdBaseDiscoverListProtocols;
Skip = 0; Skip = 0;

44
ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c
View File

@@ -52,7 +52,7 @@ ClockGetVersion (
OUT UINT32 *Version OUT UINT32 *Version
) )
{ {
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version); return ScmiGetProtocolVersion (ScmiProtocolIdClock, Version);
} }
/** Return total number of clock devices supported by the clock management /** Return total number of clock devices supported by the clock management
@@ -76,7 +76,7 @@ ClockGetTotalClocks (
EFI_STATUS Status; EFI_STATUS Status;
UINT32 *ReturnValues; UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnValues); Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@@ -122,8 +122,8 @@ ClockGetClockAttributes (
*MessageParams = ClockId; *MessageParams = ClockId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES; Cmd.MessageId = ScmiMessageIdClockAttributes;
PayloadLength = sizeof (ClockId); PayloadLength = sizeof (ClockId);
@@ -152,10 +152,10 @@ ClockGetClockAttributes (
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance. @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device. @param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device @param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear. supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps. range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates. @param[out] TotalRates Total number of rates.
@@ -203,8 +203,8 @@ ClockDescribeRates (
return Status; return Status;
} }
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES; Cmd.MessageId = ScmiMessageIdClockDescribeRates;
*MessageParams++ = ClockId; *MessageParams++ = ClockId;
@@ -236,7 +236,7 @@ ClockDescribeRates (
*TotalRates = NUM_RATES (DescribeRates->NumRatesFlags) *TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags); + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) { if (*Format == ScmiClockRateFormatDiscrete) {
RequiredArraySize = (*TotalRates) * sizeof (UINT64); RequiredArraySize = (*TotalRates) * sizeof (UINT64);
} else { } else {
// We need to return triplet of 64 bit value for each rate // We need to return triplet of 64 bit value for each rate
@@ -251,26 +251,30 @@ ClockDescribeRates (
RateOffset = 0; RateOffset = 0;
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) { if (*Format == ScmiClockRateFormatDiscrete) {
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) { for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
Rate = &DescribeRates->Rates[RateOffset++]; Rate = &DescribeRates->Rates[RateOffset++];
// Non-linear discrete rates. // Non-linear discrete rates.
RateArray[RateIndex++].Rate = ConvertTo64Bit (Rate->Low, Rate->High); RateArray[RateIndex++].DiscreteRate.Rate =
ConvertTo64Bit (Rate->Low, Rate->High);
} }
} else { } else {
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) { for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
// Linear clock rates from minimum to maximum in steps // Linear clock rates from minimum to maximum in steps
// Minimum clock rate. // Minimum clock rate.
Rate = &DescribeRates->Rates[RateOffset++]; Rate = &DescribeRates->Rates[RateOffset++];
RateArray[RateIndex].Min = ConvertTo64Bit (Rate->Low, Rate->High); RateArray[RateIndex].ContinuousRate.Min =
ConvertTo64Bit (Rate->Low, Rate->High);
Rate = &DescribeRates->Rates[RateOffset++]; Rate = &DescribeRates->Rates[RateOffset++];
// Maximum clock rate. // Maximum clock rate.
RateArray[RateIndex].Max = ConvertTo64Bit (Rate->Low, Rate->High); RateArray[RateIndex].ContinuousRate.Max =
ConvertTo64Bit (Rate->Low, Rate->High);
Rate = &DescribeRates->Rates[RateOffset++]; Rate = &DescribeRates->Rates[RateOffset++];
// Step. // Step.
RateArray[RateIndex++].Step = ConvertTo64Bit (Rate->Low, Rate->High); RateArray[RateIndex++].ContinuousRate.Step =
ConvertTo64Bit (Rate->Low, Rate->High);
} }
} }
} while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0); } while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
@@ -316,8 +320,8 @@ ClockRateGet (
// Fill arguments for clock protocol command. // Fill arguments for clock protocol command.
*MessageParams = ClockId; *MessageParams = ClockId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_GET; Cmd.MessageId = ScmiMessageIdClockRateGet;
PayloadLength = sizeof (ClockId); PayloadLength = sizeof (ClockId);
@@ -370,8 +374,8 @@ ClockRateSet (
ClockRateSetAttributes->Rate.Low = (UINT32)Rate; ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32); ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_SET; Cmd.MessageId = ScmiMessageIdClockRateSet;
PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES); PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
@@ -417,8 +421,8 @@ ClockEnable (
ClockConfigSetAttributes->ClockId = ClockId; ClockConfigSetAttributes->ClockId = ClockId;
ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0; ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET; Cmd.MessageId = ScmiMessageIdClockConfigSet;
PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES); PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);

20
ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c
View File

@@ -1,12 +1,12 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
System Control and Management Interface V1.0 @par Specification Reference:
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ - Arm System Control and Management Interface - Platform Design Document
DEN0056A_System_Control_and_Management_Interface.pdf (https://developer.arm.com/documentation/den0056/)
**/ **/
#include <Base.h> #include <Base.h>
@@ -24,9 +24,9 @@
#include "ScmiPrivate.h" #include "ScmiPrivate.h"
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = { STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
{ SCMI_PROTOCOL_ID_BASE, ScmiBaseProtocolInit }, { ScmiProtocolIdBase, ScmiBaseProtocolInit },
{ SCMI_PROTOCOL_ID_PERFORMANCE, ScmiPerformanceProtocolInit }, { ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
{ SCMI_PROTOCOL_ID_CLOCK, ScmiClockProtocolInit } { ScmiProtocolIdClock, ScmiClockProtocolInit }
}; };
/** ARM SCMI driver entry point function. /** ARM SCMI driver entry point function.
@@ -61,7 +61,7 @@ ArmScmiDxeEntryPoint (
UINT32 SupportedListSize; UINT32 SupportedListSize;
// Every SCMI implementation must implement the base protocol. // Every SCMI implementation must implement the base protocol.
ASSERT (Protocols[0].Id == SCMI_PROTOCOL_ID_BASE); ASSERT (Protocols[0].Id == ScmiProtocolIdBase);
Status = ScmiBaseProtocolInit (&ImageHandle); Status = ScmiBaseProtocolInit (&ImageHandle);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -86,7 +86,9 @@ ArmScmiDxeEntryPoint (
return Status; return Status;
} }
if (Version != BASE_PROTOCOL_VERSION) { // Accept any version between SCMI v1.0 and SCMI v2.0
if ((Version < BASE_PROTOCOL_VERSION_V1) ||
(Version > BASE_PROTOCOL_VERSION_V2)) {
ASSERT (FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }

30
ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -35,7 +35,7 @@ PerformanceGetVersion (
OUT UINT32 *Version OUT UINT32 *Version
) )
{ {
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version); return ScmiGetProtocolVersion (ScmiProtocolIdPerformance, Version);
} }
/** Return protocol attributes of the performance management protocol. /** Return protocol attributes of the performance management protocol.
@@ -59,7 +59,7 @@ PerformanceGetAttributes (
UINT32* ReturnValues; UINT32* ReturnValues;
Status = ScmiGetProtocolAttributes ( Status = ScmiGetProtocolAttributes (
SCMI_PROTOCOL_ID_PERFORMANCE, ScmiProtocolIdPerformance,
&ReturnValues &ReturnValues
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -107,8 +107,8 @@ PerformanceDomainAttributes (
*MessageParams = DomainId; *MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES; Cmd.MessageId = ScmiMessageIdPerformanceDomainAttributes;
PayloadLength = sizeof (DomainId); PayloadLength = sizeof (DomainId);
@@ -179,8 +179,8 @@ PerformanceDescribeLevels (
*MessageParams++ = DomainId; *MessageParams++ = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS; Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
do { do {
@@ -258,8 +258,8 @@ PerformanceLimitsSet (
*MessageParams++ = Limits->RangeMax; *MessageParams++ = Limits->RangeMax;
*MessageParams = Limits->RangeMin; *MessageParams = Limits->RangeMin;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET; Cmd.MessageId = ScmiMessageIdPerformanceLimitsSet;
PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS); PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
@@ -304,8 +304,8 @@ PerformanceLimitsGet (
*MessageParams = DomainId; *MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET; Cmd.MessageId = ScmiMessageIdPerformanceLimitsGet;
PayloadLength = sizeof (DomainId); PayloadLength = sizeof (DomainId);
@@ -354,8 +354,8 @@ PerformanceLevelSet (
*MessageParams++ = DomainId; *MessageParams++ = DomainId;
*MessageParams = Level; *MessageParams = Level;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET; Cmd.MessageId = ScmiMessageIdPerformanceLevelSet;
PayloadLength = sizeof (DomainId) + sizeof (Level); PayloadLength = sizeof (DomainId) + sizeof (Level);
@@ -399,8 +399,8 @@ PerformanceLevelGet (
*MessageParams = DomainId; *MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE; Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET; Cmd.MessageId = ScmiMessageIdPerformanceLevelGet;
PayloadLength = sizeof (DomainId); PayloadLength = sizeof (DomainId);

48
ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -13,41 +13,41 @@
// SCMI protocol IDs. // SCMI protocol IDs.
typedef enum { typedef enum {
SCMI_PROTOCOL_ID_BASE = 0x10, ScmiProtocolIdBase = 0x10,
SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, ScmiProtocolIdPowerDomain = 0x11,
SCMI_PROTOCOL_ID_SYSTEM_POWER = 0x12, ScmiProtocolIdSystemPower = 0x12,
SCMI_PROTOCOL_ID_PERFORMANCE = 0x13, ScmiProtocolIdPerformance = 0x13,
SCMI_PROTOCOL_ID_CLOCK = 0x14, ScmiProtocolIdClock = 0x14,
SCMI_PROTOCOL_ID_SENSOR = 0x15 ScmiProtocolIdSensor = 0x15
} SCMI_PROTOCOL_ID; } SCMI_PROTOCOL_ID;
// SCMI message types. // SCMI message types.
typedef enum { typedef enum {
SCMI_MESSAGE_TYPE_COMMAND = 0, ScmiMessageTypeCommand = 0,
SCMI_MESSAGE_TYPE_DELAYED_RESPONSE = 2, // Skipping 1 is deliberate. ScmiMessageTypeDelayedResponse = 2, // Skipping 1 is deliberate.
SCMI_MESSAGE_TYPE_NOTIFICATION = 3 ScmiMessageTypeNotification = 3
} SCMI_MESSAGE_TYPE; } SCMI_MESSAGE_TYPE;
// SCMI response error codes. // SCMI response error codes.
typedef enum { typedef enum {
SCMI_SUCCESS = 0, ScmiSuccess = 0,
SCMI_NOT_SUPPORTED = -1, ScmiNotSupported = -1,
SCMI_INVALID_PARAMETERS = -2, ScmiInvalidParameters = -2,
SCMI_DENIED = -3, ScmiDenied = -3,
SCMI_NOT_FOUND = -4, ScmiNotFound = -4,
SCMI_OUT_OF_RANGE = -5, ScmiOutOfRange = -5,
SCMI_BUSY = -6, ScmiBusy = -6,
SCMI_COMMS_ERROR = -7, ScmiCommsError = -7,
SCMI_GENERIC_ERROR = -8, ScmiGenericError = -8,
SCMI_HARDWARE_ERROR = -9, ScmiHardwareError = -9,
SCMI_PROTOCOL_ERROR = -10 ScmiProtocolError = -10
} SCMI_STATUS; } SCMI_STATUS;
// SCMI message IDs common to all protocols. // SCMI message IDs common to all protocols.
typedef enum { typedef enum {
SCMI_MESSAGE_ID_PROTOCOL_VERSION = 0x0, ScmiMessageIdProtocolVersion = 0x0,
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES = 0x1, ScmiMessageIdProtocolAttributes = 0x1,
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2 ScmiMessageIdProtocolMessageAttributes = 0x2
} SCMI_MESSAGE_ID; } SCMI_MESSAGE_ID;
// Not defined in SCMI specification but will help to identify a message. // Not defined in SCMI specification but will help to identify a message.

2
ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
View File

@@ -345,7 +345,7 @@ EfiAttributeToArmAttribute (
break; break;
case EFI_MEMORY_WC: case EFI_MEMORY_WC:
// Map to normal non-cachable // Map to normal non-cacheable
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
break; break;

6
ArmPkg/Drivers/CpuDxe/CpuDxe.h
View File

@@ -7,8 +7,8 @@
**/ **/
#ifndef __CPU_DXE_ARM_EXCEPTION_H__ #ifndef CPU_DXE_H_
#define __CPU_DXE_ARM_EXCEPTION_H__ #define CPU_DXE_H_
#include <Uefi.h> #include <Uefi.h>
@@ -143,4 +143,4 @@ SetGcdMemorySpaceAttributes (
IN UINT64 Attributes IN UINT64 Attributes
); );
#endif // __CPU_DXE_ARM_EXCEPTION_H__ #endif // CPU_DXE_H_

4
ArmPkg/Drivers/CpuDxe/CpuMpCore.c
View File

@@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
@@ -32,7 +32,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
}; };
/** Publish ARM Processor Data table in UEFI SYSTEM Table. /** Publish ARM Processor Data table in UEFI SYSTEM Table.
* @param: HobStart Pointer to the beginning of the HOB List from PEI. * @param HobStart Pointer to the beginning of the HOB List from PEI.
* *
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB. * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory

6
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
View File

@@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
**/ **/
#ifndef __GENERIC_WATCHDOG_H__ #ifndef GENERIC_WATCHDOG_H_
#define __GENERIC_WATCHDOG_H__ #define GENERIC_WATCHDOG_H_
// Refresh Frame: // Refresh Frame:
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000) #define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
@@ -21,4 +21,4 @@
#define GENERIC_WDOG_ENABLED 1 #define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0 #define GENERIC_WDOG_DISABLED 0
#endif // __GENERIC_WATCHDOG_H__ #endif // GENERIC_WATCHDOG_H_

3
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
View File

@@ -1,5 +1,5 @@
# #
# Copyright (c) 2013-2017, ARM Limited. All rights reserved. # Copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -13,6 +13,7 @@
ENTRY_POINT = GenericWatchdogEntry ENTRY_POINT = GenericWatchdogEntry
[Sources.common] [Sources.common]
GenericWatchdog.h
GenericWatchdogDxe.c GenericWatchdogDxe.c
[Packages] [Packages]

8
ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h
View File

@@ -1,13 +1,13 @@
/** @file /** @file
Copyright (c) 2016-2018, ARM Limited. All rights reserved. Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#if !defined _MM_COMMUNICATE_H_ #ifndef MM_COMMUNICATE_H_
#define _MM_COMMUNICATE_H_ #define MM_COMMUNICATE_H_
#define MM_MAJOR_VER_MASK 0xEFFF0000 #define MM_MAJOR_VER_MASK 0xEFFF0000
#define MM_MINOR_VER_MASK 0x0000FFFF #define MM_MINOR_VER_MASK 0x0000FFFF
@@ -19,4 +19,4 @@
#define MM_CALLER_MAJOR_VER 0x1UL #define MM_CALLER_MAJOR_VER 0x1UL
#define MM_CALLER_MINOR_VER 0x0 #define MM_CALLER_MINOR_VER 0x0
#endif /* _MM_COMMUNICATE_H_ */ #endif /* MM_COMMUNICATE_H_ */

3
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
View File

@@ -2,7 +2,7 @@
# #
# DXE MM Communicate driver # DXE MM Communicate driver
# #
# Copyright (c) 2016 - 2019, ARM Limited. All rights reserved. # Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -24,6 +24,7 @@
# #
[Sources.AARCH64] [Sources.AARCH64]
MmCommunicate.h
MmCommunication.c MmCommunication.c
[Packages] [Packages]

2
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
View File

@@ -51,7 +51,7 @@ EFI_FILE gSemihostFsFile = {
}; };
// //
// Device path for semi-hosting. It contains our autogened Caller ID GUID. // Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
// //
typedef struct { typedef struct {
VENDOR_DEVICE_PATH Guid; VENDOR_DEVICE_PATH Guid;

6
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
View File

@@ -7,8 +7,8 @@
**/ **/
#ifndef __SEMIHOST_FS_H__ #ifndef SEMIHOST_FS_H_
#define __SEMIHOST_FS_H__ #define SEMIHOST_FS_H_
EFI_STATUS EFI_STATUS
VolumeOpen ( VolumeOpen (
@@ -242,5 +242,5 @@ FileFlush (
IN EFI_FILE *File IN EFI_FILE *File
); );
#endif // __SEMIHOST_FS_H__ #endif // SEMIHOST_FS_H_

6
ArmPkg/Include/AsmMacroIoLib.h
View File

@@ -10,8 +10,8 @@
**/ **/
#ifndef __MACRO_IO_LIB_H__ #ifndef ASM_MACRO_IO_LIB_H_
#define __MACRO_IO_LIB_H__ #define ASM_MACRO_IO_LIB_H_
#define _ASM_FUNC(Name, Section) \ #define _ASM_FUNC(Name, Section) \
.global Name ; \ .global Name ; \
@@ -36,4 +36,4 @@
movt Reg, #:upper16:(Sym) - (. + 12) ; \ movt Reg, #:upper16:(Sym) - (. + 12) ; \
ldr Reg, [pc, Reg] ldr Reg, [pc, Reg]
#endif #endif // ASM_MACRO_IO_LIB_H_

6
ArmPkg/Include/AsmMacroIoLibV8.h
View File

@@ -10,8 +10,8 @@
**/ **/
#ifndef __MACRO_IO_LIBV8_H__ #ifndef ASM_MACRO_IO_LIBV8_H_
#define __MACRO_IO_LIBV8_H__ #define ASM_MACRO_IO_LIBV8_H_
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1 // CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2, else we die. // This only selects between EL1 and EL2, else we die.
@@ -54,4 +54,4 @@
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \ movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
movk Reg, (Val) & 0xffff movk Reg, (Val) & 0xffff
#endif // __MACRO_IO_LIBV8_H__ #endif // ASM_MACRO_IO_LIBV8_H_

18
ArmPkg/Include/Chipset/AArch64.h
View File

@@ -1,14 +1,14 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR> Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef __AARCH64_H__ #ifndef AARCH64_H_
#define __AARCH64_H__ #define AARCH64_H_
#include <Chipset/AArch64Mmu.h> #include <Chipset/AArch64Mmu.h>
@@ -39,7 +39,7 @@
// MIDR - Main ID Register definitions // MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF #define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F #define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08 #define ARM_CPU_TYPE_A72 0xD08
@@ -97,10 +97,10 @@
#define ARM_VECTOR_CUR_SP0_FIQ 0x100 #define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180 #define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SPx_SYNC 0x200 #define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPx_IRQ 0x280 #define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPx_FIQ 0x300 #define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPx_SERR 0x380 #define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_LOW_A64_SYNC 0x400 #define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480 #define ARM_VECTOR_LOW_A64_IRQ 0x480
@@ -238,4 +238,4 @@ ArmWriteCntHctl (
IN UINT32 CntHctl IN UINT32 CntHctl
); );
#endif // __AARCH64_H__ #endif // AARCH64_H_

10
ArmPkg/Include/Chipset/AArch64Mmu.h
View File

@@ -1,13 +1,13 @@
/** @file /** @file
* *
* Copyright (c) 2011-2013, ARM Limited. All rights reserved. * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
**/ **/
#ifndef __AARCH64_MMU_H_ #ifndef AARCH64_MMU_H_
#define __AARCH64_MMU_H_ #define AARCH64_MMU_H_
// //
// Memory Attribute Indirection register Definitions // Memory Attribute Indirection register Definitions
@@ -190,9 +190,9 @@
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25 // Virtual address range for 512GB of virtual space sets T*SZ to 25
#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a) #define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format // Uses LPAE Page Table format
#endif // __AARCH64_MMU_H_ #endif // AARCH64_MMU_H_

8
ArmPkg/Include/Chipset/ArmCortexA5x.h
View File

@@ -1,13 +1,13 @@
/** @file /** @file
Copyright (c) 2012-2014, ARM Limited. All rights reserved. Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef __ARM_CORTEX_A5x_H__ #ifndef ARM_CORTEX_A5X_H_
#define __ARM_CORTEX_A5x_H__ #define ARM_CORTEX_A5X_H_
// //
// Cortex A5x feature bit definitions // Cortex A5x feature bit definitions
@@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
IN UINT64 Bits IN UINT64 Bits
); );
#endif #endif // ARM_CORTEX_A5X_H_

6
ArmPkg/Include/Chipset/ArmCortexA9.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __ARM_CORTEX_A9_H__ #ifndef ARM_CORTEX_A9_H_
#define __ARM_CORTEX_A9_H__ #define ARM_CORTEX_A9_H_
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
@@ -55,5 +55,5 @@ ArmGetScuBaseAddress (
VOID VOID
); );
#endif #endif // ARM_CORTEX_A9_H_

10
ArmPkg/Include/Chipset/ArmV7.h
View File

@@ -1,14 +1,14 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR> Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef __ARM_V7_H__ #ifndef ARM_V7_H_
#define __ARM_V7_H__ #define ARM_V7_H_
#include <Chipset/ArmV7Mmu.h> #include <Chipset/ArmV7Mmu.h>
@@ -70,7 +70,7 @@
// MIDR - Main ID Register definitions // MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4 #define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF #define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F #define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03 #define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07 #define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F #define ARM_CPU_TYPE_A15 0xC0F
@@ -120,4 +120,4 @@ ArmWriteNsacr (
IN UINT32 Nsacr IN UINT32 Nsacr
); );
#endif // __ARM_V7_H__ #endif // ARM_V7_H_

6
ArmPkg/Include/Chipset/ArmV7Mmu.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARMV7_MMU_H_ #ifndef ARMV7_MMU_H_
#define __ARMV7_MMU_H_ #define ARMV7_MMU_H_
#define TTBR_NOT_OUTER_SHAREABLE BIT5 #define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0 #define TTBR_RGN_OUTER_NON_CACHEABLE 0
@@ -235,4 +235,4 @@ ConvertSectionAttributesToPageAttributes (
IN BOOLEAN IsLargePage IN BOOLEAN IsLargePage
); );
#endif #endif // ARMV7_MMU_H_

6
ArmPkg/Include/Guid/ArmMpCoreInfo.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_MP_CORE_INFO_GUID_H_ #ifndef ARM_MP_CORE_INFO_GUID_H_
#define __ARM_MP_CORE_INFO_GUID_H_ #define ARM_MP_CORE_INFO_GUID_H_
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04 #define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
#define SCU_CONFIG_REG_OFFSET 0x04 #define SCU_CONFIG_REG_OFFSET 0x04
@@ -57,4 +57,4 @@ typedef struct {
extern EFI_GUID gArmMpCoreInfoGuid; extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* MPCOREINFO_H_ */ #endif /* ARM_MP_CORE_INFO_GUID_H_ */

6
ArmPkg/Include/IndustryStandard/ArmMmSvc.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_MM_SVC_H__ #ifndef ARM_MM_SVC_H_
#define __ARM_MM_SVC_H__ #define ARM_MM_SVC_H_
/* /*
* SVC IDs to allow the MM secure partition to initialise itself, handle * SVC IDs to allow the MM secure partition to initialise itself, handle
@@ -44,4 +44,4 @@
#define SPM_MAJOR_VERSION 0 #define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1 #define SPM_MINOR_VERSION 1
#endif #endif // ARM_MM_SVC_H_

6
ArmPkg/Include/IndustryStandard/ArmStdSmc.h
View File

@@ -10,8 +10,8 @@
* (https://developer.arm.com/documentation/den0028/c/?lang=en) * (https://developer.arm.com/documentation/den0028/c/?lang=en)
**/ **/
#ifndef __ARM_STD_SMC_H__ #ifndef ARM_STD_SMC_H_
#define __ARM_STD_SMC_H__ #define ARM_STD_SMC_H_
/* /*
* SMC function IDs for Standard Service queries * SMC function IDs for Standard Service queries
@@ -129,4 +129,4 @@
/* 0xbf00ff02 is reserved */ /* 0xbf00ff02 is reserved */
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03 #define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif #endif // ARM_STD_SMC_H_

6
ArmPkg/Include/Library/ArmDisassemblerLib.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __ARM_DISASSEBLER_LIB_H__ #ifndef ARM_DISASSEMBLER_LIB_H_
#define __ARM_DISASSEBLER_LIB_H__ #define ARM_DISASSEMBLER_LIB_H_
/** /**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
@@ -34,4 +34,4 @@ DisassembleInstruction (
OUT UINTN Size OUT UINTN Size
); );
#endif #endif // ARM_DISASSEMBLER_LIB_H_

6
ArmPkg/Include/Library/ArmGenericTimerCounterLib.h
View File

@@ -7,8 +7,8 @@
**/ **/
#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__ #ifndef ARM_GENERIC_TIMER_COUNTER_LIB_H_
#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__ #define ARM_GENERIC_TIMER_COUNTER_LIB_H_
VOID VOID
EFIAPI EFIAPI
@@ -82,4 +82,4 @@ ArmGenericTimerSetCompareVal (
IN UINT64 Value IN UINT64 Value
); );
#endif #endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_

6
ArmPkg/Include/Library/ArmGicArchLib.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_GIC_ARCH_LIB_H__ #ifndef ARM_GIC_ARCH_LIB_H_
#define __ARM_GIC_ARCH_LIB_H__ #define ARM_GIC_ARCH_LIB_H_
// //
// GIC definitions // GIC definitions
@@ -24,4 +24,4 @@ ArmGicGetSupportedArchRevision (
VOID VOID
); );
#endif #endif // ARM_GIC_ARCH_LIB_H_

8
ArmPkg/Include/Library/ArmGicLib.h
View File

@@ -1,13 +1,13 @@
/** @file /** @file
* *
* Copyright (c) 2011-2018, ARM Limited. All rights reserved. * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
**/ **/
#ifndef __ARMGIC_H #ifndef ARMGIC_H_
#define __ARMGIC_H #define ARMGIC_H_
#include <Library/ArmGicArchLib.h> #include <Library/ArmGicArchLib.h>
@@ -333,4 +333,4 @@ ArmGicV3SetPriorityMask (
IN UINTN Priority IN UINTN Priority
); );
#endif #endif // ARMGIC_H_

6
ArmPkg/Include/Library/ArmHvcLib.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_HVC_LIB__ #ifndef ARM_HVC_LIB_H_
#define __ARM_HVC_LIB__ #define ARM_HVC_LIB_H_
/** /**
* The size of the HVC arguments are different between AArch64 and AArch32. * The size of the HVC arguments are different between AArch64 and AArch32.
@@ -37,4 +37,4 @@ ArmCallHvc (
IN OUT ARM_HVC_ARGS *Args IN OUT ARM_HVC_ARGS *Args
); );
#endif #endif // ARM_HVC_LIB_H_

6
ArmPkg/Include/Library/ArmLib.h
View File

@@ -8,8 +8,8 @@
**/ **/
#ifndef __ARM_LIB__ #ifndef ARM_LIB_H_
#define __ARM_LIB__ #define ARM_LIB_H_
#include <Uefi/UefiBaseType.h> #include <Uefi/UefiBaseType.h>
@@ -753,4 +753,4 @@ ArmHasSecurityExtensions (
); );
#endif // MDE_CPU_ARM #endif // MDE_CPU_ARM
#endif // __ARM_LIB__ #endif // ARM_LIB_H_

6
ArmPkg/Include/Library/ArmMmuLib.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __ARM_MMU_LIB__ #ifndef ARM_MMU_LIB_H_
#define __ARM_MMU_LIB__ #define ARM_MMU_LIB_H_
#include <Uefi/UefiBaseType.h> #include <Uefi/UefiBaseType.h>
@@ -64,4 +64,4 @@ ArmSetMemoryAttributes (
IN UINT64 Attributes IN UINT64 Attributes
); );
#endif #endif // ARM_MMU_LIB_H_

6
ArmPkg/Include/Library/ArmSmcLib.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_SMC_LIB__ #ifndef ARM_SMC_LIB_H_
#define __ARM_SMC_LIB__ #define ARM_SMC_LIB_H_
/** /**
* The size of the SMC arguments are different between AArch64 and AArch32. * The size of the SMC arguments are different between AArch64 and AArch32.
@@ -37,4 +37,4 @@ ArmCallSmc (
IN OUT ARM_SMC_ARGS *Args IN OUT ARM_SMC_ARGS *Args
); );
#endif #endif // ARM_SMC_LIB_H_

6
ArmPkg/Include/Library/ArmSvcLib.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_SVC_LIB__ #ifndef ARM_SVC_LIB_H_
#define __ARM_SVC_LIB__ #define ARM_SVC_LIB_H_
/** /**
* The size of the SVC arguments are different between AArch64 and AArch32. * The size of the SVC arguments are different between AArch64 and AArch32.
@@ -43,4 +43,4 @@ ArmCallSvc (
IN OUT ARM_SVC_ARGS *Args IN OUT ARM_SVC_ARGS *Args
); );
#endif #endif // ARM_SVC_LIB_H_

6
ArmPkg/Include/Library/DefaultExceptionHandlerLib.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__ #ifndef DEFAULT_EXCEPTION_HANDLER_LIB_H_
#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__ #define DEFAULT_EXCEPTION_HANDLER_LIB_H_
/** /**
This is the default action to take on an unexpected exception This is the default action to take on an unexpected exception
@@ -22,4 +22,4 @@ DefaultExceptionHandler (
IN OUT EFI_SYSTEM_CONTEXT SystemContext IN OUT EFI_SYSTEM_CONTEXT SystemContext
); );
#endif #endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_

70
ArmPkg/Include/Library/OemMiscLib.h
View File

@@ -162,4 +162,74 @@ OemUpdateSmbiosInfo (
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
); );
/** Fetches the Type 32 boot information status.
@return Boot status.
**/
MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
EFIAPI
OemGetBootStatus (
VOID
);
/** Fetches the chassis status when it was last booted.
@return Chassis status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisBootupState (
VOID
);
/** Fetches the chassis power supply/supplies status when last booted.
@return Chassis power supply/supplies status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisPowerSupplyState (
VOID
);
/** Fetches the chassis thermal status when last booted.
@return Chassis thermal status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisThermalState (
VOID
);
/** Fetches the chassis security status when last booted.
@return Chassis security status.
**/
MISC_CHASSIS_SECURITY_STATE
EFIAPI
OemGetChassisSecurityStatus (
VOID
);
/** Fetches the chassis height in RMUs (Rack Mount Units).
@return The height of the chassis.
**/
UINT8
EFIAPI
OemGetChassisHeight (
VOID
);
/** Fetches the number of power cords.
@return The number of power cords.
**/
UINT8
EFIAPI
OemGetChassisNumPowerCords (
VOID
);
#endif // OEM_MISC_LIB_H_ #endif // OEM_MISC_LIB_H_

17
ArmPkg/Include/Library/OpteeLib.h
View File

@@ -2,13 +2,14 @@
OP-TEE specific header file. OP-TEE specific header file.
Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef _OPTEE_H_ #ifndef OPTEE_LIB_H_
#define _OPTEE_H_ #define OPTEE_LIB_H_
/* /*
* The 'Trusted OS Call UID' is supposed to return the following UUID for * The 'Trusted OS Call UID' is supposed to return the following UUID for
@@ -45,12 +46,14 @@ typedef struct {
UINT64 C; UINT64 C;
} OPTEE_MESSAGE_PARAM_VALUE; } OPTEE_MESSAGE_PARAM_VALUE;
typedef union {
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION;
typedef struct { typedef struct {
UINT64 Attribute; UINT64 Attribute;
union { OPTEE_MESSAGE_PARAM_UNION Union;
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
} Union;
} OPTEE_MESSAGE_PARAM; } OPTEE_MESSAGE_PARAM;
#define OPTEE_MAX_CALL_PARAMS 4 #define OPTEE_MAX_CALL_PARAMS 4
@@ -114,4 +117,4 @@ OpteeInvokeFunction (
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
); );
#endif #endif // OPTEE_LIB_H_

6
ArmPkg/Include/Library/SemihostLib.h
View File

@@ -7,8 +7,8 @@
**/ **/
#ifndef __SEMIHOSTING_H__ #ifndef SEMIHOSTING_LIB_H_
#define __SEMIHOSTING_H__ #define SEMIHOSTING_LIB_H_
/* /*
* *
@@ -129,4 +129,4 @@ SemihostSystem (
IN CHAR8 *CommandLine IN CHAR8 *CommandLine
); );
#endif // __SEMIHOSTING_H__ #endif // SEMIHOSTING_LIB_H_

6
ArmPkg/Include/Library/StandaloneMmMmuLib.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __STANDALONEMM_MMU_LIB__ #ifndef STANDALONE_MM_MMU_LIB_
#define __STANDALONEMM_MMU_LIB__ #define STANDALONE_MM_MMU_LIB_
EFI_STATUS EFI_STATUS
ArmSetMemoryRegionNoExec ( ArmSetMemoryRegionNoExec (
@@ -33,4 +33,4 @@ ArmClearMemoryRegionReadOnly (
IN UINT64 Length IN UINT64 Length
); );
#endif /* __STANDALONEMM_MMU_LIB__ */ #endif /* STANDALONE_MM_MMU_LIB_ */

6
ArmPkg/Include/Ppi/ArmMpCoreInfo.h
View File

@@ -6,8 +6,8 @@
* *
**/ **/
#ifndef __ARM_MP_CORE_INFO_PPI_H__ #ifndef ARM_MP_CORE_INFO_PPI_H_
#define __ARM_MP_CORE_INFO_PPI_H__ #define ARM_MP_CORE_INFO_PPI_H_
#include <Guid/ArmMpCoreInfo.h> #include <Guid/ArmMpCoreInfo.h>
@@ -49,4 +49,4 @@ typedef struct {
extern EFI_GUID gArmMpCoreInfoPpiGuid; extern EFI_GUID gArmMpCoreInfoPpiGuid;
extern EFI_GUID gArmMpCoreInfoGuid; extern EFI_GUID gArmMpCoreInfoGuid;
#endif #endif // ARM_MP_CORE_INFO_PPI_H_

20
ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
View File

@@ -1,12 +1,12 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
System Control and Management Interface V1.0 @par Specification Reference:
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ - Arm System Control and Management Interface - Platform Design Document
DEN0056A_System_Control_and_Management_Interface.pdf (https://developer.arm.com/documentation/den0056/)
**/ **/
#ifndef ARM_SCMI_BASE_PROTOCOL_H_ #ifndef ARM_SCMI_BASE_PROTOCOL_H_
@@ -14,7 +14,8 @@
#include <Protocol/ArmScmi.h> #include <Protocol/ArmScmi.h>
#define BASE_PROTOCOL_VERSION 0x10000 #define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000
#define NUM_PROTOCOL_MASK 0xFFU #define NUM_PROTOCOL_MASK 0xFFU
#define NUM_AGENT_MASK 0xFFU #define NUM_AGENT_MASK 0xFFU
@@ -158,11 +159,10 @@ typedef struct _SCMI_BASE_PROTOCOL {
// SCMI Message IDs for Base protocol. // SCMI Message IDs for Base protocol.
typedef enum { typedef enum {
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR = 0x3, ScmiMessageIdBaseDiscoverVendor = 0x3,
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR = 0x4, ScmiMessageIdBaseDiscoverSubVendor = 0x4,
SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION = 0x5, ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS = 0x6 ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE; } SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */ #endif /* ARM_SCMI_BASE_PROTOCOL_H_ */

6
ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -89,10 +89,10 @@ EFI_STATUS
@param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance. @param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device. @param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device @param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear. supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps. range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates. @param[out] TotalRates Total number of rates.

32
ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,16 +22,16 @@ extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol. // Message Type for clock management protocol.
typedef enum { typedef enum {
SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES = 0x3, ScmiMessageIdClockAttributes = 0x3,
SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES = 0x4, ScmiMessageIdClockDescribeRates = 0x4,
SCMI_MESSAGE_ID_CLOCK_RATE_SET = 0x5, ScmiMessageIdClockRateSet = 0x5,
SCMI_MESSAGE_ID_CLOCK_RATE_GET = 0x6, ScmiMessageIdClockRateGet = 0x6,
SCMI_MESSAGE_ID_CLOCK_CONFIG_SET = 0x7 ScmiMessageIdClockConfigSet = 0x7
} SCMI_MESSAGE_ID_CLOCK; } SCMI_MESSAGE_ID_CLOCK;
typedef enum { typedef enum {
SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range. ScmiClockRateFormatDiscrete, // Non-linear range.
SCMI_CLOCK_RATE_FORMAT_LINEAR // Linear range. ScmiClockRateFormatLinear // Linear range.
} SCMI_CLOCK_RATE_FORMAT; } SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version. // Clock management protocol version.
@@ -57,12 +57,18 @@ typedef enum {
either Rate or Min/Max/Step triplet is valid. either Rate or Min/Max/Step triplet is valid.
*/ */
typedef struct { typedef struct {
union {
UINT64 Min; UINT64 Min;
UINT64 Rate;
};
UINT64 Max; UINT64 Max;
UINT64 Step; UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct {
UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE;
typedef union {
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE; } SCMI_CLOCK_RATE;
#pragma pack() #pragma pack()
@@ -133,10 +139,10 @@ EFI_STATUS
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance. @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device. @param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device @param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear. supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps. range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates. @param[out] TotalRates Total number of rates.

14
ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
View File

@@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved. Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -247,12 +247,12 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL {
} SCMI_PERFORMANCE_PROTOCOL; } SCMI_PERFORMANCE_PROTOCOL;
typedef enum { typedef enum {
SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES = 0x3, ScmiMessageIdPerformanceDomainAttributes = 0x3,
SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS = 0x4, ScmiMessageIdPerformanceDescribeLevels = 0x4,
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET = 0x5, ScmiMessageIdPerformanceLimitsSet = 0x5,
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET = 0x6, ScmiMessageIdPerformanceLimitsGet = 0x6,
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET = 0x7, ScmiMessageIdPerformanceLevelSet = 0x7,
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET = 0x8, ScmiMessageIdPerformanceLevelGet = 0x8,
} SCMI_MESSAGE_ID_PERFORMANCE; } SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */ #endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */

12
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
View File

@@ -1,7 +1,7 @@
/** @file /** @file
Generic ARM implementation of TimerLib.h Generic ARM implementation of TimerLib.h
Copyright (c) 2011-2016, ARM Limited. All rights reserved. Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,9 +20,9 @@
// Select appropriate multiply function for platform architecture. // Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM #ifdef MDE_CPU_ARM
#define MultU64xN MultU64x32 #define MULT_U64_X_N MultU64x32
#else #else
#define MultU64xN MultU64x64 #define MULT_U64_X_N MultU64x64
#endif #endif
@@ -121,7 +121,7 @@ MicroSecondDelay (
// = MicroSeconds x TICKS_PER_MICRO_SEC // = MicroSeconds x TICKS_PER_MICRO_SEC
// = MicroSeconds x Frequency.10^-6 // = MicroSeconds x Frequency.10^-6
TimerTicks64 = DivU64x32 ( TimerTicks64 = DivU64x32 (
MultU64xN ( MULT_U64_X_N (
MicroSeconds, MicroSeconds,
GetPlatformTimerFreq () GetPlatformTimerFreq ()
), ),
@@ -263,7 +263,7 @@ GetTimeInNanoSecond (
// Time = --------- x 1,000,000,000 // Time = --------- x 1,000,000,000
// Frequency // Frequency
// //
NanoSeconds = MultU64xN ( NanoSeconds = MULT_U64_X_N (
DivU64x32Remainder ( DivU64x32Remainder (
Ticks, Ticks,
TimerFreq, TimerFreq,
@@ -276,7 +276,7 @@ GetTimeInNanoSecond (
// will not overflow 64-bit. // will not overflow 64-bit.
// //
NanoSeconds += DivU64x32 ( NanoSeconds += DivU64x32 (
MultU64xN ( MULT_U64_X_N (
(UINT64) Remainder, (UINT64) Remainder,
1000000000U), 1000000000U),
TimerFreq TimerFreq

159
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c
View File

@@ -71,7 +71,7 @@ CHAR8 *gLdmStack[] = {
#define SIGN(_U) ((_U) ? "" : "-") #define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_W) ((_W) ? "!" : "") #define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"") #define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "") #define USER(_B) ((_B) ? "^" : "")
@@ -159,23 +159,24 @@ DisassembleArmInstruction (
) )
{ {
UINT32 OpCode; UINT32 OpCode;
CHAR8 *Type, *Root; CHAR8 *Type;
BOOLEAN I, P, U, B, W, L, S, H; CHAR8 *Root;
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
UINT32 Rn, Rd, Rm; UINT32 Rn, Rd, Rm;
UINT32 imode, offset_8, offset_12; UINT32 IMod, Offset8, Offset12;
UINT32 Index; UINT32 Index;
UINT32 shift_imm, shift; UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr; OpCode = **OpCodePtr;
I = (OpCode & BIT25) == BIT25; Imm = (OpCode & BIT25) == BIT25; // I
P = (OpCode & BIT24) == BIT24; Pre = (OpCode & BIT24) == BIT24; // P
U = (OpCode & BIT23) == BIT23; Up = (OpCode & BIT23) == BIT23; // U
B = (OpCode & BIT22) == BIT22; // Also called S WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
W = (OpCode & BIT21) == BIT21; Write = (OpCode & BIT21) == BIT21; // W
L = (OpCode & BIT20) == BIT20; Load = (OpCode & BIT20) == BIT20; // L
S = (OpCode & BIT6) == BIT6; Sign = (OpCode & BIT6) == BIT6; // S
H = (OpCode & BIT5) == BIT5; Half = (OpCode & BIT5) == BIT5; // H
Rn = (OpCode >> 16) & 0xf; Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf; Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf); Rm = (OpCode & 0xf);
@@ -189,7 +190,7 @@ DisassembleArmInstruction (
// LDREX, STREX // LDREX, STREX
if ((OpCode & 0x0fe000f0) == 0x01800090) { if ((OpCode & 0x0fe000f0) == 0x01800090) {
if (L) { if (Load) {
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>] // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else { } else {
@@ -201,89 +202,89 @@ DisassembleArmInstruction (
// LDM/STM // LDM/STM
if ((OpCode & 0x0e000000) == 0x08000000) { if ((OpCode & 0x0e000000) == 0x08000000) {
if (L) { if (Load) {
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers> // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^ // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^ // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else { } else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers> // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^ // A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} }
return; return;
} }
// LDR/STR Address Mode 2 // LDR/STR Address Mode 2
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) { if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
offset_12 = OpCode & 0xfff; Offset12 = OpCode & 0xfff;
if ((OpCode & 0xfd70f000 ) == 0xf550f000) { if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD"); Index = AsciiSPrint (Buf, Size, "PLD");
} else { } else {
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
} }
if (P) { if (Pre) {
if (!I) { if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>] // A5.2.2 [<Rn>, #+/-<offset_12>]
// A5.2.5 [<Rn>, #+/-<offset_12>] // A5.2.5 [<Rn>, #+/-<offset_12>]
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
} else if ((OpCode & 0x03000ff0) == 0x03000000) { } else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.3 [<Rn>, +/-<Rm>] // A5.2.3 [<Rn>, +/-<Rm>]
// A5.2.6 [<Rn>, +/-<Rm>]! // A5.2.6 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
} else { } else {
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>] // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]! // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
shift_imm = (OpCode >> 7) & 0x1f; ShiftImm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3; Shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) { if (Shift == 0x0) {
Type = "LSL"; Type = "LSL";
} else if (shift == 0x1) { } else if (Shift == 0x1) {
Type = "LSR"; Type = "LSR";
if (shift_imm == 0) { if (ShiftImm == 0) {
shift_imm = 32; ShiftImm = 32;
} }
} else if (shift == 0x2) { } else if (Shift == 0x2) {
Type = "ASR"; Type = "ASR";
} else if (shift_imm == 0) { } else if (ShiftImm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
return; return;
} else { } else {
Type = "ROR"; Type = "ROR";
} }
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
} }
} else { // !P } else { // !Pre
if (!I) { if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12> // A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
} else if ((OpCode & 0x03000ff0) == 0x03000000) { } else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.9 [<Rn>], +/-<Rm> // A5.2.9 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
} else { } else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm> // A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
shift_imm = (OpCode >> 7) & 0x1f; ShiftImm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3; Shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) { if (Shift == 0x0) {
Type = "LSL"; Type = "LSL";
} else if (shift == 0x1) { } else if (Shift == 0x1) {
Type = "LSR"; Type = "LSR";
if (shift_imm == 0) { if (ShiftImm == 0) {
shift_imm = 32; ShiftImm = 32;
} }
} else if (shift == 0x2) { } else if (Shift == 0x2) {
Type = "ASR"; Type = "ASR";
} else if (shift_imm == 0) { } else if (ShiftImm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
// FIx me // FIx me
return; return;
} else { } else {
Type = "ROR"; Type = "ROR";
} }
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
} }
} }
return; return;
@@ -292,18 +293,18 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x00000000) { if ((OpCode & 0x0e000000) == 0x00000000) {
// LDR/STR address mode 3 // LDR/STR address mode 3
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode> // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
if (L) { if (Load) {
if (!S) { if (!Sign) {
Root = "LDR%aH %a, "; Root = "LDR%aH %a, ";
} else if (!H) { } else if (!Half) {
Root = "LDR%aSB %a, "; Root = "LDR%aSB %a, ";
} else { } else {
Root = "LDR%aSH %a, "; Root = "LDR%aSH %a, ";
} }
} else { } else {
if (!S) { if (!Sign) {
Root = "STR%aH %a "; Root = "STR%aH %a ";
} else if (!H) { } else if (!Half) {
Root = "LDR%aD %a "; Root = "LDR%aD %a ";
} else { } else {
Root = "STR%aD %a "; Root = "STR%aD %a ";
@@ -312,28 +313,28 @@ DisassembleArmInstruction (
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
S = (OpCode & BIT6) == BIT6; Sign = (OpCode & BIT6) == BIT6;
H = (OpCode & BIT5) == BIT5; Half = (OpCode & BIT5) == BIT5;
offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (P & !W) { if (Pre & !Write) {
// Immediate offset/index // Immediate offset/index
if (B) { if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>] // A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]! // A5.3.4 [<Rn>, #+/-<offset_8>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else { } else {
// A5.3.3 [<Rn>, +/-<Rm>] // A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]! // A5.3.5 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
} }
} else { } else {
// Register offset/index // Register offset/index
if (B) { if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8> // A5.3.6 [<Rn>], #+/-<offset_8>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else { } else {
// A5.3.7 [<Rn>], +/-<Rm> // A5.3.7 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
} }
} }
return; return;
@@ -342,19 +343,19 @@ DisassembleArmInstruction (
if ((OpCode & 0x0fb000f0) == 0x01000050) { if ((OpCode & 0x0fb000f0) == 0x01000050) {
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>] // A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>] // A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]); AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
return; return;
} }
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) { if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!} // A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W)); AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
return; return;
} }
if ((OpCode & 0xfe500f00) == 0xf8100500) { if ((OpCode & 0xfe500f00) == 0xf8100500) {
// A4.1.59 RFE<addressing_mode> <Rn>{!} // A4.1.59 RFE<addressing_mode> <Rn>{!}
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W)); AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
return; return;
} }
@@ -369,9 +370,9 @@ DisassembleArmInstruction (
if (((OpCode >> 6) & 0x7) == 0) { if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f)); AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else { } else {
imode = (OpCode >> 18) & 0x3; IMod = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
(imode == 3) ? "ID":"IE", (IMod == 3) ? "ID":"IE",
((OpCode & BIT8) != 0) ? "A":"", ((OpCode & BIT8) != 0) ? "A":"",
((OpCode & BIT7) != 0) ? "I":"", ((OpCode & BIT7) != 0) ? "I":"",
((OpCode & BIT6) != 0) ? "F":""); ((OpCode & BIT6) != 0) ? "F":"");
@@ -390,19 +391,19 @@ DisassembleArmInstruction (
if ((OpCode & 0x0fb00000) == 0x01000000) { if ((OpCode & 0x0fb00000) == 0x01000000) {
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR // A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR"); AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
return; return;
} }
if ((OpCode & 0x0db00000) == 0x01200000) { if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm> // A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (I) { if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate> // MSR{<cond>} CPSR_<fields>, #<immediate>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2)); AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else { } else {
// MSR{<cond>} CPSR_<fields>, <Rm> // MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]); AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
} }
return; return;
} }
@@ -416,35 +417,35 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x0c000000) { if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC // A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) { if ((OpCode & 0xf0000000) == 0xf0000000) {
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd); Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
} else { } else {
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
} }
if (!P) { if (!Pre) {
if (!W) { if (!Write) {
// A5.5.5.5 [<Rn>], <option> // A5.5.5.5 [<Rn>], <option>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff); AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else { } else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4 // A.5.5.4 [<Rn>], #+/-<offset_8>*4
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff); AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
} }
} else { } else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]! // A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W)); AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
} }
} }
if ((OpCode & 0x0f000010) == 0x0e000010) { if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2 // A4.1.32 MRC2, MCR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7); AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return; return;
} }
if ((OpCode & 0x0ff00000) == 0x0c400000) { if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2 // A4.1.33 MRRC2, MCRR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm); AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return; return;
} }

158
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c
View File

@@ -9,6 +9,7 @@
try to reuse existing case entries if possible. try to reuse existing case entries if possible.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -451,7 +452,7 @@ SignExtend32 (
// in the instruction address and you get back the aligned answer // in the instruction address and you get back the aligned answer
// //
UINT32 UINT32
PCAlign4 ( PcAlign4 (
IN UINT32 Data IN UINT32 Data
) )
{ {
@@ -486,12 +487,19 @@ DisassembleThumbInstruction (
UINT32 Index; UINT32 Index;
UINT32 Offset; UINT32 Offset;
UINT16 Rd, Rn, Rm, Rt, Rt2; UINT16 Rd, Rn, Rm, Rt, Rt2;
BOOLEAN H1, H2, imod; BOOLEAN H1Bit; // H1
BOOLEAN H2Bit; // H2
BOOLEAN IMod; // imod
//BOOLEAN ItFlag; //BOOLEAN ItFlag;
UINT32 PC, Target, msbit, lsbit; UINT32 Pc, Target, MsBit, LsBit;
CHAR8 *Cond; CHAR8 *Cond;
BOOLEAN S, J1, J2, P, U, W; BOOLEAN Sign; // S
UINT32 coproc, opc1, opc2, CRd, CRn, CRm; BOOLEAN J1Bit; // J1
BOOLEAN J2Bit; // J2
BOOLEAN Pre; // P
BOOLEAN UAdd; // U
BOOLEAN WriteBack; // W
UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
UINT32 Mask; UINT32 Mask;
OpCodePtr = *OpCodePtrPtr; OpCodePtr = *OpCodePtrPtr;
@@ -504,10 +512,10 @@ DisassembleThumbInstruction (
Rd = OpCode & 0x7; Rd = OpCode & 0x7;
Rn = (OpCode >> 3) & 0x7; Rn = (OpCode >> 3) & 0x7;
Rm = (OpCode >> 6) & 0x7; Rm = (OpCode >> 6) & 0x7;
H1 = (OpCode & BIT7) != 0; H1Bit = (OpCode & BIT7) != 0;
H2 = (OpCode & BIT6) != 0; H2Bit = (OpCode & BIT6) != 0;
imod = (OpCode & BIT4) != 0; IMod = (OpCode & BIT4) != 0;
PC = (UINT32)(UINTN)OpCodePtr; Pc = (UINT32)(UINTN)OpCodePtr;
// Increment by the minimum instruction size, Thumb2 could be bigger // Increment by the minimum instruction size, Thumb2 could be bigger
*OpCodePtrPtr += 1; *OpCodePtrPtr += 1;
@@ -548,7 +556,7 @@ DisassembleThumbInstruction (
case LOAD_STORE_FORMAT3: case LOAD_STORE_FORMAT3:
// A6.5.1 <Rd>, [PC, #<8_bit_offset>] // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
Target = (OpCode & 0xff) << 2; Target = (OpCode & 0xff) << 2;
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
return; return;
case LOAD_STORE_FORMAT4: case LOAD_STORE_FORMAT4:
// Rt, [SP, #imm8] // Rt, [SP, #imm8]
@@ -583,16 +591,16 @@ DisassembleThumbInstruction (
Cond = gCondition[(OpCode >> 8) & 0xf]; Cond = gCondition[(OpCode >> 8) & 0xf];
Buf[Offset-5] = *Cond++; Buf[Offset-5] = *Cond++;
Buf[Offset-4] = *Cond; Buf[Offset-4] = *Cond;
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8)); AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
return; return;
case UNCONDITIONAL_BRANCH_SHORT: case UNCONDITIONAL_BRANCH_SHORT:
// A6.3.2 B <target_address> // A6.3.2 B <target_address>
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11)); AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
return; return;
case BRANCH_EXCHANGE: case BRANCH_EXCHANGE:
// A6.3.3 BX|BLX <Rm> // A6.3.3 BX|BLX <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]); AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
return; return;
case DATA_FORMAT1: case DATA_FORMAT1:
@@ -629,12 +637,12 @@ DisassembleThumbInstruction (
return; return;
case DATA_FORMAT8: case DATA_FORMAT8:
// A6.4.3 <Rd>|<Rn>, <Rm> // A6.4.3 <Rd>|<Rn>, <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
return; return;
case CPS_FORMAT: case CPS_FORMAT:
// A7.1.24 // A7.1.24
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f"); AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
return; return;
case ENDIAN_FORMAT: case ENDIAN_FORMAT:
@@ -645,13 +653,13 @@ DisassembleThumbInstruction (
case DATA_CBZ: case DATA_CBZ:
// CB{N}Z <Rn>, <Lable> // CB{N}Z <Rn>, <Lable>
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0); Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
return; return;
case ADR_FORMAT: case ADR_FORMAT:
// ADR <Rd>, <Label> // ADR <Rd>, <Label>
Target = (OpCode & 0xff) << 2; Target = (OpCode & 0xff) << 2;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
return; return;
case IT_BLOCK: case IT_BLOCK:
@@ -708,32 +716,32 @@ DisassembleThumbInstruction (
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1 Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
Target = SignExtend32 (Target, BIT20); Target = SignExtend32 (Target, BIT20);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
return; return;
case B_T4: case B_T4:
// S:I1:I2:imm10:imm11:0 // S:I1:I2:imm10:imm11:0
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000); Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
S = (OpCode32 & BIT26) == BIT26; Sign = (OpCode32 & BIT26) == BIT26;
J1 = (OpCode32 & BIT13) == BIT13; J1Bit = (OpCode32 & BIT13) == BIT13;
J2 = (OpCode32 & BIT11) == BIT11; J2Bit = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2 ^ S) ? BIT22 : 0); // I2 Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1 Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
Target |= (S ? BIT24 : 0); // S Target |= (Sign ? BIT24 : 0); // S
Target = SignExtend32 (Target, BIT24); Target = SignExtend32 (Target, BIT24);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
return; return;
case BL_T2: case BL_T2:
// BLX S:I1:I2:imm10:imm11:0 // BLX S:I1:I2:imm10:imm11:0
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000); Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
S = (OpCode32 & BIT26) == BIT26; Sign = (OpCode32 & BIT26) == BIT26;
J1 = (OpCode32 & BIT13) == BIT13; J1Bit = (OpCode32 & BIT13) == BIT13;
J2 = (OpCode32 & BIT11) == BIT11; J2Bit = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2 ^ S) ? BIT23 : 0); // I2 Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1 Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
Target |= (S ? BIT25 : 0); // S Target |= (Sign ? BIT25 : 0); // S
Target = SignExtend32 (Target, BIT25); Target = SignExtend32 (Target, BIT25);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
return; return;
case POP_T2: case POP_T2:
@@ -748,8 +756,8 @@ DisassembleThumbInstruction (
case STM_FORMAT: case STM_FORMAT:
// <Rn>{!}, <registers> // <Rn>{!}, <registers>
W = (OpCode32 & BIT21) == BIT21; WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff)); AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
return; return;
case LDM_REG_IMM12_SIGNED: case LDM_REG_IMM12_SIGNED:
@@ -759,7 +767,7 @@ DisassembleThumbInstruction (
// U == 0 means subtrack, U == 1 means add // U == 0 means subtrack, U == 1 means add
Target = -Target; Target = -Target;
} }
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
return; return;
case LDM_REG_INDIRECT_LSL: case LDM_REG_INDIRECT_LSL:
@@ -784,36 +792,36 @@ DisassembleThumbInstruction (
case LDM_REG_IMM8: case LDM_REG_IMM8:
// <rt>, [<rn>, {, #<imm8>}]{!} // <rt>, [<rn>, {, #<imm8>}]{!}
W = (OpCode32 & BIT8) == BIT8; WriteBack = (OpCode32 & BIT8) == BIT8;
U = (OpCode32 & BIT9) == BIT9; UAdd = (OpCode32 & BIT9) == BIT9;
P = (OpCode32 & BIT10) == BIT10; Pre = (OpCode32 & BIT10) == BIT10;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]); Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
if (P) { if (Pre) {
if ((OpCode32 & 0xff) == 0) { if ((OpCode32 & 0xff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
} }
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff); AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
} }
return; return;
case LDRD_REG_IMM8_SIGNED: case LDRD_REG_IMM8_SIGNED:
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!} // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
P = (OpCode32 & BIT24) == BIT24; // index = P Pre = (OpCode32 & BIT24) == BIT24; // index = P
U = (OpCode32 & BIT23) == BIT23; UAdd = (OpCode32 & BIT23) == BIT23;
W = (OpCode32 & BIT21) == BIT21; WriteBack = (OpCode32 & BIT21) == BIT21;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]); Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
if (P) { if (Pre) {
if ((OpCode32 & 0xff) == 0) { if ((OpCode32 & 0xff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]"); AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
} }
} else { } else {
if ((OpCode32 & 0xff) != 0) { if ((OpCode32 & 0xff) != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2); AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
} }
} }
return; return;
@@ -825,7 +833,7 @@ DisassembleThumbInstruction (
// U == 0 means subtrack, U == 1 means add // U == 0 means subtrack, U == 1 means add
Target = -Target; Target = -Target;
} }
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
return; return;
case LDREXB: case LDREXB:
@@ -840,14 +848,14 @@ DisassembleThumbInstruction (
case SRS_FORMAT: case SRS_FORMAT:
// SP{!}, #<mode> // SP{!}, #<mode>
W = (OpCode32 & BIT21) == BIT21; WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f); AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
return; return;
case RFE_FORMAT: case RFE_FORMAT:
// <Rn>{!} // <Rn>{!}
W = (OpCode32 & BIT21) == BIT21; WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
return; return;
case ADD_IMM12: case ADD_IMM12:
@@ -917,9 +925,9 @@ DisassembleThumbInstruction (
// ADDR <Rd>, <label> // ADDR <Rd>, <label>
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0); Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) { if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
Target = PCAlign4 (PC) - Target; Target = PcAlign4 (Pc) - Target;
} else { } else {
Target = PCAlign4 (PC) + Target; Target = PcAlign4 (Pc) + Target;
} }
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
return; return;
@@ -932,52 +940,52 @@ DisassembleThumbInstruction (
case BFC_THUMB2: case BFC_THUMB2:
// BFI <Rd>, <Rn>, #<lsb>, #<width> // BFI <Rd>, <Rn>, #<lsb>, #<width>
msbit = OpCode32 & 0x1f; MsBit = OpCode32 & 0x1f;
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c); LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){ if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
// BFC <Rd>, #<lsb>, #<width> // BFC <Rd>, #<lsb>, #<width>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) { } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1); AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
} }
return; return;
case CPD_THUMB2: case CPD_THUMB2:
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2> // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf; Coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf; Opc1 = (OpCode32 >> 20) & 0xf;
opc2 = (OpCode32 >> 5) & 0x7; Opc2 = (OpCode32 >> 5) & 0x7;
CRd = (OpCode32 >> 12) & 0xf; CRd = (OpCode32 >> 12) & 0xf;
CRn = (OpCode32 >> 16) & 0xf; CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf; CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm); Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
if (opc2 != 0) { if (Opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2); AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
} }
return; return;
case MRC_THUMB2: case MRC_THUMB2:
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2> // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf; Coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf; Opc1 = (OpCode32 >> 20) & 0xf;
opc2 = (OpCode32 >> 5) & 0x7; Opc2 = (OpCode32 >> 5) & 0x7;
CRn = (OpCode32 >> 16) & 0xf; CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf; CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm); Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
if (opc2 != 0) { if (Opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2); AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
} }
return; return;
case MRRC_THUMB2: case MRRC_THUMB2:
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2> // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf; Coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf; Opc1 = (OpCode32 >> 20) & 0xf;
CRn = (OpCode32 >> 16) & 0xf; CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf; CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm); Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
return; return;
case THUMB2_2REGS: case THUMB2_2REGS:

4
ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c
View File

@@ -2,6 +2,7 @@
* Exception Handling support specific for AArch64 * Exception Handling support specific for AArch64
* *
* Copyright (c) 2016 HP Development Company, L.P. * Copyright (c) 2016 HP Development Company, L.P.
* Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
@@ -27,7 +28,8 @@ RegisterEl0Stack (
IN VOID *Stack IN VOID *Stack
); );
RETURN_STATUS ArchVectorConfig( RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress IN UINTN VectorBaseAddress
) )
{ {

10
ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
View File

@@ -1,5 +1,5 @@
// //
// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR> // Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR> // Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
// Copyright (c) 2016 HP Development Company, L.P. // Copyright (c) 2016 HP Development Company, L.P.
// //
@@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
// //
// Current EL with SPx: 0x200 - 0x380 // Current EL with SPx: 0x200 - 0x380
// //
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC) VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)
ASM_PFX(SynchronousExceptionSPx): ASM_PFX(SynchronousExceptionSPx):
ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0 ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ) VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)
ASM_PFX(IrqSPx): ASM_PFX(IrqSPx):
ExceptionEntry EXCEPT_AARCH64_IRQ ExceptionEntry EXCEPT_AARCH64_IRQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ) VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)
ASM_PFX(FiqSPx): ASM_PFX(FiqSPx):
ExceptionEntry EXCEPT_AARCH64_FIQ ExceptionEntry EXCEPT_AARCH64_FIQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR) VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)
ASM_PFX(SErrorSPx): ASM_PFX(SErrorSPx):
ExceptionEntry EXCEPT_AARCH64_SERROR ExceptionEntry EXCEPT_AARCH64_SERROR

5
ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c
View File

@@ -2,7 +2,7 @@
* Exception handling support specific for ARM * Exception handling support specific for ARM
* *
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> * Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
* Copyright (c) 2014, ARM Limited. All rights reserved.<BR> * Copyright (c) 2014 - 2021, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2016 HP Development Company, L.P.<BR> * Copyright (c) 2016 HP Development Company, L.P.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -26,7 +26,8 @@ PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNME
// NOTE: This code assumes vectors are ARM and not Thumb code // NOTE: This code assumes vectors are ARM and not Thumb code
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE; UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS ArchVectorConfig( RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress IN UINTN VectorBaseAddress
) )
{ {

6
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
View File

@@ -8,8 +8,8 @@
**/ **/
#ifndef __AARCH64_LIB_H__ #ifndef AARCH64_LIB_H_
#define __AARCH64_LIB_H__ #define AARCH64_LIB_H_
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN); typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
@@ -52,5 +52,5 @@ ArmReadIdAA64Mmfr2 (
VOID VOID
); );
#endif // __AARCH64_LIB_H__ #endif // AARCH64_LIB_H_

6
ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
View File

@@ -6,8 +6,8 @@
**/ **/
#ifndef __ARM_V7_LIB_H__ #ifndef ARM_V7_LIB_H_
#define __ARM_V7_LIB_H__ #define ARM_V7_LIB_H_
#define ID_MMFR0_SHARELVL_SHIFT 12 #define ID_MMFR0_SHARELVL_SHIFT 12
#define ID_MMFR0_SHARELVL_MASK 0xf #define ID_MMFR0_SHARELVL_MASK 0xf
@@ -64,5 +64,5 @@ ArmReadIdPfr1 (
VOID VOID
); );
#endif // __ARM_V7_LIB_H__ #endif // ARM_V7_LIB_H_

6
ArmPkg/Library/ArmLib/ArmLibPrivate.h
View File

@@ -8,8 +8,8 @@
**/ **/
#ifndef __ARM_LIB_PRIVATE_H__ #ifndef ARM_LIB_PRIVATE_H_
#define __ARM_LIB_PRIVATE_H__ #define ARM_LIB_PRIVATE_H_
#define CACHE_SIZE_4_KB (3UL) #define CACHE_SIZE_4_KB (3UL)
#define CACHE_SIZE_8_KB (4UL) #define CACHE_SIZE_8_KB (4UL)
@@ -186,4 +186,4 @@ ReadCLIDR (
VOID VOID
); );
#endif // __ARM_LIB_PRIVATE_H__ #endif // ARM_LIB_PRIVATE_H_

4
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
View File

@@ -124,7 +124,7 @@ UpdatePageEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) { } else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// map to normal non-cachable // map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) { } else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes // modify cacheability attributes
@@ -254,7 +254,7 @@ UpdateSectionEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) { } else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// map to normal non-cachable // map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) { } else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes // modify cacheability attributes

6
ArmPkg/Library/ArmSoftFloatLib/platform.h
View File

@@ -1,11 +1,17 @@
/* /*
* Copyright (c) 2019, Linaro Limited * Copyright (c) 2019, Linaro Limited
* Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
*/ */
#ifndef ARM_SOFT_FLOAT_LIB_H_
#define ARM_SOFT_FLOAT_LIB_H_
#define LITTLEENDIAN 1 #define LITTLEENDIAN 1
#define INLINE static inline #define INLINE static inline
#define SOFTFLOAT_BUILTIN_CLZ 1 #define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_FAST_INT64 #define SOFTFLOAT_FAST_INT64
#include "opts-GCC.h" #include "opts-GCC.h"
#endif // ARM_SOFT_FLOAT_LIB_H_

6
ArmPkg/Library/OpteeLib/OpteeSmc.h
View File

@@ -7,8 +7,8 @@
**/ **/
#ifndef _OPTEE_SMC_H_ #ifndef OPTEE_SMC_H_
#define _OPTEE_SMC_H_ #define OPTEE_SMC_H_
/* Returned in Arg0 only from Trusted OS functions */ /* Returned in Arg0 only from Trusted OS functions */
#define OPTEE_SMC_RETURN_OK 0x0 #define OPTEE_SMC_RETURN_OK 0x0
@@ -47,4 +47,4 @@ typedef struct {
UINT8 Data4[8]; UINT8 Data4[8];
} RFC4122_UUID; } RFC4122_UUID;
#endif #endif // OPTEE_SMC_H_

6
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.h
View File

@@ -9,8 +9,8 @@
**/ **/
#ifndef _PLATFORM_BM_H_ #ifndef PLATFORM_BM_H_
#define _PLATFORM_BM_H_ #define PLATFORM_BM_H_
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
@@ -50,4 +50,4 @@ DisableQuietBoot (
VOID VOID
); );
#endif // _PLATFORM_BM_H_ #endif // PLATFORM_BM_H_

6
ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c
View File

@@ -37,11 +37,11 @@ SerialPortInitialize (
/** /**
Write data to serial device. Write data to serial device.
@param Buffer Point of data buffer which need to be writed. @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer. @param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed. @retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device. @retval !0 Actual number of bytes written to serial device.
**/ **/
@@ -103,7 +103,7 @@ SerialPortWrite (
/** /**
Read data from serial device and save the datas in buffer. Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed. @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer. @param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed. @retval 0 Read data failed.

26
ArmPkg/Library/SemihostLib/SemihostLib.c
View File

@@ -44,7 +44,7 @@ SemihostFileOpen (
OpenBlock.Mode = Mode; OpenBlock.Mode = Mode;
OpenBlock.NameLength = AsciiStrLen(FileName); OpenBlock.NameLength = AsciiStrLen(FileName);
Result = Semihost_SYS_OPEN(&OpenBlock); Result = SEMIHOST_SYS_OPEN (&OpenBlock);
if (Result == -1) { if (Result == -1) {
return RETURN_NOT_FOUND; return RETURN_NOT_FOUND;
@@ -66,7 +66,7 @@ SemihostFileSeek (
SeekBlock.Handle = FileHandle; SeekBlock.Handle = FileHandle;
SeekBlock.Location = Offset; SeekBlock.Location = Offset;
Result = Semihost_SYS_SEEK(&SeekBlock); Result = SEMIHOST_SYS_SEEK (&SeekBlock);
// Semihosting does not behave as documented. It returns the offset on // Semihosting does not behave as documented. It returns the offset on
// success. // success.
@@ -95,7 +95,7 @@ SemihostFileRead (
ReadBlock.Buffer = Buffer; ReadBlock.Buffer = Buffer;
ReadBlock.Length = *Length; ReadBlock.Length = *Length;
Result = Semihost_SYS_READ(&ReadBlock); Result = SEMIHOST_SYS_READ (&ReadBlock);
if ((*Length != 0) && (Result == *Length)) { if ((*Length != 0) && (Result == *Length)) {
return RETURN_ABORTED; return RETURN_ABORTED;
@@ -122,7 +122,7 @@ SemihostFileWrite (
WriteBlock.Buffer = Buffer; WriteBlock.Buffer = Buffer;
WriteBlock.Length = *Length; WriteBlock.Length = *Length;
*Length = Semihost_SYS_WRITE(&WriteBlock); *Length = SEMIHOST_SYS_WRITE (&WriteBlock);
if (*Length != 0) if (*Length != 0)
return RETURN_ABORTED; return RETURN_ABORTED;
@@ -135,7 +135,7 @@ SemihostFileClose (
IN UINTN FileHandle IN UINTN FileHandle
) )
{ {
if (Semihost_SYS_CLOSE (&FileHandle) == -1) { if (SEMIHOST_SYS_CLOSE (&FileHandle) == -1) {
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} else { } else {
return RETURN_SUCCESS; return RETURN_SUCCESS;
@@ -154,7 +154,7 @@ SemihostFileLength (
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
} }
Result = Semihost_SYS_FLEN(&FileHandle); Result = SEMIHOST_SYS_FLEN (&FileHandle);
if (Result == -1) { if (Result == -1) {
return RETURN_ABORTED; return RETURN_ABORTED;
@@ -195,7 +195,7 @@ SemihostFileTmpName(
TmpNameBlock.Identifier = Identifier; TmpNameBlock.Identifier = Identifier;
TmpNameBlock.Length = Length; TmpNameBlock.Length = Length;
Result = Semihost_SYS_TMPNAME (&TmpNameBlock); Result = SEMIHOST_SYS_TMPNAME (&TmpNameBlock);
if (Result != 0) { if (Result != 0) {
return RETURN_ABORTED; return RETURN_ABORTED;
@@ -220,7 +220,7 @@ SemihostFileRemove (
RemoveBlock.FileName = FileName; RemoveBlock.FileName = FileName;
RemoveBlock.NameLength = AsciiStrLen(FileName); RemoveBlock.NameLength = AsciiStrLen(FileName);
Result = Semihost_SYS_REMOVE(&RemoveBlock); Result = SEMIHOST_SYS_REMOVE (&RemoveBlock);
if (Result == 0) { if (Result == 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
@@ -258,7 +258,7 @@ SemihostFileRename(
RenameBlock.NewFileName = NewFileName; RenameBlock.NewFileName = NewFileName;
RenameBlock.NewFileNameLength = AsciiStrLen (NewFileName); RenameBlock.NewFileNameLength = AsciiStrLen (NewFileName);
Result = Semihost_SYS_RENAME (&RenameBlock); Result = SEMIHOST_SYS_RENAME (&RenameBlock);
if (Result != 0) { if (Result != 0) {
return RETURN_ABORTED; return RETURN_ABORTED;
@@ -272,7 +272,7 @@ SemihostReadCharacter (
VOID VOID
) )
{ {
return Semihost_SYS_READC(); return SEMIHOST_SYS_READC ();
} }
VOID VOID
@@ -280,7 +280,7 @@ SemihostWriteCharacter (
IN CHAR8 Character IN CHAR8 Character
) )
{ {
Semihost_SYS_WRITEC(&Character); SEMIHOST_SYS_WRITEC (&Character);
} }
VOID VOID
@@ -288,7 +288,7 @@ SemihostWriteString (
IN CHAR8 *String IN CHAR8 *String
) )
{ {
Semihost_SYS_WRITE0(String); SEMIHOST_SYS_WRITE0 (String);
} }
UINT32 UINT32
@@ -301,5 +301,5 @@ SemihostSystem (
SystemBlock.CommandLine = CommandLine; SystemBlock.CommandLine = CommandLine;
SystemBlock.CommandLength = AsciiStrLen(CommandLine); SystemBlock.CommandLength = AsciiStrLen(CommandLine);
return Semihost_SYS_SYSTEM(&SystemBlock); return SEMIHOST_SYS_SYSTEM (&SystemBlock);
} }

3
ArmPkg/Library/SemihostLib/SemihostLib.inf
View File

@@ -2,7 +2,7 @@
# Semihosting JTAG lib # Semihosting JTAG lib
# #
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -25,6 +25,7 @@
# #
[Sources.common] [Sources.common]
SemihostLib.c SemihostLib.c
SemihostPrivate.h
[Sources.ARM] [Sources.ARM]
Arm/GccSemihost.S | GCC Arm/GccSemihost.S | GCC

86
ArmPkg/Library/SemihostLib/SemihostPrivate.h
View File

@@ -1,14 +1,14 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR> Copyright (c) 2013 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
#ifndef __SEMIHOST_PRIVATE_H__ #ifndef SEMIHOST_PRIVATE_H_
#define __SEMIHOST_PRIVATE_H__ #define SEMIHOST_PRIVATE_H_
typedef struct { typedef struct {
CHAR8 *FileName; CHAR8 *FileName;
@@ -151,19 +151,19 @@ _Semihost_SYS_SYSTEM(
IN SEMIHOST_SYSTEM_BLOCK *SystemBlock IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
); );
#define Semihost_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock) #define SEMIHOST_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
#define Semihost_SYS_CLOSE(Handle) _Semihost_SYS_CLOSE(0x02, Handle) #define SEMIHOST_SYS_CLOSE(Handle) _Semihost_SYS_CLOSE(0x02, Handle)
#define Semihost_SYS_WRITE0(String) _Semihost_SYS_WRITE0(0x04, String) #define SEMIHOST_SYS_WRITE0(String) _Semihost_SYS_WRITE0(0x04, String)
#define Semihost_SYS_WRITEC(Character) _Semihost_SYS_WRITEC(0x03, Character) #define SEMIHOST_SYS_WRITEC(Character) _Semihost_SYS_WRITEC(0x03, Character)
#define Semihost_SYS_WRITE(WriteBlock) _Semihost_SYS_WRITE(0x05, WriteBlock) #define SEMIHOST_SYS_WRITE(WriteBlock) _Semihost_SYS_WRITE(0x05, WriteBlock)
#define Semihost_SYS_READ(ReadBlock) _Semihost_SYS_READ(0x06, ReadBlock) #define SEMIHOST_SYS_READ(ReadBlock) _Semihost_SYS_READ(0x06, ReadBlock)
#define Semihost_SYS_READC() _Semihost_SYS_READC(0x07, 0) #define SEMIHOST_SYS_READC() _Semihost_SYS_READC(0x07, 0)
#define Semihost_SYS_SEEK(SeekBlock) _Semihost_SYS_SEEK(0x0A, SeekBlock) #define SEMIHOST_SYS_SEEK(SeekBlock) _Semihost_SYS_SEEK(0x0A, SeekBlock)
#define Semihost_SYS_FLEN(Handle) _Semihost_SYS_FLEN(0x0C, Handle) #define SEMIHOST_SYS_FLEN(Handle) _Semihost_SYS_FLEN(0x0C, Handle)
#define Semihost_SYS_TMPNAME(TmpNameBlock) _Semihost_SYS_TMPNAME(0x0D, TmpNameBlock) #define SEMIHOST_SYS_TMPNAME(TmpNameBlock) _Semihost_SYS_TMPNAME(0x0D, TmpNameBlock)
#define Semihost_SYS_REMOVE(RemoveBlock) _Semihost_SYS_REMOVE(0x0E, RemoveBlock) #define SEMIHOST_SYS_REMOVE(RemoveBlock) _Semihost_SYS_REMOVE(0x0E, RemoveBlock)
#define Semihost_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock) #define SEMIHOST_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)
#define Semihost_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock) #define SEMIHOST_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
#elif defined(__GNUC__) // __CC_ARM #elif defined(__GNUC__) // __CC_ARM
@@ -175,38 +175,38 @@ GccSemihostCall (
IN UINTN SystemBlockAddress IN UINTN SystemBlockAddress
); // __attribute__ ((interrupt ("SVC"))); ); // __attribute__ ((interrupt ("SVC")));
#define Semihost_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock)) #define SEMIHOST_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))
#define Semihost_SYS_CLOSE(Handle) GccSemihostCall(0x02, (UINTN)(Handle)) #define SEMIHOST_SYS_CLOSE(Handle) GccSemihostCall(0x02, (UINTN)(Handle))
#define Semihost_SYS_WRITE0(String) GccSemihostCall(0x04, (UINTN)(String)) #define SEMIHOST_SYS_WRITE0(String) GccSemihostCall(0x04, (UINTN)(String))
#define Semihost_SYS_WRITEC(Character) GccSemihostCall(0x03, (UINTN)(Character)) #define SEMIHOST_SYS_WRITEC(Character) GccSemihostCall(0x03, (UINTN)(Character))
#define Semihost_SYS_WRITE(WriteBlock) GccSemihostCall(0x05, (UINTN)(WriteBlock)) #define SEMIHOST_SYS_WRITE(WriteBlock) GccSemihostCall(0x05, (UINTN)(WriteBlock))
#define Semihost_SYS_READ(ReadBlock) GccSemihostCall(0x06, (UINTN)(ReadBlock)) #define SEMIHOST_SYS_READ(ReadBlock) GccSemihostCall(0x06, (UINTN)(ReadBlock))
#define Semihost_SYS_READC() GccSemihostCall(0x07, (UINTN)(0)) #define SEMIHOST_SYS_READC() GccSemihostCall(0x07, (UINTN)(0))
#define Semihost_SYS_SEEK(SeekBlock) GccSemihostCall(0x0A, (UINTN)(SeekBlock)) #define SEMIHOST_SYS_SEEK(SeekBlock) GccSemihostCall(0x0A, (UINTN)(SeekBlock))
#define Semihost_SYS_FLEN(Handle) GccSemihostCall(0x0C, (UINTN)(Handle)) #define SEMIHOST_SYS_FLEN(Handle) GccSemihostCall(0x0C, (UINTN)(Handle))
#define Semihost_SYS_TMPNAME(TmpNameBlock) GccSemihostCall(0x0D, (UINTN)(TmpNameBlock)) #define SEMIHOST_SYS_TMPNAME(TmpNameBlock) GccSemihostCall(0x0D, (UINTN)(TmpNameBlock))
#define Semihost_SYS_REMOVE(RemoveBlock) GccSemihostCall(0x0E, (UINTN)(RemoveBlock)) #define SEMIHOST_SYS_REMOVE(RemoveBlock) GccSemihostCall(0x0E, (UINTN)(RemoveBlock))
#define Semihost_SYS_RENAME(RenameBlock) GccSemihostCall(0x0F, (UINTN)(RenameBlock)) #define SEMIHOST_SYS_RENAME(RenameBlock) GccSemihostCall(0x0F, (UINTN)(RenameBlock))
#define Semihost_SYS_SYSTEM(SystemBlock) GccSemihostCall(0x12, (UINTN)(SystemBlock)) #define SEMIHOST_SYS_SYSTEM(SystemBlock) GccSemihostCall(0x12, (UINTN)(SystemBlock))
#else // __CC_ARM #else // __CC_ARM
#define SEMIHOST_SUPPORTED FALSE #define SEMIHOST_SUPPORTED FALSE
#define Semihost_SYS_OPEN(OpenBlock) (-1) #define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
#define Semihost_SYS_CLOSE(Handle) (-1) #define SEMIHOST_SYS_CLOSE(Handle) (-1)
#define Semihost_SYS_WRITE0(String) #define SEMIHOST_SYS_WRITE0(String)
#define Semihost_SYS_WRITEC(Character) #define SEMIHOST_SYS_WRITEC(Character)
#define Semihost_SYS_WRITE(WriteBlock) (0) #define SEMIHOST_SYS_WRITE(WriteBlock) (0)
#define Semihost_SYS_READ(ReadBlock) ((ReadBlock)->Length) #define SEMIHOST_SYS_READ(ReadBlock) ((ReadBlock)->Length)
#define Semihost_SYS_READC() ('x') #define SEMIHOST_SYS_READC() ('x')
#define Semihost_SYS_SEEK(SeekBlock) (-1) #define SEMIHOST_SYS_SEEK(SeekBlock) (-1)
#define Semihost_SYS_FLEN(Handle) (-1) #define SEMIHOST_SYS_FLEN(Handle) (-1)
#define Semihost_SYS_TMPNAME(TmpNameBlock) (-1) #define SEMIHOST_SYS_TMPNAME(TmpNameBlock) (-1)
#define Semihost_SYS_REMOVE(RemoveBlock) (-1) #define SEMIHOST_SYS_REMOVE(RemoveBlock) (-1)
#define Semihost_SYS_RENAME(RenameBlock) (-1) #define SEMIHOST_SYS_RENAME(RenameBlock) (-1)
#define Semihost_SYS_SYSTEM(SystemBlock) (-1) #define SEMIHOST_SYS_SYSTEM(SystemBlock) (-1)
#endif // __CC_ARM #endif // __CC_ARM
#endif //__SEMIHOST_PRIVATE_H__ #endif // SEMIHOST_PRIVATE_H_

4
ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
View File

@@ -101,8 +101,8 @@ SendMemoryPermissionRequest (
} }
// Check error response from Callee. // Check error response from Callee.
if (*RetVal & BIT31) { if ((*RetVal & BIT31) != 0) {
// Bit 31 set means there is an error retured // Bit 31 set means there is an error returned
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and // See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and
// Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64. // Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
switch (*RetVal) { switch (*RetVal) {

4
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
View File

@@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2017 - 2018, ARM Limited. All rights reserved. # Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@@ -10,7 +10,7 @@
[Defines] [Defines]
INF_VERSION = 0x0001001A INF_VERSION = 0x0001001A
BASE_NAME = ArmMmuStandaloneMmCoreLib BASE_NAME = ArmMmuStandaloneMmCoreLib
FILE_GUID = da8f0232-fb14-42f0-922c-63104d2c70bd FILE_GUID = 44a741c2-655f-41fc-b066-179f5a9aa78a
MODULE_TYPE = MM_CORE_STANDALONE MODULE_TYPE = MM_CORE_STANDALONE
VERSION_STRING = 1.0 VERSION_STRING = 1.0
LIBRARY_CLASS = StandaloneMmMmuLib LIBRARY_CLASS = StandaloneMmMmuLib

98
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
View File

@@ -139,3 +139,101 @@ OemUpdateSmbiosInfo (
{ {
ASSERT (FALSE); ASSERT (FALSE);
} }
/** Fetches the Type 32 boot information status.
@return Boot status.
**/
MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
EFIAPI
OemGetBootStatus (
VOID
)
{
ASSERT (FALSE);
return BootInformationStatusNoError;
}
/** Fetches the chassis status when it was last booted.
@return Chassis status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisBootupState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis power supply/supplies status when last booted.
@return Chassis power supply/supplies status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisPowerSupplyState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis thermal status when last booted.
@return Chassis thermal status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisThermalState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis security status when last booted.
@return Chassis security status.
**/
MISC_CHASSIS_SECURITY_STATE
EFIAPI
OemGetChassisSecurityStatus (
VOID
)
{
ASSERT (FALSE);
return ChassisSecurityStatusNone;
}
/** Fetches the chassis height in RMUs (Rack Mount Units).
@return The height of the chassis.
**/
UINT8
EFIAPI
OemGetChassisHeight (
VOID
)
{
ASSERT (FALSE);
return 1U;
}
/** Fetches the number of power cords.
@return The number of power cords.
**/
UINT8
EFIAPI
OemGetChassisNumPowerCords (
VOID
)
{
ASSERT (FALSE);
return 1;
}

2
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
View File

@@ -23,7 +23,7 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
0, // Length, 0, // Length,
0 // Handle 0 // Handle
}, },
1, // Manufactrurer 1, // Manufacturer
MiscChassisTypeMainServerChassis, // Type MiscChassisTypeMainServerChassis, // Type
2, // Version 2, // Version
3, // SerialNumber 3, // SerialNumber

20
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
View File

@@ -39,6 +39,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
{ {
CHAR8 *OptionalStrStart; CHAR8 *OptionalStrStart;
CHAR8 *StrStart; CHAR8 *StrStart;
UINT8 *SkuNumberField;
UINTN RecordLength; UINTN RecordLength;
UINTN ManuStrLen; UINTN ManuStrLen;
UINTN VerStrLen; UINTN VerStrLen;
@@ -117,10 +118,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
ChaNumStrLen = StrLen (ChassisSkuNumber); ChaNumStrLen = StrLen (ChassisSkuNumber);
ContainedElementCount = InputData->ContainedElementCount; ContainedElementCount = InputData->ContainedElementCount;
ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);
if (ContainedElementCount > 1) {
ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT);
}
// //
// Two zeros following the last string. // Two zeros following the last string.
@@ -149,7 +147,11 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
(VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength); (VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength);
//ChassisSkuNumber //ChassisSkuNumber
*((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5; SkuNumberField = (UINT8 *)SmbiosRecord +
sizeof (SMBIOS_TABLE_TYPE3) -
sizeof (CONTAINED_ELEMENT) + ExtendLength;
*SkuNumberField = 5;
OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) +
ExtendLength + 1); ExtendLength + 1);
@@ -162,6 +164,14 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1); UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1);
StrStart += AssertTagStrLen + 1; StrStart += AssertTagStrLen + 1;
UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1); UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1);
SmbiosRecord->BootupState = OemGetChassisBootupState ();
SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();
SmbiosRecord->ThermalState = OemGetChassisThermalState ();
SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();
SmbiosRecord->Height = OemGetChassisHeight ();
SmbiosRecord->NumberofPowerCords = OemGetChassisNumPowerCords ();
// //
// Now we have got the full smbios record, call smbios protocol to add this record. // Now we have got the full smbios record, call smbios protocol to add this record.
// //

6
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c
View File

@@ -23,9 +23,9 @@
/** /**
Get next language from language code list (with separator ';'). Get next language from language code list (with separator ';').
@param LangCode Input: point to first language in the list. On @param LangCode Input: point to first language in the list. On
Otput: point to next language in the list, or Output: point to next language in the list, or
NULL if no more language in the list. NULL if no more language in the list.
@param Lang The first language in the list. @param Lang The first language in the list.
**/ **/

3
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
View File

@@ -16,6 +16,7 @@
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/OemMiscLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include "SmbiosMisc.h" #include "SmbiosMisc.h"
@@ -59,6 +60,8 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation)
SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32); SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);
SmbiosRecord->BootStatus = OemGetBootStatus ();
// //
// Now we have got the full smbios record, call smbios protocol to add this record. // Now we have got the full smbios record, call smbios protocol to add this record.
// //

100
ArmPlatformPkg/ArmPlatformPkg.ci.yaml Normal file
View File

@@ -0,0 +1,100 @@
## @file
# CI configuration for ArmPlatformPkg
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
## options defined .pytool/Plugin/LicenseCheck
"LicenseCheck": {
"IgnoreFiles": []
},
"EccCheck": {
## Exception sample looks like below:
## "ExceptionList": [
## "<ErrorID>", "<KeyWord>"
## ]
"ExceptionList": [
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
"Scripts/Ds5/"
]
},
## options defined .pytool/Plugin/CompilerPlugin
"CompilerPlugin": {
"DscPath": "ArmPlatformPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
"HostUnitTestCompilerPlugin": {
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/CharEncodingCheck
"CharEncodingCheck": {
"IgnoreFiles": []
},
## options defined .pytool/Plugin/DependencyCheck
"DependencyCheck": {
"AcceptableDependencies": [
"ArmPlatformPkg/ArmPlatformPkg.dec",
"ArmPkg/ArmPkg.dec",
"EmbeddedPkg/EmbeddedPkg.dec",
"MdeModulePkg/MdeModulePkg.dec",
"MdePkg/MdePkg.dec"
],
# For host based unit tests
"AcceptableDependencies-HOST_APPLICATION":[
"UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
],
# For UEFI shell based apps
"AcceptableDependencies-UEFI_APPLICATION":[],
"IgnoreInf": []
},
## options defined .pytool/Plugin/DscCompleteCheck
"DscCompleteCheck": {
"IgnoreInf": [],
"DscPath": "ArmPlatformPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
"HostUnitTestDscCompleteCheck": {
"IgnoreInf": [""],
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/GuidCheck
"GuidCheck": {
"IgnoreGuidName": [],
"IgnoreGuidValue": [],
"IgnoreFoldersAndFiles": [],
"IgnoreDuplicates": [],
},
## options defined .pytool/Plugin/LibraryClassCheck
"LibraryClassCheck": {
"IgnoreHeaderFile": []
},
## options defined .pytool/Plugin/SpellCheck
"SpellCheck": {
"AuditOnly": False,
"IgnoreFiles": [], # use gitignore syntax to ignore errors
# in matching files
"ExtendWords": [
"hdlcd",
"icdsgir",
"primecells"
], # words to extend to the dictionary for this package
"IgnoreStandardPaths": [ # Standard Plugin defined paths that
"*.asm", "*.s" # should be ignore
],
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
}
}

19
ArmPlatformPkg/ArmPlatformPkg.dec
View File

@@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2011-2018, ARM Limited. All rights reserved. # Copyright (c) 2011-2021, ARM Limited. All rights reserved.
# Copyright (c) 2015, Intel Corporation. All rights reserved. # Copyright (c) 2015, Intel Corporation. All rights reserved.
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -26,11 +26,28 @@
Include # Root include for the package Include # Root include for the package
[LibraryClasses] [LibraryClasses]
## @libraryclass Provides an interface to query platform information.
#
ArmPlatformLib|Include/Library/ArmPlatformLib.h ArmPlatformLib|Include/Library/ArmPlatformLib.h
## @libraryclass Provides an interface to initialize/shutdown a LCD screen.
#
LcdHwLib|Include/Library/LcdHwLib.h LcdHwLib|Include/Library/LcdHwLib.h
## @libraryclass Provides an interface to configure a LCD screen.
#
LcdPlatformLib|Include/Library/LcdPlatformLib.h LcdPlatformLib|Include/Library/LcdPlatformLib.h
## @libraryclass Provides a Nor flash interface.
#
NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
## @libraryclass Provides an interface to the clock of a PL011 device.
#
PL011UartClockLib|Include/Library/PL011UartClockLib.h PL011UartClockLib|Include/Library/PL011UartClockLib.h
## @libraryclass Provides an interface to a PL011 uart.
#
PL011UartLib|Include/Library/PL011UartLib.h PL011UartLib|Include/Library/PL011UartLib.h
[Guids.common] [Guids.common]

2
ArmPlatformPkg/ArmPlatformPkg.dsc
View File

@@ -33,6 +33,8 @@
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0 gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFdSize|0x1000 gArmTokenSpaceGuid.PcdFdSize|0x1000
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common] [LibraryClasses.common]
ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf

1
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf
View File

@@ -29,7 +29,6 @@
MdeModulePkg/MdeModulePkg.dec MdeModulePkg/MdeModulePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec EmbeddedPkg/EmbeddedPkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec
[LibraryClasses] [LibraryClasses]
BaseLib BaseLib

12
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c
View File

@@ -1,10 +1,10 @@
/** @file /** @file
*
* Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR> Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2016, Linaro Limited. All rights reserved. Copyright (c) 2016, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/

10
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/

14
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
View File

@@ -1,10 +1,10 @@
/** @file ## @file
* #
* Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR> # Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
* #
* SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
* #
**/ ##
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005

12
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
View File

@@ -1,10 +1,10 @@
/** @file /** @file
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved. Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2018, Linaro Limited. All rights reserved. Copyright (c) 2018, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/

10
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/

16
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
View File

@@ -1,11 +1,11 @@
/** @file ## @file
* #
* Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR> # Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2018, Linaro Limited. All rights reserved. # Copyright (c) 2018, Linaro Limited. All rights reserved.
* #
* SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
* #
**/ ##
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005

10
ArmPlatformPkg/Include/Library/ArmPlatformLib.h
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved. Copyright (c) 2011-2013, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/
#ifndef _ARMPLATFORMLIB_H_ #ifndef _ARMPLATFORMLIB_H_

10
ArmPlatformPkg/Include/Library/PL011UartClockLib.h
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright 2018 NXP Copyright 2018 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/
#ifndef __PL011UARTCLOCKLIB_H__ #ifndef __PL011UARTCLOCKLIB_H__

10
ArmPlatformPkg/Include/Library/PL011UartLib.h
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011-2016, ARM Limited. All rights reserved. Copyright (c) 2011-2016, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/
#ifndef __PL011_UART_LIB_H__ #ifndef __PL011_UART_LIB_H__

10
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved. Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/
#include <Library/ArmLib.h> #include <Library/ArmLib.h>

10
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c
View File

@@ -1,9 +1,9 @@
/** @file /** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved. Copyright (c) 2011, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/ **/
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>

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