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585 Commits

Author SHA1 Message Date
2b549700ac UefiPayloadPkg: Enable ESRT
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-05-29 14:29:10 -06:00
88f5720e16 MdeModulePkg/UsbBusDxe: fix NOOPT build error
gcc-11 (fedora 35):

/home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c: In function ?UsbIoBulkTransfer?:
/home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c:277:12: error: ?UsbHcBulkTransfer? accessing 80 bytes in a region of size 8 [-Werror=stringop-overflow=]

Upstream commit ae8272ef78

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2024-02-21 09:11:18 -07:00
27585e73da Update DBX to 2023-05-09
Ref: https://uefi.org/revocationlistfile
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-06-27 08:16:14 -06:00
42a443d5cd SecurityPkg: Fix debug build
For some reason only DEBUG builds fail because of the unused variable.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-06-22 13:41:43 -06:00
c466cc2ca5 Add System76 Secure Boot keys
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 18:10:00 -07:00
5c49aca613 Update DBX to 2022-09-07
Ref: https://uefi.org/revocationlistfile
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 18:10:00 -07:00
99891bd41e SecureBootConfig: Remove blank line
Remove the blank between "Delete..." and "Restore...".

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
3485d55709 SecureBootConfig: Split long strings
firmware-setup does not wrap long lines, so manually split long strings.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
c1a7127e01 SecureBootConfig: Clear PK and reset
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
2f21eddfb8 SecureBootConfig: Restore keys and reset
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
860c29c923 SecureBootConfig: Update variable and perform reset
Update the `SecureBootEnable` variable and perform a platform reset when
the enable/disable button is pressed.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
8cfead2839 SecureBootConfig: Add text key to perform the actions
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
30f6b2f3c7 SecureBootConfig: Modify UI
Rewrite the UI based on feedback from enabling the module.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
4de32568fa UiApp: Link to SecureBootConfig
Shoehorn in logic from Device Manager to show only the Secure Boot
Config entry under the firmware config form.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
ff91020528 Notify System76 security callback prior to loading boot options 2023-03-06 15:01:34 -07:00
943773983d BaseTools: Fix DevicePath tool build failure issue
Fix the DevicePath tool build failure that was introduced by
the fixes: 22130dcd98 ("Basetools: turn off gcc12 warning").
Failure cases are:
1. clang 13.1.6 on macOS
2. gcc5.4

Reported-by: Rebecca Cran <rebecca@bsdio.com>
Reported-by: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2022-08-17 11:40:12 -06:00
e91ea5561d Basetools: turn off gcc12 warning
In function ?SetDevicePathEndNode?,
    inlined from ?FileDevicePath? at DevicePathUtilities.c:857:5:
DevicePathUtilities.c:321:3: error: writing 4 bytes into a region of size 1 [-Werror=stringop-overflow=]
  321 |   memcpy (Node, &mUefiDevicePathLibEndDevicePath, sizeof (mUefiDevicePathLibEndDevicePath));
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from UefiDevicePathLib.h:22,
                 from DevicePathUtilities.c:16:
../Include/Protocol/DevicePath.h: In function ?FileDevicePath?:
../Include/Protocol/DevicePath.h:51:9: note: destination object ?Type? of size 1
   51 |   UINT8 Type;       ///< 0x01 Hardware Device Path.
      |         ^~~~

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
5e86b202de BaseTools: fix gcc12 warning
Sdk/C/LzmaEnc.c: In function ?LzmaEnc_CodeOneMemBlock?:
Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*p.rc.outStream? [-Werror=dangling-pointer=]
 2828 |   p->rc.outStream = &outStream.vt;
      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
      |                            ^~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*(CLzmaEnc *)pp.rc.outStream? [-Werror=dangling-pointer=]
 2828 |   p->rc.outStream = &outStream.vt;
      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
      |                            ^~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
cc1: all warnings being treated as errors

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
b764882195 BaseTools: fix gcc12 warning
GenFfs.c:545:5: error: pointer ?InFileHandle? used after ?fclose? [-Werror=use-after-free]
  545 |     Error(NULL, 0, 4001, "Resource", "memory cannot be allocated  of %s", InFileHandle);
      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GenFfs.c:544:5: note: call to ?fclose? here
  544 |     fclose (InFileHandle);
      |     ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
a2abc5e15f UefiPayloadPkg: Add Pop!_OS Recovery to boot text
Preserve existing UI and add the note about pressing Space to go to
the systemd-boot menu for Pop!_OS Recovery.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-12-21 15:25:08 -07:00
a618e43977 MdeModulePkg/BmBootDesciption: Remove device prefixes
Remove the device prefixes to match current System76 firmware UI in the
One Time Boot menu.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-16 10:10:20 -07:00
bbc04972bc UefiPayloadPkg: Add PCI support from DuetPkg
In coreboot, we mark GPU prefmem above 4GB, because NVIDIA wants a lot
(16GB region on the 30 series), otherwise coreboot will obviously fail
to allocate the resources.

In EDK2, we then end up hitting this assert:

    InitRootBridge: populated root bus 0, with room for 36 subordinate bus(es)
    RootBridge: PciRoot(0x0)
      Support/Attr: 7001F / 7001F
        DmaAbove4G: No
    NoExtConfSpace: No
         AllocAttr: 0 ()
               Bus: 0 - 24 Translation=0
                Io: 1000 - EFFF Translation=0
               Mem: 80400000 - 1001FFFFFF Translation=0
        MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
              PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
       PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
    ASSERT [PciHostBridgeDxe] .../edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c(120): Bridge->Mem.Limit < 0x0000000100000000ULL

So, bring back Pci*NoEnumerationDxe from the deleted DuetPkg, which
doesn't check anything and let's us boot.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
61a7f360d9 UefiPayloadPkg: Add Intel GOP driver 2021-11-11 17:49:07 -07:00
fc1c47ccad UefiPayloadPkg: Add System76 Setup menu 2021-11-11 17:49:07 -07:00
fec64b04eb Update brotli to fix compiling with GCC 11 2021-11-11 17:49:07 -07:00
05aa27ef23 MdeModulePkg/BM: Update boot options on device change
Register an event to trigger when a block device is added or removed
that will update the list of boot options. Use a refreshguid to force
the form to display the changes if it already open.
2021-11-11 17:49:07 -07:00
06cc698885 MdeModulePkg/Core: Signal notify events on protocol removal
In order for BootManager to maintain a valid list of boot options, it
must know when the BlockIo protocol is also removed, not just added.
2021-11-11 17:49:07 -07:00
cb870a1ce9 UiApp: Dynamically generated firmware configuration information page
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
90e04a7e31 MdeModulePkg/BMM: Unregister F9 and F10 hotkeys 2021-11-11 17:49:07 -07:00
1d01d2a9a7 MdeModulePkg/BMM: Remove Commit/Discard buttons 2021-11-11 17:49:07 -07:00
70e9b22f5c MdeModulePkg/BMM: Save BootOrder on list update 2021-11-11 17:49:07 -07:00
e9d6369050 MdeModulePkg/BMM: Add some debug logging 2021-11-11 17:49:07 -07:00
58d6aae969 MdeModulePkg/UiApp: Add warning if no bootable options found 2021-11-11 17:49:07 -07:00
4e0fcaba18 MdeModulePkg/BootMaintenanceManagerUiLib: Make it look like current BMM 2021-11-11 17:49:07 -07:00
2d04a62512 MdeModulePkg/UiApp: Make it look like current FrontPage
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
8a0955dfa8 MdeModulePkg/BM: Make it look like current BootMngr 2021-11-11 17:49:07 -07:00
06f4583ea5 UefiPayloadPkg: Disable EFI shell 2021-11-02 19:24:49 -06:00
9daa69a59e UefiPayloadPkg: Add library for logging to EC
Make use of the SMFI command interface to forward logs from edk2 to
System76 EC.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-02 19:24:49 -06:00
9030464a1b fix secureboot
TODO: Proper integration
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bcfe7a54aa UefiPayloadPkg/Include/Coreboot.h: Remove __packed
The keyword is not defined and will end as public variable beeing declared
in every source that includes the header.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
600c565eb2 Revert "UefiPayloadPkg: Add FV Guid for DXEFV and PLDFV"
This reverts commit 4bac086e8e.
Breaks coreboot integration.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
aae506ce44 UefiPayloadPkg/BlSMMStoreDxe: Support Secureboot
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bf2ca74bb6 UefiPayloadPkg: Update APRIORI
Make sure that:
* FaultTolerantDxe is started before VariableRuntimeDxe
  This ensures that FailedTolerantPei is not required and faults when writing
  the variable store are discovered
* SMBUSConfigLoader is started right after VariableRuntimeDxe
  This ensured that the board specific variables are updated as soon as possible
* Start SmbiosDxe and BlSupportDxeSmbios early to install board specific NULL protocols
* Start SecureBootConfigDxe right after VariableRuntimeDxe to update SecureBootKeys before
  Tcg2Dxe starts

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
654e5958cd Fix TPM detection
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
9657bbe08f MdeModulePkg: Be more verbose about SecureBoot and the reason why the boot failed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
10cbbe06d3 [HACK]UefiPayloadPkg: Fix TPM2 support without PEI
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
802391f1fe UefiPayloadPkg/SecureBootEnrollDefaultKeys: Make SecureBoot configurable
Signed-off-by: Christian Walter <christian.walter@9elements.com>
2021-11-02 19:24:49 -06:00
db04386fd9 UefiPayloadPkg: Check TPM PPI requests in PlatformBootManager
Test if the user need to confirm TPM Physical presence commands.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
7d5abcd016 UefiPayloadPkg: Parse coreboot's TPM PPI handoff buffer
Read the coreboot table containing the TPM PPI handoff buffer and
place it in gEfiTcgPhysicalPresenceInfoHob.

coreboot uses the same PPI interface as QEMU does and installs the
corresponding ACPI code to provide a full PPI interface to the OS.
The OS must reboot in order to execute the requests.

The corresponding coreboot patch can be found here:
https://review.coreboot.org/c/coreboot/+/45568

In a follow up commit the OvmfPkg PhysicalPresence library will be used
to confirm TPM PPI request. This is necessary as coreboot doesn't have
input drivers or a graphical UI that could be used.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d296a36cc4 OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu: Add timeout
Instead of waiting and infinite time, abort the TPM PPI request after
3 minutes. This allow to boot headless platforms where no keyboard is
attached or the user didn't made it in time.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bdb15bf9ba OvmfPkg: Introduce Tcg2PhysicalPresencePlatformLib
Put the PPI configuration retriveal into an own library.
That will allow to reuse the code in the UefipayloadPkg, where the
firmware provides the ACPI tables, like QEMU does on OvmfPkg.

However one major difference is that the PPI interface in UefiPayloadPkg
is not backed by a MMIO device, but resides in DRAM and is shared with ACPI code.

Add an additional parameter to provide the location of the PPI and
test if the memory region has the correct attributes.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
25af751320 UefiPayloadPkg: Add TPM support
* Add support for TPM1.2 and TPM2.

This adds measured boot support and will be extended with Secureboot.

Signed-off-by: Christian Walter <christian.walter@9elements.com>
2021-11-02 19:24:49 -06:00
7f99fae217 UefiPayloadPkg: Advertise TPM support in BlSupportDxe
In BlSupportDxe read the AcpiBoardInfo and set PcdTpmInstanceGuid
to indicate that a TPM is likely present as TPM tables had been installed
by the bootloader.

The Tcg*Dxes will probe for the TPM, so no need to do it here as well.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
c134065066 UefiPayloadPkg: Check more ACPI tables
Probe for ACPI tables
* TPM2
* TCPA
and store the result in AcpiBoardInfo.

Will be used to determine if a TPM1.2 or TPM2.0 is present.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
eec38fd383 UefiPayloadPkg: Add Secureboot support
Must use RuntimeVariableDxe instead of EmuVariableDxe.
Currently doesn't boot on qemu.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
b9564773f1 UefiPayloadPkg: Scan for Option ROMs
Install the gPciPlatformProtocol to scan for Option ROMs.

For every device we probe the Option ROM and provide a pointer
to the activated BAR if found.

It's safe to assume that all ROM bars have been enumerated,
reserved in the bridge resources and are disabled by default.
This is made a mandatory bootloader requirement in the next commit.

Enabling them and leaving them enabled will do no harm.

This can easily be tested on qemu, where it will start finding Option ROMs
for VGA and network cards.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
2021-11-02 19:24:49 -06:00
8c767bb014 Ps2KbdCtrller: Make wait for SUCCESS after BAT non-fatal
Recent model Chromebooks only return ACK, but not
BAT_SUCCESS, which causes hanging and failed ps2k init.
To mitigate this, make the absence of BAT_SUCCESS reply
non-fatal, and reduce the no-reply timeout from 4s to 1s.

Tested on google/dracia and purism/librem_14

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
7386ad5ae3 UefiPayloadPkg: don't set PcdDebugPropertyMask for release builds
Don't set PcdDebugPropertyMask for release builds, and properly set it
for debug builds based on SOURCE_DEBUG_ENABLE.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
e727453a97 SdMmcPciDxe: Reduce timeout for SD card reset
Previous 1s timeout causeed stalls on boot splash with no benefit.
Reduced to 100ms and no interruptions to boot when no SD card inserted.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
553bda4d8e BaseTools: array.fromstring and array.tostring removed in python 3.9
array.fromstring and array.tostring deprecated, and alias for
array.frombytes and array.tobytes. Deprecated since version 3.2,
have been removed in version python 3.9.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yunhua Feng <fengyunhua@byosoft.com.cn>
2021-11-02 19:24:49 -06:00
3e7febc83c BlSMMStoreDxe: make error msgs unique
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
b664a5352c UefiPayloadPkg: Allow boot timeout to be set via cmd line
Allows for devices w/o internal display to set a longer timeout
via coreboot Kconfig

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
b376a7d60f ShellPkg: disable startup script, show welcome banner
Startup script does nothing other than confuse users.
Show a welcome banner and tell users how to exit.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
3fb944f925 UefiPayloadPkg: Update APRIORI
Make sure that:
* FaultTolerantDxe is started before VariableRuntimeDxe
  This ensures that FailedTolerantPei is not required and faults when writing
  the variable store are discovered
* Start BlSupportDxeSmbios early to install board specific NULL protocols

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
1d70aa7a9b UefiCpuPkg: Disable MTRR programming for UefiPayloadPkg
The MTRRs have already been programmed by FSB.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
0bef9ccd43 UefiPayloadPkg: Add support for Firmware Volume Block Protocol
This adds support for FVB in order to support a platform independent
and non-volatile variable store on UefiPayloadPkg. It is required for
non-volatile variable support, TPM support, Secureboot support and more.

Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports
the SMMSTORE v2 feature. It implements a SMI handler that is able to
write, read and erase pages in the boot media (SPI flash).
The communication is done using a fixed communication buffer that is
allocated in CBMEM. The existence of this optional feature is advertised
by a coreboot table.
When the SMMSTORE feature is not available the variable emulation is used
by setting PcdEmuVariableNvModeEnable to TRUE.

Add a library for SMMStore to be used in DXE.

The DXE component provides runtime services and takes care of virtual to
physical mapping the communication buffers between SMM and OS.

Make use of the APRIORI DXE to initialize an empty store on the first boot
and set the PCDs to sane values before the variable driver is loaded.

Tests on Intel(R) Xeon(R) E-2288G CPU @ 3.70G showed that the SMI isn't
triggered with a probability of 1:40 of all cases when called in a tight
loop. The CPU continues running and the SMI is triggeres asynchronously
a few clock cycles later. coreboot only handels synchronous APM request
and does nothing on asynchronous APM triggers.

As there's no livesign from SMM it's impossible to tell if the handler
has run. Just wait a bit and try again to trigger a synchronous SMI.

Tests confirmed that out of 5 million tries the SMI is now always handled.

Tested on Linux and Windows 10 on real hardware.
Currently this cannot be tested on coreboot and qemu as it doesn't support
the SMMSTORE on qemu.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d3b38ea28a UefiPayloadPkg/Library/PlatformBootManagerLib: Remove broken VGA detection
This fixes an issue where the framebuffer provided by coreboot or
slimbootloader will only work on the primary VGA device. If the
framebuffer corresponds to a different device the screen will stay black.
In addition, the code doesn't work for multiple graphic cards, has
reference to non existing functions, and is a duplication of common code.

Call EfiBootManagerConnectVideoController on every display device found,
not only the legacy VGA device. This is the same as OvmfPkg does.

Allows to display output on the framebuffer set up by firmware, which might
not be the VGA device.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
69ae47ba5d UefiPayloadPkg: Add RNG support
Uses the RDRAND instruction if available and install EfiRngProtocol.
The protocol may be used by iPXE or the Linux kernel to gather entropy.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
95c492569f UefiPayloadPkg: Use new filesystem drivers
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d996a4bc9f Add filesystem drivers
Add EXT2/EXT4, exFAT, NTFS filesystem drivers.
Do not add ISO9115 drivers as it breaks El Torito boot.
2021-11-02 19:24:49 -06:00
9f528fb4c0 MdeModulePkg/Usb/Keyboard.c: don't request protocol before setting
No need to check the interface protocol then conditionally setting,
just set it to BOOT_PROTOCOL and check for error.

This is what Linux does for HID devices as some don't follow the USB spec.
One example is the Aspeed BMC HID keyboard device, which adds a massive
boot delay without this patch as it doesn't respond to 'GetProtocolRequest'.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bbab5b95b4 MdeModulePkg/Usb/Keyboard.c: remove Get/SetConfig calls
SetConfig is already called during device enumeration,
no need to do it again here.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
5e84cc0714 UefiPayloadPkg: Reduce timeout to 2s
Current firmware does not honor PcdPlatformBootTimeOut and hard-codes a
timeout of 2s.
2021-11-02 19:24:48 -06:00
2af54dd5bd UefiPayloadPkg: Stall before connecting devices
USB devices are not being detected when booting. Pause a bit for them to
be initialized and detected by EfiBootManagerConnectAll().
2021-11-02 19:24:48 -06:00
00283317d8 MdeModulePkg/BdsDxe: Forward any key for booting
Pressing escape will bring a user to the boot manager. Pressing any
other key will continue booting, forwarding the key to systemd-boot.
2021-11-02 19:24:48 -06:00
232f661f99 MdeModulePkg: Wait for input after boot failure
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
552ca5cc88 UefiPayloadPkg: Clear screen on boot error 2021-11-02 19:24:48 -06:00
94e7cfc7e7 UefiPayloadPkg: Copy PlatformBootManagerUnableToBoot() from OvmfPkg 2021-11-02 19:24:48 -06:00
de7030ed26 UefiPayloadPkg: Set ResetOnMemoryTypeInformationChange to FALSE
the default value, TRUE, causes reboots if a device boots to the
shell, exits, and then attempts to boot from another source.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
587653cd8b MdeModulePkg/SdMmcPciHcDxe: add Bayhub support
Add support for Bayhub eMMC controller found on AMD
Stoneyridge Chromebooks.

Test: build/boot various google/kahlee-based devices

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
e167ed1a3d MdeModulePkg/GraphicsConsole: don't draw cursor at 0,0
Prevents cursor from flashing on screen when
changing modes or clearing the screen.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
003534f8f0 MdeModulePkg/BmBootDesciption: Improve device descriptions
Add device type prefixes for USB, IDE, SATA, and NVMe drives.
Remove UEFI prefix, remove serial numbers.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
a363907bc9 MdeModulePkg/BmBoot: skip secondary eMMC entries
Internal eMMC devices often show multiple entries, so skip
any after the initial entry.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
530cc53f96 MdeModulePkg/Frontpage: get SMBIOS Data from table directly
rather than getting it from the EFI SMBIOS protocol

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
112268c70d MdeModulePkg/GraphicsConsole: Don't re-set video output mode
Fixes display resolution issues with booting OS X

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
726280b214 UefiPayloadPkg: Disable Device Manager 2021-11-02 19:24:48 -06:00
b1ab82d4c8 BmpSupportLib: fix BMP validation
BMP files by tools other than MS paint can have a
variable number of padding bytes, which results in
the DataSize being less than (ImageSize - HeaderSize).
Fix the check to be less stringent.

Test: use BMP created by/saved by Photoshop

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
2e16857f3d MdeModulePkg: load boot logo into BGRT table
This is a shoehorned-in implementation of an ACPI BGRT
table, ported pretty much directly from the version used
under CorebootPayloadPkg.

EDK2 provides a facility to do this already, but it assumes
the ACPI tables already exist as EFI structures, so would need
to write code to populate those using the tables already in RAM
created by coreboot. This seemed like the easier option ATM.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
308f9a49b0 MdeModulePkg/BootLogoLib: Center logo 38.2% from top of screen
Use Microsoft's recommended positioning [1] for the boot logo.

> We recommend that the logo is placed with its center at 38.2% from the
> screen's top edge. This positioning is based on the golden ratio's
> visual aesthetics and matches the Windows 10 design proportions.

[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/boot-screen-components#position-the-logo-during-post
2021-11-02 19:24:48 -06:00
7ab09015b1 MdeModulePkg/Logo: Use System76 boot logo 2021-11-02 19:24:48 -06:00
d1c0828262 UefiPayloadPkg: Enable boot logo 2021-11-02 19:24:48 -06:00
b4dd94c217 UefiPayloadPkg: Show boot message as progress text
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
f428f538b6 UefiPayloadPkg: Map ESC to Boot Manager
Change menu key from F2 to ESC, remove extranous text
2021-11-02 19:24:48 -06:00
75b91c0b9f UefiPayloadPkg: Enable PS2 keyboard by default 2021-10-21 21:32:54 -06:00
9f1dd0acb1 UefiPayloadPkg: Default to coreboot 2021-10-21 21:32:54 -06:00
6db1a5555a UefiPayloadPkg: Increase FV size
The following commits need additional space.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-10-21 21:24:56 -06:00
72f8b9d80b UefiPayloadPkg: Fix the build error when enable Core ci for UefiPayloadPkg
V1: Add quotes when using $(ARCH) in .dsc and .fdf file.
The quotes are added due to the way by which Core ci parse the .dsc file.
Add UINTN in Hob.c to fix cast from pointer to integer of different size error.
V2: Delete lines which reference ShellBinPkg.The pkg doesn't exist in edk2.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: DunTan <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I18c2027f57a4fbf291925a11226ed620b808a970
2021-10-21 21:24:48 -06:00
7b4a99be8a CryptoPkg: BaseCryptLib fix incorrect param order
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3550

Function ConvertAsn1TimeToEfiTime initializes timestamp to zeroes with
SetMem, but the actual parameters are out of order. The result is
the SetMem operation has no effect. The fix is to put the actual
parameters in the correct order.

Signed-off-by: Chris Stewart <chris.stewart@hp.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
2021-08-24 00:35:06 +00:00
8dd4fc5be6 UefiCpuPkg/CpuCacheInfoLib: Correct logical for identifying cache type
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Correct the logical for identifying "Direct mapped" cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-08-23 07:49:17 +00:00
ef56f55d19 EmbeddedPkg/NonCoherentDmaLib: Avoid dereferencing unset Map field
Map->Operation is used to select whether a DMA region that
is being bounced has the source buffer copied to it. Except
Map->Operation isn't yet set, so the behavior is somewhat
random. Instead use the passed in Operation parameter.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-17 14:01:19 +00:00
6fdd1c13a7 MdeModulePkg PCD: Reinstall PCD service PPIS when memory available
https://bugzilla.tianocore.org/show_bug.cgi?id=3525

After PciSegmentLib using Dynamic PCD for Pcie base address such
long delay found in FSP. The root cause is some of the PCD service
PPIs not shadowed to memory and flash cache may have been disabled
in NotifyPhase stage. Solution is to shadow all PCD service PPIs
to memory.

Signed-off-by: GregX Yeh <gregx.yeh@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2021-08-13 01:44:41 +00:00
ac826886c9 MdeModulePkg/UefiSortLib:Add UefiSortLib unit test
Adding two unit test case for UefiSortLib. One is a test on
sorting an array of UINT32 by using PerformQuickSort, another
is a test on comparing the same buffer by using StringCompare.
Add 'main' function name to ECC exception list to avoid ECC
error.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-08-12 08:34:04 +00:00
a776bbabd9 StandaloneMmPkg: build for 32bit arm machines
This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side directory
for several components:  StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-11 11:32:32 +00:00
b7f0226a46 StandaloneMmPkg: fix pointer/int casts against 32bit architectures
Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 11:32:32 +00:00
ca1773878d GenFv: Arm: support images entered in Thumb mode
Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
the entry instruction executes in Thumb mode.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 11:32:32 +00:00
aee0098faf ArmPkg: prepare 32bit ARM build of StandaloneMmPkg
Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.

Adds ArmmmuStandaloneMmLib library to the list of the standard
components build for ArmPkg on when ARM architectures.

Changes path of source file AArch64/ArmMmuStandaloneMmLib.c
and compile it for both 32bit and 64bit architectures.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-11 11:32:32 +00:00
03e19e6bc8 ArmPkg/IndustryStandard: 32b/64b agnostic FF-A, Mm SVC and Std SMC IDs
Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 11:32:32 +00:00
7311e96417 RedfishPkg/RefishCrtLib: Public RefishCrtLib
Public the header file, move RefishCrtLib.h from PrivateInclude/
to Include/.
RefishCrtLib.lib will be public later. (Moved out from PrivateLibrary/)

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-08-11 05:03:31 +00:00
3d359ff905 MdePkg: Fix broken coding style in Acpi64.h
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Fix a coding style issue raised by EccCheck. This issue (error code
7008) has been fixed by moving a nested union out of its structure.

Also add Acpi64.h to the "IgnoreFiles" list to stop the CI flagging
naming errors present prior to ACPI 64.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
605c4a1ff2 MdePkg: Add Cache ID to PPTT
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.137, Table 5.140, Table 5.141
- Mantis ID 2138 (https://mantis.uefi.org/mantis/view.php?id=2138)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
1803757a9b MdePkg: Add Secure Access Components in the SDEV table
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Section 5.2.26.1.1
- Mantis ID 2111 (https://mantis.uefi.org/mantis/view.php?id=2111)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
75c4a8e10d MdePkg: Add the Platform Health Assessment Table (PHAT)
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.5, Section 5.2.30
- Mantis ID 2094 (https://mantis.uefi.org/mantis/view.php?id=2094)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
0938f9235c MdePkg: Add Multiprocessor Wakeup structure
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.21, Section 5.2.12.19
- Mantis ID 2087 (https://mantis.uefi.org/mantis/view.php?id=2087)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
7b17bcd9a0 MdePkg: Add 'Type 5' PCC structure
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Section 14.1.7, Section 14.4
- Mantis ID 2010 (https://mantis.uefi.org/mantis/view.php?id=2010)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
357383bc4f MdePkg: Add flags and MinTransferSize to Generic Initiator
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.59, Section 5.2.27.1 & Section 5.2.27.4
- Mantis ID 1991 (https://mantis.uefi.org/mantis/view.php?id=1991)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
c82d6dd4a3 MdePkg: Remove DPPT table
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.5
- Mantis ID 2133 (https://mantis.uefi.org/mantis/view.php?id=2133)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
ced4cb7609 MdePkg: Add SPA Location Cookie field to SPA Range structure
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Section 5.2.25.2 System Physical Address (SPA)
  Range Structure, Table 5.109
- Mantis ID 1988 (https://mantis.uefi.org/mantis/view.php?id=1988)

Also added a blank line between #defines and structure definitions to
improve readability.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
ad3dea9861 MdePkg: Update PMTT to ACPI 6.4
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Section 5.2.21.12
- Mantis ID 1975 (https://mantis.uefi.org/mantis/view.php?id=1975)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
d910e83299 MdePkg: Rename SBSA Generic Watchdog to Arm Generic Watchdog
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Section 5.2.24, Table 5.100 & Section 5.2.24.2
- Mantis ID 2126 (https://mantis.uefi.org/mantis/view.php?id=2126)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
4d7137f261 MdePkg: Increment FADT version
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5-9
- Mantis ID 2105 (https://mantis.uefi.org/mantis/view.php?id=2105)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
5963ce5d28 MdePkg: Add ACPI 6.4 header file
Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

This patch introduces a header file for the ACPI specification version
6.4. Currently it is based on the Acpi63.h header file however makes
six changes:

1. Replace all occurences of "6_3"/"6.3" with "6_4/6.4".
2. Remove the trailing underscore from the header guard in accordance
   with the EDK2 coding standards, section 5.3.5.
3. Make Acpi64.h the latest ACPI definition included by Acpi.h.
4. Fix the BGRT Status field comment to match the ACPI 6.3A spec.
5. Fix several typos where definitions were named "PMMT" when it should
   be "PMTT".
6. Fix a typo: "PPTT Platform Communication Channel" should be "PDTT
   Platform Communication Channel".

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-08-11 01:53:28 +00:00
a7ddc7847c RedfishPkg/JsonLib: Add more JsonLib functions
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-08-10 09:59:05 -07:00
d02dbb53cd UefiPayloadPkg: Fix the non-ascii character in UniversalPayloadEntry.c
Fix the non-ascii character in UniversalPayloadEntry.c

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: DunTan <dun.tan@intel.com>
2021-08-09 07:55:53 +00:00
672bd1c711 UefiPayloadPkg: Add a macro to enable or diable the serial driver.
This patch doesn't change the default behavior.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-08-09 04:05:44 +00:00
ac6e5d6b41 UefiPayloadPkg: change the default value of some PCDs.
Change the default value of the below PCDs to diable some legacy feature.
  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-08-09 04:05:44 +00:00
d497eace3b UefiPayloadPkg: define some PCD as DynamicEX PCD
Define some PCDs as DynamicEX PCD to be used as global variable.
Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code
to set it in platformlib. That code was actually redundant.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-08-09 04:05:44 +00:00
b40bdd6ecd UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.
Add the three PCDs as fixed at build PCD:
  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
The default value is defined as Macro, so it can be passed in at build
command.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-08-09 04:05:44 +00:00
3c6107758b SecurityPkg: Fix GetSupportedAndActivePcrs counter calculation
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2855
The Tpm2GetCapabilitySupportedAndActivePcrs function prints a
count number that should reflect the *supported and currently
active* PCR banks, but the implementation in place displays
instead the count of the *supported PCR banks* retrieved
directly from the Tpm2GetCapabilityPcrs()
TPML_PCR_SELECTION output.

The counter should only take into account those PCRs banks
which are active.

Replaced usage of EFI_D_* for DEBUG_* definitions in debug
messages.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Signed-off-by: Rodrigo Gonzalez del Cueto <rodrigo.gonzalez.del.cueto@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-08-09 03:32:24 +00:00
4de77ae989 UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508

Sort the CpuCacheInfo array by CPU package ID, core type, cache level
and cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-08-09 03:01:17 +00:00
97fdcbda4e OvmfPkg: Remove Initrd LINUX_EFI_INITRD_MEDIA_GUID
Moving LINUX_EFI_INITRD_MEDIA_GUID to MdePkg, remove it from OvmfPkg.

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-05 21:35:47 +00:00
0856cdc89e MdePkg: add definition of LINUX_EFI_INITRD_MEDIA_GUID
Add LINUX_EFI_INITRD_MEDIA_GUID to our collection of GUID definitions,
it can be used in a media device path to specify a Linux style initrd
that can be loaded by the OS using the LoadFile2 protocol.

Move these defines to MdePkg from OvmfPkg as these are relevant to
non-OVMF targets as well.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2564
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-05 21:35:47 +00:00
9abc60f9f7 EmbeddedPkg/libfdt: Add strcmp and strncpy to libfdt_env.h
OpenSBI has started using those in v0.9. See:
https://github.com/riscv/opensbi/blob/v0.9/lib/utils/fdt/fdt_domain.c

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
2021-08-05 06:11:34 +00:00
6355287206 Maintainers.txt: Add new maintainer and reviewer to EmbeddedPkg/
Add Abner Chang as the maintainer of EmbeddedPkg/
Add Daniel Schaefer as the reviewer of EmbeddedPkg/

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ard Biesheuvel <ardb+tianocore@kernel.org>
Reviewed-by: Andrew Fish <afish@apple.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-08-05 05:17:55 +00:00
55266a9b8a SecurityPkg: Add option to reset secure boot keys.
This commit add option which allows reset content of Secure Boot
keys and databases to default variables.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Tested-by: Pete Batard <pete@akeo.ie> # on Raspberry Pi 4
2021-08-03 07:26:41 +00:00
45f3dd2ce9 SecurityPkg: Add new modules to Security package.
This commits adds modules and dependencies  related
to initialization and usage of default Secure Boot
 key variables to SecurityPkg.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Tested-by: Pete Batard <pete@akeo.ie> # on Raspberry Pi 4
2021-08-03 07:26:41 +00:00
19107590b6 SecurityPkg: Add EnrollFromDefaultKeys application.
This application allows user to force key enrollment from
Secure Boot default variables.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-08-03 07:26:41 +00:00
94e065582b SecurityPkg: Add SecureBootDefaultKeysDxe driver
This driver initializes default Secure Boot keys and databases
based on keys embedded in flash.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Tested-by: Pete Batard <pete@akeo.ie> # on Raspberry Pi 4
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-08-03 07:26:41 +00:00
a97e9e327e ArmPlatformPkg: Create include file for default key content.
This commits add file which can be included by platform Flash
Description File. It allows to specify certificate files, which
will be embedded into binary file. The content of these files
can be used to initialize Secure Boot default keys and databases.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-03 07:26:41 +00:00
db959018b6 SecurityPkg: Remove duplicated functions from SecureBootConfigDxe.
This commit removes functions which were added
to SecureBootVariableLib. It also adds dependecy
on that library.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-08-03 07:26:41 +00:00
b926956418 EmulatorPkg: add SecureBootVariableLib class resolution
The edk2 patch
  SecurityPkg: Create library for setting Secure Boot variables.

moves generic functions from SecureBootConfigDxe and places
them into SecureBootVariableLib. This patch adds SecureBootVariableLib
mapping for EmulatorPkg.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-08-03 07:26:41 +00:00
3d427c5f83 OvmfPkg: add SecureBootVariableLib class resolution
The edk2 patch
  SecurityPkg: Create library for setting Secure Boot variables.

moves generic functions from SecureBootConfigDxe and places
them into SecureBootVariableLib. This patch adds SecureBootVariableLib
mapping for OvmfPkg.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-03 07:26:41 +00:00
12a4d0cb9d ArmVirtPkg: add SecureBootVariableLib class resolution
The edk2 patch
  SecurityPkg: Create library for setting Secure Boot variables.

moves generic functions from SecureBootConfigDxe and places
them into SecureBootVariableLib. This patch adds SecureBootVariableLib
mapping for ArmVirtPkg platform.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-08-03 07:26:41 +00:00
9732659698 SecurityPkg: Create library for enrolling Secure Boot variables.
This commits add library, which consist functions to
enrolll Secure Boot keys and initialize Secure Boot
default variables. Some of the functions was moved
 from SecureBootConfigImpl.c file.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-08-03 07:26:41 +00:00
bb806a6e88 SecurityPkg: Create SecureBootVariableLib.
This commits add library, which consist helper functions related
to creation/removal Secure Boot variables. Some of the functions
was moved from SecureBootConfigImpl.c file.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-08-03 07:26:41 +00:00
2b47aaecef MdeModulePkg: Add BootDiscoveryPolicyUiLib.
This library extends Boot Maintenance Menu and allows to select
Boot Discovery Policy. When choice is made BootDiscoveryPolicy
variable is set. Platform code can use this variable to decide
which class of device shall be connected.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-08-03 04:59:12 +00:00
03e77558d4 BaseTools: use shutil.copyfile instead shutil.copy2
In Split tool, the copy file actions only need to
copy file content but not need to copy file metadata.

copy2() copies the file metadata that causes split
unit test failed under edk2-basetools CI environment.

So this patch changes the call of copy2() to copyfile().

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2021-08-02 03:52:15 +00:00
fc50df0d8e BaseTools: Drop check for distutils.utils
distutils.utils is no longer used anywhere, so this check can
be dropped.

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2021-08-02 03:09:59 +00:00
0b1b0a9674 python: Replace distutils.utils.split_quotes with shlex.split
distutils is deprecated and may be removed in python 3.12.
Use shlex.split which has been around since python 2.3.

shlex.split does not split on all the ASCII control characters that
split_quoted will[1], but for edk2 usage I don't think that matters.

[1] https://stackoverflow.com/questions/54999301/what-is-the-difference-between-distutils-util-split-quoted-and-shlex-split

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-08-02 03:09:59 +00:00
2e1fb41339 build: Fix python3.10 threading DeprecationWarnings
threading camelCase functions have preferred alternatives since
python2.6. python3.10 has started emitting DeprecationWarnings
for them

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-08-02 03:09:59 +00:00
3445058aea MdeModulePkg/CapsuleApp: Fix typo in error message
Fix typo in error message in CapsuleApp.

Signed-off-by: Seonghyun Park <shpark1@protonmail.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-08-02 01:56:19 +00:00
610bcc69ed ArmVirtPkg: Remove meaningless comment
The "Shell Embedded Boot Loader" description (added in
commit 6f5872b1f4) does not add any value, remove it.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Julien Grall <julien@xen.org>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-07-29 10:13:32 +00:00
8e6bb64fe4 EmbeddedPkg/VirtualRealTimeClockLib: Fix SetTime issues
This patch fixes two issues below:
1. SCT SetTime_Func failures.
   - https://github.com/pftf/RPi4/issues/164
2. Using shell time and date commands to set time can't work.

The problem is that gRT->SetTime always returns EFI_INVALID_PARAMETER
error status.

The root cause is that LibSetTime() sets RtcEpochSeconds variable with
inconsistent attributes. One is without EFI_VARIABLE_NON_VOLATILE,
the other one is with EFI_VARIABLE_NON_VOLATILE. That caused that the
variable driver returns EFI_INVALID_PARAMETER. Per UEFI spec, if a
preexisting variable is rewritten with different attributes,
SetVariable() shall not modify the variable and shall return
EFI_INVALID_PARAMETER.

Therefore, the solution is to add EFI_VARIABLE_NON_VOLATILE attribute
to the first EfiSetVariable() call to make two calls consistent.

By the way, this patch also fix a minor issue with a debug message.

Signed-off-by: Sunny Wang <sunny.wang@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Tested-by: Pete Batard <pete@akeo.ie>
2021-07-29 10:13:32 +00:00
514b3aa08e OvmfPkg/AmdSev: Enforce hash verification of kernel blobs
In the AmdSevX64 build, use BlobVerifierLibSevHashes to enforce
verification of hashes of the kernel/initrd/cmdline blobs fetched from
firmware config.

This allows for secure (measured) boot of SEV guests with QEMU's
-kernel/-initrd/-append switches (with the corresponding QEMU support
for injecting the hashes table into initial measured guest memory).

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
385b9d80a0 OvmfPkg/AmdSev: add BlobVerifierLibSevHashes
Add an implementation for BlobVerifierLib that locates the SEV hashes
table and verifies that the calculated hashes of the kernel, initrd, and
cmdline blobs indeed match the expected hashes stated in the hashes
table.

If there's a missing hash or a hash mismatch then EFI_ACCESS_DENIED is
returned which will cause a failure to load a kernel image.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Co-developed-by: James Bottomley <jejb@linux.ibm.com>
Signed-off-by: James Bottomley <jejb@linux.ibm.com>
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
[ardb: add CryptoPkg to accepted dependencies list for CI]
2021-07-29 09:49:50 +00:00
0deeab36d1 OvmfPkg/AmdSev: reserve MEMFD space for for firmware config hashes
Split the existing 4KB page reserved for SEV launch secrets into two
parts: first 3KB for SEV launch secrets and last 1KB for firmware
config hashes.

The area of the firmware config hashes will be attested (measured) by
the PSP and thus the untrusted VMM can't pass in different files from
what the guest owner allows.

Declare this in the Reset Vector table using GUID
7255371f-3a3b-4b04-927b-1da6efa8d454 and a uint32_t table of a base
and size value (similar to the structure used to declare the launch
secret block).

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Co-developed-by: Dov Murik <dovmurik@linux.ibm.com>
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Signed-off-by: James Bottomley <jejb@linux.ibm.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
5ace477f34 OvmfPkg/AmdSev/SecretPei: build hob for full page
Round up the size of the SEV launch secret area to a whole page, as
required by BuildMemoryAllocationHob.  This will allow the secret
area defined in the MEMFD to take less than a whole 4KB page.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
d10ad8444f OvmfPkg/QemuKernelLoaderFsDxe: call VerifyBlob after fetch from fw_cfg
In QemuKernelLoaderFsDxeEntrypoint we use FetchBlob to read the content
of the kernel/initrd/cmdline from the QEMU fw_cfg interface.  Insert a
call to VerifyBlob after fetching to allow BlobVerifierLib
implementations to add a verification step for these blobs.

This will allow confidential computing OVMF builds to add verification
mechanisms for these blobs that originate from an untrusted source
(QEMU).

The null implementation of BlobVerifierLib does nothing in VerifyBlob,
and therefore no functional change is expected.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Co-developed-by: James Bottomley <jejb@linux.ibm.com>
Signed-off-by: James Bottomley <jejb@linux.ibm.com>
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
6bf5580a3d ArmVirtPkg: add BlobVerifierLibNull to DSC
This prepares the ground for calling VerifyBlob() in
QemuKernelLoaderFsDxe.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
c73e31f54d OvmfPkg: add BlobVerifierLibNull to DSC
This prepares the ground for calling VerifyBlob() in
QemuKernelLoaderFsDxe.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
0cb48007f7 OvmfPkg: add library class BlobVerifierLib with null implementation
BlobVerifierLib will be used to verify blobs fetching them from QEMU's
firmware config (fw_cfg) in platforms that enable such verification.

The null implementation BlobVerifierLibNull treats all blobs as valid.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
a26a08dc1f OvmfPkg: PlatformBootManagerLibGrub: Allow executing kernel via fw_cfg
Support QEMU's -kernel option.

Create a QemuKernel.c for PlatformBootManagerLibGrub
which is an exact copy of the file
PlatformBootManagerLib/QemuKernel.c .

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: James Bottomley <jejb@linux.ibm.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
35e267cb34 OvmfPkg/AmdSev: use GenericQemuLoadImageLib in AmdSev builds
Newer kernels support efistub and therefore don't need all the legacy
stuff in X86QemuLoadImageLib, which are harder to secure.  Specifically
the verification of kernel/initrd/cmdline blobs will be added only to
the GenericQemuLoadImageLib implementation, so use that for SEV builds.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
f05eb2dfe5 OvmfPkg/AmdSev/SecretDxe: fix header comment to generic naming
Commit 96201ae7bf ("OvmfPkg/AmdSev/SecretDxe: make secret location
naming generic", 2020-12-15) replaced references to SEV with the generic
term Confidential Computing, but missed the file header comment.  Fix
the naming in that header.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: James Bottomley <jejb@linux.ibm.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-07-29 09:49:50 +00:00
dc485c556d OvmfPkg/ResetVector: add the macro to request guest termination
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The upcoming SEV-SNP support will need to make a few additional guest
termination requests depending on the failure type. Let's move the logic
to request the guest termination into a macro to keep the code readable.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb+tianocore@kernel.org>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
2021-07-29 01:04:51 +00:00
7f05102f65 OvmfPkg/ResetVector: add the macro to invoke MSR protocol based VMGEXIT
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The upcoming SEV-SNP support will need to make a few additional MSR
protocol based VMGEXIT's. Add a macro that wraps the common setup and
response validation logic in one place to keep the code readable.

While at it, define SEV_STATUS_MSR that will be used to get the SEV STATUS
MSR instead of open coding it.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb+tianocore@kernel.org>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
2021-07-29 01:04:51 +00:00
b461d67639 OvmfPkg/ResetVector: move SEV specific code in a separate file
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The PageTables64.asm was created to provide routines to set the CR3
register for 64-bit paging. During the SEV support, it grew to include a
lot of the SEV stuff. Before adding more SEV features, let's move all
the SEV-specific routines into a separate file.

No functionality change intended.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb+tianocore@kernel.org>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
2021-07-29 01:04:51 +00:00
ab796d3e2a NetworkPkg: Add HTTP Additional Event Notifications
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3496

Add new EDKII_HTTP_CALLBACK_PROTOCOL in NetworkPkg,
Send HTTP Events via EDKII_HTTP_CALLBACK_PROTOCOL
when Dns/ConnectTcp/TlsConnectSession/InitSession
occurs.

Signed-off-by: Heng Luo <heng.luo@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2021-07-28 16:19:19 +00:00
ac70e71b1f NetworkPkg: Making the HTTP IO timeout value programmable with PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3507

HTTP boot has a default set forced timeout value of 5 seconds
for getting the recovery image from a remote source.
This change allows the HTTP boot flow to get the IO timeout value
from the PcdHttpIoTimeout.
PcdHttpIoTimeout value is set in platform code.

Signed-off-by: Zachary Clark-Williams <zachary.clark-williams@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2021-07-28 16:19:19 +00:00
147f34b56c CryptoPkg/OpensslLib: Commit the auto-generated assembly files for X64
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2507

Adding the auto-generated assembly files for X64 architectures.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Christopher Zurcher <christopher.zurcher@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-07-26 07:30:11 +00:00
878a92a887 CryptoPkg/OpensslLib: Add native instruction support for X64
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2507

Adding OpensslLibX64.inf and modifying process_files.pl to process this
file and generate the necessary assembly files.
Adding OpensslLibX64Gcc.inf to allow building with GCC toolchain.
ApiHooks.c contains a stub function for a Windows API call.
uefi-asm.conf contains the limited assembly configurations for OpenSSL.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Christopher Zurcher <christopher.zurcher@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-07-26 07:30:11 +00:00
4d28a1c2fd BaseTools: Remove COMMON section from the GCC discard list
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2507

The COMMON section is used by OpenSSL assembly-optimized crypto
functions. OpenSSL assembly code is auto-generated from the submodule
and cannot be modified to remove dependence on the COMMON section.
The default -fno-common compiler flag should still prevent variable from
being emitted into the COMMON section.

Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Christopher Zurcher <christopher.zurcher@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-07-26 07:30:11 +00:00
332632abf3 Maintainers.txt: Add Jiewen Yao as OvmfPkg Maintainer
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-07-22 16:36:06 +00:00
2f5ad3f451 Maintainers.txt: Add GitHub IDs
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Andrew Fish <afish@apple.com>
2021-07-22 07:06:48 +00:00
28ef05ce10 BaseTools/Scripts: Allow GitHub ID at end Maintainers.txt lines
* Update GetMaintainer.py to support an optional GitHub ID at the
  end of maintainer and reviewer lines.
* Remove contents after email address from standard output
* Fix minor issue in --lookup to convert file path separators
  from '\' to '/' to be compatible with regular expression
  file matching.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-07-22 07:06:48 +00:00
8781b143de BaseTools/Scripts: Fix GetMaintainer.py line endings
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-07-22 07:06:48 +00:00
391cffcb61 MdeModulePkg PiSmmCore: Change MemoryAttributes message to DEBUG_VERBOSE
1. Reduce the debug message during boot.
2. Update SmmCore debug level of MemoryAttributesTable align to DxeCore.

Signed-off-by: Yang Gang <yanggang@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-22 06:24:42 +00:00
097aeeb119 MdePkg/BaseLib: Add MemoryFence implementation for RiscV64
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-21 12:34:13 +00:00
c32c5911c4 BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459

This patch adds support for R_RISCV_PCREL_LO12_S relocation type.
The logic is same as existing R_RISCV_PCREL_LO12_I relocation
except the difference between load vs store instruction formats.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Abner Chang <abner.chang@hpe.com>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-21 02:12:29 +00:00
83b43c4cb1 MdeModulePkg PCD: Print which PCD was unable to be found
When reaching the assert, it can't be debugged because the PCD is
unknown. Therefore the PCD's GUID and token number should be printed.

Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-07-21 01:21:32 +00:00
885efcd3f9 MdePkg/Include: Smbios Specification 3.4.0 changes
The following changes were addressed,
1. Smbios specs 3.4.0 table-51 bit5&6, these fields moved
   from specific MemoryArrayLocationCXLFlexbus10AddonCard
   to generic MemoryArrayLocationCXLAddonCard
   to address both CXL1.0 and 2.0 CXL revisions.
2. Smbios specs 3.4.0 table-79, The memory technology name changed
   from MemoryTechnologyIntelPersistentMemory
   to MemoryTechnologyIntelOptanePersistentMemory.

Signed-off-by: Thotala Gopi <gopi.thotala@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-20 01:50:58 +00:00
fddb8d24ec ArmPlatformPkg/Scripts: Infer dll load address from console output
cmd_load_symbols.py can only load symbols from FV. Add the possibility to
use UEFI console output to calculate dll load address and send
add-symbol-file commands directly to ArmDS debugger

dll load address can't be used directly from UEFI output, see comment in
DebugPeCoffExtraActionLib: "This may not work correctly if you generate
PE/COFF directly as then the Offset would not be required".

1) Use objdump -S module.dll | grep <_ModuleEntryPoint> to get offset
in dll (offset)
2) Use Entrypoint=<address> from UEFI console output (entrypoint)
3) dll load address is (entrypoint)-(offset)

Signed-off-by: Artem Kopotev <artem.kopotev@arm.com>
Tested-by: Pierre Gondois <Pierre.Gondois@arm.com>
2021-07-19 07:38:14 +00:00
4bac086e8e UefiPayloadPkg: Add FV Guid for DXEFV and PLDFV
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
2021-07-16 01:51:13 +00:00
cac83b6f3b IntelFsp2Pkg: Add search function for Config Editor
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3482

This patch adds a search function in the Config Editor GUI at
the top right corner. Once users key in the words to search,
it will look for the option containing the string in the
same page and display it. It also includes a README for this
function.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-07-15 14:21:14 +00:00
be282b1493 UefiPayloadPkg: Add PCD_DYNAMIC_AS_DYNAMICEX and set to True
PCD_DYNAMIC_AS_DYNAMICEX is recently added to Edk2, and it can treat
Dynamic PCD to Dynamic Ex PCD, which is Uefi Payload needs.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-07-14 04:37:08 +00:00
91f5d3b410 IntelFsp2Pkg: BaseCacheLib EfiProgramMtrr MtrrNumber Should be UINT32
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3485

CacheLib EfiProgramMtrr Function takes MTRR number as a input parameter,
in the function the parameter is defined as UINTN were as the caller
calling MTTR number in UINT32.

Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-07-14 03:54:44 +00:00
d0b6596b8e MdeModulePkg/RamDiskDxe: Init list head before registering RamDisk protocol
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3483

This patch initializes the linked list RegisteredRamDisks in
RamDiskDxeEntryPoint before the registration of gEfiRamDiskProtocolGuid
with InstallMultipleProtocolInterfaces, allowing ramdisks to be created
via a callback installed with RegisterProtocolNotify as soon as the
protocol is registered.

Without this, calling RamDisk->Register() in the callback causes a crash:

ASSERT [RamDiskDxe] MdePkg/Library/BaseLib/LinkedList.c(75): List->ForwardLink != ((void *) 0)

Signed-off-by: Trammell Hudson <hudson@trmm.net>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-07-14 03:07:48 +00:00
9bf4aee734 UefiPayloadPkg: Assign the length of UniversalPayload ExtraData
V1: Assign the length and revision of UniversalPayload ExtraData
V2: Force int to UINT16
V3: Create a local variable to hold the size of ExtraData

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: DunTan <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-07-13 08:18:35 +00:00
7d748705b1 MdeModulePkg: Change the PldHeader to Header in ExtraData.h
Change the PldHeader to Header in UNIVERSAL_PAYLOAD_EXTRA_DATA
The meaning of Pld is too general

Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Acked-by: Hao A Wu <hao.a.wu@intel.com>

Signed-off-by: DunTan <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-07-13 08:18:35 +00:00
fda5226aa3 UefiPayloadPkg: Dump hob information from boot loader
V1:
Universal Payload will consume Hobs from boot loader.
Dump all hobs in the Universal Payload entry.
V2:
Add function comments

V3:
minor change, for example Hobsize -> HobLength, SMBiosTable -> SmBiosTable

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Thiyagu Kesavan Balakrishnan <thiyagux.kesavan.balakrishnan@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-07-13 07:35:18 +00:00
fb5b6220a9 .pytool/EccCheck: Set PACKAGES_PATH env var in Ecc
When running Ecc on other repositories (e.g.: edk2-platforms with
edk2 as a submodule), edk2 modules are referenced.
E.g.: MdePkg/..
The PACKAGES_PATH env var can be used to reference other directories
containing packages. Set it so that Ecc can find these packages.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-12 14:53:55 +00:00
50672d2692 .pytool/EccCheck: Check ecc_csv exists
'workspace_path' being an absolute path leads to 'ecc_csv' being
an absolute path. Then it won't be found among 'file' as they
are relative paths.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-12 14:53:55 +00:00
a050c599df .pytool/EccCheck: Rename edk2_path as workspace_path
The edk2 path and the workspace path are identical when running
Ecc on edk2. When running Ecc on another repository
(e.g.: edk2-platforms with edk2 as a submodule of edk2-platforms),
these directories are different. Indeed, in the latter configuration,
Ecc must run git commands on the tested repository, i.e. the workspace
directory, edk2-platforms.

Thus, rename edk2_path as workspace_path.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-12 14:53:55 +00:00
22fe311bd2 .pytool/EccCheck: Locate BaseTools dir with EDK_TOOLS_PATH
The BaseTools directory is currently being located as a
sub-directory of the WORKSPACE env var. This might not be
true in other environments. Cf EDKII Build Specification,
s4.1.3 "Build Process Restrictions":
  There is no restriction on the location of the EDK_TOOLS_PATH,
  it may be located within a directory identified as the
  WORKSPACE directory, or in any other location that is
  accessible on the development workstation.

Locate the BaseTools directory using EDK_TOOLS_PATH instead.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-12 14:53:55 +00:00
40a9066439 BaseTools: Enable the flag to treat dynamic pcd as dynamicEx
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1688

In order to support binary build, build tool add a
flag to convert type of Dynamic Pcd to DynamicEx Pcd

User can append -D PCD_DYNAMIC_AS_DYNAMICEX to build command
to enable this function.
Also, user can add "PCD_DYNAMIC_AS_DYNAMICEX = TRUE/FALSE" to the
defines section of Dsc file to enable this function.
PCD_DYNAMIC_AS_DYNAMICEX is a new reserved key word for this function.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2021-07-12 07:40:07 +00:00
3de3c24755 BaseTools: Remove non-ascii character of StructurePcd comment
Currently, the ConvertFceToStructurePcd.py tool generate
StructurePcd dsc file with comments from UNI file including
non-ascii character. Following DSC spec, there should not have
non-ascii character in DSC file. This patch removes the non-ascii
character when adding the comment and changes the circle R to (R).

Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-07-12 02:18:45 +00:00
ad1009ec62 MdePkg/Include: Add STATIC_ASSERT for L'' and L"" strings
Add STATIC_ASSERT() macros to verify that the compiler is
configured correctly for the use of L'' and L"" strings.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
2021-07-09 23:43:45 +00:00
5ef08a49e3 .azurepipelines: Remove FINISHED and FAILED states
Remove 10 second delay workarounds for issues observed
when Mergify was originally enabled.  These issues are
no longer present when GitHub branch protections are
used for status checks.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-09 15:57:46 -07:00
b491eace37 .mergify: Simplify Mergify rules using GitHub status checks
* Enable Mergify queue feature to support auto rebase when
  'push' label is set and gauarntee that all EDK II CI checks
  are run before merging in changes with linear history.
* Use status checks configured in GitHub branch protections
* Allow non EDK II Maintainers to create a PR
  Requires an EDK II Maintainer to accept the change and
  request merge by adding 'push' label.  Only EDK II Maintainers
  have ability to set/clear labels.
* Do not automatically close PRs for personal builds.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-09 15:57:46 -07:00
84af6ea320 BaseTools/Scripts: Ignore Mergify merge commits in PatchCheck.py
Mergify adds merge commits to a PR when processing PRs using
the queue feature with auto rebase.  Update PatchCheck.py
to ignore commit message issues with these merge commits.
These merge commits are not added to the base branch when
the PR is merged by Mergify.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-07-09 15:57:46 -07:00
cc89d245f9 Maintainers.txt: remove Laszlo Ersek's entries
I'm relinquishing all my roles listed in "Maintainers.txt", for personal
reasons.

My email address <lersek@redhat.com> remains functional.

To my understanding, my employer is working to assign others engineers to
the edk2 project (at their discretion).

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daud? <philmd@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Andrew Fish <afish@apple.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-09 16:57:11 +00:00
f47c4676dd Pytool: SpellCheck: Defer path expansion in cspell parameters
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3454

On Linux the shell expands the wildcard paths and causes multiple files
to be missed. This change adds additional quotes to defer expansion in
order to bring parity in cspell result.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-09 08:29:54 +00:00
b560e9d9b6 IntelFsp2Pkg: PatchFv parseInfFile function modification
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required

verification : Working Fine

Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-07-08 06:49:09 +00:00
0e3b6bd0ee ArmVirtPkg: support Cloud Hypervisor in edk2
Cloud Hypervisor is KVM based VMM and is implemented in rust. Just like
other VMMs it need UEFI support to let ACPI work. That's why
Cloud Hypervisor is introduced here.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-07-07 16:41:37 +00:00
c28fc8ab3b ArmVirtPkg: Install Acpi tables for Cloud Hypervisor
There is no device like Fw-cfg in Qemu in Cloud Hypervisor, so a specific
Acpi handler is introduced here.

The handler implemented here is in a very simple way:
1. acquire the RSDP from the PCD variable in the top ".dsc";
2. get the XSDT address from RSDP structure;
3. get the ACPI tables following the XSDT structure and install them
one by one;
4. get DSDT address from FADT and install DSDT table.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-07-07 16:41:37 +00:00
31fcee6d99 ArmVirtPkg: Add PlatformHasAcpiDtDxe for Cloud Hypervisor
The ArmVirtPkg\PlatformHasAcpiDtDxe implementation is not common
and is specific for Qemu. So add a Cloud Hypervisor specific
version that decides whether the firmware should expose an ACPI
based or a Device Tree based hardware description to an operating
system.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-07-07 16:41:37 +00:00
4c051c2c65 MdeModulePkg: Update YAML file to fix CI error
Add OnigurumaUefiPort.h and OnigurumaUefiPort.c into ECC exception in
MdeModulePkg.ci.yaml in order to fix CI error.

Signed-off-by: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-07 07:04:47 +00:00
d10e058016 MdeModulePkg/RegularExpressionDxe: Fix memory assert in FreePool()
Memory buffer that is allocated by malloc() and realloc() will be
shifted by 8 bytes because Oniguruma keeps its memory signature. This 8
bytes shift is not handled while calling free() to release memory. Add
free() function to check Oniguruma signature before release memory
because memory buffer is not touched when using calloc().

Signed-off-by: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-07-07 07:04:47 +00:00
0a6b303dce UefiCpuPkg/ExceptionLib: Conditionally clear shadow stack token busy bit
When enter SMM exception, there will be a stack switch only if the IST
field of the interrupt gate is set. When CET shadow stack feature is
enabled, if there is a stack switch between SMM exception and SMM, the
shadow stack token busy bit needs to be cleared when return from SMM
exception to SMM. In UEFI BIOS, only page fault exception does the stack
swith when SMM shack guard feature is enabled. The condition of clear
shadow stack token busy bit should be SMM stack guard enabled, CET shadows
stack feature enabled and page fault exception.
The shadow stack token should be initialized by UINT64.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3462

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Qihua Zhuang <qihua.zhuang@intel.com>
Cc: Daquan Dong <daquan.dong@intel.com>
Cc: Justin Tong <justin.tong@intel.com>
Cc: Tom Xu <tom.xu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2021-07-06 08:18:21 +00:00
b3db0cb1f8 MdeModulePkg/PartitionDxe: Ignore PMBR BootIndicator per UEFI spec
Per UEFI Spec 2.8 (UEFI_Spec_2_8_final.pdf, page 114)
5.2.3 Protective MBR
Table 20. Protective MBR Partition Record protecting the entire disk

The description for BootIndicator states the following:

> Set to 0x00 to indicate a non-bootable partition. If set to any
> value other than 0x00 the behavior of this flag on non-UEFI
> systems is undefined. Must be ignored by UEFI implementations.

Unfortunately, we have been incorrectly assuming that the
BootIndicator value must be 0x00, which leads to problems
when the 'pmbr_boot' flag is set on a disk containing a GPT
(such as with GNU parted). When the flag is set, the value
changes to 0x01, causing this check to fail and the system
is rendered unbootable despite it being valid from the
perspective of the UEFI spec.

To resolve this, we drop the check for the BootIndicator
so that we stop caring about the value set there, which
restores the capability to boot such disks.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3474

Cc: Chris Murphy <chrismurphy@fedoraproject.org>
Cc: David Duncan <davdunc@amazon.com>
Cc: Lazlo Ersek <lersek@redhat.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>

Signed-off-by: Neal Gompa <ngompa@fedoraproject.org>
Message-Id: <20210705093603.575707-1-ngompa@fedoraproject.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-07-06 07:33:42 +00:00
44ced03798 OvmfPkg/Bhyve: use static PCI32Base address
It's neccessary to allocate a Graphics Stolen Memory area to enable
GPU-Passthrough for integrated Intel GPUs. Therefore, use a new
memory layout with a static Pci32Baseaddress.

Old layout:
	[...        , lowmemlimit] RAM
	[lowmemlimit, 0xE000 0000] PCI Space
New layout:
	[...        , lowmemlimit] RAM
	[lowmemlimit, gsmbase    ] Memory hole (may be absent)
	[gsmbase    , 0xC000 0000] GSM (may be absent)
	[0xC000 0000, 0xE000 0000] PCI Space

Reviewed-by: Peter Grehan <grehan@freebsd.org>
Acked-by: Rebecca Cran <rebecca@bsdio.com>
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Message-Id: <20210705110842.14088-2-c.koehne@beckhoff.com>
2021-07-05 12:12:00 +00:00
1e0c441c92 OvmfPkg/Bhyve: add USB support
An USB driver is required to use a keyboard or mouse while installing
an OS or while in a bootloader menu like grub when using GPU + USB
Passthrough.

Reviewed-by: Peter Grehan <grehan@freebsd.org>
Acked-by: Rebecca Cran <rebecca@bsdio.com>
Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
Message-Id: <20210705110842.14088-1-c.koehne@beckhoff.com>
2021-07-05 12:12:00 +00:00
fea7901dba UefiPayloadPkg: Fix the build failure
For non-universal payload, HandoffHobTable is used without initialization.
This patch fixed this failure.

Cc: Benjamin You <benjamin.you@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-07-01 21:27:07 +00:00
8697dc60cc Maintainers.txt: Update Maintainers and reviewers for UefiPayloadPkg
Add Ray Ni as UefiPayloadPkg Maintainer.
Update Maurice Ma and Benjamin You as reviewers to continue support
UefiPayloadPkg patch review.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Guo Dong <guo.dong@intel.com>
2021-07-01 17:24:39 +00:00
bb33c27fbe NetworkPkg: introduce the NETWORK_ISCSI_MD5_ENABLE feature test macro
Introduce the NETWORK_ISCSI_MD5_ENABLE feature test macro for NetworkPkg.
When explicitly set to FALSE, remove MD5 from IScsiDxe's CHAP algorithm
list.

Set NETWORK_ISCSI_MD5_ENABLE to TRUE by default, for compatibility
reasons. Not just to minimize the disruption for platforms that currently
include IScsiDxe, but also because RFC 7143 mandates MD5 for CHAP, and
some vendors' iSCSI targets support MD5 only.

With MD5 enabled, IScsiDxe will suggest SHA256, and then fall back to MD5
if the target requests it. With MD5 disabled, IScsiDxe will suggest
SHA256, and break off the connection (and session) if the target doesn't
support SHA256.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210629163337.14120-7-lersek@redhat.com>
2021-06-30 19:20:41 +00:00
47fea2abcb NetworkPkg/IScsiDxe: support SHA256 in CHAP
Insert a SHA256 CHAP_HASH structure at the start of "mChapHash".

Update ISCSI_CHAP_MAX_DIGEST_SIZE to SHA256_DIGEST_SIZE (32).

This enables the initiator and the target to negotiate SHA256 for CHAP, in
preference to MD5.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210629163337.14120-6-lersek@redhat.com>
2021-06-30 19:20:41 +00:00
903ce1d8f8 NetworkPkg/IScsiDxe: support multiple hash algorithms for CHAP
Introduce the "mChapHash" table, containing the hash algorithms supported
for CHAP. Hash algos listed at the beginning of the table are preferred by
the initiator.

In ISCSI_CHAP_STEP_ONE, send such a CHAP_A value that is the
comma-separated, ordered list of algorithm identifiers from "mChapHash".
Pre-format this value string at driver startup, in the new function
IScsiCHAPInitHashList().

(In IScsiCHAPInitHashList(), also enforce that every hash algo's digest
size fit into ISCSI_CHAP_MAX_DIGEST_SIZE, as the latter controls the
digest, outgoing challenge, and hex *allocations*.)

In ISCSI_CHAP_STEP_TWO, allow the target to select one of the offered hash
algorithms, and remember the selection for the later steps. For
ISCSI_CHAP_STEP_THREE, hash the challenge from the target with the
selected hash algo.

In ISCSI_CHAP_STEP_THREE, send the correctly sized digest to the target.
If the initiator wants mutual authentication, then generate a challenge
with as many bytes as the target's digest will have, in
ISCSI_CHAP_STEP_FOUR.

In ISCSI_CHAP_STEP_FOUR (i.e., when mutual authentication is required by
the initiator), verify the target's response (digest) with the selected
algorithm.

Clear the selected hash algorithm before every login (remember that in
IScsiDxe, every login is a leading login).

There is no peer-observable change from this patch, as it only reworks the
current MD5 support into the new internal representation.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210629163337.14120-5-lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
2021-06-30 19:20:41 +00:00
7b6c2b2a26 NetworkPkg/IScsiDxe: distinguish "maximum" and "selected" CHAP digest sizes
IScsiDxe uses the ISCSI_CHAP_RSP_LEN macro for expressing the size of the
digest (16) that it solely supports at this point (MD5).
ISCSI_CHAP_RSP_LEN is used for both (a) *allocating* digest-related
buffers (binary buffers and hex encodings alike), and (b) *processing*
binary digest buffers (comparing them, filling them, reading them).

In preparation for adding other hash algorithms, split purpose (a) from
purpose (b). For purpose (a) -- buffer allocation --, introduce
ISCSI_CHAP_MAX_DIGEST_SIZE. For purpose (b) -- processing --, rely on
MD5_DIGEST_SIZE from <BaseCryptLib.h>.

Distinguishing these purposes is justified because purpose (b) --
processing -- must depend on the hashing algorithm negotiated between
initiator and target, while for purpose (a) -- allocation --, using the
maximum supported digest size is suitable. For now, because only MD5 is
supported, introduce ISCSI_CHAP_MAX_DIGEST_SIZE *as* MD5_DIGEST_SIZE.

Note that the argument for using the digest size as the size of the
outgoing challenge (in case mutual authentication is desired by the
initiator) remains in place. Because of this, the above two purposes are
distinguished for the "ISCSI_CHAP_AUTH_DATA.OutChallenge" field as well.

This patch is functionally a no-op, just yet.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210629163337.14120-4-lersek@redhat.com>
2021-06-30 19:20:41 +00:00
7eba9f698e NetworkPkg/IScsiDxe: add horizontal whitespace to IScsiCHAP files
In the next patches, we'll need more room for various macro and parameter
names. For maintaining the current visual alignments, insert some
horizontal whitespace in preparation. "git show -b" produces no output for
this patch; the patch introduces no functional changes.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210629163337.14120-3-lersek@redhat.com>
2021-06-30 19:20:41 +00:00
49eeda113a NetworkPkg/IScsiDxe: re-set session-level authentication state before login
RFC 7143 explains that a single iSCSI session may use multiple TCP
connections. The first connection established is called the leading
connection. The login performed on the leading connection is called the
leading login. Before the session is considered full-featured, the leading
login must succeed. Further (non-leading) connections can be associated
with the session later.

(It's unclear to me from RFC 7143 whether the non-leading connections
require individual (non-leading) logins as well, but that particular
question is irrelevant from the perspective of this patch; see below.)

The data model in IScsiDxe exhibits some confusion, regarding connection /
session association:

- On one hand, the "ISCSI_SESSION.Conns" field is a *set* (it has type
  LIST_ENTRY), and accordingly, connections can be added to, and removed
  from, a session, with the IScsiAttatchConnection() and
  IScsiDetatchConnection() functions.

- On the other hand, ISCSI_MAX_CONNS_PER_SESSION has value 1, therefore no
  session will ever use more than 1 connection at a time (refer to
  instances of "Session->MaxConnections" in
  "NetworkPkg/IScsiDxe/IScsiProto.c").

This one-to-many confusion between ISCSI_SESSION and ISCSI_CONNECTION is
very visible in the CHAP logic, where the progress of the authentication
is maintained *per connection*, in the "ISCSI_CONNECTION.AuthStep" field
(with values such as ISCSI_AUTH_INITIAL, ISCSI_CHAP_STEP_ONE, etc), but
the *data* for the authentication are maintained *per session*, in the
"AuthType" and "AuthData" fields of ISCSI_SESSION. Clearly, this makes no
sense if multiple connections are eligible for logging in.

Knowing that IScsiDxe uses only one connection per session (put
differently: knowing that any connection is a leading connection, and any
login is a leading login), there is no functionality bug. But the data
model is still broken: "AuthType", "AuthData", and "AuthStep" should be
maintained at the *same* level -- be it "session-level" or "(leading)
connection-level".

Fixing this data model bug is more than what I'm signing up for. However,
I do need to add one function, in preparation for multi-hash support:
whenever a new login is attempted (put differently: whenever the leading
login is re-attempted), which always happens with a fresh connection, the
session-level authentication data needs to be rewound to a sane initial
state.

Introduce the IScsiSessionResetAuthData() function. Call it from the
central -- session-level -- IScsiSessionLogin() function, just before the
latter calls the -- connection-level -- IScsiConnLogin() function.

Right now, do nothing in IScsiSessionResetAuthData(); so functionally
speaking, the patch is a no-op.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210629163337.14120-2-lersek@redhat.com>
2021-06-30 19:20:41 +00:00
3cde0d553d UefiPayloadPkg/PayloadLoader: Remove assertion
For R_386_RELATIVE and R_X86_64_RELATIVE, today's logic assumes that
the content pointed by the Rela->r_offset is 0 but it's not always
TRUE. We observed that linker may set the content to Rela->r_addend.

The patch removes the assertion.
There is no functionality impact for this patch.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
2021-06-30 07:12:54 +00:00
939ed3a592 UefiPayloadPkg/PayloadLoader: Fix bug in locating relocation section
Per ELF spec, the DT_REL/DT_RELA tag in dynamic section stores the
virtual address of the relocation section.

But today's code logic treats it as the section offset and finds
the relocation section whose offset equals to DT_REL/DT_RELA.

The logic can work when the section offset equals to the section
virtual address. But when the ELF is generated from the link script
that reserves a sizeof(pe_header) in the file beginning, the section
offset doesn't equal to section virtual address. Such logic can
not find the relocation section.

The patch fixes this bug.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
2021-06-30 07:12:54 +00:00
580b11201e IntelFsp2Pkg: Add Config Editor tool support
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3396

This is a GUI interface that can be used by users who
would like to change configuration settings directly
from the interface without having to modify the source.

This tool depends on Python GUI tool kit Tkinter.
It runs on both Windows and Linux.

The user needs to load the YAML file along with DLT file
for a specific board into the ConfigEditor, change the desired
configuration values. Finally, generate a new configuration delta
file or a config binary blob for the newly changed values to take
effect. These will be the inputs to the merge tool or the stitch
tool so that new config changes can be merged and stitched into
the final configuration blob.

This tool also supports binary update directly and display FSP
information. It is also backward compatible for BSF file format.

Running Configuration Editor:
python ConfigEditor.py

Co-authored-by: Maurice Ma <maurice.ma@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-06-30 03:56:59 +00:00
55dee4947b MdePkg : Add IPMI Macro and Structure Defintions to resolve build errors
Build error reported for missing structures IPMI_SET_BOOT_OPTIONS_RESPONSE,
EFI_IPMI_MSG_GET_BMC_EXEC_RSP, macro EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE
when using edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg

Rename EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE

Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-30 02:14:45 +00:00
b37cfdd280 OvmfPkg/XenPlatformPei: Relocate shared_info page mapping
Unfortunately, Xen isn't ready to deal with mapping at the top of the
physical address space, so we relocate the mapping after the LAPIC
location.

See this thread about the issue with the mapping:
- https://lore.kernel.org/xen-devel/f8c4151a-6dac-d87c-ef46-eb35ada07bd9@suse.com/

The PhysicalAddressIdentityMapping() call isn't going to do anything
anymore since everything under 4GB is already mapped, but there is no
need to remove the call.

Cc: Jan Beulich <JBeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20210628132337.46345-1-anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: replace "CC:" with "Cc:", to pacify PatchCheck.py]
2021-06-29 13:40:43 +00:00
9421f5ab8d OvmfPkg/X86QemuLoadImageLib: State fw_cfg dependency in file header
Make it clear that X86QemuLoadImageLib relies on fw_cfg; prepare the
ground to add a warning about the incompatibility with boot verification
process.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210628105110.379951-6-dovmurik@linux.ibm.com>
2021-06-29 12:33:17 +00:00
cf20302474 OvmfPkg/GenericQemuLoadImageLib: Read cmdline from QemuKernelLoaderFs
Remove the QemuFwCfgLib interface used to read the QEMU cmdline
(-append argument) and the initrd size.  Instead, use the synthetic
filesystem QemuKernelLoaderFs which has three files: "kernel", "initrd",
and "cmdline".

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Message-Id: <20210628105110.379951-5-dovmurik@linux.ibm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2021-06-29 12:33:17 +00:00
24b0e9d128 Revert "OvmfPkg/QemuKernelLoaderFsDxe: don't expose kernel command line"
This reverts commit efc52d67e1.

Manually fixed conflicts in:
  OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c

Note that besides re-exposing the kernel command line as a file in the
synthetic filesystem, we also revert back to AllocatePool instead of
AllocatePages.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210628105110.379951-4-dovmurik@linux.ibm.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2021-06-29 12:33:17 +00:00
932449710c OvmfPkg/X86QemuLoadImageLib: plug cmdline blob leak on success
When QemuLoadKernelImage() ends successfully, the command-line blob is
not freed, even though it is not used elsewhere (its content is already
copied to KernelLoadedImage->LoadOptions).  The memory leak bug was
introduced in commit 7c47d89003 ("OvmfPkg: implement QEMU loader
library for X86 with legacy fallback", 2020-03-05).

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Reported-by: Laszlo Ersek <lersek@redhat.com>
Fixes: 7c47d89003
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Message-Id: <20210628105110.379951-3-dovmurik@linux.ibm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2021-06-29 12:33:17 +00:00
5a2e030f73 OvmfPkg/GenericQemuLoadImageLib: plug cmdline blob leak on success
When QemuLoadKernelImage() ends successfully, the command-line blob is
not freed, even though it is not used elsewhere (its content is already
copied to KernelLoadedImage->LoadOptions).  The memory leak bug was
introduced in commit ddd2be6b00 ("OvmfPkg: provide a generic
implementation of QemuLoadImageLib", 2020-03-05).

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Reported-by: Laszlo Ersek <lersek@redhat.com>
Fixes: ddd2be6b00
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
Message-Id: <20210628105110.379951-2-dovmurik@linux.ibm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2021-06-29 12:33:17 +00:00
d1fc3d7ef3 MdePkg: MmConfiguration: Added definition of MM Configuration PPI
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440

MM Configuration PPI was defined in PI Specification since v1.5. This
change added definition of such PPI and related GUIDs into MdePkg.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-29 05:16:44 +00:00
27b8a52957 MdePkg: MmConfiguration: Move definition of EFI_MM_RESERVED_MMRAM_REGION
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440

The definition of EFI_MM_RESERVED_MMRAM_REGION, according to PI Spec 1.5
is also referenced in EFI_PEI_MM_CONFIGURATION_PPI. Defining this
structure as is will enforce any potential usage of MM Configuration PPI
interface to include <Protocol/MmConfiguration.h>.

This change moves this structure definition to PiMultiPhase.h, which is
already included by Protocol/MmConfiguration.h through PiMmCis.h. It also
paves way for introducing Ppi/MmConfiguration.h with proper dependency.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-29 05:16:44 +00:00
abfff7c45d BaseTools GenFw: Add support for RISCV GOT/PLT relocations
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-06-29 02:47:44 +00:00
17143c4837 BaseTools: Reset ERRORLEVEL in toolsetup.bat after edk2basetools check
When using the in-source BaseTools, edksetup.bat will exit with an
ERRORLEVEL of 1 because the line in toolsetup.bat
"%PYTHON_COMMAND% -c "import edk2basetools" >NUL 2>NUL"
fails.

Ensure ERRORLEVEL is set to 0 when edksetup.bat or toolsetup.bat is
successfully run.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-25 04:15:40 +00:00
f0a3f6d9c3 BaseTools: Fix spelling of "overwrite" and "overwriting" in toolset.bat
The words "overwrite" and "overwriting" are one word and shouldn't have
hyphens.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-25 03:12:26 +00:00
333a866106 BaseTools: Remove check for Split.exe in toolset.bat
Split is now a Python tool, so BaseTools\Bin\Win32\Split.exe no longer
exists. Remove the check for it from toolsetup.bat to prevent the
erroneous claim that the binary C tools are missing.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-25 02:27:47 +00:00
19a541d70e UefiPayloadPkg: consume the BootManagerMenuFile HOB
Consume the BootManagerMenuFile HOB in PlatformBootManagerLib
This Lib is in UefiPayloadPkg

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: DunTan <dun.tan@intel.com>
2021-06-24 09:16:22 +00:00
8efd912baf UefiPayloadPkg: Add new structure for BootManagerMenuFile HOB
Add new structure for BootManagerMenuFile HOB in UefiPayloadPkg

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: DunTan <dun.tan@intel.com>
2021-06-24 09:16:22 +00:00
caa139fe17 UefiPayloadPkg: Add PcdResetOnMemoryTypeInformationChange in UefiPayloadPkg
This PCD will be consumed by Universal Payload

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
3eb72b308a UefiPayloadPkg: Add PcdInstallAcpiSdtProtocol feature in UefiPayloadPkg
To install ACPI SDT protocol, define PcdInstallAcpiSdtProtocol as TRUE.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
2db0ed93ff UefiPayloadPkg: Add macro to enable and disable some drivers
Add macro EMU_VARIABLE_ENABLE and DISABLE_RESET_SYSTEM to include
or exclude some drivers from Payload

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
86e6948cfb UefiPayloadPkg: Remove assert when reserve MMIO/IO resource for devices
Some boot loader may already reserve MMIO/IO resource for IOAPIC and HPET,
so remove the assert when reserve MMIO/IO resource for IOAPIC and HPET

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
6b69f73b59 UefiPayloadPkg: Include UniversalPayLoad modules in UefiPayloadPkg.dsc
Add a new macro "UNIVERSAL_PAYLOAD" to build Universal Payload.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
27cb64fffc UefiPayloadPkg: Fix up UPL Pcd database
Edk2 bootloader will pass the pei pcd database, and UPL also contain a
PCD database.
Dxe PCD driver has the assumption that the two PCD database can be
catenated and the local token number should be successive。
This patch will manually fix up the UPL PCD database to meet that
assumption.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
b208d37c73 UefiPayloadPkg: Get and enter DxeCore for Universal Payload
From gUniversalPayloadExtraDataGuid Guid Hob, get the Dxe FV information,
and get the Dxe Core from the FV.
Also, make sure if there are muliple FV hob, the FV hob pointing to this FV
will be the first in the hob list.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
0ff6de9358 UefiPayloadPkg: Create separate Payload Entry for UniversalPayload
This patch create the UniversalPayload Entry based on the UefiPayload
Entry. It implements the logic to find a proper memory range to create the
new Hob and migrate the Hobs from Bootloader.
To make the change history clear, the logic to get the DxeCore will be in
the next patch.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
d63595c3c9 UefiPayloadPkg: Update the function definition of HobConstructor
Update the function defination of HobConstructor to align the Phit Hob
structure.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
a75c029f60 UefiPayloadPkg: Add a separate PlatformHookLib for Universal Payload
Add a new separate PlatformHookLib for Universal Payload to consume Guid
Hob gUniversalPayloadSerialPortInfoGuid to get serial port information

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
ea0bd5f6a7 MdeModulePkg: Add new structure for the Universal Payload Serial Port Info
Add Universal Payload Serial Port Info definition header file according to
Universal Payload's documentation as below:
https://universalpayload.github.io/documentation/

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
82f727c4af UefiPayloadPkg: Add HobLib for UniversalPayload
For payload entry, use PayloadEntryHobLib as HobLib and payload entry
should initialize hob base.
For DxeCore, use new added DxeHobLib as HobLib, and DxeCore will
initialize hob base.
For Dxe Driver, use new added DxeHobLib as HobLib, and use DxeHobListLib
to initialize hob base.

Adding a new library DxeHobLib + DxeHobListLib instead of using the
DxeHobLib.inf in MdePkg is because the constructor needed be separated
from DxeHobLib.
If not, when building UefiPayloadPkg, the dependency chain is as below:
DebugLib -> SerialPortLib -> PlatformHookLib -> HobLib -> DebugLib
Each library has a constructor, and this becomes a constructor circle.
To break the circle, separate the constructor from the HobLib as a new
DxeHobListLib, which won't depend on DebugLib.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-24 09:16:22 +00:00
12e34cd2f7 OvmfPkg/Bhyve: clean up TPM_ENABLE remnants
TPM support hasn't been tested and any lines in the .dsc and .fdf files
that appear to show support are bogus. Remove them.

This fixes https://bugzilla.tianocore.org/show_bug.cgi?id=3354 .

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Message-Id: <20210612204340.52290-1-rebecca@bsdio.com>
Reviewed-by: Peter Grehan <grehan@freebsd.org>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-06-24 07:59:36 +00:00
eba32695ee CryptoPkg/BaseCryptLib: Enabled CryptSha512 for Smm/Runtime drivers
Intel Platform utility Syscfg/sysfwupdt will trigger SMI
to enter BIOS interface. then BIOS invoke EncodePassword
in SMM mode to check password.
it's need sha384(in CryptSha512.c) in SMM mode.

the origin SmmCryptLib.lib size is 1389KB,
after changed, the size is 1391KB.

the origin RuntimeCryptLib.lib size is 911KB,
after changed,the size is 913KB.

in SmmCryptLib.inf and RuntimeCryptLib.inf,
change CryptSha512NULL.c to CryptSha512.c.

https://bugzilla.tianocore.org/show_bug.cgi?id=3423

Signed-off-by: xueshengfeng <xueshengfeng@byosoft.com.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-06-24 02:46:14 +00:00
18b2272e4d Azurepipeline: SpellCheck: Enforce Node dependency to use version 14.x
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

Per update from Cspell tool, the minimal requirement of Cspell 5.x
regarding Node is 12 and above. This has caused multple Cspell failures
during CI build validation:
"Failed to process "**.c" TypeError: text.matchAll(...) is not a function
or its return value is not iterable"

This change updates the lowest required node version to 14.x to support
Cspell functionalities.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
2021-06-24 01:53:23 +00:00
20ca528828 CryptoPkg: BaseCryptLib: Update Salt length requirement for RSA-PSS scheme.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3455

Enforce salt length to be equal to digest length for RSA-PSS
encoding scheme.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>

Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-06-23 15:19:44 +00:00
7471751a4d UefiPayloadPkg/UefiPayloadEntry: Remove 4GB memory WA
Previous it would hang in CpuDxe if DXE drivers are dispatched above 4GB.
Now remove the work around since the fixed in CpuDxe are merged.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
2021-06-22 19:03:48 +00:00
1e5e58d39b UefiPayloadPkg/UefiPayloadEntry: Improve bootloader memrange parsing
Currently several DXE crash due to invalid memory resource settings.
The PciHostBridgeDxe which expects the MMCONF and PCI Aperature
to be EfiMemoryMappedIO, but currently those regions are (partly)
mapped as EfiReservedMemoryType.

coreboot and slimbootloader provide an e820 compatible memory map,
which doesn't work well with EDK2 as the e820 spec is missing MMIO regions.
In e820 'reserved' could either mean "DRAM used by boot firmware" or "MMIO
in use and not detectable by OS".

Guess Top of lower usable DRAM (TOLUD) by walking the bootloader provided
memory ranges. Memory types of RAM, ACPI and ACPI NVS below 4 GiB are used
to increment TOLUD and reserved memory ranges touching TOLUD at the base
are also assumed to be reserved DRAM, which increment TOLUD.

Then mark everything reserved below TOLUD as EfiReservedMemoryType and
everything reserved above TOLUD as EfiMemoryMappedIO.

This fixes assertions seen in PciHostBridgeDxe.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
2021-06-22 18:04:36 +00:00
4dda0f7ab4 ArmVirtPkg: Enable PCIe support for Kvmtool
PCIe support has been added to the Kvmtool virtual machine
manager. Therefore, enable PCIe support for Kvmtool firmware.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
2021-06-22 17:04:45 +00:00
5959879e92 ArmVirtPkg: Add PCIe host bridge utility lib for ArmVirtPkg
PCIe support has been added to Kvmtool Virtual Machine Manager.
The PCI host bridge utility lib is used to retrieve information
about the Root Bridges in a platform.
Therefore, add an instance of PciHostBridgeUtilityLib as this is
required to enable PCIe support for Kvmtool firmware.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
2021-06-22 17:04:45 +00:00
d9a7612f8d MdeModulePkg/BdsDxe: Update BdsEntry to use Variable Policy
Changed BdsEntry.c to use Variable Policy instead of Variable Lock
as Variable Lock will be Deprecated eventually

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kenneth Lautner <kenlautner3@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-22 08:21:09 +00:00
6cfeeb71c4 UefiCpuPkg/CpuCommonFeaturesLib: Correct the CPU location check
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424

Processor location information check needs to updated
When Core 0 is disabled.

In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in comments
to match the correct MSR name.

Signed-off-by: Daoxiang Li <daoxiang.li@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-06-21 03:12:17 +00:00
a63914d3f6 ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h
Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-18 15:25:57 +00:00
1162ae8297 Maintainers.txt: Add reviewers for ACPI and SMBIOS modules
Per discussion with MdeModulePkg package maintainer, add
Zhiguang as one of the reviewers for ACPI and SMBIOS modules.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-06-17 03:54:08 +00:00
2847c72fda Maintainers.txt: Add Reviewers for Universal Payload definitions
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-06-17 03:54:08 +00:00
cdf7544703 MdeModulePkg PciBusDxe: Increase the width of data read during oprom shadow
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2989

Long times spent on shadowing oprom from graphics card to system memory.
We are currently using 8 bit read cycles. This needs to be wider,
at least 32bit reads to reduce the time for oprom shadow.

Signed-off-by: Sumana Venur <sumana.venur@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-06-17 03:01:55 +00:00
04ddd1271e ArmPkg: SpellCheck: Update valid acronyms in ExtendedWords
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

Spellcheck was not covering all specified files due to CSpell v5 and
Node v10 incompatibility of current CI pipeline configuration.

This change updates ExtendedWords for ArmPkg with valid acronyms to avoid
potential spell errors.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-06-16 14:40:00 +00:00
610385fa3b ArmPlatformPkg: SpellCheck: Switch spellcheck CI to AuditOnly
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

Spellcheck was not covering all specified files due to CSpell v5 and
Node v10 incompatibility of current CI pipeline configuration.

This change switches the spellcheck for ArmPlatformPkg to AuditOnly to
avoid potentially numerous spell errors. The correction action is to be
revisited by package maintainers once the tool incompatibility is
resolved.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-06-16 14:40:00 +00:00
9cf9de668f StandaloneMmPkg: Core: Spelling error in comment
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

This change fixed a misspelling that was not caught by spell check.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-06-16 14:40:00 +00:00
1b380aa603 BaseTools GenFw: Keep read only alloc section as text when convert ELF
This is the fix of the regression issue at c6b872c6.
Based on ELF spec, readonly alloc section is .rodata section. It is used.
This fix is to add back original check logic for ELF section. Now,
the readonly alloc section and execute alloc section are regarded as .text.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-06-16 14:11:57 +00:00
ab2b389e7a PeiCore: Remove assertion when failing to load PE image
EFI_PEI_LOAD_FILE_PPI is invoked by DxeIpl for loading DxeCore.
It's possible that the instance produced by PeiCore fails to load but
other instances of EFI_PEI_LOAD_FILE_PPI can load.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-16 07:51:00 +00:00
fe471d4a57 UefiPayloadPkg: Add PayloadLoaderPeim which can load ELF payload
Per universal payload spec, the payload is in ELF format.
The patch adds a payload loader that supports to load ELF image.

The location of extra data sections whose names start with "upld."
is stored in UNIVERSAL_PAYLOAD_EXTRA_DATA HOB.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
2021-06-16 07:51:00 +00:00
c511426abe MdeModulePkg/UniversalPayload: Add definition for extra info in payload
The payload is in ELF format per the universal payload spec.
UNIVERSAL_PAYLOAD_INFO_HEADER is stored in the ELF payload as a separate
section named ".upld_info".

Extra data needed by payload is stored in sections whose name starts
with ".upld.".

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-06-16 07:51:00 +00:00
fa24b6ed26 UefiPayloadPkg: Use DynamicEx instead of Dynamic to pass PCD across binary
When passing PCD database from Edk2 boot loader to Universal Payload, the
local token number in boot loader PCD database can be different with that
in Payload PCD database.
Dynamic PCD directly use local token number, while DynamicEx will search
token number by Guid and ExTokenNumber, which are unique pair and can make
sure finding the correct token number in boot loader's PCD database.
Therefore, using DynamicEx instead of Dynamic.
Also, explicitly define some PCDs as DynamicEx, or their default type will
be Dynamic

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
8c0d678063 UefiPayloadPkg: Create gUniversalPayloadAcpiTableGuid Hob
From SysTableInfo Hob, get ACPI table address, and create
gUniversalPayloadAcpiTableGuid Hob to store it.
Remove directly adding ACPI table to ConfigurationTable.
Dxe ACPI driver will parse it and install ACPI table from Guid Hob.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
761329ee27 MdeModulePkg/ACPI: Install ACPI table from HOB.
If HOB contains APCI table information, entry point of AcpiTableDxe.inf
should parse the APCI table from HOB, and install these tables.
We assume the whole ACPI table
(starting with EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER)
is contained by a single gEfiAcpiTableGuid HOB.

If error happens when installing ACPI table, stop installing and removing
all the tables that are already added.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
75293330ea MdeModulePkg: Add new structure for the Universal Payload ACPI Table Hob
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
302a8f353c UefiPayloadPkg: Create gUniversalPayloadSmbiosTableGuid Hob
From SysTableInfo Hob, get Smbios table address, and create
gUniversalPayloadSmbiosTableGuid Hob to store it. Remove directly adding
smbios table to ConfigurationTable.
Dxe module SmbiosDxe will parse it and install smbios table from it.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
70e8c9c3bc MdeModulePkg/Universal/SmbiosDxe: Scan for existing tables
The default EfiSmbiosProtocol operates on an empty SMBIOS table.
The SMBIOS tables are provided by the bootloader on UefiPayloadPkg.
Scan for existing tables in SmbiosDxe and load them if they seem valid.
This fixes the settings menu not showing any hardware information, instead
only "0 MB RAM" was displayed.
Tests showed that the OS can still see the SMBIOS tables.

SmbiosDxe will get the SMBIOS from a guid Hob.
Also will keep the SmbiosHandle if it is available.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
9d53e01efe MdeModulePkg: Add new structure for the Universal Payload SMBios Table Hob
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
99de2e7e03 UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob
UefiPayload parse gUniversalPayloadPciRootBridgeInfoGuid Guid Hob to
retrieve PCI root bridges information.
gUniversalPayloadPciRootBridgeInfoGuid Guid Hob should be created by
Bootloader.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
b597b6e24c MdeModulePkg: Add new structure for the PCI Root Bridge Info Hob
Also add ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid open
CI issue, because UID and HID are terms which are already used in current
source code.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
d8c18ba3f4 MdeModulePkg: Add Universal Payload general definition header file
Add Universal Payload general definition header file according to
Universal Payload's documentation as below:
https://universalpayload.github.io/documentation/

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
d58016b768 UefiPayloadPkg: Get platform specific logic via protocol for BDS
Currently, BDS driver will link a PlatformBootManagerLib, which contains
platform specific logic. This patch get the platform specific logic from
a protocol, so that platform logic for Boot manager can be in another
binary.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-16 05:20:19 +00:00
11b1c1d4b9 SecurityPkg: TcgStorageOpalLib: Initialize SupportedAttributes parameter.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3408

The value of SupportedAttributes in OpalGetSupportedAttributesInfo ()
is left undetermined, if the caller doesn't initialize it.
Initialize it in the function entry.

Signed-off-by: Scottie Kuo <scottie.kuo@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maggie Chu <maggie.chu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Jian J Wang <jian.j.wang@intel.com>
2021-06-15 08:43:25 +00:00
1ad794b627 MdeModulePkg: Fix device path when boot manager menu is from different FV
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3441

When the boot manager menu is from different FV, the current logic still
use the device path of the FV as the module links to this library

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-06-15 08:08:15 +00:00
288bd74a22 Pytool: SpellCheck: Fix incorrect file mask across package matrices
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3443

Existing implementation could modify class global data that causes
potential incorrect file mask to be used for execution of plugin.

This change switches class variable to be tuple so that it cannot be
accidently modified. Local usage of STANDARD_PLUGIN_DEFINED_PATHS is also
changed to copy to new list before modification.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-15 07:12:13 +00:00
b8649cf2a3 NetworkPkg/IScsiDxe: check IScsiHexToBin() return values
IScsiDxe (that is, the initiator) receives two hex-encoded strings from
the iSCSI target:

- CHAP_C, where the target challenges the initiator,

- CHAP_R, where the target answers the challenge from the initiator (in
  case the initiator wants mutual authentication).

Accordingly, we have two IScsiHexToBin() call sites:

- At the CHAP_C decoding site, check whether the decoding succeeds. The
  decoded buffer ("AuthData->InChallenge") can accommodate 1024 bytes,
  which is a permissible restriction on the target, per
  <https://tools.ietf.org/html/rfc7143#section-12.1.3>. Shorter challenges
  from the target are acceptable.

- At the CHAP_R decoding site, enforce that the decoding both succeed, and
  provide exactly ISCSI_CHAP_RSP_LEN bytes. CHAP_R contains the digest
  calculated by the target, therefore it must be of fixed size. We may
  only call IScsiCHAPAuthTarget() if "TargetRsp" has been fully populated.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210608121259.32451-11-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
54e90edaed NetworkPkg/IScsiDxe: fix IScsiHexToBin() buffer overflow
The IScsiHexToBin() function documents the EFI_BUFFER_TOO_SMALL return
condition, but never actually checks whether the decoded buffer fits into
the caller-provided room (i.e., the input value of "BinLength"), and
EFI_BUFFER_TOO_SMALL is never returned. The decoding of "HexStr" can
overflow "BinBuffer".

This is remotely exploitable, as shown in a subsequent patch, which adds
error checking to the IScsiHexToBin() call sites. This issue allows the
target to compromise the initiator.

Introduce EFI_BAD_BUFFER_SIZE, in addition to the existent
EFI_BUFFER_TOO_SMALL, for reporting a special case of the buffer overflow,
plus actually catch the buffer overflow.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210608121259.32451-10-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
47b76780b4 NetworkPkg/IScsiDxe: fix IScsiHexToBin() hex parsing
The IScsiHexToBin() function has the following parser issues:

(1) If the *subject sequence* in "HexStr" is empty, the function returns
    EFI_SUCCESS (with "BinLength" set to 0 on output). Such inputs should
    be rejected.

(2) The function mis-handles a "HexStr" that ends with a stray nibble. For
    example, if "HexStr" is "0xABC", the function decodes it to the bytes
    {0xAB, 0x0C}, sets "BinLength" to 2 on output, and returns
    EFI_SUCCESS. Such inputs should be rejected.

(3) If an invalid hex char is found in "HexStr", the function treats it as
    end-of-hex-string, and returns EFI_SUCCESS. Such inputs should be
    rejected.

All of the above cases are remotely triggerable, as shown in a subsequent
patch, which adds error checking to the IScsiHexToBin() call sites. While
the initiator is not immediately compromised, incorrectly parsing CHAP_R
from the target, in case of mutual authentication, is not great.

Extend the interface contract of IScsiHexToBin() with
EFI_INVALID_PARAMETER, for reporting issues (1) through (3), and implement
the new checks.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210608121259.32451-9-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
dc469f1371 NetworkPkg/IScsiDxe: reformat IScsiHexToBin() leading comment block
We'll need further return values for IScsiHexToBin() in a subsequent
patch; make room for them in the leading comment block of the function.
While at it, rewrap the comment block to 80 characters width.

No functional changes.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210608121259.32451-8-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
d90fff40cb NetworkPkg/IScsiDxe: assert that IScsiBinToHex() always succeeds
IScsiBinToHex() is called for encoding:

- the answer to the target's challenge; that is, CHAP_R;

- the challenge for the target, in case mutual authentication is enabled;
  that is, CHAP_C.

The initiator controls the size of both blobs, the sizes of their hex
encodings are correctly calculated in "RspLen" and "ChallengeLen".
Therefore the IScsiBinToHex() calls never fail; assert that.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210608121259.32451-7-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
cf01b2dc8f NetworkPkg/IScsiDxe: fix potential integer overflow in IScsiBinToHex()
Considering IScsiBinToHex():

>   if (((*HexLength) - 3) < BinLength * 2) {
>     *HexLength = BinLength * 2 + 3;
>   }

the following subexpressions are problematic:

  (*HexLength) - 3
  BinLength * 2
  BinLength * 2 + 3

The first one may wrap under zero, the latter two may wrap over
MAX_UINT32.

Rewrite the calculation using SafeIntLib.

While at it, change the type of the "Index" variable from UINTN to UINT32.
The largest "Index"-based value that we calculate is

  Index * 2 + 2                                (with (Index == BinLength))

Because the patch makes

  BinLength * 2 + 3

safe to calculate in UINT32, using UINT32 for

  Index * 2 + 2                                (with (Index == BinLength))

is safe too. Consistently using UINT32 improves readability.

This patch is best reviewed with "git show -W".

The integer overflows that this patch fixes are theoretical; a subsequent
patch in the series will audit the IScsiBinToHex() call sites, and show
that none of them can fail.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210608121259.32451-6-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
e8f28b09e6 NetworkPkg/IScsiDxe: clean up library class dependencies
Sort the library class dependencies in the #include directives and in the
INF file. Remove the DpcLib class from the #include directives -- it is
not listed in the INF file, and IScsiDxe doesn't call either DpcLib API
(QueueDpc(), DispatchDpc()). No functional changes.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210608121259.32451-5-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
95616b8661 NetworkPkg/IScsiDxe: clean up "ISCSI_CHAP_AUTH_DATA.OutChallengeLength"
The "ISCSI_CHAP_AUTH_DATA.OutChallenge" field is declared as a UINT8 array
with ISCSI_CHAP_AUTH_MAX_LEN (1024) elements. However, when the challenge
is generated and formatted, only ISCSI_CHAP_RSP_LEN (16) octets are used
in the array.

Change the array size to ISCSI_CHAP_RSP_LEN, and remove the (now unused)
ISCSI_CHAP_AUTH_MAX_LEN macro.

Remove the "ISCSI_CHAP_AUTH_DATA.OutChallengeLength" field, which is
superfluous too.

Most importantly, explain in a new comment *why* tying the challenge size
to the digest size (ISCSI_CHAP_RSP_LEN) has always made sense. (See also
Linux kernel commit 19f5f88ed779, "scsi: target: iscsi: tie the challenge
length to the hash digest size", 2019-11-06.) For sure, the motivation
that the new comment now explains has always been there, and has always
been the same, for IScsiDxe; it's just that now we spell it out too.

No change in peer-visible behavior.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210608121259.32451-4-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
29cab43bb7 NetworkPkg/IScsiDxe: simplify "ISCSI_CHAP_AUTH_DATA.InChallenge" size
The ISCSI_CHAP_AUTH_MAX_LEN macro is defined with value 1024.

The usage of this macro currently involves a semantic (not functional)
bug, which we're going to fix in a subsequent patch, eliminating
ISCSI_CHAP_AUTH_MAX_LEN altogether.

For now, remove the macro's usage from all
"ISCSI_CHAP_AUTH_DATA.InChallenge" contexts. This is doable without
duplicating open-coded constants.

No changes in functionality.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Message-Id: <20210608121259.32451-3-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
83761337ec NetworkPkg/IScsiDxe: wrap IScsiCHAP source files to 80 characters
Working with overlong lines is difficult for me; rewrap the CHAP-related
source files in IScsiDxe to 80 characters width. No functional changes.

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3356
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210608121259.32451-2-lersek@redhat.com>
2021-06-09 17:25:03 +00:00
702ba436ed OvmfPkg/PlatformCI: bump QEMU choco package version to 2021.5.5
We currently require QEMU choco package version 2020.08.14 (from commit
3ab9d60fcb), in "OvmfPkg/PlatformCI/.azurepipelines/Windows-VS2019.yml".
Said package version references the following URLs:

https://community.chocolatey.org/packages/Qemu/2020.08.14#files
-> https://qemu.weilnetz.de/w32/qemu-w32-setup-20200814.exe
-> https://qemu.weilnetz.de/w64/qemu-w64-setup-20200814.exe

These URLs no longer work; Stefan Weil seems to have moved the binaries to
the following archive directories:

- https://qemu.weilnetz.de/w32/2020/
- https://qemu.weilnetz.de/w64/2020/

In theory, the old QEMU choco packages should be fixed (their powershell
scripts should be updated to reference the new URLs on Stefan Weil's
website). However, this PlatformCI issue is blocking the merging of the
security fix for TianoCore#3356, so getting PlatformCI functional again is
urgent. Let's bump our QEMU choco package requirement to 2021.5.5, whose
URLs work, for now.

(Currently we cannot use any other choco package version, as Stefan's
directories <https://qemu.weilnetz.de/w32> and
<https://qemu.weilnetz.de/w64>, without any further subdirectories, only
offer the 20210505 EXE files.)

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210609155731.10431-1-lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-06-09 16:43:39 +00:00
beb443fde0 ShellPkg: Fix typo
Fix typo of 'specified' in UefiShellDriver1CommandsLib.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2021-06-09 06:12:52 +00:00
558d83ab1a OvmfPkg/README: Fix typo in README
Fix typographical error in the OvmfPkg/README by correcting the 'an'
mistyped as 'and'.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: mikuback@linux.microsoft.com
Cc: ray.ni@intel.com
Signed-off-by: Kaaira Gupta <kaaira7319@gmail.com>
Message-Id: <20210605171712.GA16976@kaaira-HP-Pavilion-Notebook>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-06-07 17:47:35 +00:00
ddb3fdbef3 BaseTools GenFw: Fix regression issue to convert the image to ACPI data
Commit c6b872c updates GenFw base code attribute to find .text section.
With GCC49 tool chain, aslc file is compiled into elf image.
But, its text section has no CODE attribute. So, it can't be detected
by new GenFw tool.For this type file. its text section is not required.
Its data section will be converted to acpi table.

This fix is to remove assert check when the generated image is ACPI data.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Tested-by: Leif Lindholm <leif@nuviainc.com>
2021-06-06 08:03:00 +00:00
51adb689e1 OvmfPkg: restrict XenPlatformLib to BdsDxe in the IA32, IA32X64, X64 DSCs
The "OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf"
library instance is used in the following platform DSC files in edk2:

  OvmfPkg/OvmfPkgIa32.dsc
  OvmfPkg/OvmfPkgIa32X64.dsc
  OvmfPkg/OvmfPkgX64.dsc
  OvmfPkg/OvmfXen.dsc

The Xen customizations are very light-weight in this
PlatformBootManagerLib instance. Isolating them statically, for the sake
of the first three DSC files, would save negligible binary code size, and
would likely worsen code complexity (by way of introducing new internal
interfaces) or blow up source code size (by duplicating almost the entire
lib instance source code). So for now, keep this one bit of Xen dynamism
even on QEMU.

However, because it's only PlatformBootManagerLib now that uses
XenPlatformLib (for the above-stated enlightenment), restrict the
XenPlatformLib class resolution in the first three DSC files to the only
DXE driver that consumes PlatformBootManagerLib (and therefore
XenPlatformLib): BdsDxe. This will cause a build failure later if someone
attempts to call a XenPlatformLib API (that is, tries to re-introduce Xen
enlightenment) in a different module in these non-Xen DSC files.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-44-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
ce270905bf OvmfPkg/SmbiosPlatformDxe: split Xen entry point from QEMU entry point
Remove the SmbiosTablePublishEntry() function from "SmbiosPlatformDxe.c".
"SmbiosPlatformDxe.c" becomes hypervisor-agnostic.

Add SmbiosTablePublishEntry() back, simplified for QEMU, to the existent
file "Qemu.c". The GetQemuSmbiosTables() function no longer needs to be
declared in "SmbiosPlatformDxe.h"; "SmbiosPlatformDxe.h" becomes
hypervisor-agnostic.

Add SmbiosTablePublishEntry() back, renamed and simplified for Xen, to the
new, arch-independent file "Xen.c". (The existent Xen-specific C files are
arch-dependent.)

Update both INF files; remove the dependencies that are now superfluous in
each.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-43-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
d4a8aaee73 OvmfPkg/SmbiosPlatformDxe: create Xen-specific module INF file
"OvmfPkg/SmbiosPlatformDxe" is structured somewhat differently from the
drivers duplicated and trimmed thus far in this series. The final QEMU and
Xen versions will share a relatively significant amount of code, therefore
duplicating the whole driver is less useful, even temporarily. Instead,
duplicate the INF file, in preparation for customizing the entry point
function.

Because ArmVirtXen doesn't actually include OvmfPkg/SmbiosPlatformDxe [*],
there is only one platform that's supposed to consume the new driver:
OvmfXen. Switch OvmfXen to the new driver at once.

[*] See commit 164cf40383 ("OvmfPkg: SmbiosPlatformDxe: restrict current
    Xen code to IA32/X64", 2015-07-26).

This patch is best viewed with "git show --find-copies-harder".

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-42-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
9d84e74ca0 OvmfPkg/SmbiosPlatformDxe: declare InstallAllStructures() in header file
Add an extern declaration for the InstallAllStructures() function to the
"SmbiosPlatformDxe.h" header file. (The leading comment block and the
prototype are simply copied from "SmbiosPlatformDxe.c".)

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-41-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
a8ab14424e OvmfPkg/SmbiosPlatformDxe: split GetXenSmbiosTables() decl. to new header
Move the declaration of the GetXenSmbiosTables() function to a new header
file called "XenSmbiosPlatformDxe.h". (The only declaration that remains
in "SmbiosPlatformDxe.h" for now is that of GetQemuSmbiosTables().)

Modify the pattern in "Maintainers.txt" so that the new file be covered in
the "OvmfPkg: Xen-related modules" section.

This patch is best viewed with "git show --no-renames".

Cc: Andrew Fish <afish@apple.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-40-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-04 16:01:50 +00:00
4db374562f OvmfPkg/SmbiosPlatformDxe: locate SMBIOS protocol in InstallAllStructures()
Locate the SMBIOS protocol internally to the InstallAllStructures()
function. This has no performance impact (InstallAllStructures() is only
called once), but moving the code from the entry point function makes the
latter smaller. And that will be useful when we split the entry point
function to two versions.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-39-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
5072593738 OvmfPkg/SmbiosPlatformDxe: return EFI_NOT_FOUND if there is no SMBIOS data
According to the function-top comment, SmbiosTablePublishEntry() is
supposed to return an error code if no SMBIOS data is found, from either
GetXenSmbiosTables() or GetQemuSmbiosTables(). Currently the function
returns EFI_SUCCESS in this case however (propagated from
gBS->LocateProtocol()). Make the return code match the documentation.

(This issue is not too important, but it gets in the way of splitting the
entry point function next.)

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-38-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
7e25086a00 OvmfPkg/SmbiosPlatformDxe: clean up #includes and INF
- Sort all sections in the INF file.

- Remove unused packages (MdeModulePkg) and lib classes (BaseMemoryLib)
  from the INF file.

- Restrict some lib classes (BaseLib, HobLib) and GUIDs (gEfiXenInfoGuid)
  to IA32 and X64, in the INF file; only the IA32/X64 Xen implementation
  requires these.

- Don't make "SmbiosPlatformDxe.h" #include everything just as a
  convenience. Spell out directly needed #includes in every file (annotate
  each with an example identifier consumed), drop unused #includes.

- Keep #includes sorted.

- Remove the leading underscore from the #include guard macro name in
  "SmbiosPlatformDxe.h".

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-37-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
8af38170b5 OvmfPkg/PciHostBridgeLibScan: clean up file names and file-top comments
Rename "XenSupport.c" to "ScanForRootBridges.c", after the main function
in it.

Update the file-top comments; refer to both Bhyve and Xen.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-36-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
4c81178cf0 OvmfPkg/PciHostBridgeLibScan: remove PcdOvmfHostBridgePciDevId
The "OvmfPkg/Library/PciHostBridgeLibScan/PciHostBridgeLibScan.inf"
instance is used in the following platforms in edk2:

  OvmfPkg/Bhyve/BhyveX64.dsc
  OvmfPkg/OvmfXen.dsc

Neither Bhyve nor Xen provide a Q35 board, therefore the expression

  PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID

always evaluates to TRUE, in the PciHostBridgeLibScan instance.

Replace the expression with constant TRUE, eliminating the PCD dependency.

(In effect, this reports that the root bridge being registered does not
support extended PCI config space.)

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-35-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
33d4f3e39e OvmfPkg/PciHostBridgeLibScan: remove QEMU (fw_cfg) support
The "OvmfPkg/Library/PciHostBridgeLibScan/PciHostBridgeLibScan.inf"
instance is used in the following platforms in edk2:

  OvmfPkg/Bhyve/BhyveX64.dsc
  OvmfPkg/OvmfXen.dsc

Both platforms define "PcdPciDisableBusEnumeration" with Fixed-at-Build
access method, and TRUE value. Remove the PCD from the
PciHostBridgeLibScan instance, and everything else that is useful only
when the PCD is FALSE.

In practice, this removes the PciHostBridgeUtilityGetRootBridges()
function call, which is based on fw-cfg; see
"OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c".

(Note that the dependency on PciHostBridgeUtilityLib remains in place,
given that the PciHostBridgeLibScan instance continues using lower-level
functions from the library that do not depend on fw-cfg.)

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-34-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
242678da2a OvmfPkg/PciHostBridgeLib: remove Bhyve and Xen support
The "OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf" instance is
used by the following platforms in edk2:

  OvmfPkg/AmdSev/AmdSevX64.dsc
  OvmfPkg/OvmfPkgIa32.dsc
  OvmfPkg/OvmfPkgIa32X64.dsc
  OvmfPkg/OvmfPkgX64.dsc

All these platforms statically inherit PcdPciDisableBusEnumeration=FALSE
from "MdeModulePkg.dec". Remove the the PCD and everything that depends on
it from the PciHostBridgeLib instance. Namely, remove the logic that
determines the root bridge apertures by (a) scanning the entire bus,
device and function number space, and (b) parsing the BAR values that were
pre-set by the Bhyve or Xen machinery.

"XenSupport.c" used to be listed explicitly in "Maintainers.txt", remove
it from that spot too.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-33-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-04 16:01:50 +00:00
307763c3da OvmfPkg/OvmfXen: consume PciHostBridgeLibScan
Switch the OvmfXen platform from the "OvmfPkg/PciHostBridgeLib" instance
to the "OvmfPkg/PciHostBridgeLibScan" instance. Currently this is a no-op
functionally; we'll customize the "PciHostBridgeLibScan" instance later.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-32-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
c2f24ba321 OvmfPkg/Bhyve: consume PciHostBridgeLibScan
Switch the Bhyve platform from the "OvmfPkg/PciHostBridgeLib" instance to
the "OvmfPkg/PciHostBridgeLibScan" instance. Currently this is a no-op
functionally; we'll customize the "PciHostBridgeLibScan" instance later.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-31-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2021-06-04 16:01:50 +00:00
e120c962f5 OvmfPkg/PciHostBridgeLibScan: create from PciHostBridgeLib
Create an almost verbatim copy of the
"OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf" library instance.

The new PciHostBridgeLibScan instance will ultimately duplicate a
negligible amount of code from the original, and will be used by the Bhyve
and OvmfXen platforms.

List the new driver in "Maintainers.txt", in the "OvmfPkg: bhyve-related
modules" and "OvmfPkg: Xen-related modules" sections.

This patch should be reviewed with "git show --find-copies-harder".

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-30-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
32fef03563 OvmfPkg/PciHostBridgeLib: consolidate #includes and INF file sections
- In every C file, list every necessary public #include individually, with
  an example identifier that's actually consumed.

- Place all public #includes first, all module-private #includes second.
  Separate them with a single empty line. Keep each section sorted in
  itself.

- Sort all sections in the INF file, except [Defines].

- Add unlisted lib classes.

- Remove unnecessary #include directives, add unlisted #include
  directives.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-29-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
984c93ece3 OvmfPkg/IncompatiblePciDeviceSupportDxe: remove PcdPciDisableBusEnumeration
At this point, the IncompatiblePciDeviceSupportDxe driver is included in
the following platforms in edk2:

  OvmfPkg/AmdSev/AmdSevX64.dsc
  OvmfPkg/OvmfPkgIa32.dsc
  OvmfPkg/OvmfPkgIa32X64.dsc
  OvmfPkg/OvmfPkgX64.dsc

All those platforms inherit FALSE for "PcdPciDisableBusEnumeration" from
"MdeModulePkg.dec".

This makes the PcdGetBool() call in the entry point of the driver
superfluous; remove it. Clean up now unused dependencies in the INF file
as well.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-28-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
8c8f886f27 OvmfPkg/Bhyve: remove IncompatiblePciDeviceSupport DXE driver
The entry point function of "OvmfPkg/IncompatiblePciDeviceSupportDxe",
namely DriverInitialize()
[OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c],
bails out immediately if "PcdPciDisableBusEnumeration" is TRUE.

The Bhyve platform statically assigns this PCD TRUE. Thus, remove the
driver from the Bhyve platform.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-27-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
b005f9f1f5 OvmfPkg/OvmfXen: remove IncompatiblePciDeviceSupport DXE driver
The entry point function of "OvmfPkg/IncompatiblePciDeviceSupportDxe",
namely DriverInitialize()
[OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.c],
bails out immediately if "PcdPciDisableBusEnumeration" is TRUE.

The OvmfXen platform statically assigns this PCD TRUE. Thus, remove the
driver from the OvmfXen platform.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-26-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
e43cca74ad OvmfPkg/Bhyve: make "PcdPciDisableBusEnumeration" Fixed-at-Build
The Bhyve platform specifies the dynamic access method for
"PcdPciDisableBusEnumeration" needlessly.

After the DSC file sets the PCD to TRUE by default, the PCD is never
written again. In particular, the
"OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf" file references the PCD
superfluously.

Make the PCD Fixed-At-Build, and remove the PCD reference from the INF
file.

(Note that further simplifications are possible in
"OvmfPkg/Bhyve/AcpiPlatformDxe", but those are out of scope for this patch
series.)

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-25-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2021-06-04 16:01:50 +00:00
2833589ad0 OvmfPkg: drop PcdPciDisableBusEnumeration from the AmdSev platform
With the Xen-dependent PcdSetBoolS() call removed from
OvmfPkg/PlatformPei, the "AmdSevX64.dsc" platform never writes
"PcdPciDisableBusEnumeration". This means we don't need a dynamic default
for the PCD in the DSC file; it could be declared Fixed-at-Build.

However, because the PCD's default value in "MdeModulePkg.dec" is FALSE,
remove the (same-value) platform default altogether.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-24-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
8899e3fe6a OvmfPkg: drop PcdPciDisableBusEnumeration from the IA32, IA32X64, X64 DSCs
With the Xen-dependent PcdSetBoolS() call removed from
OvmfPkg/PlatformPei, the "OvmfPkgIa32.dsc", "OvmfPkgIa32X64.dsc",
"OvmfPkgX64.dsc" platforms never write "PcdPciDisableBusEnumeration". This
means we don't need a dynamic default for the PCD in the DSC files; it
could be declared Fixed-at-Build.

However, because the PCD's default value in "MdeModulePkg.dec" is FALSE,
remove the (same-value) platform defaults altogether.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-23-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
d06eb2d1d9 OvmfPkg/PlatformPei: remove Xen support
The "OvmfPkg/PlatformPei/PlatformPei.inf" module is used by the following
platform DSCs:

  OvmfPkg/AmdSev/AmdSevX64.dsc
  OvmfPkg/OvmfPkgIa32.dsc
  OvmfPkg/OvmfPkgIa32X64.dsc
  OvmfPkg/OvmfPkgX64.dsc

Remove Xen support from "OvmfPkg/PlatformPei", including any dependencies
that now become unused. The basic idea is to substitute FALSE for "mXen".

Remove "OvmfPkg/PlatformPei" from the "OvmfPkg: Xen-related modules"
section of "Maintainers.txt".

This patch is best reviewed with "git show -b -W".

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-22-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-04 16:01:50 +00:00
3357ac7380 OvmfPkg/XenAcpiPlatformDxe: remove delayed ACPI table installation
Because "PcdPciDisableBusEnumeration" is always TRUE in the OvmfXen
platform, we can remove the delayed ACPI table installation from
XenAcpiPlatformDxe. A number of dependencies become useless this way;
remove them too.

(Note that, conversely, in the QemuFwCfgAcpiPlatformDxe driver, we
*cannot* assume that "PcdPciDisableBusEnumeration" is always FALSE,
regardless of Xen: in the ArmVirtQemu platform, the PCD may carry either
FALSE or TRUE, dependent on whether or not the QEMU "virt" machine
configuration includes a PCIe host controller, respectively.)

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-21-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
e7641171b6 OvmfPkg/OvmfXen: make "PcdPciDisableBusEnumeration" Fixed-at-Build
The OvmfXen platform specifies the dynamic access method for
"PcdPciDisableBusEnumeration" needlessly.

After the DSC file sets the PCD to TRUE by default, the InitializeXen()
function in XenPlatformPei superfluously sets the PCD to TRUE again. There
are no other writes to the PCD in the platform.

Make the PCD Fixed-At-Build, and remove the access (in fact, the whole
InitializeXen() function) from XenPlatformPei.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-20-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
d491c88a0c OvmfPkg/AcpiTables: remove unused module
The "OvmfPkg/AcpiTables/AcpiTables.inf" module is no longer used by any
module in edk2; remove it.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-19-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
4174c5c787 OvmfPkg/Bhyve/AcpiPlatformDxe: fix file path typo in comment
The built-in ACPI tables for Bhyve are located in the
"OvmfPkg/Bhyve/AcpiTables" module, not in the "OvmfPkg/AcpiTables" module.
Correct the typo in a code comment.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-18-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2021-06-04 16:01:50 +00:00
8f8d3d90c5 OvmfPkg/XenAcpiPlatformDxe: remove OVMF's built-in ACPI tables
Xen is an advanced hypervisor; no Xen guest can function correctly without
the hypervisor's dynamically provided ACPI tables. Remove the built-in
(fallback) tables from XenAcpiPlatformDxe -- and the OvmfXen platform.

Remove any dependencies from XenAcpiPlatformDxe that are no longer needed.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-17-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
3f975ee570 OvmfPkg/XenAcpiPlatformDxe: remove the InstallAcpiTable() helper function
The InstallAcpiTable() helper function buys us nothing. Reduce code
complexity by removing the function.

This patch is best viewed with "git show -b".

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-16-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
d6ba8aa6ef OvmfPkg/XenAcpiPlatformDxe: remove QEMU fw_cfg dependency
The QemuDetected() function wraps QemuFwCfgIsAvailable(); it always fails
on Xen. Because of that, we can eliminate the QemuDetected() call itself
from the Xen ACPI platform driver, and then the rest of "Qemu.c" becomes
useless -- the workhorse function of that source file is
QemuInstallAcpiTable(), which we no longer call.

Remove any dependencies that are no longer needed by the
XenAcpiPlatformDxe driver.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-15-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
4115840c28 OvmfPkg/XenAcpiPlatformDxe: remove the QEMU ACPI linker/loader client
The root of the QEMU ACPI linker/loader client in XenAcpiPlatformDxe is
the InstallQemuFwCfgTables() function. This function always fails on Xen,
due to its top-most QemuFwCfgFindFile() call.

Remove the InstallQemuFwCfgTables() function call from XenAcpiPlatformDxe,
along with all dependencies that now become unused.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-14-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
a31fcb5096 OvmfPkg/AcpiPlatformDxe: remove the "AcpiPlatformDxe.inf" driver
The "OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf" module is no longer
referenced in any platform DSC file; remove it.

That orphans the "AcpiPlatform.c", "Qemu.c" and "Xen.c" files in the
"OvmfPkg/AcpiPlatformDxe/" directory; remove them.

That in turn removes the only definitions of the InstallAcpiTable(),
QemuDetected(), QemuInstallAcpiTable(), InstallXenTables() functions in
the "OvmfPkg/AcpiPlatformDxe/" directory, so remove their declarations
from "AcpiPlatform.h".

Remove "OvmfPkg/AcpiPlatformDxe/Xen.c" from the "OvmfPkg: Xen-related
modules" section of "Maintainers.txt", as well.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-13-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-04 16:01:50 +00:00
c9bba52fc7 OvmfPkg/XenAcpiPlatformDxe: create from AcpiPlatformDxe
Create an almost verbatim copy of the
"OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf" driver for the OvmfXen
platform. We're going to trim the driver in subsequent patches.
Ultimately, the XenAcpiPlatformDxe driver will duplicate a negligible
amount of code that is currently present in the QemuFwCfgAcpiPlatformDxe
driver.

List the new driver in "Maintainers.txt", in the "OvmfPkg: Xen-related
modules" section.

Switch the OvmfXen platform to the new driver at once.

This patch should be reviewed with "git show --find-copies-harder".

Cc: Andrew Fish <afish@apple.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien@xen.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-12-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-06-04 16:01:50 +00:00
cc302b799e OvmfPkg/AcpiPlatformDxe: consolidate #includes and [LibraryClasses]
- #include only such public headers in "AcpiPlatform.h" that are required
  by the function declarations and type definitions introduced in
  "AcpiPlatform.h". Don't use "AcpiPlatform.h" as a convenience #include
  file.

- In every file, list every necessary public #include individually, with
  an example identifier that's actually consumed.

- Remove unnecessary lib classes, add unlisted lib classes.

- Remove unnecessary #include directives, add unlisted #include
  directives.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-11-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
747b1ef725 OvmfPkg/AcpiPlatformDxe: move "QemuLoader.h" to IndustryStandard
Turn the "QemuLoader.h" header into a public (IndustryStandard) one. The
QEMU ACPI linker-loader interface is stable between QEMU and multiple
guest firmwares.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-10-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
6d1e56e715 OvmfPkg/AcpiPlatformDxe/QemuLoader.h: remove QemuFwCfgLib class dependency
"QemuLoader.h" needs the QEMU_FW_CFG_FNAME_SIZE macro. This macro used to
live in the QemuFwCfgLib class header, but we moved it to the more
foundational IndustryStandard include file called "QemuFwCfg.h" in commit
5583a8a4ff ("OvmfPkg/QemuFwCfgLib: move types/macros from lib class to
IndustryStandard", 2017-02-22).

Replace the lib class dependency with the more basic IndustryStandard
dependency in "QemuLoader.h".

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-9-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
180f1908b3 OvmfPkg/AcpiPlatformDxe: sort #includes and [LibraryClasses]
Place all public #includes first, all module-private #includes second.
Separate them with a single empty line. Keep each section sorted in
itself.

Sort all sections in both INF files.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-8-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
2a85d9b07e OvmfPkg/AcpiPlatformDxe: fix header file warts
- Remove the leading underscores from the #include guard macro names;
  clean up the names in general.

- Remove the useless "Include/" directory prefix from the public header
  pathnames.

- Fix incorrect file-top comment.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-7-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
ae4aa4a346 OvmfPkg/README: bump minimum QEMU version to 1.7.1, machine types to 1.7
Due to switching to the QemuFwCfgAcpiPlatformDxe driver earlier in this
series, require QEMU version 1.7.1 in the "OvmfPkg/README" file, and
require 1.7 or later machine types too.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-6-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
d697037446 OvmfPkg: switch the AmdSev platform to the fw_cfg-only ACPI platform driver
For consistency with the historical OvmfPkg* platforms, switch the
remotely attested, QEMU/KVM-only, AmdSev platform from the AcpiPlatformDxe
driver to the QemuFwCfgAcpiPlatformDxe driver.

No module remains dependent on XenPlatformLib, so remove the
XenPlatformLib class resolution too, from the DSC file.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-5-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
7bc04a75a7 OvmfPkg: switch IA32, IA32X64, X64 to the fw_cfg-only ACPI platform driver
Switch the historical OvmfPkg* platforms from the AcpiPlatformDxe driver
to the QemuFwCfgAcpiPlatformDxe driver. (The latter is used by the
ArmVirtQemu* platforms as well.)

The change effectively replaces the following call tree:

  InstallAcpiTables                [AcpiPlatform.c]

    XenDetected                    [XenPlatformLib] *
    InstallXenTables               [Xen.c]          *
      GetXenAcpiRsdp               [Xen.c]          *

    InstallQemuFwCfgTables         [QemuFwCfgAcpi.c]
      ...

    InstallOvmfFvTables            [AcpiPlatform.c] *
      QemuDetected                 [Qemu.c]         *
      LocateFvInstanceWithTables   [AcpiPlatform.c] *
        QemuInstallAcpiTable       [Qemu.c]         *
          QemuInstallAcpiMadtTable [Qemu.c]         *
            CountBits16            [Qemu.c]         *
          QemuInstallAcpiSsdtTable [Qemu.c]         *
            GetSuspendStates       [Qemu.c]         *
            PopulateFwData         [Qemu.c]         *

with the one below:

  InstallAcpiTables        [QemuFwCfgAcpiPlatform.c]
    InstallQemuFwCfgTables [QemuFwCfgAcpi.c]
      ...

eliminating the sub-trees highlighted with "*".

There are two consequences:

(1) Xen compatibility is removed from the ACPI platform driver of the
   historical OvmfPkg* platforms.

(2) The ACPI tables that are statically built into OVMF (via
    "OvmfPkg/AcpiTables/AcpiTables.inf") are never installed. In
    particular, OVMF's own runtime preparation of the MADT and SSDT is
    eliminated.

Because of (2), remove the "OvmfPkg/AcpiTables/AcpiTables.inf" module as
well -- and then the ACPITABLE build rule too.

Note that (2) only removes effectively dead code; the QEMU ACPI
linker-loader has taken priority since QEMU 1.7.1 (2014). References:

- https://wiki.qemu.org/Planning/1.7
- https://wiki.qemu.org/Features/ACPITableGeneration
- edk2 commit 96bbdbc856 ("OvmfPkg: AcpiPlatformDxe: download ACPI
                            tables from QEMU", 2014-03-31)
- edk2 commit 387536e472 ("OvmfPkg: AcpiPlatformDxe: implement QEMU's
                            full ACPI table loader interface", 2014-09-22)

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-4-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
aa7f19f480 OvmfPkg: remove the Xen drivers from the AmdSev platform
For symmetry with the historical OvmfPkg* platforms, remove the three Xen
drivers from the remotely attested, QEMU/KVM-only, AmdSev platform. Xen
(HVM and PVH) guests are supported by the dedicated OvmfXen platform.

No module remains dependent on XenHypercallLib, so remove the
XenHypercallLib class resolution too, from the DSC file.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-3-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
e25566cd2b OvmfPkg: remove the Xen drivers from the IA32, IA32X64, and X64 platforms
Remove the three Xen drivers as the first step for removing Xen support
from the historical OvmfPkg* platforms. Xen (HVM and PVH) guests are
supported by the dedicated OvmfXen platform.

No module remains dependent on XenHypercallLib, so remove the
XenHypercallLib class resolutions too, from the DSC files.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2122
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210526201446.12554-2-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-06-04 16:01:50 +00:00
924c2b847f BaseTools: Change CLANG8ELF to CLANGDWARF
CLANGDWARF is more proper because it's similar to CLANGPDB that generates
PE images but with DWARF debug symbols.
This toolchain is needed for creating ELF format universal payload that
follows https://universalpayload.github.io/documentation/.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-04 09:20:06 +00:00
e1636fe18f BaseTools: Update ClangBase.lds to keep dynamic section
The .dynamic section is needed for ELF runtime relocation.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-04 09:20:06 +00:00
4b56ad2049 BaseTools: Add new CLANG8ELF tool chain for new LLVM/CLANG8
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1603
LLVM/CLANG8 formal release http://releases.llvm.org/download.html#8.0.0
It can be downloaded and installed in Windows/Linux/Mac OS.
CLANG8ELF tool chain is added to generate ELF image, and convert to PE/COFF.
On Windows OS, set CLANG_HOST_BIN=n, set CLANG8_BIN=LLVM installed directory
For example:
  set CLANG_HOST_BIN=n # use windows nmake
  set CLANG8_BIN=C:\Program Files\LLVM\bin\
On Linux/Mac, set CLANG8_BIN=LLVM installed directory

This tool chain can be used to compile the firmware code. On windows OS,
Visual Studio is still required to compile BaseTools C tools and nmake.exe.
On Linux/Mac OS, gcc is used to compile BaseTools C tools. make is used
for makefile.

This tool chain is verified on OVMF Ia32, X64 and Ia32X64 to boot Shell.
This tool chain is verified in Windows/Linux and Mac OS.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Feng Bob C <bob.c.feng@intel.com>
2021-06-04 09:20:06 +00:00
cf9959adff BaseTools: Update build_rule to skip CLANG resource section generation
LLVM/CLANG doesn't support resource section generation when ELF image generated.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Feng Bob C <bob.c.feng@intel.com>
2021-06-04 09:20:06 +00:00
c6b872c6ab BaseTools GenFw: Support CLANG8ELF with conversion ELF to PE/COFF image
CLANG8ELF tool chain generated ELF image with the different attributes
in section. Update GenFw to handle them.
1. .text section with writable attribute (support)
2. .reloc section has the symbol for *ABS* (skip)

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Feng Bob C <bob.c.feng@intel.com>
2021-06-04 09:20:06 +00:00
c1aa3bab12 BaseTools: Add ClangBase.lds for CLANG8 tool chain with max-page-size
LLVM LLD linker doesn't support common-page-size option. So, max-page-size
is used. To not impact GCC tool chain, new ClangBase.lds is added.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Feng Bob C <bob.c.feng@intel.com>
2021-06-04 09:20:06 +00:00
c410ad4da4 MdePkg/BaseLib: Fix AsmReadSs() with GCC toolchain
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3405

AsmReadSs() in Ia32/GccInlinePriv.c and X64/GccInlinePriv.c return the
DS segment selector value instead of SS.

Signed-off-by: Satoshi Tanda <tanda.sat@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-06-04 03:24:04 +00:00
75e9154f81 OvmfPkg/VirtioMmioDeviceLib: Add EFIAPI to VirtioMmioSetQueueAddress
This error was found while compiling VirtioMmioDeviceLib for X64
with the GCC5 toolchain, where EFIAPI makes a difference.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20210602045935.762211-1-kraxel@redhat.com>
[lersek@redhat.com: prepend module name to subject, trim subject back to
 allowed length]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-06-02 17:40:46 +00:00
1f515342d8 DynamicTablesPkg: Use AML_NAME_SEG_SIZE define
Use the newly introduced defined value in:
MdePkg/Include/IndustryStandard/AcpiAml.h

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-06-02 09:57:17 +00:00
039e07f626 MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE definition
A NameSeg is made 4 chars.
Cf. ACPI 6.4 s20.2.2 "Name Objects Encoding":
NameSeg := <leadnamechar namechar namechar namechar>
Notice that NameSegs shorter than 4 characters are filled
with trailing underscores (‘_’s).

AML_NAME_SEG_SIZE is currently defined in:
- DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
Since the value can be inferred from the ACPI specification
and to avoid multiple definitions, move it to
MdePkg/Include/IndustryStandard/

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-06-02 09:57:17 +00:00
b5379899b3 MdeModulePkg/Xhci: Fix TRT when data length is 0
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418

According to xhci spec, at USB packet level, a Control Transfer
consists of multiple transactions partitioned into stages: a
setup stage, an optional data stage, and a terminating status
stage. If Data Stage does not exist, the Transfer Type flag(TRT)
should be No Data Stage.
So if data length equals to 0, TRT is set to 0.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-06-02 07:55:57 +00:00
b233eb1849 EmbeddedPkg/RealTimeClockRuntimeDxe: Improve GetWakeupTime
GetWakeupTime should return full time information, including
the daylight/timezone. Make use of the existing non-volatile
variables for that purpose. Moreover add an error checking
of possibly invalid parameters.
This partially fixes FWTS and SCT Set/GetWakeupTime tests on
Marvell platforms.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-06-02 07:16:28 +00:00
fdf3666f01 MdePkg: Update DBG2 and SPCR header with NVIDIA 16550 Subtype
Add macros for NVIDIA 16550 UART specific debug port subtype in both
DBG2 as well as SPCR header file.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-06-01 03:28:16 +00:00
197e27c90a MdePkg: Add new 16550-compatible Serial Port Subtypes to DBG2
The Microsoft Debug Port Table 2 (DBG2) specification revision
May 31, 2017 adds support for 16550-compatible Serial Port
Subtype with parameters defined in Generic Address Structure (GAS) [1]

Reflect that in the EDK2 headers.

[1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2021-06-01 03:28:16 +00:00
d3ff5dbe1d MdePkg: MmControl: Fix function and structure definition mismatches
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3397

Current Ppi/MmControl.h file has structure definition of "struct
_PEI_MM_CONTROL_PPI". This name mismatches with its definition in PI
Specification v1.7 (Errata) as "struct _EFI_PEI_MM_CONTROL_PPI".

In addition, field types "PEI_MM_ACTIVATE" and "PEI_MM_DEACTIVATE" used
in "struct _PEI_MM_CONTROL_PPI" mismatches with the definition of
"EFI_PEI_MM_ACTIVATE" and "EFI_PEI_MM_DEACTIVATE" in the PI spec.

This change fixes these mismatches by using the PI spec defined names.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Fixes: 6f33f7a262
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-01 02:10:53 +00:00
fe5da0927a IntelFsp2WrapperPkg: Remove microcode related PCDs
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334

IntelFsp2WrapperPkg defines following PCDs:
  PcdCpuMicrocodePatchAddress
  PcdCpuMicrocodePatchRegionSize
  PcdFlashMicrocodeOffset

But the PCD name caused confusion because UefiCpuPkg defines:
  PcdCpuMicrocodePatchAddress
  PcdCpuMicrocodePatchRegionSize

PcdCpuMicrocodePatchAddress in IntelFsp2WrapperPkg means the base
address of the FV that holds the microcode.
PcdCpuMicrocodePatchAddress in UefiCpuPkg means the address of the
microcode.

The relationship between the PCDs is:
IntelFsp2WrapperPkg.PcdCpuMicrocodePatchAddress
 +  IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset
 == UefiCpuPkg.PcdCpuMicrocodePatchAddress

IntelFsp2WrapperPkg.PcdCpuMicrocodePatchRegionSize
 -  IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset
 == UefiCpuPkg.PcdCpuMicrocodePatchRegionSize

To avoid confusion and actually the PCDs in IntelFsp2WrapperPkg
are only used by a sample FSP-T wrapper, this patch removes
the 3 PCDs defined in IntelFsp2WrapperPkg.

The FSP-T wrapper is updated to directly use the ones in UefiCpuPkg.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2021-05-31 03:14:08 +00:00
adfa3327d4 OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The Flush parameter is used to provide a hint whether the specified range
is Mmio address. Now that we have a dedicated helper to clear the
memory encryption mask for the Mmio address range, its safe to remove the
Flush parameter from MemEncryptSev{Set,Clear}PageEncMask().

Since the address specified in the MemEncryptSev{Set,Clear}PageEncMask()
points to a system RAM, thus a cache flush is required during the
encryption mask update.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-14-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
b4a8de5d27 OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask()
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio address range.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-13-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
8ee4e52ba8 OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc mask
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio address range.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-12-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
c394fa4c9e OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear EncMask
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
for the Mmio and NonExistent address range.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-11-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
901a9bfc3a OvmfPkg/BaseMemEncryptSevLib: introduce MemEncryptSevClearMmioPageEncMask()
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The MemEncryptSevClearMmioPageEncMask() helper can be used for clearing
the memory encryption mask for the Mmio region.

The MemEncryptSevClearMmioPageEncMask() is a simplified version of
MemEncryptSevClearPageEncMask() -- it does not flush the caches after
clearing the page encryption mask.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-10-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
2b5b2ff04d MdePkg/BaseLib: add support for RMPADJUST instruction
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The RMPADJUST instruction will be used by the SEV-SNP guest to modify the
RMP permissions for a guest page. See AMD APM volume 3 for further
details.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-9-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
5a7cbd54a1 MdePkg/BaseLib: add support for PVALIDATE instruction
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The PVALIDATE instruction validates or rescinds validation of a guest
page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
bits OF, ZF, AF, PF and SF are set based on this return code. If the
instruction completed succesfully, the rFLAGS bit CF indicates if the
contents of the RMP entry were changed or not.

For more information about the instruction see AMD APM volume 3.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
dfd41aef78 MdePkg/Register/Amd: define GHCB macros for SNP AP creation
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled
in the guest VM. See the GHCB specification, Table 5 "List of Supported
Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details.

While at it, define the VMSA state save area that is required for creating
the AP. The save area format is defined in AMD APM volume 2, Table B-4
(there is a mistake in the table that defines the size of the reserved
area at offset 0xc8 as a dword, when it is actually a word). The format of
the save area segment registers is further defined in AMD APM volume 2,
sections 10 and 15.5.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com>
[lersek@redhat.com: fix typo in BZ reference]
2021-05-29 12:15:21 +00:00
4665fa6503 MdePkg/Register/Amd: define GHCB macro for the Page State Change
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

The Page State Change NAE exit will be used by the SEV-SNP guest to
request a page state change using the GHCB protocol. See the GHCB
spec section 4.1.6 and 2.3.1 for more detail on the structure
definitions.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Erdem Aktas <erdemaktas@google.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-6-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
f0983b2074 MdePkg/Register/Amd: define GHCB macro for Register GPA structure
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

An SEV-SNP guest is required to perform the GHCB GPA registration. See
the GHCB specification for further details.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Erdem Aktas <erdemaktas@google.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-5-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
34e16ff883 MdePkg/Register/Amd: define GHCB macros for hypervisor feature detection
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of GHCB introduces advertisement of features that are supported
by the hypervisor. See the GHCB spec section 2.2 for an additional details.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Erdem Aktas <erdemaktas@google.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-4-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
f828fc9876 MdePkg/Register/Amd: realign macros with more space for future expansion
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
Unfortunately, the names for those NAEs break the alignment. Add some
white spaces so that the SNP support patches do not break the alignment.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
0095070e70 MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Define the SEV-SNP MSR bits.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
2021-05-29 12:15:21 +00:00
dbc22a1785 UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324

The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed so that
when PcdSevEsIsEnabled is true, they will track the previous reset buffer
allocation in order to ensure that the new buffer allocation is below the
previous allocation. When PcdSevEsIsEnabled is false, the original logic
is followed.

Fixes: 7b7508ad78
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Marvin Häuser <mhaeuser@posteo.de>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <3cae2ac836884b131725866264e0a0e1897052de.1621024125.git.thomas.lendacky@amd.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2021-05-29 11:33:16 +00:00
b8ed8c0fb2 Maintainers.txt: add Sami Mujawar as top-level ArmVirtPkg reviewer
For distributing ArmVirtPkg patch review tasks better, move Sami Mujawar
from the "ArmVirtPkg: Kvmtool" section to the top-level "ArmVirtPkg"
section.

Given that "ArmVirtPkg: Kvmtool" remains without a specific "R" role,
remove "ArmVirtPkg: Kvmtool" altogether.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Julien Grall <julien@xen.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210514114857.12286-1-lersek@redhat.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-05-29 10:48:22 +00:00
e1999b264f ArmPkg/ArmGic: Fix maximum number of interrupts in GICv3
Bugzilla: 3415 (https://bugzilla.tianocore.org/show_bug.cgi?id=3415)

The GICv3 architecture supports up to 1020 ordinary interrupt
lines. The actual number of interrupts supported is described by the
ITLinesNumber field in the GICD_TYPER register. The total number of
implemented registers is normally calculated as
32*(ITLinesNumber+1). However, maximum value (0x1f) is a special case
since that would indicate that 1024 interrupts are implemented.

Add handling for this special case in ArmGicGetMaxNumInterrupts.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
2021-05-27 10:08:32 +00:00
cfa6ffb113 MdeModulePkg/VariableLock: downgrade compatibility warnings to DEBUG_WARN
Commit a18a9bde36 ("MdeModulePkg/Variable/RuntimeDxe: Restore Variable
Lock Protocol behavior", 2020-12-15), for bug 3111, added two such sets of
debug messages that:

(a) are relevant for developers,

(b) yet should not necessarily poke end-users, because no functionality
suffers in practice.

Both message sets are in function VariableLockRequestToLock(): the first
is a generic interface deprecation warning; the second is the
double-locking situation, which we permit for compatibility (return status
EFI_SUCCESS).

Both message sets should be emitted with the DEBUG_WARN mask, not the most
serious DEBUG_ERROR mask. On some platforms, the serial console carries
both terminal traffic, and grave (DEBUG_ERROR-only) log messages. On such
platforms, both message sets may be perceived as a nuisance by end-users,
as there is nothing they can do, and there's nothing they *should* do --
in practice, nothing malfunctions.

(Such a platform is ArmVirtQemu, built with "-D
DEBUG_PRINT_ERROR_LEVEL=0x80000000".)

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3410
Fixes: a18a9bde36
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210521204037.11980-1-lersek@redhat.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-23 12:06:55 +00:00
1fb80369b7 MdeModulePkg/PlatformDriOverrideDxe: Fix overflow condition check
Code mistake, VariableIndex is smaller normally than buffer+buffersize
so should not break loop.

Signed-off-by: Walon Li <walon.li@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-21 08:31:39 +00:00
04ae17218d BaseTools: build: Set ReturnCode on POSTBUILD fail
When build.by POSTBUILD handling section returns other than 0, set
ReturnCode to POSTBUILD_ERROR so build.py exits with return code other
than 0.

Fix for https://bugzilla.tianocore.org/show_bug.cgi?id=1977

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-21 06:52:36 +00:00
15ee7b7689 CryptoPkg/BaseCryptLib: Fix possible uninitialized use
`Result` can be used uninitialized in both functions after following
either first or second `goto` statement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-05-19 01:39:49 +00:00
4c79f9bc20 MdeModulePkg/PciBusDxe: Fix possible uninitialized use
If the function gets invalid value for the `ResizableBarOp` parameter
and asserts are disabled, `Bit` can be used uninitialized.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-05-19 01:39:49 +00:00
aecfbc81a9 ShellPkg/HttpDynamicCommand: Fix possible uninitialized use
`Status` can be used uninitialized:

    /* Evaluates to FALSE */
    if (ShellGetExecutionBreakFlag ()) {
        Status = EFI_ABORTED;
        break;
    }

    /* Evaluates to FALSE */
    if (!Context->ContentDownloaded && !Context->ResponseToken.Event) {
        Status = ...;
        ASSERT_EFI_ERROR (Status);
    } else {
        ResponseMessage.Data.Response = NULL;
    }

    /* UNINITIALIZED USE */
    if (EFI_ERROR (Status)) {
        break;
    }

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-19 01:39:49 +00:00
42ec0a315b MdeModulePkg: Retrieve boot manager menu from any fv
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384

Currently, UefiBootManagerLib has the below assumption:
  Assume the BootManagerMenuFile is in the same FV as the module links to this library.
It has some limitation now, so remove the assumption.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2021-05-18 13:52:06 +00:00
29e300ff81 UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation
5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-05-18 08:07:57 +00:00
1fbf5e30ae IntelFsp2Pkg: YAML script bug fix
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3395

This patch fixes the issue observed during
BSF file to YAML file conversion. It also
addresses the issue during multibyte array
data conversion check, for example the data
representation of 0xFFFF instead of 0xFF, 0xFF
would be thrown exception "Array size is not
proper" without this patch.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-05-18 00:46:45 +00:00
d2e0c473e6 BaseTools: Add DTCPP_FLAGS for GCC5 RISCV64 toolchain
Some/all platforms are going to require EDK2 to build a device tree and
use it in the early stages of boot.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-05-17 04:22:20 +00:00
9cd854e19d BaseTools/Brotli: Fix compressed data loss issue
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2946

Currenly, when using the Brotli tool to compress data, the output
compressed binary file does not record complete compressed data
when size of input file is too large, which makes the data loss and
will trigger decompress-check issue.

The Brotli document mentioned:
The brotli tool use BrotliEncoderCompressStream method to compresses
input stream to output stream. Under some circumstances (e.g. lack of
output stream capacity) the BrotliEncoderOperation would require
several calls to BrotliEncoderCompressStream. The method must be
called again until both input stream is depleted and encoder has no
more output after the method is called.

This patch fixes this issue based on the Brotli document.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-05-17 03:45:13 +00:00
e0cb5e1814 MdeModulePkg: Fix various typos
Fix various typos throughout MdeModulePkg.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-05-17 02:10:31 +00:00
32928415e3 UefiCpuPkg/CpuExceptionHandler: Add missing comma to exception name array
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3373

An update to expand the mExceptionNameStr array failed to add a comma
after original last entry, therefore causing the #CP name to have extra
incorrect characters and the remaining entries to be indexed incorrectly
(off by 1).

Add a comma after the "#CP" entry to resolve this issue.

Fixes: 5277540e37
Cc: Allen Wynn <Allen_Wynn@Dell.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <40e55bf6563ed8ea4962a1219efbe1ab77a56cc4.1620919615.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-05-14 11:26:17 +00:00
d82c4693f8 OvmfPkg/VirtioFsDxe: suppress incorrect gcc warnings
`CreateDirectoryIfCreating` is used only if `PermitCreation` is set.

`NewNodeIsDirectory` might not set in case of error, but that would lead
to leaving the function before invalid use.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Message-Id: <20210511225616.5942-3-sergei@posteo.net>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-05-14 10:00:13 +00:00
eec44cdd00 ShellPkg/UefiShellCommandLib: suppress incorrect gcc warning
`Dupes` is used only if `Duplicates != NULL` and function is left if
allocation of memory for `Dupes` fails, so it can't be used
uninitialized.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
Message-Id: <20210511225616.5942-2-sergei@posteo.net>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-05-14 10:00:13 +00:00
22ac5cc9d9 CryptoPkg: BaseCryptLib: Add RSA PSS verify support
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3314

This patch uses Openssl's EVP API's to perform RSASSA-PSS verification
of a binary blob.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2021-05-14 03:35:33 +00:00
5531fd48de BaseTools: Add support for version 3 of FMP Image Header structure
Add support for the ImageCapsuleSupport field, introduced in version 3
of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This
structure member is used to indicate if the corresponding payload has
support for authentication and dependency.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-05-12 01:03:53 +00:00
6933c78e4d UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385

A VS2012 build fails with a cast conversion warning when the SEV-ES work
area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.

When casting from a PCD value to a pointer, the cast should first be done
to a UINTN and then to the pointer. Update the code to perform a cast to
a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Fixes: 7b7508ad78
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <c89bc819856d448360430c32cb3833a9667f987b.1620656694.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-05-11 17:45:40 +00:00
4e5ecdbac8 SecurityPkg: Add support for RngDxe on AARCH64
AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.

Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-05-11 16:26:05 +00:00
9301e5644c MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions
Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that is a part of FEAT_RNG.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-05-11 16:26:05 +00:00
ef3840c1ff BaseTools: Fix DSC override of Guided tool
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

If the DSC file provides an override of a Guided tool path
and/or Guided tool GUID value, then make sure the one from the
DSC file is used if it is higher priority than the Guided tool
in the tools_def.txt file.  This makes the Guided tool used by
GenFds match the tool listed GuidedSectionTools.txt.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-05-10 23:28:58 +00:00
375f2d8e68 ArmPkg: Update SCMI Base Protocol version to 0x20000
The SCP-firmware has moved to full support for SCMIv2 which means that
the base protocol can be either compliant with SCMI v1 or v2.

Allow any version between SCMI v1.0 and SCMI v2.0 to be compatible
with the current implementation.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Tested-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-05-10 15:46:42 +00:00
f297b7f200 UnitTestFrameworkPkg: Sample unit test hangs when running in OVMF/QEMU
Sample unit tests in UnitTestFrameworkPkg hangs when running in OVMF/QEMU
environment. Build target is X64/GCC5. Fixing this issue by adding EFIAPI
to ReportPrint() function that use VA_ARGS.

Signed-off-by: Getnat Ejigu <getnatejigu@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2021-05-04 00:51:20 +00:00
8c8f49f0dc BaseTools: Fix New Target/ToolChain/Arch in DSC [BuildOptions] issues
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

* Save/Restore global state in GetToolChainAndFamilyFromDsc()
  This resolves an issue where the multi-arch build for
  UefiPayloadPkg would skip the autogen and build of IA32
  components.
* Expand tools wildcard.
  This resolves the issue where autogen makefile contents
  would have a BUIDLRULEFAMILY tools definitions with an
  '*' in the tool field that breaks the build from invalid
  makefile syntax.
* Build rule family higher priority than Family.
  This resolves the issue where flags were appended from
  both the BUILDRULEFAMILY and FAMILY when only
  BUILDRULEFAMILY should be appended when present.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Steven Shi <steven.shi@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Andrew Fish <afish@apple.com>
2021-05-03 18:16:23 +00:00
1e6b0394d6 OvmfPkg/Tcg2ConfigPei: Update Depex for IA32 and X64
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

The OVMF Tcg2Config PEIM adds the gOvmfTpmMmioAccessiblePpiGuid as a
Depex for IA32 and X64 builds so that the MMIO range is properly mapped
as unencrypted for an SEV-ES guest before the Tcg2Config PEIM is loaded.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <d6538e6c557173d260e272a0e5659683175e2e06.1619716333.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-30 18:35:50 +00:00
8e7edbbf5d OvmfPkg/TpmMmioSevDecryptPei: Mark TPM MMIO range as unencrypted for SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

During PEI, the MMIO range for the TPM is marked as encrypted when running
as an SEV guest. While this isn't an issue for an SEV guest because of
the way the nested page fault is handled, it does result in an SEV-ES
guest terminating because of a mitigation check in the #VC handler to
prevent MMIO to an encrypted address. For an SEV-ES guest, this range
must be marked as unencrypted.

Create a new x86 PEIM for TPM support that will map the TPM MMIO range as
unencrypted when SEV-ES is active. The gOvmfTpmMmioAccessiblePpiGuid PPI
will be unconditionally installed before exiting. The PEIM will exit with
the EFI_ABORTED status so that the PEIM does not stay resident. This new
PEIM will depend on the installation of the permanent PEI RAM, by
PlatformPei, so that in case page table splitting is required during the
clearing of the encryption bit, the new page table(s) will be allocated
from permanent PEI RAM.

Update all OVMF Ia32 and X64 build packages to include this new PEIM.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <42794cec1f9d5bc24cbfb9dcdbe5e281ef259ef5.1619716333.git.thomas.lendacky@amd.com>
[lersek@redhat.com: refresh subject line]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-30 18:35:50 +00:00
a3f12cd471 OvmfPkg: Define a new PPI GUID to signal TPM MMIO accessability
Define a new PPI GUID that is to be used as a signal of when it is safe
to access the TPM MMIO range. This is needed so that, when SEV is active,
the MMIO range can be mapped unencrypted before it is accessed.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <03e292339273721724c8b14605cfe9d7bbe45a71.1619716333.git.thomas.lendacky@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-30 18:35:50 +00:00
cc71bd9709 OvmfPkg/VmgExitLib: Add support for new MMIO MOV opcodes
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

Enabling TPM support results in guest termination of an SEV-ES guest
because it uses MMIO opcodes that are not currently supported.

Add support for the new MMIO opcodes (0xA0 - 0xA3), MOV instructions which
use a memory offset directly encoded in the instruction. Also, add a DEBUG
statement to identify an unsupported MMIO opcode being used.

Fixes: c45f678a1e
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <2fdde57707b52ae39c49341c9d97053aaff56e4a.1619716333.git.thomas.lendacky@amd.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2021-04-30 18:35:50 +00:00
75d1a7903d OvfmPkg/VmgExitLib: Properly decode MMIO MOVZX and MOVSX opcodes
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345

The MOVZX and MOVSX instructions use the ModRM byte in the instruction,
but the instruction decoding support was not decoding it. This resulted
in invalid decoding and failing of the MMIO operation. Also, when
performing the zero-extend or sign-extend operation, the memory operation
should be using the size, and not the size enumeration value.

Add the ModRM byte decoding for the MOVZX and MOVSX opcodes and use the
true data size to perform the extend operations. Additionally, add a
DEBUG statement identifying the MMIO address being flagged as encrypted
during the MMIO address validation.

Fixes: c45f678a1e
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <5949d54cb2c9ab69256f67ed5654b32654c0501c.1619716333.git.thomas.lendacky@amd.com>
2021-04-30 18:35:50 +00:00
ab957f036f BaseTools/Source/Python: New Target/ToolChain/Arch in DSC [BuildOptions]
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359

Update BaseTools to support new build targets, new tool chains,
and new architectures declared in DSC file [BuildOptions] sections.

* Do not expand * when tools_def.txt is parsed.  Only expand when
  both tools_def.txt and DSC [BuilsOptions] sections have been parsed.
  This also requires more flexible matching of tool keys that contain *
  in tool key fields.

* Pre-scan the platform DSC file for FAMILY and TOOLCHAIN declarations
  DSC in [BuildOptions] sections before the FAMILY and TOOLCHAIN need
  to be known.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-29 07:29:17 +00:00
612edbe6cd EmulatorPkg: Temp remove IA32 GCC CI builds
EmulatorPkg IA32 GCC builds are not working due to a failure
to install the i386 library dependencies in Ubuntu 18.04.

Temporarily disable these specific CI tests until the issue
can be resolved.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-04-29 05:38:20 +00:00
01c0ab90be AzurePipelines: Add support for ArmPlatformPkg
Add an entry to build the ArmPlatformPkg in the CI.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3349
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
7c4f05dc05 AzurePipelines: Add support for ArmPkg
Add an entry to build the ArmPkg in the CI.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3348
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
ec9683ec0f .pytool: Document LicenseCheck and EccCheck
Add an entry in the documentation for the LicenseCheck and
EccCheck plugins.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
a4cf19597f .pytool: Enable CI for ArmPlatformPkg
Enable the CI for the ArmPlatformPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
2942cb5815 .pytool: Enable CI for ArmPkg
Enable the CI for the ArmPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
1cb1087749 ArmPlatformPkg: Add ArmPlatformPkg.ci.yaml
Add ArmPlatformPkg.ci.yaml to configure the CI for the
ArmPlatformPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
f11252e9fd ArmPkg: Add ArmPkg.ci.yaml
Add ArmPkg.ci.yaml to configure the CI for the
ArmPkg.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
b8de64bede ArmPkg: Correct small typos
The 'cspell' CI test detected some small typos in ArmPkg.
Correct them.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
c2bd8a1a82 ArmPkg: Add OemMiscLibNull library to ArmPkg.dsc
Add the OemMiscLibNull library to the [Components] section of
ArmPkg.dsc, allowing to complete the 'DscCompleteCheck' CI test.

According to .pytool/Readme about the 'DscCompleteCheck' test:
The test considers it an error if any INF does not appear in the
`Components` section of the package-level DSC.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
a145d5f240 ArmPkg: Re-order libraries in ArmPkg.dec
This patch alphabetically orders libraries advertised in ArmPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
2021-04-28 12:03:51 +00:00
3093c95de8 ArmPkg: Document libraries in ArmPkg.dec
This patch documents the libraries advertised in ArmPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
2021-04-28 12:03:51 +00:00
ecfe47968e ArmPlatformPkg: Document libraries in ArmPlatformPkg.dec
This patch documents the libraries advertised in ArmPlatformPkg.dec.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
d03f71dd8b ArmPkg: Add missing library headers to ArmPkg.dec
Some library headers are missing/incorrect in ArmPkg.dec.
This makes the 'LibraryClassCheck' CI test fail. This patch
adds/corrects them.

According to .pytool/Readme about the 'LibraryClassCheck' test:
This test scans at all library header files found in the
`Library` folders in all of the package's declared include
directories and ensures that all files have a matching
LibraryClass declaration in the DEC file for the package.

Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3254
Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3258
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
fd9cc2052e ArmPkg: Fix Ecc error 3002 in StandaloneMmMmuLib
This patch fixes the following Ecc reported error:
Non-Boolean comparisons should use a compare operator
(==, !=, >, < >=, <=)

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
cc15a619a6 ArmPkg: Fix Ecc error 8003
This patch fixes the following Ecc reported error:
The #ifndef at the start of an include file should have
one postfix underscore, and no prefix underscore character

Some include guards have been modified to match the name of the
header file. Some comments have also been added on the closing
'#endif'.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-28 12:03:51 +00:00
5b90b8abb4 ArmPkg: Fix typo of Manufacturer in comment in SmbiosMiscDxe
'Manufacturer' was spelled wrongly in a comment in
MiscChassisManufacturerData.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-04-27 12:46:26 +00:00
13f32d4a64 ArmPkg: Fix calculation of offset of chassis SKU Number in SmbiosMiscDxe
The calculation of the chassis SKU number field was being calculated
incorrectly, forgetting that there's one element already present in
the structure.
Fix the calculation and improve code readability by introducing a
SkuNumberField variable.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-04-27 12:46:26 +00:00
bbeb1bea41 ArmPkg: Allow platforms to report their boot status via OemMiscLib call
Add a new function to OemMiscLib to allow platforms to report their boot
status into the Type32 SMBIOS table.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-04-27 12:46:26 +00:00
bf2b99990e ArmPkg: Allow platforms to supply more data for SMBIOS Type3 record
Add OemMiscLib calls to allow platforms to provide the following
information about the chassis:

o Bootup state
o Power supply/supplies state
o Thermal state
o Security state
o Chassis height (in RMU)
o Number of power cords

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-04-27 12:46:26 +00:00
8d2012035d BaseTools/GenMake: Sort generated makefile tool definitions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3353

Sort the tool definition content of generated makefiles to help
verify that makefile contents have not changed after BaseTools
code changes.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2021-04-27 05:56:39 +00:00
5396354b86 SecurityPkg: Add constraints on PK strength
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3293

Add constraints on the key strength of enrolled platform key(PK), which
must be greater than or equal to 2048 bit. PK key strength is required
by Intel SDL and MSFT, etc. This limitation prevents user from using
weak keys as PK.

The original code to check the certificate file type is placed in a new
function CheckX509Certificate(), which checks if the X.509 certificate
meets the requirements of encode type, RSA-Key strengh, etc.

Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>
Reviewed-by: Min Xu <min.m.xu@intel.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
2021-04-26 16:24:32 +00:00
f2f4c6be2d BaseTools/Source/Python: Verify TAB_TOD_DEFINES_FAMILY key present
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3344

Veify that TAB_TOD_DEFINES_FAMILY key is present in ToolDef
dictionary before access.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-23 18:55:51 +00:00
61680cac5e Maintainers.txt: Add 'Erdem Aktas' to Confidential Computing reviewers
Add 'Erdem Aktas' as a reviewer for OvmfPkg/Confidential Computing.

Signed-off-by: Erdem Aktas <erdemaktas@google.com>
Message-Id: <a557b66c92d3e44dcd02db7ee3800d1f9fef81b4.1619102863.git.erdemaktas@google.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Min M Xu <min.m.xu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-23 11:27:59 +00:00
d3b0d007a1 BaseTools: Add double quote around CLANG_BIN path string
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3341

Current CLANG_BIN env variable is set without double quote
around the LLVM default installation path string in windows,
which causes some CI build service cannot find the LLVM path
in windows.
This patch enhance it to add double quote around it.

Signed-off-by: Steven Shi <steven.shi@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-20 10:21:17 +00:00
0bbc207275 MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309

Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
(07h) data structure.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed: Ray Ni <ray.ni@intel.com>
2021-04-20 01:27:58 +00:00
c3dcbce26f UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3300

Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm
driver will check a global variable mPhysicalAddressBits, and eventually
cap any value larger than 39 at 39.

This global variable is used in ConvertMemoryPageAttributes, which backs
SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor
that supports more than 39 bits width, trying to mark page table regions
higher than 39-bit will always return EFI_UNSUPPROTED.

This change updated the interface of SetStaticPageTable function to take
PhysicalAddressBits as an input parameter, in order to avoid changing/
accessing the global variable.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Fixes: 4eee0cc7cc
Signed-off-by: Kun Qin <kuqin12@gmail.com>
2021-04-20 00:32:24 +00:00
64138c95db BaseTools/Conf/tools_def.template: Remove redundant MAKE statements
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3337

Remove redundant MAKE_PATH and MAKE_FLAGS statements for
VS20xx tool chains.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2021-04-19 18:06:50 +00:00
8c75a07208 DynamicTablesPkg: Set the Access size for the DBG2 table
The DBG2 table generator set the access size for the UART to
DWORD (4 bytes) by default. However, according to Section B
Generic UART, Arm Base System Architecture 1.0, Platform
Design Document, a Generic UART can have BYTE, WORD or DWORD
access sizes. To address this an AccessSize field has been
introduced in CM_ARM_SERIAL_PORT_INFO object.

This patch updates the DBG2 generator to setup the AccessSize
field in the Generic Address Structure (GAS) for the UART in
the DBG2 table with information provided by the platform.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-19 13:28:26 +00:00
a300f2a3f5 DynamicTablesPkg: Set the Access size for the SPCR table
The SPCR table generator set the access size for the UART to
DWORD (4 bytes) by default. However, according to Section B
Generic UART, Arm Base System Architecture 1.0, Platform
Design Document, a Generic UART can have BYTE, WORD or DWORD
access sizes. To address this an AccessSize field has been
introduced in CM_ARM_SERIAL_PORT_INFO object.

This patch updates the SPCR generator to setup the AccessSize
field in the Generic Address Structure (GAS) for the UART in
the SPCR table with information provided by the platform.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-19 13:28:26 +00:00
c8cf71ec9c DynamicTablesPkg: Add access size to CM_ARM_SERIAL_PORT_INFO
Add access size to CM_ARM_SERIAL_PORT_INFO so that this can be
passed down to the Generic Address Structure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-19 13:28:26 +00:00
10bf6c40f6 ShellPkg: Rename Address Size to Access size
This matches the ACPI spec 6.3, table 5.1: Generic Address Structure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-19 13:28:26 +00:00
99e7e48cc7 SecurityPkg/FvReportPei: remove redundant sizeof
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3333

In function InstallPreHashFvPpi, when calculating the size
of struct HASH_INFO, sizeof is used twice. This bug does
not lead to buffer overflow, "sizeof (HASH_INFO)" is 4,
whereas "sizeof (sizeof (HASH_INFO))" is 4 or 8.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-04-16 08:39:59 +00:00
9abc447b72 RedfishPkg: Add EDK2 Redfish Foundation diagrams
The Readme.md to delineate the EDK2 Redfish foundation driver
stack diagrams.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Fan Wang <fan.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2021-04-16 04:12:16 +00:00
96479947bc ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_PERFORMANCE
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
063f8483b9 ArmPkg: Fix Ecc error 8005 for SCMI_CLOCK_RATE_FORMAT
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
bd8efb4f8e ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_CLOCK
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
1f93d0c5a3 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_BASE
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
84262ca3d9 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
dc6c6397b8 ArmPkg: Fix Ecc error 8005 for SCMI_STATUS
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
68c1868565 ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_TYPE
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
462f95ec5b ArmPkg: Fix Ecc error 8005 for SCMI_PROTOCOL_ID
This patch fixes the following Ecc reported error:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
2f2c0a8b9f ArmPkg: Fix Ecc error 8005/8007 in ArmDisassemblerLib
This patch fixes the following Ecc reported error:
8005:
Variable name does not follow the rules:
1. First character should be upper case
2. Must contain lower case characters
3. No white space characters
4. Global variable name must start with a 'g'

8007:
There should be no use of short (single character) variable names

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
60e49aac4e ArmPkg: Fix Ecc error 7008 for OPTEE_MESSAGE_PARAM
This patch fixes the following Ecc reported error:
Complex types should be typedef-ed

The error is due to the a nested structure declaration.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
39b3e14c99 ArmPkg: Fix Ecc error 7008 for SCMI_CLOCK_RATE
This patch fixes the following Ecc reported error:
Complex types should be typedef-ed

The error is due to the a nested structure declaration.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
3c0c1d3fae ArmPkg: Rename include guard in ArmGicLib.h
Edk2 coding standard states that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
f21e72135d ArmPkg: Fix Ecc error 6001 in ArmSoftFloatLib
This patch fixes the following Ecc reported error:
All include file contents should be guarded by
a #ifndef statement.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
152015fa65 ArmPkg: Fix Ecc error 6001 in MmCommunicationDxe
This patch fixes the following Ecc reported error:
All include file contents should be guarded by
a #ifndef statement.

This patch replaces a "#if !defined [...]" statement
by a "#ifndef [...]" statement, preventing Ecc to
throw an error.

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
74b41d5648 ArmPkg: Fix Ecc error 5003 in ArmExceptionLib
This patch fixes the following Ecc reported error:
Function name should be left justified,
followed by the beginning of the parameter list,
with the closing parenthesis on its own line,
indented two spaces

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
22693153d1 ArmPkg: Remove ArmGic/ArmGicSecLib.c
Commit: 142fa386eb
removes the ArmGicSecLib. The file ArmGic/ArmGicSecLib.c
was exclusively used by this library. Thus, this file should
also be removed.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
11bd8e249f ArmPkg: Fix Ecc error 10014 in SemihostLib
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Library/SemihostLib/SemihostPrivate.h]
is existing in module
ArmPkg/Library/SemihostLib/SemihostLib.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
29bf905976 ArmPkg: Fix Ecc error 10014 in MmCommunicationDxe
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h]
is existing in module
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
a563c84779 ArmPkg: Fix Ecc error 10014 in GenericWatchdogDxe
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h]
is existing in module
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
but is not described in the INF file.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
d9f0b84c1d ArmPkg: Fix Ecc error 10014 in ArmScmiDxe
This patch fixes the following Ecc reported error:
No used module files found

The source files
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h]
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h]
[ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h]
are existing in module
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
but are not described in INF the file.

The patch also re-orders the files in the
[Sources.common] section.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
aec0ce7ca8 ArmPkg: Fix Ecc error 10016 in StandaloneMmMmuLib
This patch fixes the following Ecc reported error:
Module file has FILE_GUID collision with other
module file

The two .inf files with clashing GUID are:
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf

As ArmMmuBaseLib.inf is older than ArmMmuStandaloneMmLib.inf,
it has precedence.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
d892336899 ArmPkg: Fix Ecc error 10006 in ArmPkg.dsc
This patch fixes the following Ecc reported error:
There should be no unnecessary inclusion of library
classes in the INF file

This comes with the additional information:
The Library Class [BootLogoLib]
is not used in any platform
The Library Class [DxeServicesLib]
is not used in any platform
The Library Class [UefiBootManagerLib]
is not used in any platform
The Library Class [PeCoffExtraActionLib]
is not used in any platform

ArmPkg/ArmPkg.dsc builds the modules requiring thses libraries,
but doesn't build the required libraries. This patch adds
the missing libraries to the [LibraryClasses.common] section.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
ea61e597e1 ArmPkg: Fix Ecc error 9005 in CpuDxe
This patch fixes the following Ecc reported error:
Only Doxygen commands '@bug', '@todo', '@example', '@file',
'@attention', '@param', '@post', '@pre', '@retval', '@return',
'@sa', '@since', '@test', '@note', '@par', '@endcode', '@code',
'@{', '@}' are allowed to mark the code

This patch removes the ":" character following the "@param"
doxygen command.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
0fc54a6a55 ArmPkg: Fix Ecc error 8001 in ArmArchTimerLib
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used for #define
declarations

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
b9d4976998 ArmPkg: Fix Ecc error 8001 in SemihostLib
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
a4d95d7cf9 ArmPkg: Fix Ecc error 8001 in Chipset
This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard of ArmCortexA5x.h is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:53:39 +00:00
8948fb0974 ArmPlatformPkg: Remove package dependency in NorFlashStandaloneMm
The DependencyCheck available in .pytool detects an unnecessary
dependency of the NorFlashStandaloneMm.inf module over the
EmbeddedPkg package.
This patch removes this dependency.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Tested-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-04-15 19:24:14 +00:00
890e6d466c ArmPlatformPkg: Fix Ecc error 9001
This patch fixes the following Ecc reported error:
INF/DEC/DSC/FDF file header comment should begin
with "## @file" or "# @file" at the very top file

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:24:14 +00:00
5a5440d0dc ArmPlatformPkg: Fix Ecc error 8001
This patch fixes the following Ecc reported error:
File header doesn't exist File header comment missing
the ""Copyright""

Even though a copyright is present in the header file,
the leading '*' char prevents the Ecc tool from detecting it.
According to the edk2 coding specifcation, section 5.2.3
"File Heading", there should not be leading '*' char.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-15 19:24:14 +00:00
3c13938079 BaseTools/Source/Python: Remove CPU architecture assumptions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Remove build breaks in the following tools when a check against
a fixed set of CPU architectures is made.

* Build
* GenFds
* TargetTool

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-15 15:58:44 +00:00
251f9b3906 BaseTools/Source/C: Remove CPU architecture assumptions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Remove build breaks in the following tools when a check against
a fixed set of CPU architectures is made.

* GenFw

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-15 15:58:44 +00:00
d0bf83e1cc CryptoPkg/Library/Include: Allow CPU specific defines to be predefined
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assume a fixed set of CPU architectures.

Update SIXTY_FOUR_BIT and THIRTY_TWO_BIT defines in the
CryptoPkg to allow one of them to be predefined on the EDK II
build command line using /D flag or in DSC file [BuildOptions]
sections.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2021-04-15 15:58:44 +00:00
db2338af0d MdePkg/Include: Allow CPU specific defines to be predefined
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308

The EDK II Build Specifications do not restrict the set of
CPU architectures that can be supported.  Remove places in
the EDK II that assumes a fixed set of CPU architectures.

Update EFI_REMOVABLE_MEDIA_FILE_NAME to allow it to be
predefined in tools_def.txt or a DSC file [BuildOptions]
section using a *_*_*_CC_FLAGS statement.

Add support for the following two defines.  If neither are
defines, then preserve the current behavior.  If either is
defined, then compare these 16-bit values to Machine in the
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) and
EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) macros.

* EFI_IMAGE_MACHINE_TYPE_VALUE
* EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-15 15:58:44 +00:00
7cc8cd7b58 RedfishPkg/RestJsonStructureDxe: Fix typo in function header
In v2, BZ reference is added.

BZ#:3030
Fix the typo [in]/[out] of parameter DestroyStructure in
function header.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-04-15 07:33:32 +00:00
2ad22420a7 UnitTestFrameworkPkg: Use TianoCore mirror of cmocka repository
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3301

The cmocka repository https://git.cryptomilk.org/projects/cmocka.git
has gone down a few times in past year.  When it is down, it blocks
EDK II CI.  A mirror of this repository has been created in the
TianoCore organization at https://github.com/tianocore/edk2-cmocka.git
and uses a GitHub Action to auto-sync changes from
https://git.cryptomilk.org/projects/cmocka.git.

* Update .gitmodules to use https://github.com/tianocore/edk2-cmocka.git
  instead of https://git.cryptomilk.org/projects/cmocka.git.

* Update README.rst to reference the COPYING file in
  https://github.com/tianocore/edk2-cmocka.git with the cmocka license.

* Update Azure Pipelines YML files to remove a temporary workaround that
  used an alternate GitHub mirror of cmocka.  With the workaround removed,
  EDK II CI always uses the TianoCore mirror of cmocka.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-14 17:28:46 +00:00
c055be5b82 BaseTools/PlatformAutoGen: MAKE_FLAGS and MAKE_PATH fixes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3312

Update parsing of MAKE_FLAGS in DSC [BuildOptions] sections
to split the flags into a list to be compatible with
running the make command using Popen().  Parsing MAKE_FLAGS
from tools_def.txt already uses _SplitOption().  This change
uses the same _SplitOption() method for MAKE_FLAGS from a
DSC [BuildOptions] section.

Also update the parsing of MAKE_PATH to support MAKE_PATH
from tools_def.txt or the DSC [BuildOptions] section.  MAKE_PATH
in DSC [BuildOptions] section is higher priority than MAKE_PATH
in tools_def.txt.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-04-14 16:28:41 +00:00
037090cb7c MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchain
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325

1. AsmReadMsr64() in X64/GccInlinePriv.c
AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead
returns False. This causes build error with the CLANG toolchain.

2. AsmWriteMsr64() in X64/GccInlinePriv.c
In the case that FilterBeforeMsrWrite changes Value and returns True,
The original Value, not the changed Value, is written to the MSR.
This behavior is different from the one of AsmWriteMsr64() in
X64/WriteMsr64.c for the MSFT toolchain.

Signed-off-by: Takuto Naito <naitaku@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-14 01:50:19 +00:00
83876950ab DynamicTablesPkg: Remove EArmObjExtendedInterruptInfo
The EArmObjExtendedInterruptInfo doesn't exist. Remove any reference
to this enum.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-13 14:14:49 +00:00
cc00dbcb19 DynamicTablesPkg: Re-order GicItsIdentifierArray struct
The structure is not correctly placed in the file. Move it
so it follows the EARM_OBJECT_ID enum order.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-13 14:14:49 +00:00
71cdb91f31 OvmfPkg/OvmfXen: Set PcdFSBClock
Update gEfiMdePkgTokenSpaceGuid.PcdFSBClock so it can have the correct
value when SecPeiDxeTimerLibCpu start to use it for the APIC timer.

Currently, nothing appear to use the value in PcdFSBClock before
XenPlatformPei had a chance to set it even though TimerLib is included
in modules run before XenPlatformPei.

XenPlatformPei doesn't use any of the functions that would use that
value. No other modules in the PEI phase seems to use the TimerLib
before PcdFSBClock is set. There are currently two other modules in
the PEI phase that needs the TimerLib:
- S3Resume2Pei, but only because LocalApicLib needs it, but nothing is
  using the value from PcdFSBClock.
- CpuMpPei, but I believe it only runs after XenPlatformPei

Before the PEI phase, there's the SEC phase, and SecMain needs
TimerLib because of LocalApicLib. And it initialise the APIC timers
for the debug agent. But I don't think any of the DebugLib that
OvmfXen could use are actually using the *Delay functions in TimerLib,
and so would not use the value from PcdFSBClock which would be
uninitialised.

A simple runtime test showed that TimerLib doesn't use PcdFSBClock
value before it is set.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-8-anthony.perard@citrix.com>
[lersek@redhat.com: cast Freq to UINT32 for PcdSet32S(), not for ASSERT()]
2021-04-13 11:54:58 +00:00
c75c640512 OvmfPkg/XenPlatformPei: Calibrate APIC timer frequency
Calculate the frequency of the APIC timer that Xen provides.

Even though the frequency is currently hard-coded, it isn't part of
the public ABI that Xen provides and thus may change at any time. OVMF
needs to determine the frequency by an other mean.

Fortunately, Xen provides a way to determines the frequency of the
TSC, so we can use TSC to calibrate the frequency of the APIC timer.
That information is found in the shared_info page which we map and
unmap once done (XenBusDxe is going to map the page somewhere else).

The shared_info page is mapped at the highest physical address allowed
as it doesn't need to be in the RAM, thus there's a call to update the
page table.

The calculated frequency is only logged in this patch, it will be used
in a following patch.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-7-anthony.perard@citrix.com>
2021-04-13 11:54:58 +00:00
51e0bd28bb OvmfPkg/XenPlatformPei: Map extra physical address
Some information available in a Xen guest can be mapped anywhere in
the physical address space and they don't need to be backed by RAM.
For example, the shared info page.

While it's easier to put those pages anywhere, it is better to avoid
mapping it where the RAM is. It might split a nice 1G guest page table
into 4k pages and thus reducing performance of the guest when it
accesses its memory. Also mapping a page like the shared info page and
then unmapping it or mapping it somewhere else would leave a hole in
the RAM that the guest would propably not be able to use anymore.

So the patch introduces a new function which can be used to 1:1
mapping of guest physical memory above 4G during the PEI phase so we
can map the Xen shared pages outside of memory that can be used by
guest, and as high as possible.

Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-6-anthony.perard@citrix.com>
2021-04-13 11:54:58 +00:00
9d6861494a OvmfPkg/IndustryStandard: Introduce PageTable.h
We are going to use the page table structure in yet another place,
collect the types and macro that can be used from another module
rather than making yet another copy.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <20210412133003.146438-5-anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-13 11:54:58 +00:00
896e689841 OvmfPkg/IndustryStandard/Xen: Apply EDK2 coding style to XEN_VCPU_TIME_INFO
We are going to use new fields from the Xen headers. Apply the EDK2
coding style so that the code that is going to use it doesn't look out
of place.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-4-anthony.perard@citrix.com>
2021-04-13 11:54:58 +00:00
44ad51d6b1 MdePkg: Allow PcdFSBClock to by Dynamic
We are going to want to change the value of PcdFSBClock at run time in
OvmfXen, so move it to the PcdsDynamic section.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-3-anthony.perard@citrix.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-13 11:54:58 +00:00
29280c7084 OvmfPkg/XenResetVector: Silent a warning from nasm
To avoid nasm generating a warning, replace the macro by the value
expected to be stored in eax.
  Ia32/XenPVHMain.asm:76: warning: dword data exceeds bounds

Reported-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210412133003.146438-2-anthony.perard@citrix.com>
2021-04-13 11:54:58 +00:00
16136f218d DynamicTablesPkg: add validation for PcdNonBsaCompliant16550SerialHid
According to ACPI 6.4, 6.1.5 _HID states:

  - A valid PNP ID must be of the form "AAA####" where A is an uppercase
    letter and # is a hex digit.
  - A valid ACPI ID must be of the form "NNNN####" where N is an uppercase
    letter or a digit ('0'-'9') and # is a hex digit.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-04-13 10:38:14 +00:00
54211ab10f SecurityPkg/Tcg2Smm: Initialize local Status variable
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3277

Initializes the Status variable in TcgMmReadyToLock().

Fixes a Clang build failure:
Tcg2Smm.c - SecurityPkg\Tcg\Tcg2Smm\Tcg2Smm.c:254:7: error:
variable 'Status' is used uninitialized whenever 'if'
condition is false [-Werror,-Wsometimes-uninitialized]

Initializing this variable is required to address a practical
scenario in which the return value of TcgMmReadyToLock() is
undefined based on conditional evaluation in the function.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Kun Qin <kun.q@outlook.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-04-13 01:57:43 +00:00
f8e6bcb6e7 MdeModulePkg: Initialize temp variable in VarCheckPolicyLib
DumpVariablePolicy() will return EFI_INVALID_PARAMETER if the Buffer
pointer is NULL and the indirect Size is anything but 0. Since this
TempSize was not being initialized it is very likely that this sequence
would not return the total buffer size as expected.

Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=3310

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-13 01:24:13 +00:00
4b59b22fed BaseTools/Conf: Fix MAKE_FLAGS typos in tools_def.template
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3313

Change MAKE_FLAG to MAKE_FLAGS to match required name from
EDK II Build Specifications for VS20xx tool chains.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2021-04-12 18:51:29 +00:00
a7d8e28b29 UefiCpuPkg: PiSmmCpuDxeSmm: Check buffer size before accessing
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3283

Current SMM Save State routine does not check the number of bytes to be
read, when it comse to read IO_INFO, before casting the incoming buffer
to EFI_SMM_SAVE_STATE_IO_INFO. This could potentially cause memory
corruption due to extra bytes are written out of buffer boundary.

This change adds a width check before copying IoInfo into output buffer.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210406195254.1018-2-kuqin12@gmail.com>
2021-04-12 17:23:54 +00:00
2072c22a0d RedfishPkg/RedfishConfigHandler: EDKII RedfishConfigHandler Protocol
BZ:2919

The driver is used to manage EDK2 Redfish Configuration Handler
Protocol installed by EDK2 Redfish feature drivers.
This is the EDK2 Redfish client driver written based on the EDK2
Redfish foundation to initialize EDK2 Redfish feature drivers.

EDK2 Redfish feature drivers are used to provision/consume/update
the firmware owns Redfish properties during system power on
initialization.

RedfishConfigHandlerCommon.c has the common code for the driver
instances used in different EDK2 boot phases or used by different
driver models in the future contribution.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Fan Wang <fan.wang@intel.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-04-12 07:40:31 +00:00
7e7b729f6c RedfishPkg/RedfishDiscoverDxe: EFI Redfish Discover Protocol
BZ#:2906
EDK2 EFI Redfish Discover Protocol implementation. Refer to UEFI
spec 2.9 section 31.1.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Fan Wang <fan.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-04-12 07:02:23 +00:00
5eb2de2d98 UefiCpuPkg/CpuTimerLib: Update LIBRARY_CLASS of Base instance.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2832

Update LIBRARY_CLASS of BaseCpuTimerLib to remove the usage limitation,
otherwise the Base instance cannot be used in some types of modules.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-04-12 03:20:24 +00:00
97336fdee4 ShellPkg: Fix smbiosview system enclosure type table
The SystemEnclosureTypeTable in QueryTable.c contained a couple
of errors: value 0x10 is "Lunch Box" not "Main Server Chassis", and
the Sub Notebook value was repeated as 0x13 when that entry is for
"SubChassis". The entries in-between needed adjusted.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2021-04-12 02:19:39 +00:00
efa7f4df0f UefiCpuPkg/PiSmmCpuDxeSmm: Support detect SMM shadow stack overflow
Use SMM stack guard feature to detect SMM shadow stack overflow.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3280

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Roger Feng <roger.feng@intel.com>
2021-04-09 05:33:35 +00:00
bce0328431 UefiCpuPkg/MpInitLib: Consume MicrocodeLib to remove duplicated code
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-04-09 01:43:18 +00:00
83c7f8178b UefiPayloadPkg/UefiPayloadPkg.dsc: Consume MicrocodeLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
2021-04-09 01:43:18 +00:00
030f71dfc4 OvmfPkg: Add MicrocodeLib in DSC files.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
2021-04-09 01:43:18 +00:00
1a957f17bc UefiCpuPkg: Add MicrocodeLib for loading microcode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-04-09 01:43:18 +00:00
19d5bccc76 UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2832

1. Remove PEI instance(PeiCpuTimerLib).
PeiCpuTimerLib is currently designed to save time by getting CPU TSC
frequency from Hob. BaseCpuTimerLib is designed to calculate TSC frequency
by using CPUID[15h] each time.
The time it takes to find CpuCrystalFrequencyHob (about 2000ns) is much
longer than it takes to calculate TSC frequency with CPUID[15h] (about
450ns), which means using BaseCpuTimerLib to trigger a delay is more
accurate than using PeiCpuTimerLib, recommend to use BaseCpuTimerLib
instead of PeiCpuTimerLib.

2. Remove DXE instance(DxeCpuTimerLib).
DxeCpuTimerLib is designed to calculate TSC frequency with CPUID[15h] in
its constructor function, then save it in a global variable. For this
design, once the driver containing this instance is running, this
constructor function is called, it will take extra time to calculate TSC
frequency.
The time it takes to get TSC frequency from global variable is shorter
than it takes to calculate TSC frequency with CPUID[15h], but 450ns is a
short time, the impact on the platform is very limited.
In addition, in order to simplify the code, recommend to use
BaseCpuTimerLib instead of DxeCpuTimerLib.

I did some experiments on one server platform and collected following data:
1. Average time required to find CpuCrystalFrequencyHob: about 2000 ns.
2. Average time required to find the last Hob: about 2700 ns.
2. Average time required to calculate TSC frequency: about 450 ns.

Reference code:
    //
    // Calculate average time required to find Hob.
    //
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - GetFirstGuidHob (1000 cycles)\n"));
    Ticks1 = AsmReadTsc();
    for (i = 0; i < 1000; i++) {
      GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);
    }
    Ticks2 = AsmReadTsc();

    if (GuidHob == NULL) {
      DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - CpuCrystalFrequencyHob can not be found!\n"));
    } else {
      DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - Average time required to find Hob = %d ns\n", \
          DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));
    }

    //
    // Calculate average time required to calculate CPU frequency.
    //
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - CpuidCoreClockCalculateTscFrequency (1000 cycles)\n"));
    Ticks1 = AsmReadTsc();
    for (i = 0; i < 1000; i++) {
      Freq = CpuidCoreClockCalculateTscFrequency ();
    }
    Ticks2 = AsmReadTsc();
    DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]  - Average time required to calculate TSC frequency = %d ns\n", \
        DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-04-09 01:00:22 +00:00
dc4d42302c MdePkg/Baseib: Filter/trace MSR access for IA32/X64
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-04-08 02:02:57 +00:00
38c8be123a MdePkg/IoLib: Filter/trace port IO/MMIO access
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-04-08 02:02:57 +00:00
9c08b3e7d5 MdeModulePkg/PiDxeS3BootScriptLib: Rename mAcpiS3Enable to avoid dup symbol
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3297

Rename the global variable mAcpiS3Enable to mS3BootScriptAcpiS3Enable
to avoid duplicate symbol errors from CLANGPDB tool change when
PiDxeS3BootScriptLib from the MdeModulePkg is linked with PiSmmCpuDxeSmm
from the UefiCpuPkg.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-04-07 16:10:59 +00:00
4ac0296201 MdePkg/BaseLib: Add support for the XSETBV instruction
*v2: refine the coding format.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.

Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509ab

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-06 00:43:49 +00:00
f95cdd316c CryptoPkg: Simplify DSC by using UnitTestFrameworkPkgTarget.dsc.inc
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3288

Simplify the DSC file by using the library mappings from
UnitTestFrameworkPkgTarget.dsc.inc to build the CryptoPkg
target based unit tests that run from the UEFI Shell.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-04-03 01:54:22 +00:00
8c89229885 CryptoPkg/Private/Protocol/Crypto.h: Remove duplicate function type
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3287

Remove duplicate declaration of the function prototype
EDKII_CRYPTO_RSA_GET_PUBLIC_KEY_FROM_X509.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-01 23:16:31 +00:00
8c10a2c014 MdePkg/Include/Protocol: EFI_RESET_NOTIFICATION_PROTOCOL duplicate
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3286

Remove duplicate declaration of structure type
EFI_RESET_NOTIFICATION_PROTOCOL from ResetNotification.h.  The
forward declaration of the top of this file already declared
this type.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-01 23:16:31 +00:00
32976569af MdePkg/Include/Protocol: EFI_HII POPUP_PROTOCOL duplicate declaration
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3285

Remove duplicate declaration of structure type
EFI_HII_POPUP_PROTOCOL from HiiPopup.h.  The forward
declaration of the top of this file already declared
this type.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-04-01 23:16:31 +00:00
62bad17dca UnitTestFrameworkPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
08c65f7c4d UefiPayloadPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
2021-03-31 05:47:10 +00:00
3c3a0dd9d7 UefiCpuPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
349cd45b5f StandaloneMmPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-03-31 05:47:10 +00:00
42a492fb3e SourceLevelDebugPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-03-31 05:47:10 +00:00
df79bfb87b SignedCapsulePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
25b77b5090 ShellPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
0d03ffc766 SecurityPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-03-31 05:47:10 +00:00
d2263c06c9 RedfishPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
2021-03-31 05:47:10 +00:00
389b3b83e4 PcAtChipsetPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
d4ab7201f2 OvmfPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
d04b47962d NetworkPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
821e042f42 MdePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
e0df328f6f MdeModulePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-03-31 05:47:10 +00:00
2b46d175cb IntelFsp2WrapperPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-03-31 05:47:10 +00:00
2ee287b9fd IntelFsp2Pkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2021-03-31 05:47:10 +00:00
8e03191dde FmpDevicePkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
8cb0edc689 FatPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
991c898775 EmulatorPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
edc37612f7 EmbeddedPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
e2158c4a09 DynamicTablesPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-03-31 05:47:10 +00:00
ae25aeaf55 CryptoPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2021-03-31 05:47:10 +00:00
c8a5d99302 ArmVirtPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-31 05:47:10 +00:00
96afc54688 ArmPlatformPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-03-31 05:47:10 +00:00
83d4afa4db ArmPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2021-03-31 05:47:10 +00:00
98ff7e3c63 MdePkg: Add MdeLibs.dsc.inc file to MdePkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc is added for some default libraries provided by MdePkg.
Platform can include MdeLibs.dsc.inc file to avoid some potential
incompatible changes to platform dsc file in future.

Only add RegisterFilterLib into it as the first version of MdeLibs.dsc.inc.
Can update and maintain MdeLibs.dsc.inc gradually later.

"MdeLibs.dsc.inc" for the [LibraryClasses*] section(s)

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-30 12:48:30 +00:00
1c11e7a214 MdePkg: Add RegisterFilterLib class and NULL instance
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

1. Add a new library class (RegisterFilterLib) to filter
and trace port IO/MMIO/MSR access.
2. Add a NULL instance (RegisterFilterLibNull) can be used
to keep current behavior.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
2021-03-30 12:48:30 +00:00
b33cf5bfcb ShellPkg/UefiHandleParsingLib: Support EFI Redfish protocols
Add handle parsing for EFI Redfish Discover protocol.
Add handle parsing for EFI RestEx protocol.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Peter O'Hanley <peter.ohanley@hpe.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-26 02:56:22 +00:00
fe66288873 MdePkg/Include: EFI Redfish Discover protocol
Move GUID definition of EFI Redfish Discover protocol
to under MdePkg. With this we don't have dependency of
RedfishPkg in ShellPkg.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Cc: Peter O'Hanley <peter.ohanley@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-26 02:56:22 +00:00
4bf2a5b045 MdePkg: use CpuPause() in CpuDeadLoop()
CpuPause() might allow the CPU to go into a lower power state
state while we spin.

On X86, CpuPause() executes a PAUSE instruction which the Intel
and AMD specs describe as follows:

Intel:
  "PAUSE: An additional function of the PAUSE instruction is to reduce
  the power consumed by a processor while executing a spin loop. A
  processor can execute a spin-wait loop extremely quickly, causing the
  processor to consume a lot of power while it waits for the resource it
  is spinning on to become available. Inserting a pause instruction in a
  spin-wait loop greatly reduces the processor?s power consumption."

AMD:
  "PAUSE: Improves the performance of spin loops, by providing a hint to
  the processor that the current code is in a spin loop. The processor
  may use this to optimize power consumption while in the spin loop.
  Architecturally, this instruction behaves like a NOP instruction."

On RISC-V and ARM64, CpuPause() executes a NOP, which is no worse than
the tight loop we have.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-25 03:40:17 +00:00
30691a4b40 UefiCpuPkg/SmmCommunication: Remove out-dated comments
The comments in PiSmmCommunicationPei.c describe the whole memory
layout of the SMRAM regarding the SMM communication.

But SHA-1: 8b1d149390
PiSmmCommunicationSmm: Deprecate SMM Communication ACPI Table
removed the code that produces the ACPI Table.

This change updates the accordingly comments.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-25 02:34:29 +00:00
aa75965349 MdeModulePkg: Initialize local variable value before they are used
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
This change is to fix the false compiler error on GCC49 release build.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-25 01:54:46 +00:00
f037af6ecb OvmfPkg: strip build paths in release builds
GenFw will embed a NB10 section which contains the path to the input file,
which means the output files have build paths embedded in them.  To reduce
information leakage and ensure reproducible builds, pass --zero in release
builds to remove this information.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3256
Signed-off-by: Ross Burton <ross.burton@arm.com>
Message-Id: <20210324115819.605436-1-ross.burton@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-24 22:07:32 +00:00
0ecdcb6142 CryptoPkg/OpensslLib: Upgrade OpenSSL to 1.1.1j
Update openssl from 1.1.1g to 1.1.1j. Current OpenSSL version
1.1.1g contains the vulnerabilities of CVE-2021-23841 and
CVE-2021-23840. The related vulnerable API EVP_DecryptUpdate
are used in drivers.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3266

Besides, the opensslconf.h automatically generated by process_files.pl.
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Liu Wei <weix.c.liu@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2021-03-23 05:37:56 +00:00
3d0df0f076 ShellPkg/Pci: Add valid check for PCI extended config space parser
Bugzilla: 3262 (https://bugzilla.tianocore.org/show_bug.cgi?id=3262)

No need to print PCIe details while CapabilityId is 0xFFFF.
Limit the NextCapabilityOffset to PCI configuration space.

Signed-off-by: VincentX Ke <vincentx.ke@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2021-03-22 01:37:30 +00:00
ca31888271 OvmfPkg/X86QemuLoadImageLib: Handle allocation failure for CommandLine
The CommandLine and InitrdData may be set to NULL if the provided
size is too large. Because the zero page is mapped, this would not
cause an immediate crash but can lead to memory corruption instead.
This patch just adds validation and returns error if either allocation
has failed.

Signed-off-by: Martin Radev <martin.b.radev@gmail.com>
Message-Id: <YFPJsaGzVWQxoEU4@martin-ThinkPad-T440p>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
[lersek@redhat.com: drop unnecessary empty line from code; remove personal
 (hence likely unstable) repo reference from commit message]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-19 18:13:51 +00:00
eb07bfb09e Maintainers: rename the OVMF SEV subsystem to "Confidential Computing"
The implementation of Intel TDX for OVMF has begun (TianoCore#3249).
Generalize the OVMF SEV section in "Maintainers.txt" to "Confidential
Computing". Add Jiewen Yao and Min Xu to the list of reviewers. Sort the
reviewer list alphabetically, for easier extension in the future.

After the rename, restore the alphabetical ordering between subsystem
titles in "Maintainers.txt".

TDX-related pathnames should be listed in this subsystem (with "F:"
patterns) in the future.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3249
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210310185649.19801-3-lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: James Bottomley <jejb@linux.ibm.com>
Acked-by: Min Xu <min.m.xu@intel.com>
2021-03-18 17:12:02 +00:00
87a80dc4f2 Maintainers: refresh the OVMF SEV subsystem after TianoCore #2198 and #3077
Tom added initial SEV-ES support (tracked under TianoCore#2198) in commit
range 7f7f511c5a74..7f0b28415cb4. The last commit in that range created
the "OvmfPkg: SEV-related modules" section in "Maintainers.txt".

However, we didn't list the "OvmfPkg/ResetVector" module, which had
received significant updates, enabling QEMU to learn details about the
firmware, from parsing the flash image. The SEC phase of OVMF
("OvmfPkg/Sec") gained a new responsibility as well (#VC exception
handling). List both modules now.

James introduced the remote attested / encrypted boot OVMF platform (under
TianoCore#3077) in commit range ef3e73c6a0c0..01726b6d23d4. This work
further extended "OvmfPkg/ResetVector", and added:

  OvmfPkg/AmdSev/
  OvmfPkg/Include/Guid/ConfidentialComputingSecret.h
  OvmfPkg/Library/PlatformBootManagerLibGrub/

List these too in the "OvmfPkg: SEV-related modules" section, and
designate James as a reviewer.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3077
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210310185649.19801-2-lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: James Bottomley <jejb@linux.ibm.com>
Acked-by: Min Xu <min.m.xu@intel.com>
2021-03-18 17:12:02 +00:00
9fd7e88c23 MdePkg: Support standalone MM Driver Unload capability
https://bugzilla.tianocore.org/show_bug.cgi?id=3240

This patch is to support standalone MM Driver Unload capability
by providing _DriverUnloadHandler() function.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-18 04:16:21 +00:00
f9c53a69ed ShellPkg/SmbiosView: add more items for smbiosview -t 3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3177
Add ContainedElementCount, ContainedElementRecordLength and
ContainedElements for smbiosview type 3.

Signed-off-by: Mars CC Lin <mars_cc_lin@phoenix.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Philippe Mathieu-Daude <philmd@redhat.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2021-03-18 03:10:45 +00:00
ce6c2b0016 BaseTools/Ecc: Make Ecc only check first include guard
The Ecc tool checks the format of the include guard. This check is
currently done on all the names following the '#ifndef' statement.
It should only be done on the first include guard.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3252
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-03-18 02:04:18 +00:00
313d86c956 UefiCpuPkg/CpuDxe: Guarantee GDT is below 4GB
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3233

GDT needs to be allocated below 4GB in 64bit environment
because AP needs it for entering to protected mode.
CPU running in big real mode cannot access above 4GB GDT.

But CpuDxe driver contains below code:
  gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
  .....
  gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;

The AllocateRuntimePool() may allocate memory above 4GB.
Thus, we cannot use AllocateRuntimePool (), instead,
we should use AllocatePages() to make sure GDT is below 4GB space.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-18 01:11:23 +00:00
773b0bc283 UefiCpuPkg/CpuDxe: Rename variables to follow EDKII coding standard
The change doesn't impact any functionality.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-18 01:11:23 +00:00
030ba3097a UefiCpuPkg/MpInitLib: avoid printing debug messages in AP
MpInitLib contains a function MicrocodeDetect() which is called by
all threads as an AP procedure.
Today this function contains below code:

    if (CurrentRevision != LatestRevision) {
      AcquireSpinLock(&CpuMpData->MpLock);
      DEBUG ((
        EFI_D_ERROR,
        "Updated microcode signature [0x%08x] does not match \
        loaded microcode signature [0x%08x]\n",
        CurrentRevision, LatestRevision
        ));
      ReleaseSpinLock(&CpuMpData->MpLock);
    }

When the if-check is passed, the code may call into PEI services:
1. AcquireSpinLock
   When the PcdSpinTimeout is not 0, TimerLib
   GetPerformanceCounterProperties() is called. And some of the
   TimerLib implementations would get the information cached in
   HOB. But AP procedure cannot call PEI services to retrieve the
   HOB list.

2. DEBUG
   Certain DebugLib relies on ReportStatusCode services and the
   ReportStatusCode PPI is retrieved through the PEI services.
   DebugLibSerialPort should be used.
   But when SerialPortLib is implemented to depend on PEI services,
   even using DebugLibSerialPort can still cause AP calls PEI
   services resulting hang.

It causes a lot of debugging effort on the platform side.

There are 2 options to fix the problem:
1. make sure platform DSC chooses the proper DebugLib and set the
   PcdSpinTimeout to 0. So that AcquireSpinLock and DEBUG don't call
   PEI services.
2. remove the AcquireSpinLock and DEBUG call from the procedure.

Option #2 is preferred because it's not practical to ask every
platform DSC to be written properly.

Following option #2, there are two sub-options:
2.A. Just remove the if-check.
2.B. Capture the CurrentRevision and ExpectedRevision in the memory
     for each AP and print them together from BSP.

The patch follows option 2.B.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-17 12:39:31 +00:00
e4ff3773b7 UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Support collecting cache associative type in CpuCacheInfoLib.
This prevents the user from using additional code to obtain the
same information.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-17 11:27:39 +00:00
2e51b27fed MdePkg/UefiLib: Correct the arguments passed to IsLanguageSupported()
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3211

Correct the arguments passed to the IsLanguageSupported() function in
AddUnicodeString2() and LookupUnicodeString2() as expected by the function

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chandramohan Akula <chandramohan.akula@broadcom.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-17 01:42:43 +00:00
66a31de7ee EmbeddedPkg/PrePiHobLib: replace duplicate GUID
Currently there is a duplicate GUID shared by two INFs.
This rolls the INF for the PrePiHobLib.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2381
Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2021-03-16 20:41:18 +00:00
f3bdfc4186 OvmfPkg/SmmControl2Dxe: negotiate CPU hot-unplug
Advertise OVMF support for CPU hot-unplug and negotiate it
if QEMU requests the feature.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-11-ankur.a.arora@oracle.com>
[lersek@redhat.com: preserve the empty line between the ICH9_LPC_SMI_F_*
 group of macro definitions and the SCRATCH_BUFFER type definition]
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
f053288863 OvmfPkg/CpuHotplugSmm: do actual CPU hot-eject
Add logic in EjectCpu() to do the actual the CPU ejection.

On the BSP, ejection happens by first selecting the CPU via
its QemuSelector and then sending the QEMU "eject" command.
QEMU in-turn signals the remote VCPU thread which context-switches
the CPU out of the SMI handler.

Meanwhile the CPU being ejected, waits around in its holding
area until it is context-switched out. Note that it is possible
that a slow CPU gets ejected before it reaches the wait loop.
However, this would never happen before it has executed the
"AllCpusInSync" loop in SmiRendezvous().
It can mean that an ejected CPU does not execute code after
that point but given that the CPU state will be destroyed by
QEMU, the missed cleanup is no great loss.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-10-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: unneeded inner QemuSelector declaration in EjectCpu()
 triggers VS warning #4456 (local variable shadowed); remove it]
2021-03-16 13:21:46 +00:00
30c69d2cfa OvmfPkg/CpuHotplugSmm: add EjectCpu()
Add EjectCpu(), which handles the CPU ejection, and provides a holding
area for said CPUs. It is called via SmmCpuFeaturesRendezvousExit(),
at the tail end of the SMI handling.

Also UnplugCpus() now stashes QEMU Selectors of CPUs which need to be
ejected in CPU_HOT_EJECT_DATA.QemuSelectorMap. This is used by
EjectCpu() to identify CPUs marked for ejection.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-9-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
af9c77e151 OvmfPkg/SmmCpuFeaturesLib: call CPU hot-eject handler
Call the CPU hot-eject handler if one is installed. The condition for
installation is (PcdCpuMaxLogicalProcessorNumber > 1), and there's
a hot-unplug request.

The handler is called from SmmCpuFeaturesRendezvousExit(), which is
in-turn called at the tail-end of SmiRendezvous() after the BSP has
signalled an SMI exit via the "AllCpusInSync" loop.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-8-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
b6d5996706 OvmfPkg/SmmCpuFeaturesLib: init CPU ejection state
Init CPU_HOT_EJECT_DATA, which will be used to share CPU ejection
state between SmmCpuFeaturesLib (via PiSmmCpuDxeSmm) and CpuHotPlugSmm.

The init happens via SmmCpuFeaturesSmmRelocationComplete(), and so it
will run as part of the PiSmmCpuDxeSmm entry point function,
PiCpuSmmEntry(). Once inited, CPU_HOT_EJECT_DATA is exposed via
PcdCpuHotEjectDataAddress.

The CPU hot-eject handler (CPU_HOT_EJECT_DATA->Handler) is setup when
there is an ejection request via CpuHotplugSmm.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-7-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
8ade9d425a OvmfPkg: define CPU_HOT_EJECT_DATA
Define CPU_HOT_EJECT_DATA and add PCD PcdCpuHotEjectDataAddress, which
will be used to share CPU ejection state between OvmfPkg/CpuHotPlugSmm
and PiSmmCpuDxeSmm.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-6-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
15e6ae8ea4 OvmfPkg/CpuHotplugSmm: introduce UnplugCpus()
Introduce UnplugCpus() which maps each APIC ID being unplugged
onto the hardware ID of the processor and informs PiSmmCpuDxeSmm
of removal by calling EFI_SMM_CPU_SERVICE_PROTOCOL.RemoveProcessor().

With this change we handle the first phase of unplug where we collect
the CPUs that need to be unplugged and mark them for removal in SMM
data structures.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-5-ankur.a.arora@oracle.com>
2021-03-16 13:21:46 +00:00
2d92e052c3 OvmfPkg/CpuHotplugSmm: add Qemu Cpu Status helper
Add QemuCpuhpWriteCpuStatus() which will be used to update the QEMU
CPU status register. On error, it hangs in a similar fashion as
other helper functions.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-4-ankur.a.arora@oracle.com>
2021-03-16 13:21:46 +00:00
a752dd0746 OvmfPkg/CpuHotplugSmm: collect hot-unplug events
Process fw_remove events in QemuCpuhpCollectApicIds(), and collect APIC IDs
and QEMU CPU Selectors for CPUs being hot-unplugged.

In addition, we now ignore CPUs which only have remove set. These
CPUs haven't been processed by OSPM yet.

This is based on the QEMU hot-unplug protocol documented here:
  https://lore.kernel.org/qemu-devel/20201204170939.1815522-3-imammedo@redhat.com/

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Message-Id: <20210312062656.2477515-3-ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-16 13:21:46 +00:00
0cb242e336 OvmfPkg/CpuHotplugSmm: refactor hotplug logic
Refactor CpuHotplugMmi() to pull out the CPU hotplug logic into
ProcessHotAddedCpus(). This is in preparation for supporting CPU
hot-unplug.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Aaron Young <aaron.young@oracle.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3132
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210312062656.2477515-2-ankur.a.arora@oracle.com>
2021-03-16 13:21:46 +00:00
4751a48aeb RedfishPkg/Library: RedfishLib
EDK2 port of DMTF libredfish project. We clone the necessary files
from open source project libredfish (https://github.com/DMTF/
libredfish) tag v1.0.0 and revise it to incorporate with edk2
firmware code base.

The reason of cloning the necessary files instead of using extern
submodule of libredfish project:
libredfish as a C library which is executed under Windows and
Linux. It could be binded with other programming languages such as
java and python. The library uses curl library as the communication service with Redfish, which is not easy to be abstracted and
replaced with EFI specific protocols (e.g. EFI_REST_EX_PROTOCOL or
payload encode/decode library) and EFI data types. We had the
conversation with DMTF community and they think edk2 is a firmware
solution but not the programming language,
therefore they rejected to have edk2 as a binding to libredfish.
According to above, we decide to clone the necessary files from
libredfish modify it to incorporate with edk2.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Ting Ye <ting.ye@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Fan Wang <fan.wang@intel.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
2021-03-11 08:44:51 +00:00
54ba08c6b6 UefiCpuPkg/PiSmmCpu: Don't allocate Token for SmmStartupThisAp
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3199

When Token points to mSmmStartupThisApToken, this routine is called
from SmmStartupThisAp() in non-blocking mode due to
PcdCpuSmmBlockStartupThisAp == FALSE.

In this case, caller wants to startup AP procedure in non-blocking
mode and cannot get the completion status from the Token because there
is no way to return the Token to caller from SmmStartupThisAp().
Caller needs to use its specific way to query the completion status.

There is no need to allocate a token for such case so the 3 overheads
can be avoided:
1. Call AllocateTokenBuffer() when there is no free token.
2. Get a free token from the token buffer.
3. Call ReleaseToken() in APHandler().

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-11 01:44:51 +00:00
edd46cd407 UefiCpuPkg/SmmCpuFeaturesLib: Add Standalone MM support
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3218

Adds an INF for StandaloneMmCpuFeaturesLib, which supports building
the SmmCpuFeaturesLib code for Standalone MM. Minimal code changes
are made to allow reuse of existing code for Standalone MM.

The original INF file names are left intact (continue to use SMM
terminology) to retain backward compatibility with platforms that
use those INFs. Similarly, the pre-existing C file names are
unchanged to be consistent with the INF file names.

Note that all references in library source files to PiSmm.h have
been changed to PiMm.h for consistency.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Message-Id: <20210217213227.1277-6-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-08 18:07:32 +00:00
e542e05d4f UefiCpuPkg/SmmCpuFeaturesLib: Abstract PcdCpuMaxLogicalProcessorNumber
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3218

Adds a new function called GetCpuMaxLogicalProcessorNumber() to
return the number of maximum CPU logical processors (currently
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber).

This allows the the mechanism used to retrieve the CPU maximum
logical processor number to be abstracted from the logic that
needs the value.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-5-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2021-03-08 18:07:32 +00:00
2002e950ea UefiCpuPkg/SmmCpuFeaturesLib: Cleanup library constructors
There's currently two library instances:
  1. SmmCpuFeaturesLib
  2. SmmCpuFeaturesLibStm

There's two constructor functions:
  1. SmmCpuFeaturesLibConstructor()
  2. SmmCpuFeaturesLibStmConstructor()

SmmCpuFeaturesLibConstructor() is called by
SmmCpuFeaturesLibStmConstructor() since the functionality in that
function is required by both library instances.

The declaration for SmmCpuFeaturesLibConstructor() is embedded in
"SmmStm.c" instead of being declared in a header file. Further,
that constructor function is called by the STM specific constructor.

This change moves the common code to a function called
CpuFeaturesLibInitialization() which is declared in an internal
library header file "CpuFeaturesLib.h". Each constructor simply
calls this function to perform the common functionality.

Additionally, SmmCpuFeaturesLibConstructor() is moved from
SmmCpuFeaturesLibNoStm.c into a instance-specific file allowing
SmmCpuFeaturesLibNoStm.c to contain no STM implementation agnostic
to a particular library instance.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-4-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2021-03-08 18:07:32 +00:00
61dc3b3399 UefiCpuPkg/SmmCpuFeaturesLib: Rename SmmCpuFeaturesLib.c
This change renames SmmCpuFeaturesLib.c to SmmCpuFeaturesLibCommon.c
to better convey that this file contains library implementation
common to all library instances.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Message-Id: <20210217213227.1277-3-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2021-03-08 18:07:32 +00:00
3e062ea498 UefiCpuPkg/SmmCpuFeaturesLib: Move multi-instance function decl to header
FinishSmmCpuFeaturesInitializeProcessor() is a multi-instance
internal library function that is currently not declared in a
header file but embedded in "SmmCpuFeaturesLib.c".

This change cleans up the declaration moving it to a new header
file "CpuFeaturesLib.h" and removing the local declaration in
"SmmCpuFeaturesLib.c".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20210217213227.1277-2-mikuback@linux.microsoft.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
[lersek@redhat.com: replace the guard macro "_CPU_FEATURES_LIB_H_" with
 "CPU_FEATURES_LIB_H_", for fixing ECC 8003, per commit 6ffbb3581a]
2021-03-08 18:07:32 +00:00
94fa95c874 EmbeddedPkg: Only print LibGetTime message about compile time epoch once
The message "LibGetTime: RtcEpochSeconds non volatile variable was not
found - Using compilation time epoch." can be printed a very large
number of times, causing log files to become excessively large. This is
because the RtcEpochSeconds variable only gets set if LibSetTime is
called, for example by running 'time 12:00' in the UEFI Shell.

Avoid this by setting RtcEpochSeconds to BUILD_EPOCH (EpochSeconds)
after printing the message. It's set to a volatile variable so the
message will be displayed on future boots and not hidden.

Commit 44ae214591 reduced the verbosity of
the message to DEBUG_VERBOSE. Revert it back to DEBUG_INFO so it's more
prominent now that it doesn't get printed so frequently.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2021-03-08 12:28:20 +00:00
d28a681534 BaseTools: Modify struct parser for StructPcd
Currently the struct parser for StructPcd Generation does not
filter the types such as UINT8 which should be ignored successfully.
This patch modifies this issue.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-03-08 04:01:55 +00:00
dd6c0a0ba3 BaseTools: Adjust StructurePcd List Order.
Currently StructurePcd.dsc have the list order issue. For a Pcd
with several elements, the list indexs are used to distinguish
these elements like this:

PcdName.name.offset_name[0]|0x0
PcdName.name.offset_name[10]|0x0
PcdName.name.offset_name[11]|0x0
...
PcdName.name.offset_name[2]|0x0
...

However, the index is not strictly sorted by decimal numerical order,
which is not user friendly. One more sort rule for index is added to
the current rules to support for decimal numerical order in this patch.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-03-08 03:14:35 +00:00
8c61f1934d UefiCpuPkg/MpInitLib: Remove unused Lock from MP_CPU_EXCHANGE_INFO
The Lock is no longer needed since "LOCK XADD" was used in
MpFuncs.nasm for ApIndex atomic increment.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-08 02:22:37 +00:00
2fba7d4ee4 UefiCpuPkg/MpInitLib: Use NASM struc to avoid hardcode offset
In Windows environment, "dumpbin /disasm" is used to verify the
disassembly before and after using NASM struc doesn't change.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2021-03-08 02:22:37 +00:00
e59760f87e MdePkg/Nasm.inc: add macros for C types used in structure definition
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
2021-03-08 02:22:37 +00:00
b8a92fa2fe BaseTools: Update the NASM CI dependency
Update the external dependency (consumed by Edk2Tools) version for NASM,
as agreed in recent community meetings:
https://edk2.groups.io/g/devel/message/71289
https://edk2.groups.io/g/devel/message/71070

This is primarily used by CI builds, but may also be used by platforms.

Signed-off-by: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-03-08 01:33:44 +00:00
59a3ccb09e SecurityPkg: Tcg2Acpi: Added unblock memory interface for NVS region
This changes added usage of MmUnblockMemoryLib to explicitly request
allocated NVS region to be accessible from MM environment. It will bring
in compatibility with architectures that supports full memory blockage
inside MM.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB31026F3F8C3FAA39D74CE4BAF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
8802583c48 SecurityPkg: Tcg2Smm: Added support for Standalone Mm
https://bugzilla.tianocore.org/show_bug.cgi?id=3169

This change added Standalone MM instance of Tcg2. The notify function for
Standalone MM instance is left empty.

A dependency DXE driver with a Depex of gEfiMmCommunication2ProtocolGuid
was created to indicate the readiness of Standalone MM Tcg2 driver.

Lastly, the support of CI build for Tcg2 Standalone MM module is added.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB3102C3F99CBADFCC5F8A821CF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
3c2dc30d1b SecurityPkg: Tcg2Smm: Separate Tcg2Smm into 2 modules
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3169

This change separated the original Tcg2Smm module into 2 drivers: the
SMM driver that registers callback for physical presence and memory
clear; the Tcg2Acpi driver that patches and publishes ACPI table for
runtime use.

Tcg2Smm introduced an SMI root handler to allow Tcg2Acpi to communicate
the NVS region used by Tpm.asl and exchange the registered SwSmiValue.

Lastly, Tcg2Smm driver will publish gTcg2MmSwSmiRegisteredGuid at the end
of entrypoint to ensure Tcg2Acpi to load after Tcg2Smm is ready to
communicate.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB310295CC623EF7C062844DFFF3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
e2d6833c11 SecurityPkg: Tcg2Smm: Switching from gSmst to gMmst
This change replaced gSmst with gMmst to support broader compatibility
under MM environment for Tcg2Smm driver.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Message-Id: <MWHPR06MB310218F28C7AAF8DB375E963F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
f463dbaded MdeModulePkg: VariableSmmRuntimeDxe: Added request unblock memory interface
This changes added usage of MmUnblockMemoryLib to explicitly request
runtime cache regions(and its indicators) to be accessible from MM
environment when PcdEnableVariableRuntimeCache is enabled. It will bring
in compatibility with architectures that supports full memory blockage
inside MM.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Message-Id: <MWHPR06MB31026EA41F28F2CE12B68574F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
05a757c9c6 OvmfPkg: resolve MmUnblockMemoryLib (mainly for VariableSmmRuntimeDxe)
This change added NULL MmUnblockMemoryLib instance in dsc files of
OvmfPkg to pass CI build. When SMM_REQUIRE flag is set, the library
interface is consumed by VariableSmmRuntimeDxe to better support variable
runtime cache feature.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <MWHPR06MB31028DFAB7AE46E32E5F9F86F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
7cda5d9e3a MdePkg: MmUnblockMemoryLib: Added definition and null instance
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3168

This interface provides an abstration layer to allow MM modules to access
requested areas that are outside of MMRAM. On MM model that blocks all
non-MMRAM accesses, areas requested through this API will be mapped or
unblocked for accessibility inside MM environment.

For MM modules that need to access regions outside of MMRAMs, the agents
that set up these regions are responsible for invoking this API in order
for these memory areas to be accessible from inside MM.

Example usages:
1. To enable runtime cache feature for variable service, Variable MM
module will need to access the allocated runtime buffer. Thus the agent
sets up these buffers, VariableSmmRuntimeDxe, will need to invoke this
API to make these regions accessible by Variable MM.
2. For TPM ACPI table to communicate to physical presence handler, the
corresponding NVS region has to be accessible from inside MM. Once the
NVS region are assigned, it needs to be unblocked thourgh this API.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>

Signed-off-by: Kun Qin <kun.q@outlook.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Message-Id: <MWHPR06MB31028AF0D0785B93E4E7CF63F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
2021-03-05 15:25:07 +00:00
c5740f3606 MdeModulePkg/UfsPassThruDxe: Improve Device initialization polling Loop
https://bugzilla.tianocore.org/show_bug.cgi?id=3217

Current Ufs Pass thru driver polls for 5us and return success even when
the timeout occurs.
There are cards that can take upto 600ms for Init and hence increased
the time out for fDeviceInit polling loop.

Signed-off-by: Bandaru <purna.chandra.rao.bandaru@intel.com>
Cc: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2021-03-05 08:43:23 +00:00
934 changed files with 118282 additions and 11564 deletions

View File

@ -51,9 +51,6 @@ steps:
# Set default
- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch)

View File

@ -21,6 +21,9 @@ jobs:
#Use matrix to speed up the build process
strategy:
matrix:
TARGET_ARM_ARMPLATFORM:
Build.Pkgs: 'ArmPkg,ArmPlatformPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
TARGET_MDE_CPU:
Build.Pkgs: 'MdePkg,UefiCpuPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
@ -64,23 +67,3 @@ jobs:
build_pkgs: $(Build.Pkgs)
build_targets: $(Build.Targets)
build_archs: ${{ parameters.arch_list }}
- job: FINISHED
dependsOn: Build_${{ parameters.tool_chain_tag }}
condition: succeeded()
steps:
- checkout: none
- script: |
echo FINISHED
sleep 10
displayName: FINISHED
- job: FAILED
dependsOn: Build_${{ parameters.tool_chain_tag }}
condition: failed()
steps:
- checkout: none
- script: |
echo FAILED
sleep 10
displayName: FAILED

View File

@ -31,9 +31,6 @@ steps:
echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch)

View File

@ -13,7 +13,7 @@ parameters:
steps:
- task: NodeTool@0
inputs:
versionSpec: '10.x'
versionSpec: '14.x'
#checkLatest: false # Optional
condition: and(gt(variables.pkg_count, 0), succeeded())

2
.gitmodules vendored
View File

@ -6,7 +6,7 @@
url = https://github.com/ucb-bar/berkeley-softfloat-3.git
[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
url = https://git.cryptomilk.org/projects/cmocka.git
url = https://github.com/tianocore/edk2-cmocka.git
[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
url = https://github.com/kkos/oniguruma

View File

@ -16,7 +16,7 @@
# * This file must be checked into the 'default' branch of a repo. Copies
# of this file on other branches of a repo are ignored by Mergify.
#
# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# https://github.com/apps/mergify
@ -24,74 +24,27 @@
#
##
pull_request_rules:
queue_rules:
- name: default
conditions:
- base~=(^main|^master|^stable/)
- label=push
pull_request_rules:
- name: Automatically merge a PR when all required checks pass and 'push' label is present
conditions:
- base~=(^master|^stable/)
- base~=(^main|^master|^stable/)
- label=push
- author=@tianocore/edk-ii-maintainers
- status-success=tianocore.PatchCheck
- status-success=Ubuntu GCC5 PR
- status-success=Windows VS2019 PR
actions:
merge:
strict: true
queue:
method: rebase
- name: Automatically close a PR when all required checks pass and 'push' label is not present
conditions:
- base~=(^master|^stable/)
- -label=push
- -closed
- status-success=tianocore.PatchCheck
- status-success=Ubuntu GCC5 PR
- status-success=Windows VS2019 PR
- status-success=Ubuntu GCC5 PR (FINISHED)
- status-success=Windows VS2019 PR (FINISHED)
actions:
close:
message: All checks passed. Auto close personal build.
rebase_fallback: none
name: default
- name: Post a comment on a PR that can not be merged due to a merge conflict
conditions:
- base~=(^master|^stable/)
- base~=(^main|^master|^stable/)
- conflict
actions:
comment:
message: PR can not be merged due to conflict. Please rebase and resubmit
- name: Automatically close a PR that fails the EDK II Maintainers membership check and 'push' label is present
conditions:
- base~=(^master|^stable/)
- label=push
- -author=@tianocore/edk-ii-maintainers
actions:
close:
message: PR submitter is not a member of the Tianocore EDK II Maintainers team
- name: Post a comment on a PR if PatchCheck fails
conditions:
- base~=(^master|^stable/)
- status-failure=tianocore.PatchCheck
actions:
comment:
message: PR can not be merged due to a PatchCheck failure. Please resolve and resubmit
- name: Post a comment on a PR if Ubuntu GCC5 fails
conditions:
- base~=(^master|^stable/)
- status-failure=Ubuntu GCC5 PR
- status-success=Ubuntu GCC5 PR (FAILED)
actions:
comment:
message: PR can not be merged due to an Ubuntu GCC5 failure. Please resolve and resubmit
- name: Post a comment on a PR if Windows VS2019 fails
conditions:
- base~=(^master|^stable/)
- status-failure=Windows VS2019 PR
- status-success=Windows VS2019 PR (FAILED)
actions:
comment:
message: PR can not be merged due to a Windows VS2019 failure. Please resolve and resubmit

View File

@ -49,7 +49,9 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
''' return iterable of edk2 packages supported by this build.
These should be edk2 workspace relative paths '''
return ("ArmVirtPkg",
return ("ArmPkg",
"ArmPlatformPkg",
"ArmVirtPkg",
"DynamicTablesPkg",
"EmulatorPkg",
"MdePkg",

View File

@ -1,5 +1,6 @@
# @file EccCheck.py
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@ -60,18 +61,20 @@ class EccCheck(ICiBuildPlugin):
# - Junit Logger
# - output_stream the StringIO output stream from this plugin via logging
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
edk2_path = Edk2pathObj.WorkspacePath
python_path = os.path.join(edk2_path, "BaseTools", "Source", "Python")
workspace_path = Edk2pathObj.WorkspacePath
basetools_path = environment.GetValue("EDK_TOOLS_PATH")
python_path = os.path.join(basetools_path, "Source", "Python")
env = shell_environment.GetEnvironment()
env.set_shell_var('PYTHONPATH', python_path)
env.set_shell_var('WORKSPACE', edk2_path)
env.set_shell_var('WORKSPACE', workspace_path)
env.set_shell_var('PACKAGES_PATH', os.pathsep.join(Edk2pathObj.PackagePathList))
self.ECC_PASS = True
self.ApplyConfig(pkgconfig, edk2_path, packagename)
self.ApplyConfig(pkgconfig, workspace_path, basetools_path, packagename)
modify_dir_list = self.GetModifyDir(packagename)
patch = self.GetDiff(packagename)
ecc_diff_range = self.GetDiffRange(patch, packagename, edk2_path)
self.GenerateEccReport(modify_dir_list, ecc_diff_range, edk2_path)
ecc_log = os.path.join(edk2_path, "Ecc.log")
ecc_diff_range = self.GetDiffRange(patch, packagename, workspace_path)
self.GenerateEccReport(modify_dir_list, ecc_diff_range, workspace_path, basetools_path)
ecc_log = os.path.join(workspace_path, "Ecc.log")
self.RevertCode()
if self.ECC_PASS:
tc.SetSuccess()
@ -176,24 +179,24 @@ class EccCheck(ICiBuildPlugin):
return comment_range
def GenerateEccReport(self, modify_dir_list: List[str], ecc_diff_range: Dict[str, List[Tuple[int, int]]],
edk2_path: str) -> None:
workspace_path: str, basetools_path: str) -> None:
ecc_need = False
ecc_run = True
config = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "config.ini")
exception = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "exception.xml")
report = os.path.join(edk2_path, "Ecc.csv")
config = os.path.join(basetools_path, "Source", "Python", "Ecc", "config.ini")
exception = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
report = os.path.join(workspace_path, "Ecc.csv")
for modify_dir in modify_dir_list:
target = os.path.join(edk2_path, modify_dir)
target = os.path.join(workspace_path, modify_dir)
logging.info('Run ECC tool for the commit in %s' % modify_dir)
ecc_need = True
ecc_params = "-c {0} -e {1} -t {2} -r {3}".format(config, exception, target, report)
return_code = RunCmd("Ecc", ecc_params, workingdir=edk2_path)
return_code = RunCmd("Ecc", ecc_params, workingdir=workspace_path)
if return_code != 0:
ecc_run = False
break
if not ecc_run:
logging.error('Fail to run ECC tool')
self.ParseEccReport(ecc_diff_range, edk2_path)
self.ParseEccReport(ecc_diff_range, workspace_path)
if not ecc_need:
logging.info("Doesn't need run ECC check")
@ -202,13 +205,12 @@ class EccCheck(ICiBuildPlugin):
RunCmd("git", revert_params)
return
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], edk2_path: str) -> None:
ecc_log = os.path.join(edk2_path, "Ecc.log")
ecc_csv = "Ecc.csv"
file = os.listdir(edk2_path)
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], workspace_path: str) -> None:
ecc_log = os.path.join(workspace_path, "Ecc.log")
ecc_csv = os.path.join(workspace_path, "Ecc.csv")
row_lines = []
ignore_error_code = self.GetIgnoreErrorCode()
if ecc_csv in file:
if os.path.exists(ecc_csv):
with open(ecc_csv) as csv_file:
reader = csv.reader(csv_file)
for row in reader:
@ -234,10 +236,10 @@ class EccCheck(ICiBuildPlugin):
log.writelines(all_line)
return
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], edk2_path: str, pkg: str) -> None:
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], workspace_path: str, basetools_path: str, pkg: str) -> None:
if "IgnoreFiles" in pkgconfig:
for a in pkgconfig["IgnoreFiles"]:
a = os.path.join(edk2_path, pkg, a)
a = os.path.join(workspace_path, pkg, a)
a = a.replace(os.sep, "/")
logging.info("Ignoring Files {0}".format(a))
@ -251,7 +253,7 @@ class EccCheck(ICiBuildPlugin):
if "ExceptionList" in pkgconfig:
exception_list = pkgconfig["ExceptionList"]
exception_xml = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "exception.xml")
exception_xml = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
try:
logging.info("Appending exceptions")
self.AppendException(exception_list, exception_xml)

View File

@ -37,12 +37,12 @@ class SpellCheck(ICiBuildPlugin):
#
# A package can remove any of these using IgnoreStandardPaths
#
STANDARD_PLUGIN_DEFINED_PATHS = ["*.c", "*.h",
STANDARD_PLUGIN_DEFINED_PATHS = ("*.c", "*.h",
"*.nasm", "*.asm", "*.masm", "*.s",
"*.asl",
"*.dsc", "*.dec", "*.fdf", "*.inf",
"*.md", "*.txt"
]
)
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
""" Provide the testcase name and classname for use in reporting
@ -107,7 +107,8 @@ class SpellCheck(ICiBuildPlugin):
version_aggregator.GetVersionAggregator().ReportVersion(
"CSpell", cspell_version, version_aggregator.VersionTypes.INFO)
package_relative_paths_to_spell_check = SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS
# copy the default as a list
package_relative_paths_to_spell_check = list(SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS)
#
# Allow the ci.yaml to remove any of the above standard paths
@ -133,7 +134,8 @@ class SpellCheck(ICiBuildPlugin):
#
relpath = os.path.relpath(abs_pkg_path)
cpsell_paths = " ".join(
[f"{relpath}/**/{x}" for x in package_relative_paths_to_spell_check])
# Double quote each path to defer expansion to cspell parameters
[f'"{relpath}/**/{x}"' for x in package_relative_paths_to_spell_check])
# Make the config file
config_file_path = os.path.join(

View File

@ -4,8 +4,8 @@
| Package | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues |
| :---- | :----- | :---- | :--- |
| ArmPkg |
| ArmPlatformPkg |
| ArmPkg | | :heavy_check_mark: |
| ArmPlatformPkg | | :heavy_check_mark: |
| ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README |
| CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
| DynamicTablesPkg | | :heavy_check_mark: |
@ -254,6 +254,16 @@ Install
More cspell info: https://github.com/streetsidesoftware/cspell
### License Checking - LicenseCheck
Scans all new added files in a package to make sure code is contributed under
BSD-2-Clause-Patent.
### Ecc tool - EccCheck
Run the Ecc tool on the package. The Ecc tool is available in the BaseTools
package. It checks that the code complies to the EDKII coding standard.
## PyTool Scopes
Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning

240
ArmPkg/ArmPkg.ci.yaml Normal file
View File

@ -0,0 +1,240 @@
## @file
# CI configuration for ArmPkg
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
## options defined .pytool/Plugin/LicenseCheck
"LicenseCheck": {
"IgnoreFiles": []
},
"EccCheck": {
## Exception sample looks like below:
## "ExceptionList": [
## "<ErrorID>", "<KeyWord>"
## ]
"ExceptionList": [
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
"Library/ArmSoftFloatLib/berkeley-softfloat-3"
]
},
## options defined .pytool/Plugin/CompilerPlugin
"CompilerPlugin": {
"DscPath": "ArmPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
"HostUnitTestCompilerPlugin": {
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/CharEncodingCheck
"CharEncodingCheck": {
"IgnoreFiles": []
},
## options defined .pytool/Plugin/DependencyCheck
"DependencyCheck": {
"AcceptableDependencies": [
"ArmPlatformPkg/ArmPlatformPkg.dec",
"ArmPkg/ArmPkg.dec",
"EmbeddedPkg/EmbeddedPkg.dec",
"MdeModulePkg/MdeModulePkg.dec",
"MdePkg/MdePkg.dec",
"ShellPkg/ShellPkg.dec"
],
# For host based unit tests
"AcceptableDependencies-HOST_APPLICATION":[
"UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
],
# For UEFI shell based apps
"AcceptableDependencies-UEFI_APPLICATION":[],
"IgnoreInf": []
},
## options defined .pytool/Plugin/DscCompleteCheck
"DscCompleteCheck": {
"IgnoreInf": [],
"DscPath": "ArmPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
"HostUnitTestDscCompleteCheck": {
"IgnoreInf": [""],
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/GuidCheck
"GuidCheck": {
"IgnoreGuidName": [],
"IgnoreGuidValue": [],
"IgnoreFoldersAndFiles": [],
"IgnoreDuplicates": [],
},
## options defined .pytool/Plugin/LibraryClassCheck
"LibraryClassCheck": {
"IgnoreHeaderFile": []
},
## options defined .pytool/Plugin/SpellCheck
"SpellCheck": {
"AuditOnly": False,
"IgnoreFiles": [
"Library/ArmSoftFloatLib/berkeley-softfloat-3/**"
], # use gitignore syntax to ignore errors
# in matching files
"ExtendWords": [
"api's",
"ackintid",
"actlr",
"aeabi",
"asedis",
"ashldi",
"ashrdi",
"baddr",
"ccidx",
"ccsidr",
"clidr",
"clrex",
"clzsi",
"cnthctl",
"cortexa",
"cpacr",
"cpuactlr",
"csselr",
"ctzsi",
"cygdrive",
"cygpaths",
"datas",
"dcmpeq",
"dcmpge",
"dcmpgt",
"dcmple",
"dcmplt",
"ddisable",
"divdi",
"divsi",
"dmdepkg",
"dpref",
"drsub",
"fcmpeq",
"fcmpge",
"fcmpgt",
"fcmple",
"fcmplt",
"ffreestanding",
"frsub",
"hisilicon",
"iccabpr",
"iccbpr",
"icciar",
"iccicr",
"icciidr",
"iccpir",
"iccpmr",
"iccrpr",
"icdabr",
"icdicer",
"icdicfr",
"icdicpr",
"icdictr",
"icdiidr",
"icdiser",
"icdisr",
"icdppisr",
"icdsgir",
"icdspr",
"icenabler",
"intid",
"ipriority",
"irouter",
"isenabler",
"istatus",
"itargets",
"lable",
"ldivmod",
"ldmdb",
"ldmia",
"ldrbt",
"ldrex",
"ldrexb",
"ldrexd",
"ldrexh",
"ldrhbt",
"ldrht",
"ldrsb",
"ldrsbt",
"ldrsh",
"lshrdi",
"moddi",
"modsi",
"mpcore",
"mpidr",
"muldi",
"mullu",
"nonshareable",
"nsacr",
"nsasedis",
"nuvia",
"oldit",
"pcten",
"plpis",
"procno",
"readc",
"revsh",
"rfedb",
"sctlr",
"smccc",
"smlabb",
"smlabt",
"smlad",
"smladx",
"smlatb",
"smlatt",
"smlawb",
"smlawt",
"smlsd",
"smlsdx",
"smmla",
"smmlar",
"smmls",
"smmlsr",
"sourcery",
"srsdb",
"ssacr",
"stmdb",
"stmia",
"strbt",
"strexb",
"strexd",
"strexh",
"strht",
"switchu",
"tpidrurw",
"ttbcr",
"typer",
"ucmpdi",
"udivdi",
"udivmoddi",
"udivsi",
"uefi's",
"uldiv",
"umoddi",
"umodsi",
"usada",
"vlpis",
"writec"
], # words to extend to the dictionary for this package
"IgnoreStandardPaths": [ # Standard Plugin defined paths that
"*.asm", "*.s" # should be ignore
],
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
}
}

View File

@ -2,7 +2,7 @@
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -27,15 +27,68 @@
Include # Root include for the package
[LibraryClasses.common]
ArmLib|Include/Library/ArmLib.h
ArmMmuLib|Include/Library/ArmMmuLib.h
SemihostLib|Include/Library/Semihosting.h
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
## @libraryclass Convert Arm instructions to a human readable format.
#
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
## @libraryclass Provides an interface to Arm generic counters.
#
ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
## @libraryclass Provides an interface to initialize a
# Generic Interrupt Controller (GIC).
#
ArmGicArchLib|Include/Library/ArmGicArchLib.h
ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
## @libraryclass Provides a Generic Interrupt Controller (GIC)
# configuration interface.
#
ArmGicLib|Include/Library/ArmGicLib.h
## @libraryclass Provides a HyperVisor Call (HVC) interface.
#
ArmHvcLib|Include/Library/ArmHvcLib.h
## @libraryclass Provides an interface to Arm registers.
#
ArmLib|Include/Library/ArmLib.h
## @libraryclass Provides a Mmu interface.
#
ArmMmuLib|Include/Library/ArmMmuLib.h
## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
# for the System Control and Management Interface (SCMI).
#
ArmMtlLib|Include/Library/ArmMtlLib.h
## @libraryclass Provides a System Monitor Call (SMC) interface.
#
ArmSmcLib|Include/Library/ArmSmcLib.h
## @libraryclass Provides a SuperVisor Call (SVC) interface.
#
ArmSvcLib|Include/Library/ArmSvcLib.h
## @libraryclass Provides a default exception handler.
#
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
## @libraryclass Provides an interface to query miscellaneous OEM
# information.
#
OemMiscLib|Include/Library/OemMiscLib.h
## @libraryclass Provides an OpTee interface.
#
OpteeLib|Include/Library/OpteeLib.h
## @libraryclass Provides a semihosting interface.
#
SemihostLib|Include/Library/SemihostLib.h
## @libraryclass Provides an interface for a StandaloneMm Mmu.
#
StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
[Guids.common]
@ -84,7 +137,7 @@
# hardware coherency (i.e., no virtualization or cache coherent DMA)
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
[PcdsFeatureFlag.AARCH64]
[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
## Used to select method for requesting services from S-EL1.<BR><BR>
# TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
# FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>

View File

@ -2,7 +2,7 @@
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2018, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation.<BR>
#
@ -32,17 +32,22 @@
[PcdsFixedAtBuild]
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
@ -50,6 +55,7 @@
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@ -150,8 +156,11 @@
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
[Components.AARCH64]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
[Components.AARCH64, Components.ARM]
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf

View File

@ -6,8 +6,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
--*/
#ifndef __ARM_GIC_DXE_H__
#define __ARM_GIC_DXE_H__
#ifndef ARM_GIC_DXE_H_
#define ARM_GIC_DXE_H_
#include <Library/ArmGicLib.h>
#include <Library/ArmLib.h>
@ -76,4 +76,4 @@ GicGetDistributorIcfgBaseAndBit (
OUT UINTN *Config1Bit
);
#endif
#endif // ARM_GIC_DXE_H_

View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@ -120,7 +120,14 @@ ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase
)
{
return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
//
// Interrupt ID 1020-1023 are reserved.
//
return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);
}
VOID

View File

@ -1,58 +0,0 @@
/** @file
*
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
/*
* This function configures the interrupts set by the mask to be secure.
*
*/
VOID
EFIAPI
ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
)
{
UINTN Index;
UINT32 InterruptStatus;
// We must not have more interrupts defined by the mask than the number of available interrupts
ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
// Set all the interrupts defined by the mask as Secure
for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
}
}
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
)
{
// Turn on the GIC distributor
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
}
VOID
EFIAPI
ArmGicSetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
)
{
ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
}

View File

@ -121,7 +121,7 @@ GicV2GetInterruptSourceState (
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_UNSUPPORTED Source interrupt is not supported
**/

View File

@ -115,7 +115,7 @@ GicV3GetInterruptSourceState (
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/

View File

@ -1,6 +1,6 @@
#/** @file
#
# Copyright (c) 2017-2018, Arm Limited. All rights reserved.
# Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -18,11 +18,16 @@
ENTRY_POINT = ArmScmiDxeEntryPoint
[Sources.common]
Scmi.c
ArmScmiBaseProtocolPrivate.h
ArmScmiClockProtocolPrivate.h
ArmScmiPerformanceProtocolPrivate.h
ScmiBaseProtocol.c
Scmi.c
ScmiClockProtocol.c
ScmiDxe.c
ScmiDxe.h
ScmiPerformanceProtocol.c
ScmiPrivate.h
[Packages]
ArmPkg/ArmPkg.dec

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -22,7 +22,7 @@
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command.
/** Return values for ScmiMessageIdPerformanceDescribeLevels command.
SCMI Spec section 4.5.2.5
**/
typedef struct {

View File

@ -95,7 +95,7 @@ ScmiCommandExecute (
// Fill in message header.
MessageHeader = SCMI_MESSAGE_HEADER (
Command->MessageId,
SCMI_MESSAGE_TYPE_COMMAND,
ScmiMessageTypeCommand,
Command->ProtocolId
);
@ -123,7 +123,7 @@ ScmiCommandExecute (
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
if (Response->Status != SCMI_SUCCESS) {
if (Response->Status != ScmiSuccess) {
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
Command->ProtocolId,
Command->MessageId,
@ -195,7 +195,7 @@ ScmiGetProtocolVersion (
Status = ScmiProtocolDiscoveryCommon (
ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_VERSION,
ScmiMessageIdProtocolVersion,
(UINT32**)&ProtocolVersion
);
if (EFI_ERROR (Status)) {
@ -224,7 +224,7 @@ ScmiGetProtocolAttributes (
{
return ScmiProtocolDiscoveryCommon (
ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES,
ScmiMessageIdProtocolAttributes,
ReturnValues
);
}
@ -246,7 +246,7 @@ ScmiGetProtocolMessageAttributes (
{
return ScmiProtocolDiscoveryCommon (
ProtocolId,
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES,
ScmiMessageIdProtocolMessageAttributes,
ReturnValues
);
}

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -34,7 +34,7 @@ BaseGetVersion (
OUT UINT32 *Version
)
{
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version);
return ScmiGetProtocolVersion (ScmiProtocolIdBase, Version);
}
/** Return total number of SCMI protocols supported by the SCP firmware.
@ -57,7 +57,7 @@ BaseGetTotalProtocols (
EFI_STATUS Status;
UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValues);
Status = ScmiGetProtocolAttributes (ScmiProtocolIdBase, &ReturnValues);
if (EFI_ERROR (Status)) {
return Status;
}
@ -69,9 +69,9 @@ BaseGetTotalProtocols (
/** Common function which returns vendor details.
@param[in] MessageId SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR
@param[in] MessageId ScmiMessageIdBaseDiscoverVendor
OR
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR
ScmiMessageIdBaseDiscoverSubVendor
@param[out] VendorIdentifier ASCII name of the vendor/subvendor.
@ -91,7 +91,7 @@ BaseDiscoverVendorDetails (
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = MessageId;
PayloadLength = 0;
@ -133,7 +133,7 @@ BaseDiscoverVendor (
)
{
return BaseDiscoverVendorDetails (
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR,
ScmiMessageIdBaseDiscoverVendor,
VendorIdentifier
);
}
@ -156,7 +156,7 @@ BaseDiscoverSubVendor (
)
{
return BaseDiscoverVendorDetails (
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR,
ScmiMessageIdBaseDiscoverSubVendor,
VendorIdentifier
);
}
@ -183,8 +183,8 @@ BaseDiscoverImplVersion (
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION;
Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = ScmiMessageIdBaseDiscoverImplementationVersion;
PayloadLength = 0;
@ -250,8 +250,8 @@ BaseDiscoverListProtocols (
return EFI_BUFFER_TOO_SMALL;
}
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS;
Cmd.ProtocolId = ScmiProtocolIdBase;
Cmd.MessageId = ScmiMessageIdBaseDiscoverListProtocols;
Skip = 0;

View File

@ -52,7 +52,7 @@ ClockGetVersion (
OUT UINT32 *Version
)
{
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version);
return ScmiGetProtocolVersion (ScmiProtocolIdClock, Version);
}
/** Return total number of clock devices supported by the clock management
@ -76,7 +76,7 @@ ClockGetTotalClocks (
EFI_STATUS Status;
UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnValues);
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
if (EFI_ERROR (Status)) {
return Status;
}
@ -122,8 +122,8 @@ ClockGetClockAttributes (
*MessageParams = ClockId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockAttributes;
PayloadLength = sizeof (ClockId);
@ -152,10 +152,10 @@ ClockGetClockAttributes (
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates.
@ -203,8 +203,8 @@ ClockDescribeRates (
return Status;
}
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockDescribeRates;
*MessageParams++ = ClockId;
@ -236,7 +236,7 @@ ClockDescribeRates (
*TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
if (*Format == ScmiClockRateFormatDiscrete) {
RequiredArraySize = (*TotalRates) * sizeof (UINT64);
} else {
// We need to return triplet of 64 bit value for each rate
@ -251,26 +251,30 @@ ClockDescribeRates (
RateOffset = 0;
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
if (*Format == ScmiClockRateFormatDiscrete) {
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
Rate = &DescribeRates->Rates[RateOffset++];
// Non-linear discrete rates.
RateArray[RateIndex++].Rate = ConvertTo64Bit (Rate->Low, Rate->High);
RateArray[RateIndex++].DiscreteRate.Rate =
ConvertTo64Bit (Rate->Low, Rate->High);
}
} else {
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
// Linear clock rates from minimum to maximum in steps
// Minimum clock rate.
Rate = &DescribeRates->Rates[RateOffset++];
RateArray[RateIndex].Min = ConvertTo64Bit (Rate->Low, Rate->High);
RateArray[RateIndex].ContinuousRate.Min =
ConvertTo64Bit (Rate->Low, Rate->High);
Rate = &DescribeRates->Rates[RateOffset++];
// Maximum clock rate.
RateArray[RateIndex].Max = ConvertTo64Bit (Rate->Low, Rate->High);
RateArray[RateIndex].ContinuousRate.Max =
ConvertTo64Bit (Rate->Low, Rate->High);
Rate = &DescribeRates->Rates[RateOffset++];
// Step.
RateArray[RateIndex++].Step = ConvertTo64Bit (Rate->Low, Rate->High);
RateArray[RateIndex++].ContinuousRate.Step =
ConvertTo64Bit (Rate->Low, Rate->High);
}
}
} while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
@ -316,8 +320,8 @@ ClockRateGet (
// Fill arguments for clock protocol command.
*MessageParams = ClockId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_GET;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateGet;
PayloadLength = sizeof (ClockId);
@ -370,8 +374,8 @@ ClockRateSet (
ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_SET;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateSet;
PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
@ -417,8 +421,8 @@ ClockEnable (
ClockConfigSetAttributes->ClockId = ClockId;
ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockConfigSet;
PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);

View File

@ -1,12 +1,12 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
System Control and Management Interface V1.0
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
@par Specification Reference:
- Arm System Control and Management Interface - Platform Design Document
(https://developer.arm.com/documentation/den0056/)
**/
#include <Base.h>
@ -24,9 +24,9 @@
#include "ScmiPrivate.h"
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
{ SCMI_PROTOCOL_ID_BASE, ScmiBaseProtocolInit },
{ SCMI_PROTOCOL_ID_PERFORMANCE, ScmiPerformanceProtocolInit },
{ SCMI_PROTOCOL_ID_CLOCK, ScmiClockProtocolInit }
{ ScmiProtocolIdBase, ScmiBaseProtocolInit },
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
{ ScmiProtocolIdClock, ScmiClockProtocolInit }
};
/** ARM SCMI driver entry point function.
@ -61,7 +61,7 @@ ArmScmiDxeEntryPoint (
UINT32 SupportedListSize;
// Every SCMI implementation must implement the base protocol.
ASSERT (Protocols[0].Id == SCMI_PROTOCOL_ID_BASE);
ASSERT (Protocols[0].Id == ScmiProtocolIdBase);
Status = ScmiBaseProtocolInit (&ImageHandle);
if (EFI_ERROR (Status)) {
@ -86,7 +86,9 @@ ArmScmiDxeEntryPoint (
return Status;
}
if (Version != BASE_PROTOCOL_VERSION) {
// Accept any version between SCMI v1.0 and SCMI v2.0
if ((Version < BASE_PROTOCOL_VERSION_V1) ||
(Version > BASE_PROTOCOL_VERSION_V2)) {
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -35,7 +35,7 @@ PerformanceGetVersion (
OUT UINT32 *Version
)
{
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version);
return ScmiGetProtocolVersion (ScmiProtocolIdPerformance, Version);
}
/** Return protocol attributes of the performance management protocol.
@ -59,7 +59,7 @@ PerformanceGetAttributes (
UINT32* ReturnValues;
Status = ScmiGetProtocolAttributes (
SCMI_PROTOCOL_ID_PERFORMANCE,
ScmiProtocolIdPerformance,
&ReturnValues
);
if (EFI_ERROR (Status)) {
@ -107,8 +107,8 @@ PerformanceDomainAttributes (
*MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceDomainAttributes;
PayloadLength = sizeof (DomainId);
@ -179,8 +179,8 @@ PerformanceDescribeLevels (
*MessageParams++ = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
do {
@ -258,8 +258,8 @@ PerformanceLimitsSet (
*MessageParams++ = Limits->RangeMax;
*MessageParams = Limits->RangeMin;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceLimitsSet;
PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
@ -304,8 +304,8 @@ PerformanceLimitsGet (
*MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceLimitsGet;
PayloadLength = sizeof (DomainId);
@ -354,8 +354,8 @@ PerformanceLevelSet (
*MessageParams++ = DomainId;
*MessageParams = Level;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceLevelSet;
PayloadLength = sizeof (DomainId) + sizeof (Level);
@ -399,8 +399,8 @@ PerformanceLevelGet (
*MessageParams = DomainId;
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET;
Cmd.ProtocolId = ScmiProtocolIdPerformance;
Cmd.MessageId = ScmiMessageIdPerformanceLevelGet;
PayloadLength = sizeof (DomainId);

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -13,41 +13,41 @@
// SCMI protocol IDs.
typedef enum {
SCMI_PROTOCOL_ID_BASE = 0x10,
SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
SCMI_PROTOCOL_ID_SYSTEM_POWER = 0x12,
SCMI_PROTOCOL_ID_PERFORMANCE = 0x13,
SCMI_PROTOCOL_ID_CLOCK = 0x14,
SCMI_PROTOCOL_ID_SENSOR = 0x15
ScmiProtocolIdBase = 0x10,
ScmiProtocolIdPowerDomain = 0x11,
ScmiProtocolIdSystemPower = 0x12,
ScmiProtocolIdPerformance = 0x13,
ScmiProtocolIdClock = 0x14,
ScmiProtocolIdSensor = 0x15
} SCMI_PROTOCOL_ID;
// SCMI message types.
typedef enum {
SCMI_MESSAGE_TYPE_COMMAND = 0,
SCMI_MESSAGE_TYPE_DELAYED_RESPONSE = 2, // Skipping 1 is deliberate.
SCMI_MESSAGE_TYPE_NOTIFICATION = 3
ScmiMessageTypeCommand = 0,
ScmiMessageTypeDelayedResponse = 2, // Skipping 1 is deliberate.
ScmiMessageTypeNotification = 3
} SCMI_MESSAGE_TYPE;
// SCMI response error codes.
typedef enum {
SCMI_SUCCESS = 0,
SCMI_NOT_SUPPORTED = -1,
SCMI_INVALID_PARAMETERS = -2,
SCMI_DENIED = -3,
SCMI_NOT_FOUND = -4,
SCMI_OUT_OF_RANGE = -5,
SCMI_BUSY = -6,
SCMI_COMMS_ERROR = -7,
SCMI_GENERIC_ERROR = -8,
SCMI_HARDWARE_ERROR = -9,
SCMI_PROTOCOL_ERROR = -10
ScmiSuccess = 0,
ScmiNotSupported = -1,
ScmiInvalidParameters = -2,
ScmiDenied = -3,
ScmiNotFound = -4,
ScmiOutOfRange = -5,
ScmiBusy = -6,
ScmiCommsError = -7,
ScmiGenericError = -8,
ScmiHardwareError = -9,
ScmiProtocolError = -10
} SCMI_STATUS;
// SCMI message IDs common to all protocols.
typedef enum {
SCMI_MESSAGE_ID_PROTOCOL_VERSION = 0x0,
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES = 0x1,
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2
ScmiMessageIdProtocolVersion = 0x0,
ScmiMessageIdProtocolAttributes = 0x1,
ScmiMessageIdProtocolMessageAttributes = 0x2
} SCMI_MESSAGE_ID;
// Not defined in SCMI specification but will help to identify a message.

View File

@ -345,7 +345,7 @@ EfiAttributeToArmAttribute (
break;
case EFI_MEMORY_WC:
// Map to normal non-cachable
// Map to normal non-cacheable
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
break;

View File

@ -7,8 +7,8 @@
**/
#ifndef __CPU_DXE_ARM_EXCEPTION_H__
#define __CPU_DXE_ARM_EXCEPTION_H__
#ifndef CPU_DXE_H_
#define CPU_DXE_H_
#include <Uefi.h>
@ -143,4 +143,4 @@ SetGcdMemorySpaceAttributes (
IN UINT64 Attributes
);
#endif // __CPU_DXE_ARM_EXCEPTION_H__
#endif // CPU_DXE_H_

View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@ -32,7 +32,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
};
/** Publish ARM Processor Data table in UEFI SYSTEM Table.
* @param: HobStart Pointer to the beginning of the HOB List from PEI.
* @param HobStart Pointer to the beginning of the HOB List from PEI.
*
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory

View File

@ -5,8 +5,8 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __GENERIC_WATCHDOG_H__
#define __GENERIC_WATCHDOG_H__
#ifndef GENERIC_WATCHDOG_H_
#define GENERIC_WATCHDOG_H_
// Refresh Frame:
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
@ -21,4 +21,4 @@
#define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0
#endif // __GENERIC_WATCHDOG_H__
#endif // GENERIC_WATCHDOG_H_

View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2017, ARM Limited. All rights reserved.
# Copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -13,6 +13,7 @@
ENTRY_POINT = GenericWatchdogEntry
[Sources.common]
GenericWatchdog.h
GenericWatchdogDxe.c
[Packages]

View File

@ -1,13 +1,13 @@
/** @file
Copyright (c) 2016-2018, ARM Limited. All rights reserved.
Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#if !defined _MM_COMMUNICATE_H_
#define _MM_COMMUNICATE_H_
#ifndef MM_COMMUNICATE_H_
#define MM_COMMUNICATE_H_
#define MM_MAJOR_VER_MASK 0xEFFF0000
#define MM_MINOR_VER_MASK 0x0000FFFF
@ -19,4 +19,4 @@
#define MM_CALLER_MAJOR_VER 0x1UL
#define MM_CALLER_MINOR_VER 0x0
#endif /* _MM_COMMUNICATE_H_ */
#endif /* MM_COMMUNICATE_H_ */

View File

@ -2,7 +2,7 @@
#
# DXE MM Communicate driver
#
# Copyright (c) 2016 - 2019, ARM Limited. All rights reserved.
# Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -24,6 +24,7 @@
#
[Sources.AARCH64]
MmCommunicate.h
MmCommunication.c
[Packages]

View File

@ -51,7 +51,7 @@ EFI_FILE gSemihostFsFile = {
};
//
// Device path for semi-hosting. It contains our autogened Caller ID GUID.
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;

View File

@ -7,8 +7,8 @@
**/
#ifndef __SEMIHOST_FS_H__
#define __SEMIHOST_FS_H__
#ifndef SEMIHOST_FS_H_
#define SEMIHOST_FS_H_
EFI_STATUS
VolumeOpen (
@ -242,5 +242,5 @@ FileFlush (
IN EFI_FILE *File
);
#endif // __SEMIHOST_FS_H__
#endif // SEMIHOST_FS_H_

View File

@ -10,8 +10,8 @@
**/
#ifndef __MACRO_IO_LIB_H__
#define __MACRO_IO_LIB_H__
#ifndef ASM_MACRO_IO_LIB_H_
#define ASM_MACRO_IO_LIB_H_
#define _ASM_FUNC(Name, Section) \
.global Name ; \
@ -36,4 +36,4 @@
movt Reg, #:upper16:(Sym) - (. + 12) ; \
ldr Reg, [pc, Reg]
#endif
#endif // ASM_MACRO_IO_LIB_H_

View File

@ -10,8 +10,8 @@
**/
#ifndef __MACRO_IO_LIBV8_H__
#define __MACRO_IO_LIBV8_H__
#ifndef ASM_MACRO_IO_LIBV8_H_
#define ASM_MACRO_IO_LIBV8_H_
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2, else we die.
@ -54,4 +54,4 @@
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
movk Reg, (Val) & 0xffff
#endif // __MACRO_IO_LIBV8_H__
#endif // ASM_MACRO_IO_LIBV8_H_

View File

@ -1,14 +1,14 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __AARCH64_H__
#define __AARCH64_H__
#ifndef AARCH64_H_
#define AARCH64_H_
#include <Chipset/AArch64Mmu.h>
@ -39,7 +39,7 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08
@ -97,10 +97,10 @@
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SPx_SYNC 0x200
#define ARM_VECTOR_CUR_SPx_IRQ 0x280
#define ARM_VECTOR_CUR_SPx_FIQ 0x300
#define ARM_VECTOR_CUR_SPx_SERR 0x380
#define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480
@ -238,4 +238,4 @@ ArmWriteCntHctl (
IN UINT32 CntHctl
);
#endif // __AARCH64_H__
#endif // AARCH64_H_

View File

@ -1,13 +1,13 @@
/** @file
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __AARCH64_MMU_H_
#define __AARCH64_MMU_H_
#ifndef AARCH64_MMU_H_
#define AARCH64_MMU_H_
//
// Memory Attribute Indirection register Definitions
@ -190,9 +190,9 @@
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25
#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format
#endif // __AARCH64_MMU_H_
#endif // AARCH64_MMU_H_

View File

@ -1,13 +1,13 @@
/** @file
Copyright (c) 2012-2014, ARM Limited. All rights reserved.
Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __ARM_CORTEX_A5x_H__
#define __ARM_CORTEX_A5x_H__
#ifndef ARM_CORTEX_A5X_H_
#define ARM_CORTEX_A5X_H_
//
// Cortex A5x feature bit definitions
@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
IN UINT64 Bits
);
#endif
#endif // ARM_CORTEX_A5X_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __ARM_CORTEX_A9_H__
#define __ARM_CORTEX_A9_H__
#ifndef ARM_CORTEX_A9_H_
#define ARM_CORTEX_A9_H_
#include <Chipset/ArmV7.h>
@ -55,5 +55,5 @@ ArmGetScuBaseAddress (
VOID
);
#endif
#endif // ARM_CORTEX_A9_H_

View File

@ -1,14 +1,14 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __ARM_V7_H__
#define __ARM_V7_H__
#ifndef ARM_V7_H_
#define ARM_V7_H_
#include <Chipset/ArmV7Mmu.h>
@ -70,7 +70,7 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
@ -120,4 +120,4 @@ ArmWriteNsacr (
IN UINT32 Nsacr
);
#endif // __ARM_V7_H__
#endif // ARM_V7_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARMV7_MMU_H_
#define __ARMV7_MMU_H_
#ifndef ARMV7_MMU_H_
#define ARMV7_MMU_H_
#define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
@ -235,4 +235,4 @@ ConvertSectionAttributesToPageAttributes (
IN BOOLEAN IsLargePage
);
#endif
#endif // ARMV7_MMU_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_MP_CORE_INFO_GUID_H_
#define __ARM_MP_CORE_INFO_GUID_H_
#ifndef ARM_MP_CORE_INFO_GUID_H_
#define ARM_MP_CORE_INFO_GUID_H_
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
#define SCU_CONFIG_REG_OFFSET 0x04
@ -57,4 +57,4 @@ typedef struct {
extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* MPCOREINFO_H_ */
#endif /* ARM_MP_CORE_INFO_GUID_H_ */

View File

@ -0,0 +1,112 @@
/** @file
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef ARM_CACHE_H_
#define ARM_CACHE_H_
#include <Uefi/UefiBaseType.h>
// The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
UINT32 InD :1; ///< Instruction not Data bit
UINT32 Level :3; ///< Cache level (zero based)
UINT32 TnD :1; ///< Allocation not Data bit
UINT32 Reserved :27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
typedef enum
{
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
CsselrCacheTypeInstruction,
CsselrCacheTypeMax
} CSSELR_CACHE_TYPE;
/// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :10; ///< Associativity - 1
UINT64 NumSets :15; ///< Number of sets in the cache -1
UINT64 Unknown :4; ///< Reserved, UNKNOWN
UINT64 Reserved :32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :21; ///< Associativity - 1
UINT64 Reserved1 :8; ///< Reserved, RES0
UINT64 NumSets :24; ///< Number of sets in the cache -1
UINT64 Reserved2 :8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
UINT64 LineSize : 3;
UINT64 Associativity : 21;
UINT64 Reserved : 8;
UINT64 Unallocated : 32;
} BitsCcidxAA32;
UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
UINT32 NumSets :24; ///< Number of sets in the cache - 1
UINT32 Reserved :8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
*
* The lower 32 bits are the same for both AARCH32 and AARCH64
* so we can use the same structure for both.
**/
typedef union {
struct {
UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
typedef enum {
/// No cache is present
ClidrCacheTypeNone = 0,
/// There is only an instruction cache
ClidrCacheTypeInstructionOnly,
/// There is only a data cache
ClidrCacheTypeDataOnly,
/// There are separate data and instruction caches
ClidrCacheTypeSeparate,
/// There is a unified cache
ClidrCacheTypeUnified,
ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */

View File

@ -17,9 +17,21 @@
#define ARM_FFA_SVC_H_
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif
#define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_MM_SVC_H__
#define __ARM_MM_SVC_H__
#ifndef ARM_MM_SVC_H_
#define ARM_MM_SVC_H_
/*
* SVC IDs to allow the MM secure partition to initialise itself, handle
@ -15,10 +15,25 @@
* privileged operations on its behalf.
*/
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
@ -44,4 +59,4 @@
#define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1
#endif
#endif // ARM_MM_SVC_H_

View File

@ -10,8 +10,8 @@
* (https://developer.arm.com/documentation/den0028/c/?lang=en)
**/
#ifndef __ARM_STD_SMC_H__
#define __ARM_STD_SMC_H__
#ifndef ARM_STD_SMC_H_
#define ARM_STD_SMC_H_
/*
* SMC function IDs for Standard Service queries
@ -49,6 +49,14 @@
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif
/* MM return error codes */
#define ARM_SMC_MM_RET_SUCCESS 0
#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
@ -129,4 +137,4 @@
/* 0xbf00ff02 is reserved */
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif
#endif // ARM_STD_SMC_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __ARM_DISASSEBLER_LIB_H__
#define __ARM_DISASSEBLER_LIB_H__
#ifndef ARM_DISASSEMBLER_LIB_H_
#define ARM_DISASSEMBLER_LIB_H_
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
@ -34,4 +34,4 @@ DisassembleInstruction (
OUT UINTN Size
);
#endif
#endif // ARM_DISASSEMBLER_LIB_H_

View File

@ -7,8 +7,8 @@
**/
#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__
#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__
#ifndef ARM_GENERIC_TIMER_COUNTER_LIB_H_
#define ARM_GENERIC_TIMER_COUNTER_LIB_H_
VOID
EFIAPI
@ -82,4 +82,4 @@ ArmGenericTimerSetCompareVal (
IN UINT64 Value
);
#endif
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_GIC_ARCH_LIB_H__
#define __ARM_GIC_ARCH_LIB_H__
#ifndef ARM_GIC_ARCH_LIB_H_
#define ARM_GIC_ARCH_LIB_H_
//
// GIC definitions
@ -24,4 +24,4 @@ ArmGicGetSupportedArchRevision (
VOID
);
#endif
#endif // ARM_GIC_ARCH_LIB_H_

View File

@ -1,13 +1,13 @@
/** @file
*
* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __ARMGIC_H
#define __ARMGIC_H
#ifndef ARMGIC_H_
#define ARMGIC_H_
#include <Library/ArmGicArchLib.h>
@ -333,4 +333,4 @@ ArmGicV3SetPriorityMask (
IN UINTN Priority
);
#endif
#endif // ARMGIC_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_HVC_LIB__
#define __ARM_HVC_LIB__
#ifndef ARM_HVC_LIB_H_
#define ARM_HVC_LIB_H_
/**
* The size of the HVC arguments are different between AArch64 and AArch32.
@ -37,4 +37,4 @@ ArmCallHvc (
IN OUT ARM_HVC_ARGS *Args
);
#endif
#endif // ARM_HVC_LIB_H_

View File

@ -2,14 +2,14 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __ARM_LIB__
#define __ARM_LIB__
#ifndef ARM_LIB_H_
#define ARM_LIB_H_
#include <Uefi/UefiBaseType.h>
@ -109,9 +109,37 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
// The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL 7
/** Reads the CCSIDR register for the specified cache.
@param CSSELR The CSSELR cache selection register value.
@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
Returns the contents of the CCSIDR register in AARCH32 mode.
**/
UINTN
ReadCCSIDR (
IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@param CSSELR The CSSELR cache selection register value
@return The contents of the CCSIDR2 register for the specified cache.
**/
UINT32
ReadCCSIDR2 (
IN UINT32 CSSELR
);
/** Reads the Cache Level ID (CLIDR) register.
@return The contents of the CLIDR_EL1 register.
**/
UINT32
ReadCLIDR (
VOID
);
UINTN
EFIAPI
@ -753,4 +781,4 @@ ArmHasSecurityExtensions (
);
#endif // MDE_CPU_ARM
#endif // __ARM_LIB__
#endif // ARM_LIB_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __ARM_MMU_LIB__
#define __ARM_MMU_LIB__
#ifndef ARM_MMU_LIB_H_
#define ARM_MMU_LIB_H_
#include <Uefi/UefiBaseType.h>
@ -64,4 +64,4 @@ ArmSetMemoryAttributes (
IN UINT64 Attributes
);
#endif
#endif // ARM_MMU_LIB_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_SMC_LIB__
#define __ARM_SMC_LIB__
#ifndef ARM_SMC_LIB_H_
#define ARM_SMC_LIB_H_
/**
* The size of the SMC arguments are different between AArch64 and AArch32.
@ -37,4 +37,4 @@ ArmCallSmc (
IN OUT ARM_SMC_ARGS *Args
);
#endif
#endif // ARM_SMC_LIB_H_

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_SVC_LIB__
#define __ARM_SVC_LIB__
#ifndef ARM_SVC_LIB_H_
#define ARM_SVC_LIB_H_
/**
* The size of the SVC arguments are different between AArch64 and AArch32.
@ -43,4 +43,4 @@ ArmCallSvc (
IN OUT ARM_SVC_ARGS *Args
);
#endif
#endif // ARM_SVC_LIB_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
#ifndef DEFAULT_EXCEPTION_HANDLER_LIB_H_
#define DEFAULT_EXCEPTION_HANDLER_LIB_H_
/**
This is the default action to take on an unexpected exception
@ -22,4 +22,4 @@ DefaultExceptionHandler (
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_

View File

@ -162,4 +162,74 @@ OemUpdateSmbiosInfo (
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);
/** Fetches the Type 32 boot information status.
@return Boot status.
**/
MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
EFIAPI
OemGetBootStatus (
VOID
);
/** Fetches the chassis status when it was last booted.
@return Chassis status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisBootupState (
VOID
);
/** Fetches the chassis power supply/supplies status when last booted.
@return Chassis power supply/supplies status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisPowerSupplyState (
VOID
);
/** Fetches the chassis thermal status when last booted.
@return Chassis thermal status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisThermalState (
VOID
);
/** Fetches the chassis security status when last booted.
@return Chassis security status.
**/
MISC_CHASSIS_SECURITY_STATE
EFIAPI
OemGetChassisSecurityStatus (
VOID
);
/** Fetches the chassis height in RMUs (Rack Mount Units).
@return The height of the chassis.
**/
UINT8
EFIAPI
OemGetChassisHeight (
VOID
);
/** Fetches the number of power cords.
@return The number of power cords.
**/
UINT8
EFIAPI
OemGetChassisNumPowerCords (
VOID
);
#endif // OEM_MISC_LIB_H_

View File

@ -2,13 +2,14 @@
OP-TEE specific header file.
Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _OPTEE_H_
#define _OPTEE_H_
#ifndef OPTEE_LIB_H_
#define OPTEE_LIB_H_
/*
* The 'Trusted OS Call UID' is supposed to return the following UUID for
@ -45,12 +46,14 @@ typedef struct {
UINT64 C;
} OPTEE_MESSAGE_PARAM_VALUE;
typedef union {
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION;
typedef struct {
UINT64 Attribute;
union {
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
} Union;
OPTEE_MESSAGE_PARAM_UNION Union;
} OPTEE_MESSAGE_PARAM;
#define OPTEE_MAX_CALL_PARAMS 4
@ -114,4 +117,4 @@ OpteeInvokeFunction (
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
);
#endif
#endif // OPTEE_LIB_H_

View File

@ -7,8 +7,8 @@
**/
#ifndef __SEMIHOSTING_H__
#define __SEMIHOSTING_H__
#ifndef SEMIHOSTING_LIB_H_
#define SEMIHOSTING_LIB_H_
/*
*
@ -129,4 +129,4 @@ SemihostSystem (
IN CHAR8 *CommandLine
);
#endif // __SEMIHOSTING_H__
#endif // SEMIHOSTING_LIB_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __STANDALONEMM_MMU_LIB__
#define __STANDALONEMM_MMU_LIB__
#ifndef STANDALONE_MM_MMU_LIB_
#define STANDALONE_MM_MMU_LIB_
EFI_STATUS
ArmSetMemoryRegionNoExec (
@ -33,4 +33,4 @@ ArmClearMemoryRegionReadOnly (
IN UINT64 Length
);
#endif /* __STANDALONEMM_MMU_LIB__ */
#endif /* STANDALONE_MM_MMU_LIB_ */

View File

@ -6,8 +6,8 @@
*
**/
#ifndef __ARM_MP_CORE_INFO_PPI_H__
#define __ARM_MP_CORE_INFO_PPI_H__
#ifndef ARM_MP_CORE_INFO_PPI_H_
#define ARM_MP_CORE_INFO_PPI_H_
#include <Guid/ArmMpCoreInfo.h>
@ -49,4 +49,4 @@ typedef struct {
extern EFI_GUID gArmMpCoreInfoPpiGuid;
extern EFI_GUID gArmMpCoreInfoGuid;
#endif
#endif // ARM_MP_CORE_INFO_PPI_H_

View File

@ -1,12 +1,12 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
System Control and Management Interface V1.0
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
@par Specification Reference:
- Arm System Control and Management Interface - Platform Design Document
(https://developer.arm.com/documentation/den0056/)
**/
#ifndef ARM_SCMI_BASE_PROTOCOL_H_
@ -14,7 +14,8 @@
#include <Protocol/ArmScmi.h>
#define BASE_PROTOCOL_VERSION 0x10000
#define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000
#define NUM_PROTOCOL_MASK 0xFFU
#define NUM_AGENT_MASK 0xFFU
@ -158,11 +159,10 @@ typedef struct _SCMI_BASE_PROTOCOL {
// SCMI Message IDs for Base protocol.
typedef enum {
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR = 0x3,
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR = 0x4,
SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION = 0x5,
SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS = 0x6
ScmiMessageIdBaseDiscoverVendor = 0x3,
ScmiMessageIdBaseDiscoverSubVendor = 0x4,
ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -89,10 +89,10 @@ EFI_STATUS
@param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates.

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -22,16 +22,16 @@ extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol.
typedef enum {
SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES = 0x3,
SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES = 0x4,
SCMI_MESSAGE_ID_CLOCK_RATE_SET = 0x5,
SCMI_MESSAGE_ID_CLOCK_RATE_GET = 0x6,
SCMI_MESSAGE_ID_CLOCK_CONFIG_SET = 0x7
ScmiMessageIdClockAttributes = 0x3,
ScmiMessageIdClockDescribeRates = 0x4,
ScmiMessageIdClockRateSet = 0x5,
ScmiMessageIdClockRateGet = 0x6,
ScmiMessageIdClockConfigSet = 0x7
} SCMI_MESSAGE_ID_CLOCK;
typedef enum {
SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range.
SCMI_CLOCK_RATE_FORMAT_LINEAR // Linear range.
ScmiClockRateFormatDiscrete, // Non-linear range.
ScmiClockRateFormatLinear // Linear range.
} SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version.
@ -57,12 +57,18 @@ typedef enum {
either Rate or Min/Max/Step triplet is valid.
*/
typedef struct {
union {
UINT64 Min;
UINT64 Rate;
};
UINT64 Max;
UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct {
UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE;
typedef union {
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE;
#pragma pack()
@ -133,10 +139,10 @@ EFI_STATUS
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
@param[in] ClockId Identifier for the clock device.
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
supports range of clock rates which are non-linear.
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
ScmiClockRateFormatLinear: Clock device supports
range of linear clock rates from Min to Max in steps.
@param[out] TotalRates Total number of rates.

View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -247,12 +247,12 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL {
} SCMI_PERFORMANCE_PROTOCOL;
typedef enum {
SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES = 0x3,
SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS = 0x4,
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET = 0x5,
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET = 0x6,
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET = 0x7,
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET = 0x8,
ScmiMessageIdPerformanceDomainAttributes = 0x3,
ScmiMessageIdPerformanceDescribeLevels = 0x4,
ScmiMessageIdPerformanceLimitsSet = 0x5,
ScmiMessageIdPerformanceLimitsGet = 0x6,
ScmiMessageIdPerformanceLevelSet = 0x7,
ScmiMessageIdPerformanceLevelGet = 0x8,
} SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */

View File

@ -1,7 +1,7 @@
/** @file
Generic ARM implementation of TimerLib.h
Copyright (c) 2011-2016, ARM Limited. All rights reserved.
Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -20,9 +20,9 @@
// Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM
#define MultU64xN MultU64x32
#define MULT_U64_X_N MultU64x32
#else
#define MultU64xN MultU64x64
#define MULT_U64_X_N MultU64x64
#endif
@ -121,7 +121,7 @@ MicroSecondDelay (
// = MicroSeconds x TICKS_PER_MICRO_SEC
// = MicroSeconds x Frequency.10^-6
TimerTicks64 = DivU64x32 (
MultU64xN (
MULT_U64_X_N (
MicroSeconds,
GetPlatformTimerFreq ()
),
@ -263,7 +263,7 @@ GetTimeInNanoSecond (
// Time = --------- x 1,000,000,000
// Frequency
//
NanoSeconds = MultU64xN (
NanoSeconds = MULT_U64_X_N (
DivU64x32Remainder (
Ticks,
TimerFreq,
@ -276,7 +276,7 @@ GetTimeInNanoSecond (
// will not overflow 64-bit.
//
NanoSeconds += DivU64x32 (
MultU64xN (
MULT_U64_X_N (
(UINT64) Remainder,
1000000000U),
TimerFreq

View File

@ -71,7 +71,7 @@ CHAR8 *gLdmStack[] = {
#define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_W) ((_W) ? "!" : "")
#define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
@ -159,23 +159,24 @@ DisassembleArmInstruction (
)
{
UINT32 OpCode;
CHAR8 *Type, *Root;
BOOLEAN I, P, U, B, W, L, S, H;
CHAR8 *Type;
CHAR8 *Root;
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
UINT32 Rn, Rd, Rm;
UINT32 imode, offset_8, offset_12;
UINT32 IMod, Offset8, Offset12;
UINT32 Index;
UINT32 shift_imm, shift;
UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr;
I = (OpCode & BIT25) == BIT25;
P = (OpCode & BIT24) == BIT24;
U = (OpCode & BIT23) == BIT23;
B = (OpCode & BIT22) == BIT22; // Also called S
W = (OpCode & BIT21) == BIT21;
L = (OpCode & BIT20) == BIT20;
S = (OpCode & BIT6) == BIT6;
H = (OpCode & BIT5) == BIT5;
Imm = (OpCode & BIT25) == BIT25; // I
Pre = (OpCode & BIT24) == BIT24; // P
Up = (OpCode & BIT23) == BIT23; // U
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
Write = (OpCode & BIT21) == BIT21; // W
Load = (OpCode & BIT20) == BIT20; // L
Sign = (OpCode & BIT6) == BIT6; // S
Half = (OpCode & BIT5) == BIT5; // H
Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf);
@ -189,7 +190,7 @@ DisassembleArmInstruction (
// LDREX, STREX
if ((OpCode & 0x0fe000f0) == 0x01800090) {
if (L) {
if (Load) {
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else {
@ -201,89 +202,89 @@ DisassembleArmInstruction (
// LDM/STM
if ((OpCode & 0x0e000000) == 0x08000000) {
if (L) {
if (Load) {
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
}
return;
}
// LDR/STR Address Mode 2
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
offset_12 = OpCode & 0xfff;
Offset12 = OpCode & 0xfff;
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD");
} else {
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
}
if (P) {
if (!I) {
if (Pre) {
if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>]
// A5.2.5 [<Rn>, #+/-<offset_12>]
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.3 [<Rn>, +/-<Rm>]
// A5.2.6 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
} else {
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
shift_imm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) {
ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
} else if (shift == 0x1) {
} else if (Shift == 0x1) {
Type = "LSR";
if (shift_imm == 0) {
shift_imm = 32;
if (ShiftImm == 0) {
ShiftImm = 32;
}
} else if (shift == 0x2) {
} else if (Shift == 0x2) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
} else if (ShiftImm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
return;
} else {
Type = "ROR";
}
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
}
} else { // !P
if (!I) {
} else { // !Pre
if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
// A5.2.9 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
} else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
shift_imm = (OpCode >> 7) & 0x1f;
shift = (OpCode >> 5) & 0x3;
ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3;
if (shift == 0x0) {
if (Shift == 0x0) {
Type = "LSL";
} else if (shift == 0x1) {
} else if (Shift == 0x1) {
Type = "LSR";
if (shift_imm == 0) {
shift_imm = 32;
if (ShiftImm == 0) {
ShiftImm = 32;
}
} else if (shift == 0x2) {
} else if (Shift == 0x2) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
} else if (ShiftImm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
// FIx me
return;
} else {
Type = "ROR";
}
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
}
}
return;
@ -292,18 +293,18 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x00000000) {
// LDR/STR address mode 3
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
if (L) {
if (!S) {
if (Load) {
if (!Sign) {
Root = "LDR%aH %a, ";
} else if (!H) {
} else if (!Half) {
Root = "LDR%aSB %a, ";
} else {
Root = "LDR%aSH %a, ";
}
} else {
if (!S) {
if (!Sign) {
Root = "STR%aH %a ";
} else if (!H) {
} else if (!Half) {
Root = "LDR%aD %a ";
} else {
Root = "STR%aD %a ";
@ -312,28 +313,28 @@ DisassembleArmInstruction (
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
S = (OpCode & BIT6) == BIT6;
H = (OpCode & BIT5) == BIT5;
offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (P & !W) {
Sign = (OpCode & BIT6) == BIT6;
Half = (OpCode & BIT5) == BIT5;
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (Pre & !Write) {
// Immediate offset/index
if (B) {
if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else {
// A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
}
} else {
// Register offset/index
if (B) {
if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else {
// A5.3.7 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
}
}
return;
@ -342,19 +343,19 @@ DisassembleArmInstruction (
if ((OpCode & 0x0fb000f0) == 0x01000050) {
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
return;
}
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
return;
}
if ((OpCode & 0xfe500f00) == 0xf8100500) {
// A4.1.59 RFE<addressing_mode> <Rn>{!}
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
return;
}
@ -369,9 +370,9 @@ DisassembleArmInstruction (
if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
imode = (OpCode >> 18) & 0x3;
IMod = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
(imode == 3) ? "ID":"IE",
(IMod == 3) ? "ID":"IE",
((OpCode & BIT8) != 0) ? "A":"",
((OpCode & BIT7) != 0) ? "I":"",
((OpCode & BIT6) != 0) ? "F":"");
@ -390,19 +391,19 @@ DisassembleArmInstruction (
if ((OpCode & 0x0fb00000) == 0x01000000) {
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
return;
}
if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (I) {
if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else {
// MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
}
return;
}
@ -416,35 +417,35 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) {
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
} else {
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
}
if (!P) {
if (!W) {
if (!Pre) {
if (!Write) {
// A5.5.5.5 [<Rn>], <option>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
}
} else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
}
}
if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return;
}

View File

@ -9,6 +9,7 @@
try to reuse existing case entries if possible.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -451,7 +452,7 @@ SignExtend32 (
// in the instruction address and you get back the aligned answer
//
UINT32
PCAlign4 (
PcAlign4 (
IN UINT32 Data
)
{
@ -486,12 +487,19 @@ DisassembleThumbInstruction (
UINT32 Index;
UINT32 Offset;
UINT16 Rd, Rn, Rm, Rt, Rt2;
BOOLEAN H1, H2, imod;
BOOLEAN H1Bit; // H1
BOOLEAN H2Bit; // H2
BOOLEAN IMod; // imod
//BOOLEAN ItFlag;
UINT32 PC, Target, msbit, lsbit;
UINT32 Pc, Target, MsBit, LsBit;
CHAR8 *Cond;
BOOLEAN S, J1, J2, P, U, W;
UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
BOOLEAN Sign; // S
BOOLEAN J1Bit; // J1
BOOLEAN J2Bit; // J2
BOOLEAN Pre; // P
BOOLEAN UAdd; // U
BOOLEAN WriteBack; // W
UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
UINT32 Mask;
OpCodePtr = *OpCodePtrPtr;
@ -504,10 +512,10 @@ DisassembleThumbInstruction (
Rd = OpCode & 0x7;
Rn = (OpCode >> 3) & 0x7;
Rm = (OpCode >> 6) & 0x7;
H1 = (OpCode & BIT7) != 0;
H2 = (OpCode & BIT6) != 0;
imod = (OpCode & BIT4) != 0;
PC = (UINT32)(UINTN)OpCodePtr;
H1Bit = (OpCode & BIT7) != 0;
H2Bit = (OpCode & BIT6) != 0;
IMod = (OpCode & BIT4) != 0;
Pc = (UINT32)(UINTN)OpCodePtr;
// Increment by the minimum instruction size, Thumb2 could be bigger
*OpCodePtrPtr += 1;
@ -548,7 +556,7 @@ DisassembleThumbInstruction (
case LOAD_STORE_FORMAT3:
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
Target = (OpCode & 0xff) << 2;
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
return;
case LOAD_STORE_FORMAT4:
// Rt, [SP, #imm8]
@ -583,16 +591,16 @@ DisassembleThumbInstruction (
Cond = gCondition[(OpCode >> 8) & 0xf];
Buf[Offset-5] = *Cond++;
Buf[Offset-4] = *Cond;
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
return;
case UNCONDITIONAL_BRANCH_SHORT:
// A6.3.2 B <target_address>
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
return;
case BRANCH_EXCHANGE:
// A6.3.3 BX|BLX <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
return;
case DATA_FORMAT1:
@ -629,12 +637,12 @@ DisassembleThumbInstruction (
return;
case DATA_FORMAT8:
// A6.4.3 <Rd>|<Rn>, <Rm>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
return;
case CPS_FORMAT:
// A7.1.24
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
return;
case ENDIAN_FORMAT:
@ -645,13 +653,13 @@ DisassembleThumbInstruction (
case DATA_CBZ:
// CB{N}Z <Rn>, <Lable>
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
return;
case ADR_FORMAT:
// ADR <Rd>, <Label>
Target = (OpCode & 0xff) << 2;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
return;
case IT_BLOCK:
@ -708,32 +716,32 @@ DisassembleThumbInstruction (
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
Target = SignExtend32 (Target, BIT20);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
return;
case B_T4:
// S:I1:I2:imm10:imm11:0
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
S = (OpCode32 & BIT26) == BIT26;
J1 = (OpCode32 & BIT13) == BIT13;
J2 = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2 ^ S) ? BIT22 : 0); // I2
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
Target |= (S ? BIT24 : 0); // S
Sign = (OpCode32 & BIT26) == BIT26;
J1Bit = (OpCode32 & BIT13) == BIT13;
J2Bit = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
Target |= (Sign ? BIT24 : 0); // S
Target = SignExtend32 (Target, BIT24);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
return;
case BL_T2:
// BLX S:I1:I2:imm10:imm11:0
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
S = (OpCode32 & BIT26) == BIT26;
J1 = (OpCode32 & BIT13) == BIT13;
J2 = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2 ^ S) ? BIT23 : 0); // I2
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
Target |= (S ? BIT25 : 0); // S
Sign = (OpCode32 & BIT26) == BIT26;
J1Bit = (OpCode32 & BIT13) == BIT13;
J2Bit = (OpCode32 & BIT11) == BIT11;
Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
Target |= (Sign ? BIT25 : 0); // S
Target = SignExtend32 (Target, BIT25);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
return;
case POP_T2:
@ -748,8 +756,8 @@ DisassembleThumbInstruction (
case STM_FORMAT:
// <Rn>{!}, <registers>
W = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
return;
case LDM_REG_IMM12_SIGNED:
@ -759,7 +767,7 @@ DisassembleThumbInstruction (
// U == 0 means subtrack, U == 1 means add
Target = -Target;
}
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
return;
case LDM_REG_INDIRECT_LSL:
@ -784,36 +792,36 @@ DisassembleThumbInstruction (
case LDM_REG_IMM8:
// <rt>, [<rn>, {, #<imm8>}]{!}
W = (OpCode32 & BIT8) == BIT8;
U = (OpCode32 & BIT9) == BIT9;
P = (OpCode32 & BIT10) == BIT10;
WriteBack = (OpCode32 & BIT8) == BIT8;
UAdd = (OpCode32 & BIT9) == BIT9;
Pre = (OpCode32 & BIT10) == BIT10;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
if (P) {
if (Pre) {
if ((OpCode32 & 0xff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
} else {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
}
} else {
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
}
return;
case LDRD_REG_IMM8_SIGNED:
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
P = (OpCode32 & BIT24) == BIT24; // index = P
U = (OpCode32 & BIT23) == BIT23;
W = (OpCode32 & BIT21) == BIT21;
Pre = (OpCode32 & BIT24) == BIT24; // index = P
UAdd = (OpCode32 & BIT23) == BIT23;
WriteBack = (OpCode32 & BIT21) == BIT21;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
if (P) {
if (Pre) {
if ((OpCode32 & 0xff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
}
} else {
if ((OpCode32 & 0xff) != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
}
}
return;
@ -825,7 +833,7 @@ DisassembleThumbInstruction (
// U == 0 means subtrack, U == 1 means add
Target = -Target;
}
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
return;
case LDREXB:
@ -840,14 +848,14 @@ DisassembleThumbInstruction (
case SRS_FORMAT:
// SP{!}, #<mode>
W = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);
WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
return;
case RFE_FORMAT:
// <Rn>{!}
W = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
WriteBack = (OpCode32 & BIT21) == BIT21;
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
return;
case ADD_IMM12:
@ -917,9 +925,9 @@ DisassembleThumbInstruction (
// ADDR <Rd>, <label>
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
Target = PCAlign4 (PC) - Target;
Target = PcAlign4 (Pc) - Target;
} else {
Target = PCAlign4 (PC) + Target;
Target = PcAlign4 (Pc) + Target;
}
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
return;
@ -932,52 +940,52 @@ DisassembleThumbInstruction (
case BFC_THUMB2:
// BFI <Rd>, <Rn>, #<lsb>, #<width>
msbit = OpCode32 & 0x1f;
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
MsBit = OpCode32 & 0x1f;
LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
// BFC <Rd>, #<lsb>, #<width>
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
} else {
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
}
return;
case CPD_THUMB2:
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf;
opc2 = (OpCode32 >> 5) & 0x7;
Coproc = (OpCode32 >> 8) & 0xf;
Opc1 = (OpCode32 >> 20) & 0xf;
Opc2 = (OpCode32 >> 5) & 0x7;
CRd = (OpCode32 >> 12) & 0xf;
CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
if (opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
if (Opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
}
return;
case MRC_THUMB2:
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf;
opc2 = (OpCode32 >> 5) & 0x7;
Coproc = (OpCode32 >> 8) & 0xf;
Opc1 = (OpCode32 >> 20) & 0xf;
Opc2 = (OpCode32 >> 5) & 0x7;
CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
if (opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
if (Opc2 != 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
}
return;
case MRRC_THUMB2:
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
coproc = (OpCode32 >> 8) & 0xf;
opc1 = (OpCode32 >> 20) & 0xf;
Coproc = (OpCode32 >> 8) & 0xf;
Opc1 = (OpCode32 >> 20) & 0xf;
CRn = (OpCode32 >> 16) & 0xf;
CRm = OpCode32 & 0xf;
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
return;
case THUMB2_2REGS:

View File

@ -2,6 +2,7 @@
* Exception Handling support specific for AArch64
*
* Copyright (c) 2016 HP Development Company, L.P.
* Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@ -27,7 +28,8 @@ RegisterEl0Stack (
IN VOID *Stack
);
RETURN_STATUS ArchVectorConfig(
RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress
)
{

View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>
// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
// Copyright (c) 2016 HP Development Company, L.P.
//
@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
//
// Current EL with SPx: 0x200 - 0x380
//
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)
ASM_PFX(SynchronousExceptionSPx):
ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)
ASM_PFX(IrqSPx):
ExceptionEntry EXCEPT_AARCH64_IRQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)
ASM_PFX(FiqSPx):
ExceptionEntry EXCEPT_AARCH64_FIQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)
ASM_PFX(SErrorSPx):
ExceptionEntry EXCEPT_AARCH64_SERROR

View File

@ -2,7 +2,7 @@
* Exception handling support specific for ARM
*
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
* Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
* Copyright (c) 2014 - 2021, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2016 HP Development Company, L.P.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@ -26,7 +26,8 @@ PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNME
// NOTE: This code assumes vectors are ARM and not Thumb code
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS ArchVectorConfig(
RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress
)
{

View File

@ -8,8 +8,8 @@
**/
#ifndef __AARCH64_LIB_H__
#define __AARCH64_LIB_H__
#ifndef AARCH64_LIB_H_
#define AARCH64_LIB_H_
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
@ -52,5 +52,5 @@ ArmReadIdAA64Mmfr2 (
VOID
);
#endif // __AARCH64_LIB_H__
#endif // AARCH64_LIB_H_

View File

@ -6,8 +6,8 @@
**/
#ifndef __ARM_V7_LIB_H__
#define __ARM_V7_LIB_H__
#ifndef ARM_V7_LIB_H_
#define ARM_V7_LIB_H_
#define ID_MMFR0_SHARELVL_SHIFT 12
#define ID_MMFR0_SHARELVL_MASK 0xf
@ -64,5 +64,5 @@ ArmReadIdPfr1 (
VOID
);
#endif // __ARM_V7_LIB_H__
#endif // ARM_V7_LIB_H_

View File

@ -8,8 +8,8 @@
**/
#ifndef __ARM_LIB_PRIVATE_H__
#define __ARM_LIB_PRIVATE_H__
#ifndef ARM_LIB_PRIVATE_H_
#define ARM_LIB_PRIVATE_H_
#define CACHE_SIZE_4_KB (3UL)
#define CACHE_SIZE_8_KB (4UL)
@ -52,101 +52,6 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
UINT32 InD :1; ///< Instruction not Data bit
UINT32 Level :3; ///< Cache level (zero based)
UINT32 TnD :1; ///< Allocation not Data bit
UINT32 Reserved :27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
typedef enum
{
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
CsselrCacheTypeInstruction,
CsselrCacheTypeMax
} CSSELR_CACHE_TYPE;
/// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :10; ///< Associativity - 1
UINT64 NumSets :15; ///< Number of sets in the cache -1
UINT64 Unknown :4; ///< Reserved, UNKNOWN
UINT64 Reserved :32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :21; ///< Associativity - 1
UINT64 Reserved1 :8; ///< Reserved, RES0
UINT64 NumSets :24; ///< Number of sets in the cache -1
UINT64 Reserved2 :8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
UINT64 LineSize : 3;
UINT64 Associativity : 21;
UINT64 Reserved : 8;
UINT64 Unallocated : 32;
} BitsCcidxAA32;
UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
UINT32 NumSets :24; ///< Number of sets in the cache - 1
UINT32 Reserved :8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
*
* The lower 32 bits are the same for both AARCH32 and AARCH64
* so we can use the same structure for both.
**/
typedef union {
struct {
UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
typedef enum {
/// No cache is present
ClidrCacheTypeNone = 0,
/// There is only an instruction cache
ClidrCacheTypeInstructionOnly,
/// There is only a data cache
ClidrCacheTypeDataOnly,
/// There are separate data and instruction caches
ClidrCacheTypeSeparate,
/// There is a unified cache
ClidrCacheTypeUnified,
ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
VOID
CPSRMaskInsert (
IN UINT32 Mask,
@ -158,32 +63,4 @@ CPSRRead (
VOID
);
/** Reads the CCSIDR register for the specified cache.
@param CSSELR The CSSELR cache selection register value.
@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
Returns the contents of the CCSIDR register in AARCH32 mode.
**/
UINTN
ReadCCSIDR (
IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@param CSSELR The CSSELR cache selection register value
@return The contents of the CCSIDR2 register for the specified cache.
**/
UINT32
ReadCCSIDR2 (
IN UINT32 CSSELR
);
UINT32
ReadCLIDR (
VOID
);
#endif // __ARM_LIB_PRIVATE_H__
#endif // ARM_LIB_PRIVATE_H_

View File

@ -124,7 +124,7 @@ UpdatePageEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// map to normal non-cachable
// map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes
@ -254,7 +254,7 @@ UpdateSectionEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// map to normal non-cachable
// map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes

View File

@ -1,11 +1,17 @@
/*
* Copyright (c) 2019, Linaro Limited
* Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*/
#ifndef ARM_SOFT_FLOAT_LIB_H_
#define ARM_SOFT_FLOAT_LIB_H_
#define LITTLEENDIAN 1
#define INLINE static inline
#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_FAST_INT64
#include "opts-GCC.h"
#endif // ARM_SOFT_FLOAT_LIB_H_

View File

@ -7,8 +7,8 @@
**/
#ifndef _OPTEE_SMC_H_
#define _OPTEE_SMC_H_
#ifndef OPTEE_SMC_H_
#define OPTEE_SMC_H_
/* Returned in Arg0 only from Trusted OS functions */
#define OPTEE_SMC_RETURN_OK 0x0
@ -47,4 +47,4 @@ typedef struct {
UINT8 Data4[8];
} RFC4122_UUID;
#endif
#endif // OPTEE_SMC_H_

View File

@ -9,8 +9,8 @@
**/
#ifndef _PLATFORM_BM_H_
#define _PLATFORM_BM_H_
#ifndef PLATFORM_BM_H_
#define PLATFORM_BM_H_
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
@ -50,4 +50,4 @@ DisableQuietBoot (
VOID
);
#endif // _PLATFORM_BM_H_
#endif // PLATFORM_BM_H_

View File

@ -37,11 +37,11 @@ SerialPortInitialize (
/**
Write data to serial device.
@param Buffer Point of data buffer which need to be writed.
@param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
@retval !0 Actual number of bytes written to serial device.
**/
@ -103,7 +103,7 @@ SerialPortWrite (
/**
Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.

View File

@ -44,7 +44,7 @@ SemihostFileOpen (
OpenBlock.Mode = Mode;
OpenBlock.NameLength = AsciiStrLen(FileName);
Result = Semihost_SYS_OPEN(&OpenBlock);
Result = SEMIHOST_SYS_OPEN (&OpenBlock);
if (Result == -1) {
return RETURN_NOT_FOUND;
@ -66,7 +66,7 @@ SemihostFileSeek (
SeekBlock.Handle = FileHandle;
SeekBlock.Location = Offset;
Result = Semihost_SYS_SEEK(&SeekBlock);
Result = SEMIHOST_SYS_SEEK (&SeekBlock);
// Semihosting does not behave as documented. It returns the offset on
// success.
@ -95,7 +95,7 @@ SemihostFileRead (
ReadBlock.Buffer = Buffer;
ReadBlock.Length = *Length;
Result = Semihost_SYS_READ(&ReadBlock);
Result = SEMIHOST_SYS_READ (&ReadBlock);
if ((*Length != 0) && (Result == *Length)) {
return RETURN_ABORTED;
@ -122,7 +122,7 @@ SemihostFileWrite (
WriteBlock.Buffer = Buffer;
WriteBlock.Length = *Length;
*Length = Semihost_SYS_WRITE(&WriteBlock);
*Length = SEMIHOST_SYS_WRITE (&WriteBlock);
if (*Length != 0)
return RETURN_ABORTED;
@ -135,7 +135,7 @@ SemihostFileClose (
IN UINTN FileHandle
)
{
if (Semihost_SYS_CLOSE (&FileHandle) == -1) {
if (SEMIHOST_SYS_CLOSE (&FileHandle) == -1) {
return RETURN_INVALID_PARAMETER;
} else {
return RETURN_SUCCESS;
@ -154,7 +154,7 @@ SemihostFileLength (
return RETURN_INVALID_PARAMETER;
}
Result = Semihost_SYS_FLEN(&FileHandle);
Result = SEMIHOST_SYS_FLEN (&FileHandle);
if (Result == -1) {
return RETURN_ABORTED;
@ -195,7 +195,7 @@ SemihostFileTmpName(
TmpNameBlock.Identifier = Identifier;
TmpNameBlock.Length = Length;
Result = Semihost_SYS_TMPNAME (&TmpNameBlock);
Result = SEMIHOST_SYS_TMPNAME (&TmpNameBlock);
if (Result != 0) {
return RETURN_ABORTED;
@ -220,7 +220,7 @@ SemihostFileRemove (
RemoveBlock.FileName = FileName;
RemoveBlock.NameLength = AsciiStrLen(FileName);
Result = Semihost_SYS_REMOVE(&RemoveBlock);
Result = SEMIHOST_SYS_REMOVE (&RemoveBlock);
if (Result == 0) {
return RETURN_SUCCESS;
@ -258,7 +258,7 @@ SemihostFileRename(
RenameBlock.NewFileName = NewFileName;
RenameBlock.NewFileNameLength = AsciiStrLen (NewFileName);
Result = Semihost_SYS_RENAME (&RenameBlock);
Result = SEMIHOST_SYS_RENAME (&RenameBlock);
if (Result != 0) {
return RETURN_ABORTED;
@ -272,7 +272,7 @@ SemihostReadCharacter (
VOID
)
{
return Semihost_SYS_READC();
return SEMIHOST_SYS_READC ();
}
VOID
@ -280,7 +280,7 @@ SemihostWriteCharacter (
IN CHAR8 Character
)
{
Semihost_SYS_WRITEC(&Character);
SEMIHOST_SYS_WRITEC (&Character);
}
VOID
@ -288,7 +288,7 @@ SemihostWriteString (
IN CHAR8 *String
)
{
Semihost_SYS_WRITE0(String);
SEMIHOST_SYS_WRITE0 (String);
}
UINT32
@ -301,5 +301,5 @@ SemihostSystem (
SystemBlock.CommandLine = CommandLine;
SystemBlock.CommandLength = AsciiStrLen(CommandLine);
return Semihost_SYS_SYSTEM(&SystemBlock);
return SEMIHOST_SYS_SYSTEM (&SystemBlock);
}

View File

@ -2,7 +2,7 @@
# Semihosting JTAG lib
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -25,6 +25,7 @@
#
[Sources.common]
SemihostLib.c
SemihostPrivate.h
[Sources.ARM]
Arm/GccSemihost.S | GCC

View File

@ -1,14 +1,14 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2013 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __SEMIHOST_PRIVATE_H__
#define __SEMIHOST_PRIVATE_H__
#ifndef SEMIHOST_PRIVATE_H_
#define SEMIHOST_PRIVATE_H_
typedef struct {
CHAR8 *FileName;
@ -151,19 +151,19 @@ _Semihost_SYS_SYSTEM(
IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
);
#define Semihost_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
#define Semihost_SYS_CLOSE(Handle) _Semihost_SYS_CLOSE(0x02, Handle)
#define Semihost_SYS_WRITE0(String) _Semihost_SYS_WRITE0(0x04, String)
#define Semihost_SYS_WRITEC(Character) _Semihost_SYS_WRITEC(0x03, Character)
#define Semihost_SYS_WRITE(WriteBlock) _Semihost_SYS_WRITE(0x05, WriteBlock)
#define Semihost_SYS_READ(ReadBlock) _Semihost_SYS_READ(0x06, ReadBlock)
#define Semihost_SYS_READC() _Semihost_SYS_READC(0x07, 0)
#define Semihost_SYS_SEEK(SeekBlock) _Semihost_SYS_SEEK(0x0A, SeekBlock)
#define Semihost_SYS_FLEN(Handle) _Semihost_SYS_FLEN(0x0C, Handle)
#define Semihost_SYS_TMPNAME(TmpNameBlock) _Semihost_SYS_TMPNAME(0x0D, TmpNameBlock)
#define Semihost_SYS_REMOVE(RemoveBlock) _Semihost_SYS_REMOVE(0x0E, RemoveBlock)
#define Semihost_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)
#define Semihost_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
#define SEMIHOST_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
#define SEMIHOST_SYS_CLOSE(Handle) _Semihost_SYS_CLOSE(0x02, Handle)
#define SEMIHOST_SYS_WRITE0(String) _Semihost_SYS_WRITE0(0x04, String)
#define SEMIHOST_SYS_WRITEC(Character) _Semihost_SYS_WRITEC(0x03, Character)
#define SEMIHOST_SYS_WRITE(WriteBlock) _Semihost_SYS_WRITE(0x05, WriteBlock)
#define SEMIHOST_SYS_READ(ReadBlock) _Semihost_SYS_READ(0x06, ReadBlock)
#define SEMIHOST_SYS_READC() _Semihost_SYS_READC(0x07, 0)
#define SEMIHOST_SYS_SEEK(SeekBlock) _Semihost_SYS_SEEK(0x0A, SeekBlock)
#define SEMIHOST_SYS_FLEN(Handle) _Semihost_SYS_FLEN(0x0C, Handle)
#define SEMIHOST_SYS_TMPNAME(TmpNameBlock) _Semihost_SYS_TMPNAME(0x0D, TmpNameBlock)
#define SEMIHOST_SYS_REMOVE(RemoveBlock) _Semihost_SYS_REMOVE(0x0E, RemoveBlock)
#define SEMIHOST_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)
#define SEMIHOST_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
#elif defined(__GNUC__) // __CC_ARM
@ -175,38 +175,38 @@ GccSemihostCall (
IN UINTN SystemBlockAddress
); // __attribute__ ((interrupt ("SVC")));
#define Semihost_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))
#define Semihost_SYS_CLOSE(Handle) GccSemihostCall(0x02, (UINTN)(Handle))
#define Semihost_SYS_WRITE0(String) GccSemihostCall(0x04, (UINTN)(String))
#define Semihost_SYS_WRITEC(Character) GccSemihostCall(0x03, (UINTN)(Character))
#define Semihost_SYS_WRITE(WriteBlock) GccSemihostCall(0x05, (UINTN)(WriteBlock))
#define Semihost_SYS_READ(ReadBlock) GccSemihostCall(0x06, (UINTN)(ReadBlock))
#define Semihost_SYS_READC() GccSemihostCall(0x07, (UINTN)(0))
#define Semihost_SYS_SEEK(SeekBlock) GccSemihostCall(0x0A, (UINTN)(SeekBlock))
#define Semihost_SYS_FLEN(Handle) GccSemihostCall(0x0C, (UINTN)(Handle))
#define Semihost_SYS_TMPNAME(TmpNameBlock) GccSemihostCall(0x0D, (UINTN)(TmpNameBlock))
#define Semihost_SYS_REMOVE(RemoveBlock) GccSemihostCall(0x0E, (UINTN)(RemoveBlock))
#define Semihost_SYS_RENAME(RenameBlock) GccSemihostCall(0x0F, (UINTN)(RenameBlock))
#define Semihost_SYS_SYSTEM(SystemBlock) GccSemihostCall(0x12, (UINTN)(SystemBlock))
#define SEMIHOST_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))
#define SEMIHOST_SYS_CLOSE(Handle) GccSemihostCall(0x02, (UINTN)(Handle))
#define SEMIHOST_SYS_WRITE0(String) GccSemihostCall(0x04, (UINTN)(String))
#define SEMIHOST_SYS_WRITEC(Character) GccSemihostCall(0x03, (UINTN)(Character))
#define SEMIHOST_SYS_WRITE(WriteBlock) GccSemihostCall(0x05, (UINTN)(WriteBlock))
#define SEMIHOST_SYS_READ(ReadBlock) GccSemihostCall(0x06, (UINTN)(ReadBlock))
#define SEMIHOST_SYS_READC() GccSemihostCall(0x07, (UINTN)(0))
#define SEMIHOST_SYS_SEEK(SeekBlock) GccSemihostCall(0x0A, (UINTN)(SeekBlock))
#define SEMIHOST_SYS_FLEN(Handle) GccSemihostCall(0x0C, (UINTN)(Handle))
#define SEMIHOST_SYS_TMPNAME(TmpNameBlock) GccSemihostCall(0x0D, (UINTN)(TmpNameBlock))
#define SEMIHOST_SYS_REMOVE(RemoveBlock) GccSemihostCall(0x0E, (UINTN)(RemoveBlock))
#define SEMIHOST_SYS_RENAME(RenameBlock) GccSemihostCall(0x0F, (UINTN)(RenameBlock))
#define SEMIHOST_SYS_SYSTEM(SystemBlock) GccSemihostCall(0x12, (UINTN)(SystemBlock))
#else // __CC_ARM
#define SEMIHOST_SUPPORTED FALSE
#define Semihost_SYS_OPEN(OpenBlock) (-1)
#define Semihost_SYS_CLOSE(Handle) (-1)
#define Semihost_SYS_WRITE0(String)
#define Semihost_SYS_WRITEC(Character)
#define Semihost_SYS_WRITE(WriteBlock) (0)
#define Semihost_SYS_READ(ReadBlock) ((ReadBlock)->Length)
#define Semihost_SYS_READC() ('x')
#define Semihost_SYS_SEEK(SeekBlock) (-1)
#define Semihost_SYS_FLEN(Handle) (-1)
#define Semihost_SYS_TMPNAME(TmpNameBlock) (-1)
#define Semihost_SYS_REMOVE(RemoveBlock) (-1)
#define Semihost_SYS_RENAME(RenameBlock) (-1)
#define Semihost_SYS_SYSTEM(SystemBlock) (-1)
#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
#define SEMIHOST_SYS_CLOSE(Handle) (-1)
#define SEMIHOST_SYS_WRITE0(String)
#define SEMIHOST_SYS_WRITEC(Character)
#define SEMIHOST_SYS_WRITE(WriteBlock) (0)
#define SEMIHOST_SYS_READ(ReadBlock) ((ReadBlock)->Length)
#define SEMIHOST_SYS_READC() ('x')
#define SEMIHOST_SYS_SEEK(SeekBlock) (-1)
#define SEMIHOST_SYS_FLEN(Handle) (-1)
#define SEMIHOST_SYS_TMPNAME(TmpNameBlock) (-1)
#define SEMIHOST_SYS_REMOVE(RemoveBlock) (-1)
#define SEMIHOST_SYS_RENAME(RenameBlock) (-1)
#define SEMIHOST_SYS_SYSTEM(SystemBlock) (-1)
#endif // __CC_ARM
#endif //__SEMIHOST_PRIVATE_H__
#endif // SEMIHOST_PRIVATE_H_

View File

@ -2,6 +2,7 @@
File managing the MMU for ARMv8 architecture in S-EL0
Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
Copyright (c) 2021, Linaro Limited
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
@ -62,7 +63,7 @@ SendMemoryPermissionRequest (
// for other Direct Request calls which are not atomic
// We therefore check only for Direct Response by the
// callee.
if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP) {
// A Direct Response means FF-A success
// Now check the payload for errors
// The callee sends back the return value
@ -101,8 +102,8 @@ SendMemoryPermissionRequest (
}
// Check error response from Callee.
if (*RetVal & BIT31) {
// Bit 31 set means there is an error retured
if ((*RetVal & BIT31) != 0) {
// Bit 31 set means there is an error returned
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and
// Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
switch (*RetVal) {
@ -164,13 +165,13 @@ GetMemoryPermissions (
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
} else {
SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = 0;
@ -219,15 +220,15 @@ RequestMemoryPermissionChange (
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
SvcArgs.Arg5 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg6 = Permissions;
} else {
SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg3 = Permissions;

View File

@ -1,6 +1,6 @@
#/** @file
#
# Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.
# Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -10,20 +10,20 @@
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = ArmMmuStandaloneMmCoreLib
FILE_GUID = da8f0232-fb14-42f0-922c-63104d2c70bd
FILE_GUID = 44a741c2-655f-41fc-b066-179f5a9aa78a
MODULE_TYPE = MM_CORE_STANDALONE
VERSION_STRING = 1.0
LIBRARY_CLASS = StandaloneMmMmuLib
PI_SPECIFICATION_VERSION = 0x00010032
[Sources.AARCH64]
AArch64/ArmMmuStandaloneMmLib.c
[Sources]
ArmMmuStandaloneMmLib.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[FeaturePcd.AARCH64]
[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable
[LibraryClasses]

View File

@ -139,3 +139,101 @@ OemUpdateSmbiosInfo (
{
ASSERT (FALSE);
}
/** Fetches the Type 32 boot information status.
@return Boot status.
**/
MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
EFIAPI
OemGetBootStatus (
VOID
)
{
ASSERT (FALSE);
return BootInformationStatusNoError;
}
/** Fetches the chassis status when it was last booted.
@return Chassis status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisBootupState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis power supply/supplies status when last booted.
@return Chassis power supply/supplies status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisPowerSupplyState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis thermal status when last booted.
@return Chassis thermal status.
**/
MISC_CHASSIS_STATE
EFIAPI
OemGetChassisThermalState (
VOID
)
{
ASSERT (FALSE);
return ChassisStateSafe;
}
/** Fetches the chassis security status when last booted.
@return Chassis security status.
**/
MISC_CHASSIS_SECURITY_STATE
EFIAPI
OemGetChassisSecurityStatus (
VOID
)
{
ASSERT (FALSE);
return ChassisSecurityStatusNone;
}
/** Fetches the chassis height in RMUs (Rack Mount Units).
@return The height of the chassis.
**/
UINT8
EFIAPI
OemGetChassisHeight (
VOID
)
{
ASSERT (FALSE);
return 1U;
}
/** Fetches the number of power cords.
@return The number of power cords.
**/
UINT8
EFIAPI
OemGetChassisNumPowerCords (
VOID
)
{
ASSERT (FALSE);
return 1;
}

View File

@ -10,11 +10,11 @@
#include <Uefi.h>
#include <Protocol/Smbios.h>
#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmSmcLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>

View File

@ -8,8 +8,8 @@
**/
#include <Uefi.h>
#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include "SmbiosProcessor.h"

View File

@ -8,8 +8,8 @@
**/
#include <Uefi.h>
#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include "SmbiosProcessor.h"

View File

@ -8,10 +8,10 @@
**/
#include <Uefi.h>
#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>

View File

@ -23,7 +23,7 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
0, // Length,
0 // Handle
},
1, // Manufactrurer
1, // Manufacturer
MiscChassisTypeMainServerChassis, // Type
2, // Version
3, // SerialNumber

View File

@ -39,6 +39,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
{
CHAR8 *OptionalStrStart;
CHAR8 *StrStart;
UINT8 *SkuNumberField;
UINTN RecordLength;
UINTN ManuStrLen;
UINTN VerStrLen;
@ -117,10 +118,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
ChaNumStrLen = StrLen (ChassisSkuNumber);
ContainedElementCount = InputData->ContainedElementCount;
if (ContainedElementCount > 1) {
ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT);
}
ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);
//
// Two zeros following the last string.
@ -149,7 +147,11 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
(VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength);
//ChassisSkuNumber
*((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5;
SkuNumberField = (UINT8 *)SmbiosRecord +
sizeof (SMBIOS_TABLE_TYPE3) -
sizeof (CONTAINED_ELEMENT) + ExtendLength;
*SkuNumberField = 5;
OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) +
ExtendLength + 1);
@ -162,6 +164,14 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1);
StrStart += AssertTagStrLen + 1;
UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1);
SmbiosRecord->BootupState = OemGetChassisBootupState ();
SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();
SmbiosRecord->ThermalState = OemGetChassisThermalState ();
SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();
SmbiosRecord->Height = OemGetChassisHeight ();
SmbiosRecord->NumberofPowerCords = OemGetChassisNumPowerCords ();
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//

View File

@ -23,9 +23,9 @@
/**
Get next language from language code list (with separator ';').
@param LangCode Input: point to first language in the list. On
Otput: point to next language in the list, or
NULL if no more language in the list.
@param LangCode Input: point to first language in the list. On
Output: point to next language in the list, or
NULL if no more language in the list.
@param Lang The first language in the list.
**/

View File

@ -16,6 +16,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/OemMiscLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include "SmbiosMisc.h"
@ -59,6 +60,8 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation)
SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);
SmbiosRecord->BootStatus = OemGetBootStatus ();
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//

View File

@ -0,0 +1,100 @@
## @file
# CI configuration for ArmPlatformPkg
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
## options defined .pytool/Plugin/LicenseCheck
"LicenseCheck": {
"IgnoreFiles": []
},
"EccCheck": {
## Exception sample looks like below:
## "ExceptionList": [
## "<ErrorID>", "<KeyWord>"
## ]
"ExceptionList": [
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
"Scripts/Ds5/"
]
},
## options defined .pytool/Plugin/CompilerPlugin
"CompilerPlugin": {
"DscPath": "ArmPlatformPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
"HostUnitTestCompilerPlugin": {
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/CharEncodingCheck
"CharEncodingCheck": {
"IgnoreFiles": []
},
## options defined .pytool/Plugin/DependencyCheck
"DependencyCheck": {
"AcceptableDependencies": [
"ArmPlatformPkg/ArmPlatformPkg.dec",
"ArmPkg/ArmPkg.dec",
"EmbeddedPkg/EmbeddedPkg.dec",
"MdeModulePkg/MdeModulePkg.dec",
"MdePkg/MdePkg.dec"
],
# For host based unit tests
"AcceptableDependencies-HOST_APPLICATION":[
"UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
],
# For UEFI shell based apps
"AcceptableDependencies-UEFI_APPLICATION":[],
"IgnoreInf": []
},
## options defined .pytool/Plugin/DscCompleteCheck
"DscCompleteCheck": {
"IgnoreInf": [],
"DscPath": "ArmPlatformPkg.dsc"
},
## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
"HostUnitTestDscCompleteCheck": {
"IgnoreInf": [""],
"DscPath": "" # Don't support this test
},
## options defined .pytool/Plugin/GuidCheck
"GuidCheck": {
"IgnoreGuidName": [],
"IgnoreGuidValue": [],
"IgnoreFoldersAndFiles": [],
"IgnoreDuplicates": [],
},
## options defined .pytool/Plugin/LibraryClassCheck
"LibraryClassCheck": {
"IgnoreHeaderFile": []
},
## options defined .pytool/Plugin/SpellCheck
"SpellCheck": {
"AuditOnly": True,
"IgnoreFiles": [], # use gitignore syntax to ignore errors
# in matching files
"ExtendWords": [
"hdlcd",
"icdsgir",
"primecells"
], # words to extend to the dictionary for this package
"IgnoreStandardPaths": [ # Standard Plugin defined paths that
"*.asm", "*.s" # should be ignore
],
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
}
}

View File

@ -1,6 +1,6 @@
#/** @file
#
# Copyright (c) 2011-2018, ARM Limited. All rights reserved.
# Copyright (c) 2011-2021, ARM Limited. All rights reserved.
# Copyright (c) 2015, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@ -26,11 +26,28 @@
Include # Root include for the package
[LibraryClasses]
## @libraryclass Provides an interface to query platform information.
#
ArmPlatformLib|Include/Library/ArmPlatformLib.h
## @libraryclass Provides an interface to initialize/shutdown a LCD screen.
#
LcdHwLib|Include/Library/LcdHwLib.h
## @libraryclass Provides an interface to configure a LCD screen.
#
LcdPlatformLib|Include/Library/LcdPlatformLib.h
## @libraryclass Provides a Nor flash interface.
#
NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
## @libraryclass Provides an interface to the clock of a PL011 device.
#
PL011UartClockLib|Include/Library/PL011UartClockLib.h
## @libraryclass Provides an interface to a PL011 uart.
#
PL011UartLib|Include/Library/PL011UartLib.h
[Guids.common]

View File

@ -33,6 +33,8 @@
gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
gArmTokenSpaceGuid.PcdFdSize|0x1000
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf

View File

@ -29,7 +29,6 @@
MdeModulePkg/MdeModulePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec
[LibraryClasses]
BaseLib

View File

@ -1,10 +1,10 @@
/** @file
*
* Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2016, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
Copyright (c) 2016, Linaro Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

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