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3 Commits

Author SHA1 Message Date
Bob Feng
8674aecb6a BaseTools: Fix the issue caused by tostring() removal on Py39
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3136

Python 3.9 remove the array.array.tostring and
array.array.fromstring() function. This patch
is to use other method to replace tostring() and
fromstring()

Signed-off-by: Bob Feng <bob.c.feng@intel.com>

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Mingyue Liang <mingyuex.liang@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2021-06-09 19:45:57 -06:00
Cole Robinson
563bd1f035 BaseTools: Work around array.array.tostring() removal in python 3.9
In python3, array.array.tostring() was a compat alias for tobytes().
tostring() was removed in python 3.9.

Convert this to use tolist() which should be valid for all python
versions.

This fixes this build error on python3.9:

(Python 3.9.0b5 on linux) Traceback (most recent call last):
  File "/root/edk2/edk2-edk2-stable202002/BaseTools/BinWrappers/PosixLike/../../Source/Python/Trim/Trim.py", line 593, in Main
    GenerateVfrBinSec(CommandOptions.ModuleName, CommandOptions.DebugDir, CommandOptions.OutputFile)
  File "/root/edk2/edk2-edk2-stable202002/BaseTools/BinWrappers/PosixLike/../../Source/Python/Trim/Trim.py", line 449, in GenerateVfrBinSec
    VfrUniOffsetList = GetVariableOffset(MapFileName, EfiFileName, VfrNameList)
  File "/root/edk2/edk2-edk2-stable202002/BaseTools/Source/Python/Common/Misc.py", line 88, in GetVariableOffset
    return _parseForGCC(lines, efifilepath, varnames)
  File "/root/edk2/edk2-edk2-stable202002/BaseTools/Source/Python/Common/Misc.py", line 151, in _parseForGCC
    efisecs = PeImageClass(efifilepath).SectionHeaderList
  File "/root/edk2/edk2-edk2-stable202002/BaseTools/Source/Python/Common/Misc.py", line 1638, in __init__
    if ByteArray.tostring() != b'PE\0\0':
AttributeError: 'array.array' object has no attribute 'tostring'

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-06-09 19:45:51 -06:00
Cole Robinson
2415686bbc BaseTools: fix ucs-2 lookup on python 3.9
python3.9 changed/fixed codec.register behavior to always replace
hyphen with underscore for passed in codec names:

  https://bugs.python.org/issue37751

So the custom Ucs2Search needs to be adapted to handle 'ucs_2' in
addition to existing 'ucs-2' for back compat.

This fixes test failures on python3.9, example:

======================================================================
FAIL: testUtf16InUniFile (CheckUnicodeSourceFiles.Tests)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/builddir/build/BUILD/edk2-edk2-stable202002/BaseTools/Source/Python/AutoGen/UniClassObject.py", line 375, in PreProcess
    FileIn = UniFileClassObject.OpenUniFile(LongFilePath(File.Path))
  File "/builddir/build/BUILD/edk2-edk2-stable202002/BaseTools/Source/Python/AutoGen/UniClassObject.py", line 303, in OpenUniFile
    UniFileClassObject.VerifyUcs2Data(FileIn, FileName, Encoding)
  File "/builddir/build/BUILD/edk2-edk2-stable202002/BaseTools/Source/Python/AutoGen/UniClassObject.py", line 312, in VerifyUcs2Data
    Ucs2Info = codecs.lookup('ucs-2')
LookupError: unknown encoding: ucs-2

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2021-06-09 19:45:43 -06:00
1426 changed files with 19643 additions and 140353 deletions

View File

@@ -7,10 +7,8 @@
##
trigger:
- master
- stable/*
pr:
- master
- stable/*
jobs:
- template: templates/pr-gate-build-job.yml

View File

@@ -5,7 +5,7 @@
# NOTE: This example monitors pull requests against the edk2-ci branch. Most
# environments would replace 'edk2-ci' with 'master'.
#
# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# https://github.com/tianocore
@@ -16,7 +16,6 @@ trigger: none
pr:
- master
- stable/*
pool:
vmImage: 'ubuntu-latest'

View File

@@ -6,11 +6,9 @@
##
trigger:
- master
- stable/*
pr:
- master
- stable/*
jobs:
- template: templates/pr-gate-build-job.yml

View File

@@ -51,15 +51,6 @@ steps:
# Set default
- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch)
displayName: fetch target branch
condition: eq(variables['Build.Reason'], 'PullRequest')
# trim the package list if this is a PR
- task: CmdLine@1
displayName: Check if ${{ parameters.build_pkg }} need testing

View File

@@ -4,7 +4,6 @@
# template file used to build supported packages.
#
# Copyright (c) Microsoft Corporation.
# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -31,17 +30,17 @@ jobs:
Build.Pkgs: 'MdeModulePkg'
Build.Targets: 'RELEASE,NO-TARGET'
TARGET_NETWORK:
Build.Pkgs: 'NetworkPkg,RedfishPkg'
Build.Pkgs: 'NetworkPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
TARGET_OTHER:
Build.Pkgs: 'PcAtChipsetPkg,ShellPkg,StandaloneMmPkg'
Build.Pkgs: 'PcAtChipsetPkg,ShellPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
TARGET_FMP_FAT_TEST:
Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg,DynamicTablesPkg'
Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
TARGET_CRYPTO:
Build.Pkgs: 'CryptoPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
TARGET_SECURITY:
Build.Pkgs: 'SecurityPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'

View File

@@ -31,15 +31,6 @@ steps:
echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
# Use altername cmocka repo
- bash: git config --global url.https://github.com/neverware-mirrors/cmocka.git.insteadOf https://git.cryptomilk.org/projects/cmocka.git
# Fetch the target branch so that pr_eval can diff them.
# Seems like azure pipelines/github changed checkout process in nov 2020.
- script: git fetch origin $(System.PullRequest.targetBranch)
displayName: fetch target branch
condition: eq(variables['Build.Reason'], 'PullRequest')
# trim the package list if this is a PR
- task: CmdLine@1
displayName: Check if ${{ parameters.build_pkgs }} need testing

3
.gitmodules vendored
View File

@@ -17,6 +17,3 @@
path = BaseTools/Source/C/BrotliCompress/brotli
url = https://github.com/google/brotli
ignore = untracked
[submodule "RedfishPkg/Library/JsonLib/jansson"]
path = RedfishPkg/Library/JsonLib/jansson
url = https://github.com/akheron/jansson

View File

@@ -38,7 +38,6 @@ Jim Dailey <Jim.Dailey@Dell.com>
Jim Dailey <Jim.Dailey@Dell.com> <Jim_Dailey@Dell.com>
Laszlo Ersek <lersek@redhat.com> <lersek@6f19259b-4bc3-4df7-8a09-765794883524>
Laszlo Ersek <lersek@redhat.com> <lersek@Edk2>
Liming Gao <gaoliming@byosoft.com.cn>
Liming Gao <liming.gao@intel.com> <Gao, Liming liming.gao@intel.com>
Liming Gao <liming.gao@intel.com> <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>
Liming Gao <liming.gao@intel.com> <lgao4@Edk2>
@@ -48,7 +47,6 @@ Marc-André Lureau <marcandre.lureau@redhat.com> <marcandre.lureau@redhat.com>
Marvin Häuser <Marvin.Haeuser@outlook.com>
Marvin Häuser <Marvin.Haeuser@outlook.com> edk2-devel <edk2-devel-bounces@lists.01.org>
Marvin Häuser <mhaeuser@outlook.de>
Matt DeVillier <matt.devillier@gmail.com>
Maurice Ma <maurice.ma@intel.com>
Michael Kubacki <michael.a.kubacki@intel.com>
Michael Kubacki <michael.a.kubacki@intel.com> </o=Intel/ou=External (FYDIBOHF25SPDLT)/cn=Recipients/cn=3c8b0226e75f4ab08d20c151cb7a8a72>
@@ -62,20 +60,14 @@ Ray Ni <ray.ni@intel.com> <niruiyu@Edk2>
Ray Ni <ray.ni@intel.com> <ruiyu.ni@intel.com>
Ray Ni <ray.ni@intel.com> <Ruiyu.ni@Intel.com>
Ray Ni <ray.ni@intel.com> <ruyu.ni@intel.com>
Rebecca Cran <rebecca@bluestop.org>
Rebecca Cran <rebecca@bsdio.com>
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <elhaj@hpe.com>
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <Samer El-Haj-Mahmoud elhaj@hp.com>
Shenglei Zhang <shenglei.zhang@intel.com>
Star Zeng <star.zeng@intel.com>
Star Zeng <star.zeng@intel.com> <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524>
Star Zeng <star.zeng@intel.com> <lzeng14@Edk2>
Tom Lendacky <thomas.lendacky@amd.com>
Vitaly Cheptsov <vit9696@protonmail.com> Vitaly Cheptsov via Groups.Io <vit9696=protonmail.com@groups.io>
Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Vladimir Olovyannikov via edk2-devel <edk2-devel@lists.01.org>
Wei6 Xu <wei6.xu@intel.com>
Yonghong Zhu <yonghong.zhu@intel.com>
Yonghong Zhu <yonghong.zhu@intel.com> <yzhu52@Edk2>
Yu-Chen Lin <yuchenlin@synology.com>
Zhichao Gao <zhichao.gao@intel.com>
Zhiguang Liu <zhiguang.liu@intel.com>

View File

@@ -16,7 +16,7 @@
# * This file must be checked into the 'default' branch of a repo. Copies
# of this file on other branches of a repo are ignored by Mergify.
#
# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# https://github.com/apps/mergify
@@ -28,7 +28,7 @@ pull_request_rules:
- name: Automatically merge a PR when all required checks pass and 'push' label is present
conditions:
- base~=(^master|^stable/)
- base=master
- label=push
- author=@tianocore/edk-ii-maintainers
- status-success=tianocore.PatchCheck
@@ -41,7 +41,7 @@ pull_request_rules:
- name: Automatically close a PR when all required checks pass and 'push' label is not present
conditions:
- base~=(^master|^stable/)
- base=master
- -label=push
- -closed
- status-success=tianocore.PatchCheck
@@ -55,7 +55,7 @@ pull_request_rules:
- name: Post a comment on a PR that can not be merged due to a merge conflict
conditions:
- base~=(^master|^stable/)
- base=master
- conflict
actions:
comment:
@@ -63,7 +63,7 @@ pull_request_rules:
- name: Automatically close a PR that fails the EDK II Maintainers membership check and 'push' label is present
conditions:
- base~=(^master|^stable/)
- base=master
- label=push
- -author=@tianocore/edk-ii-maintainers
actions:
@@ -72,7 +72,7 @@ pull_request_rules:
- name: Post a comment on a PR if PatchCheck fails
conditions:
- base~=(^master|^stable/)
- base=master
- status-failure=tianocore.PatchCheck
actions:
comment:
@@ -80,7 +80,7 @@ pull_request_rules:
- name: Post a comment on a PR if Ubuntu GCC5 fails
conditions:
- base~=(^master|^stable/)
- base=master
- status-failure=Ubuntu GCC5 PR
- status-success=Ubuntu GCC5 PR (FAILED)
actions:
@@ -89,7 +89,7 @@ pull_request_rules:
- name: Post a comment on a PR if Windows VS2019 fails
conditions:
- base~=(^master|^stable/)
- base=master
- status-failure=Windows VS2019 PR
- status-success=Windows VS2019 PR (FAILED)
actions:

View File

@@ -2,7 +2,6 @@
#
# Copyright (c) Microsoft Corporation.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import os
@@ -22,24 +21,16 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
self.ActualTargets = []
self.ActualArchitectures = []
self.ActualToolChainTag = ""
self.UseBuiltInBaseTools = None
self.ActualScopes = None
# ####################################################################################### #
# Extra CmdLine configuration #
# ####################################################################################### #
def AddCommandLineOptions(self, parserObj):
group = parserObj.add_mutually_exclusive_group()
group.add_argument("-force_piptools", "--fpt", dest="force_piptools", action="store_true", default=False, help="Force the system to use pip tools")
group.add_argument("-no_piptools", "--npt", dest="no_piptools", action="store_true", default=False, help="Force the system to not use pip tools")
pass
def RetrieveCommandLineOptions(self, args):
super().RetrieveCommandLineOptions(args)
if args.force_piptools:
self.UseBuiltInBaseTools = True
if args.no_piptools:
self.UseBuiltInBaseTools = False
pass
# ####################################################################################### #
# Default Support for this Ci Build #
@@ -50,7 +41,6 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
These should be edk2 workspace relative paths '''
return ("ArmVirtPkg",
"DynamicTablesPkg",
"EmulatorPkg",
"MdePkg",
"MdeModulePkg",
@@ -60,12 +50,10 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
"UefiCpuPkg",
"FmpDevicePkg",
"ShellPkg",
"StandaloneMmPkg",
"FatPkg",
"CryptoPkg",
"UnitTestFrameworkPkg",
"OvmfPkg",
"RedfishPkg"
"OvmfPkg"
)
def GetArchitecturesSupported(self):
@@ -136,38 +124,19 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
def GetActiveScopes(self):
''' return tuple containing scopes that should be active for this process '''
if self.ActualScopes is None:
scopes = ("cibuild", "edk2-build", "host-based-test")
scopes = ("cibuild", "edk2-build", "host-based-test")
self.ActualToolChainTag = shell_environment.GetBuildVars().GetValue("TOOL_CHAIN_TAG", "")
self.ActualToolChainTag = shell_environment.GetBuildVars().GetValue("TOOL_CHAIN_TAG", "")
is_linux = GetHostInfo().os.upper() == "LINUX"
if GetHostInfo().os.upper() == "LINUX" and self.ActualToolChainTag.upper().startswith("GCC"):
if "AARCH64" in self.ActualArchitectures:
scopes += ("gcc_aarch64_linux",)
if "ARM" in self.ActualArchitectures:
scopes += ("gcc_arm_linux",)
if "RISCV64" in self.ActualArchitectures:
scopes += ("gcc_riscv64_unknown",)
if self.UseBuiltInBaseTools is None:
is_linux = GetHostInfo().os.upper() == "LINUX"
# try and import the pip module for basetools
try:
import edk2basetools
self.UseBuiltInBaseTools = True
except ImportError:
self.UseBuiltInBaseTools = False
pass
if self.UseBuiltInBaseTools == True:
scopes += ('pipbuild-unix',) if is_linux else ('pipbuild-win',)
logging.warning("Using Pip Tools based BaseTools")
else:
logging.warning("Falling back to using in-tree BaseTools")
if is_linux and self.ActualToolChainTag.upper().startswith("GCC"):
if "AARCH64" in self.ActualArchitectures:
scopes += ("gcc_aarch64_linux",)
if "ARM" in self.ActualArchitectures:
scopes += ("gcc_arm_linux",)
if "RISCV64" in self.ActualArchitectures:
scopes += ("gcc_riscv64_unknown",)
self.ActualScopes = scopes
return self.ActualScopes
return scopes
def GetRequiredSubmodules(self):
''' return iterable containing RequiredSubmodule objects.
@@ -186,8 +155,6 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
"MdeModulePkg/Library/BrotliCustomDecompressLib/brotli", False))
rs.append(RequiredSubmodule(
"BaseTools/Source/C/BrotliCompress/brotli", False))
rs.append(RequiredSubmodule(
"RedfishPkg/Library/JsonLib/jansson", False))
return rs
def GetName(self):

View File

@@ -1,309 +0,0 @@
# @file EccCheck.py
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import os
import shutil
import re
import csv
import xml.dom.minidom
from typing import List, Dict, Tuple
import logging
from io import StringIO
from edk2toolext.environment import shell_environment
from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
from edk2toolext.environment.var_dict import VarDict
from edk2toollib.utility_functions import RunCmd
class EccCheck(ICiBuildPlugin):
"""
A CiBuildPlugin that finds the Ecc issues of newly added code in pull request.
Configuration options:
"EccCheck": {
"ExceptionList": [],
"IgnoreFiles": []
},
"""
ReModifyFile = re.compile(r'[B-Q,S-Z]+[\d]*\t(.*)')
FindModifyFile = re.compile(r'\+\+\+ b\/(.*)')
LineScopePattern = (r'@@ -\d*\,*\d* \+\d*\,*\d* @@.*')
LineNumRange = re.compile(r'@@ -\d*\,*\d* \+(\d*)\,*(\d*) @@.*')
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
""" Provide the testcase name and classname for use in reporting
testclassname: a descriptive string for the testcase can include whitespace
classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
Args:
packagename: string containing name of package to build
environment: The VarDict for the test to run in
Returns:
a tuple containing the testcase name and the classname
(testcasename, classname)
"""
return ("Check for efi coding style for " + packagename, packagename + ".EccCheck")
##
# External function of plugin. This function is used to perform the task of the ci_build_plugin Plugin
#
# - package is the edk2 path to package. This means workspace/packagepath relative.
# - edk2path object configured with workspace and packages path
# - PkgConfig Object (dict) for the pkg
# - EnvConfig Object
# - Plugin Manager Instance
# - Plugin Helper Obj Instance
# - Junit Logger
# - output_stream the StringIO output stream from this plugin via logging
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
edk2_path = Edk2pathObj.WorkspacePath
python_path = os.path.join(edk2_path, "BaseTools", "Source", "Python")
env = shell_environment.GetEnvironment()
env.set_shell_var('PYTHONPATH', python_path)
env.set_shell_var('WORKSPACE', edk2_path)
self.ECC_PASS = True
self.ApplyConfig(pkgconfig, edk2_path, packagename)
modify_dir_list = self.GetModifyDir(packagename)
patch = self.GetDiff(packagename)
ecc_diff_range = self.GetDiffRange(patch, packagename, edk2_path)
self.GenerateEccReport(modify_dir_list, ecc_diff_range, edk2_path)
ecc_log = os.path.join(edk2_path, "Ecc.log")
self.RevertCode()
if self.ECC_PASS:
tc.SetSuccess()
self.RemoveFile(ecc_log)
return 0
else:
with open(ecc_log, encoding='utf8') as output:
ecc_output = output.readlines()
for line in ecc_output:
logging.error(line.strip())
self.RemoveFile(ecc_log)
tc.SetFailed("EccCheck failed for {0}".format(packagename), "Ecc detected issues")
return 1
def RevertCode(self) -> None:
submoudle_params = "submodule update --init"
RunCmd("git", submoudle_params)
reset_params = "reset HEAD --hard"
RunCmd("git", reset_params)
def GetDiff(self, pkg: str) -> List[str]:
return_buffer = StringIO()
params = "diff --unified=0 origin/master HEAD"
RunCmd("git", params, outstream=return_buffer)
p = return_buffer.getvalue().strip()
patch = p.split("\n")
return_buffer.close()
return patch
def RemoveFile(self, file: str) -> None:
if os.path.exists(file):
os.remove(file)
return
def GetModifyDir(self, pkg: str) -> List[str]:
return_buffer = StringIO()
params = "diff --name-status" + ' HEAD' + ' origin/master'
RunCmd("git", params, outstream=return_buffer)
p1 = return_buffer.getvalue().strip()
dir_list = p1.split("\n")
return_buffer.close()
modify_dir_list = []
for modify_dir in dir_list:
file_path = self.ReModifyFile.findall(modify_dir)
if file_path:
file_dir = os.path.dirname(file_path[0])
else:
continue
if pkg in file_dir and file_dir != pkg:
modify_dir_list.append('%s' % file_dir)
else:
continue
modify_dir_list = list(set(modify_dir_list))
return modify_dir_list
def GetDiffRange(self, patch_diff: List[str], pkg: str, workingdir: str) -> Dict[str, List[Tuple[int, int]]]:
IsDelete = True
StartCheck = False
range_directory: Dict[str, List[Tuple[int, int]]] = {}
for line in patch_diff:
modify_file = self.FindModifyFile.findall(line)
if modify_file and pkg in modify_file[0] and not StartCheck and os.path.isfile(modify_file[0]):
modify_file_comment_dic = self.GetCommentRange(modify_file[0], workingdir)
IsDelete = False
StartCheck = True
modify_file_dic = modify_file[0]
modify_file_dic = modify_file_dic.replace("/", os.sep)
range_directory[modify_file_dic] = []
elif line.startswith('--- '):
StartCheck = False
elif re.match(self.LineScopePattern, line, re.I) and not IsDelete and StartCheck:
start_line = self.LineNumRange.search(line).group(1)
line_range = self.LineNumRange.search(line).group(2)
if not line_range:
line_range = '1'
range_directory[modify_file_dic].append((int(start_line), int(start_line) + int(line_range) - 1))
for i in modify_file_comment_dic:
if int(i[0]) <= int(start_line) <= int(i[1]):
range_directory[modify_file_dic].append(i)
return range_directory
def GetCommentRange(self, modify_file: str, workingdir: str) -> List[Tuple[int, int]]:
modify_file_path = os.path.join(workingdir, modify_file)
with open(modify_file_path) as f:
line_no = 1
comment_range: List[Tuple[int, int]] = []
Start = False
for line in f:
if line.startswith('/**'):
start_no = line_no
Start = True
if line.startswith('**/') and Start:
end_no = line_no
Start = False
comment_range.append((int(start_no), int(end_no)))
line_no += 1
if comment_range and comment_range[0][0] == 1:
del comment_range[0]
return comment_range
def GenerateEccReport(self, modify_dir_list: List[str], ecc_diff_range: Dict[str, List[Tuple[int, int]]],
edk2_path: str) -> None:
ecc_need = False
ecc_run = True
config = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "config.ini")
exception = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "exception.xml")
report = os.path.join(edk2_path, "Ecc.csv")
for modify_dir in modify_dir_list:
target = os.path.join(edk2_path, modify_dir)
logging.info('Run ECC tool for the commit in %s' % modify_dir)
ecc_need = True
ecc_params = "-c {0} -e {1} -t {2} -r {3}".format(config, exception, target, report)
return_code = RunCmd("Ecc", ecc_params, workingdir=edk2_path)
if return_code != 0:
ecc_run = False
break
if not ecc_run:
logging.error('Fail to run ECC tool')
self.ParseEccReport(ecc_diff_range, edk2_path)
if not ecc_need:
logging.info("Doesn't need run ECC check")
revert_params = "checkout -- {}".format(exception)
RunCmd("git", revert_params)
return
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], edk2_path: str) -> None:
ecc_log = os.path.join(edk2_path, "Ecc.log")
ecc_csv = "Ecc.csv"
file = os.listdir(edk2_path)
row_lines = []
ignore_error_code = self.GetIgnoreErrorCode()
if ecc_csv in file:
with open(ecc_csv) as csv_file:
reader = csv.reader(csv_file)
for row in reader:
for modify_file in ecc_diff_range:
if modify_file in row[3]:
for i in ecc_diff_range[modify_file]:
line_no = int(row[4])
if i[0] <= line_no <= i[1] and row[1] not in ignore_error_code:
row[0] = '\nEFI coding style error'
row[1] = 'Error code: ' + row[1]
row[3] = 'file: ' + row[3]
row[4] = 'Line number: ' + row[4]
row_line = '\n *'.join(row)
row_lines.append(row_line)
break
break
if row_lines:
self.ECC_PASS = False
with open(ecc_log, 'a') as log:
all_line = '\n'.join(row_lines)
all_line = all_line + '\n'
log.writelines(all_line)
return
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], edk2_path: str, pkg: str) -> None:
if "IgnoreFiles" in pkgconfig:
for a in pkgconfig["IgnoreFiles"]:
a = os.path.join(edk2_path, pkg, a)
a = a.replace(os.sep, "/")
logging.info("Ignoring Files {0}".format(a))
if os.path.exists(a):
if os.path.isfile(a):
self.RemoveFile(a)
elif os.path.isdir(a):
shutil.rmtree(a)
else:
logging.error("EccCheck.IgnoreInf -> {0} not found in filesystem. Invalid ignore files".format(a))
if "ExceptionList" in pkgconfig:
exception_list = pkgconfig["ExceptionList"]
exception_xml = os.path.join(edk2_path, "BaseTools", "Source", "Python", "Ecc", "exception.xml")
try:
logging.info("Appending exceptions")
self.AppendException(exception_list, exception_xml)
except Exception as e:
logging.error("Fail to apply exceptions")
raise e
return
def AppendException(self, exception_list: List[str], exception_xml: str) -> None:
error_code_list = exception_list[::2]
keyword_list = exception_list[1::2]
dom_tree = xml.dom.minidom.parse(exception_xml)
root_node = dom_tree.documentElement
for error_code, keyword in zip(error_code_list, keyword_list):
customer_node = dom_tree.createElement("Exception")
keyword_node = dom_tree.createElement("KeyWord")
keyword_node_text_value = dom_tree.createTextNode(keyword)
keyword_node.appendChild(keyword_node_text_value)
customer_node.appendChild(keyword_node)
error_code_node = dom_tree.createElement("ErrorID")
error_code_text_value = dom_tree.createTextNode(error_code)
error_code_node.appendChild(error_code_text_value)
customer_node.appendChild(error_code_node)
root_node.appendChild(customer_node)
with open(exception_xml, 'w') as f:
dom_tree.writexml(f, indent='', addindent='', newl='\n', encoding='UTF-8')
return
def GetIgnoreErrorCode(self) -> set:
"""
Below are kinds of error code that are accurate in ecc scanning of edk2 level.
But EccCheck plugin is partial scanning so they are always false positive issues.
The mapping relationship of error code and error message is listed BaseTools/Sourc/Python/Ecc/EccToolError.py
"""
ignore_error_code = {
"10000",
"10001",
"10002",
"10003",
"10004",
"10005",
"10006",
"10007",
"10008",
"10009",
"10010",
"10011",
"10012",
"10013",
"10015",
"10016",
"10017",
"10022",
}
return ignore_error_code

View File

@@ -1,11 +0,0 @@
## @file
# CiBuildPlugin used to check Ecc issues
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
"scope": "cibuild",
"name": "EccCheck Test",
"module": "EccCheck"
}

View File

@@ -1,15 +0,0 @@
# EFI Coding style Check Plugin
This CiBuildPlugin finds the Ecc issues of newly added code in pull request.
## Configuration
The plugin can be configured to ignore certain files and issues.
"EccCheck": {
"ExceptionList": [],
"IgnoreFiles": []
},
"""
OPTIONAL List of file to ignore.

View File

@@ -1,115 +0,0 @@
# @file LicenseCheck.py
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import os
import logging
import re
from io import StringIO
from typing import List, Tuple
from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
from edk2toolext.environment.var_dict import VarDict
from edk2toollib.utility_functions import RunCmd
class LicenseCheck(ICiBuildPlugin):
"""
A CiBuildPlugin to check the license for new added files.
Configuration options:
"LicenseCheck": {
"IgnoreFiles": []
},
"""
license_format_preflix = 'SPDX-License-Identifier'
bsd2_patent = 'BSD-2-Clause-Patent'
Readdedfileformat = re.compile(r'\+\+\+ b\/(.*)')
file_extension_list = [".c", ".h", ".inf", ".dsc", ".dec", ".py", ".bat", ".sh", ".uni", ".yaml",
".fdf", ".inc", "yml", ".asm", ".asm16", ".asl", ".vfr", ".s", ".S", ".aslc",
".nasm", ".nasmb", ".idf", ".Vfr", ".H"]
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
""" Provide the testcase name and classname for use in reporting
testclassname: a descriptive string for the testcase can include whitespace
classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
Args:
packagename: string containing name of package to build
environment: The VarDict for the test to run in
Returns:
a tuple containing the testcase name and the classname
(testcasename, classname)
"""
return ("Check for license for " + packagename, packagename + ".LicenseCheck")
##
# External function of plugin. This function is used to perform the task of the ci_build_plugin Plugin
#
# - package is the edk2 path to package. This means workspace/packagepath relative.
# - edk2path object configured with workspace and packages path
# - PkgConfig Object (dict) for the pkg
# - EnvConfig Object
# - Plugin Manager Instance
# - Plugin Helper Obj Instance
# - Junit Logger
# - output_stream the StringIO output stream from this plugin via logging
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
return_buffer = StringIO()
params = "diff --unified=0 origin/master HEAD"
RunCmd("git", params, outstream=return_buffer)
p = return_buffer.getvalue().strip()
patch = p.split("\n")
return_buffer.close()
ignore_files = []
if "IgnoreFiles" in pkgconfig:
ignore_files = pkgconfig["IgnoreFiles"]
self.ok = True
self.startcheck = False
self.license = True
self.all_file_pass = True
count = len(patch)
line_index = 0
for line in patch:
if line.startswith('--- /dev/null'):
nextline = patch[line_index + 1]
added_file = self.Readdedfileformat.search(nextline).group(1)
added_file_extension = os.path.splitext(added_file)[1]
if added_file_extension in self.file_extension_list and packagename in added_file:
if (self.IsIgnoreFile(added_file, ignore_files)):
line_index = line_index + 1
continue
self.startcheck = True
self.license = False
if self.startcheck and self.license_format_preflix in line:
if self.bsd2_patent in line:
self.license = True
if line_index + 1 == count or patch[line_index + 1].startswith('diff --') and self.startcheck:
if not self.license:
self.all_file_pass = False
error_message = "Invalid license in: " + added_file + " Hint: Only BSD-2-Clause-Patent is accepted."
logging.error(error_message)
self.startcheck = False
self.license = True
line_index = line_index + 1
if self.all_file_pass:
tc.SetSuccess()
return 0
else:
tc.SetFailed("License Check {0} Failed. ".format(packagename), "LICENSE_CHECK_FAILED")
return 1
def IsIgnoreFile(self, file: str, ignore_files: List[str]) -> bool:
for f in ignore_files:
if f in file:
return True
return False

View File

@@ -1,11 +0,0 @@
## @file
# CiBuildPlugin used to check license issues for new added files
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
"scope": "cibuild",
"name": "License Check Test",
"module": "LicenseCheck"
}

View File

@@ -1,17 +0,0 @@
# License Check Plugin
This CiBuildPlugin scans all new added files in a package to make sure code
is contributed under BSD-2-Clause-Patent.
## Configuration
The plugin can be configured to ignore certain files.
``` yaml
"LicenseCheck": {
"IgnoreFiles": []
}
```
### IgnoreFiles
OPTIONAL List of file to ignore.

View File

@@ -178,6 +178,5 @@
"vcruntimed",
"ucrtd",
"msvcrtd",
"XIPFLAGS"
]
}

View File

@@ -8,7 +8,7 @@
| ArmPlatformPkg |
| ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README |
| CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
| DynamicTablesPkg | | :heavy_check_mark: |
| DynamicTablesPkg |
| EmbeddedPkg |
| EmulatorPkg | SEE PACKAGE README | SEE PACKAGE README | Spell checking in audit mode
| FatPkg | :heavy_check_mark: | :heavy_check_mark: |
@@ -24,7 +24,7 @@
| ShellPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 3 modules are not being built by DSC
| SignedCapsulePkg |
| SourceLevelDebugPkg |
| StandaloneMmPkg | :heavy_check_mark: | :heavy_check_mark: |
| StandaloneMmPkg |
| UefiCpuPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 2 binary modules not being built by DSC
| UefiPayloadPkg |
| UnitTestFrameworkPkg | :heavy_check_mark: | :heavy_check_mark: |

View File

@@ -84,13 +84,6 @@
# hardware coherency (i.e., no virtualization or cache coherent DMA)
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
[PcdsFeatureFlag.AARCH64]
## Used to select method for requesting services from S-EL1.<BR><BR>
# TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
# FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
# @Prompt Enable FF-A support.
gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
@@ -122,20 +115,6 @@
# The Primary Core is ClusterId[0] & CoreId[0]
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
#
# SMBIOS PCDs
#
gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
#
# ARM L2x0 PCDs
#
@@ -236,9 +215,6 @@
gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
[PcdsFixedAtBuild.common, PcdsDynamic.common]
#
# ARM Architectural Timer

View File

@@ -29,9 +29,6 @@
RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
[PcdsFixedAtBuild]
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
[LibraryClasses.common]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -84,8 +81,6 @@
ArmMtlLib|ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -147,11 +142,8 @@
ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
[Components.AARCH64]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf

View File

@@ -25,13 +25,10 @@
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
#define ISENABLER_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))
#define ICENABLER_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
#define IPRIORITY_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))
/**
*
@@ -202,50 +199,6 @@ ArmGicEndOfInterrupt (
}
}
VOID
EFIAPI
ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate register offset and bit position
RegOffset = Source / 4;
RegShift = (Source % 4) * 8;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) {
MmioAndThenOr32 (
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
Priority << RegShift
);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
Revision
);
if (GicCpuRedistributorBase == 0) {
return;
}
MmioAndThenOr32 (
IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),
~(0xff << RegShift),
Priority << RegShift
);
}
}
VOID
EFIAPI
ArmGicEnableInterrupt (

View File

@@ -374,6 +374,8 @@ GicV3DxeInitialize (
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT64 CpuTarget;
UINT64 MpId;
@@ -395,11 +397,12 @@ GicV3DxeInitialize (
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
// Set Priority
ArmGicSetInterruptPriority (
mGicDistributorBase,
mGicRedistributorsBase,
Index,
ARM_GIC_DEFAULT_PRIORITY
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}

View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -161,9 +161,8 @@ ScmiProtocolDiscoveryCommon (
)
{
SCMI_COMMAND Command;
UINT32 PayloadLength;
UINT32 PayloadLength = 0;
PayloadLength = 0;
Command.ProtocolId = ProtocolId;
Command.MessageId = MessageId;

View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -189,14 +189,12 @@ ClockDescribeRates (
CLOCK_DESCRIBE_RATES *DescribeRates;
CLOCK_RATE_DWORD *Rate;
UINT32 RequiredArraySize;
UINT32 RateIndex;
UINT32 RequiredArraySize = 0;
UINT32 RateIndex = 0;
UINT32 RateNo;
UINT32 RateOffset;
*TotalRates = 0;
RequiredArraySize = 0;
RateIndex = 0;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {

View File

@@ -2,7 +2,7 @@
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -189,7 +189,7 @@ SyncCacheConfig (
)
{
EFI_STATUS Status;
UINT32 PageAttribute;
UINT32 PageAttribute = 0;
UINT64 *FirstLevelTableAddress;
UINTN TableLevel;
UINTN TableCount;
@@ -282,12 +282,12 @@ EfiAttributeToArmAttribute (
ArmAttributes |= TT_AF;
// Determine protection attributes
if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
if (EfiAttributes & EFI_MEMORY_RO) {
ArmAttributes |= TT_AP_RO_RO;
}
// Process eXecute Never attribute
if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
if (EfiAttributes & EFI_MEMORY_XP) {
ArmAttributes |= TT_PXN_MASK;
}

View File

@@ -2,7 +2,7 @@
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -155,8 +155,8 @@ SyncCacheConfigPage (
EFI_STATUS Status;
UINT32 i;
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
UINT32 NextPageAttributes;
UINT32 PageAttributes;
UINT32 NextPageAttributes = 0;
UINT32 PageAttributes = 0;
UINT32 BaseAddress;
UINT64 GcdAttributes;
@@ -226,8 +226,8 @@ SyncCacheConfig (
UINT32 i;
EFI_PHYSICAL_ADDRESS NextRegionBase;
UINT64 NextRegionLength;
UINT32 NextSectionAttributes;
UINT32 SectionAttributes;
UINT32 NextSectionAttributes = 0;
UINT32 SectionAttributes = 0;
UINT64 GcdAttributes;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINTN NumberOfDescriptors;
@@ -366,14 +366,14 @@ EfiAttributeToArmAttribute (
}
// Determine protection attributes
if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
if (EfiAttributes & EFI_MEMORY_RO) {
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
} else {
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
}
// Determine eXecute Never attribute
if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
if (EfiAttributes & EFI_MEMORY_XP) {
ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
}

View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -14,8 +14,7 @@
EFI_STATUS
InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu
)
{
) {
EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
@@ -93,8 +92,7 @@ EFI_STATUS
RegisterInterruptHandler(
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
) {
// pass down to CpuExceptionHandlerLib
return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
}

View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
Copyright (c) 2016-2019, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -96,7 +96,7 @@ MmCommunication2Communicate (
sizeof (CommunicateHeader->MessageLength);
// If the length of the CommBuffer is 0 then return the expected length.
if (CommSize != 0) {
if (CommSize) {
// This case can be used by the consumer of this driver to find out the
// max size that can be used for allocating CommBuffer.
if ((*CommSize == 0) ||

View File

@@ -1,7 +1,7 @@
/** @file
Timer Architecture Protocol driver of the ARM flavor
Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
Copyright (c) 2011-2013 ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -307,7 +307,7 @@ TimerInterruptHandler (
// Check if the timer interrupt is active
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
if (mTimerNotifyFunction != 0) {
if (mTimerNotifyFunction) {
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
}
@@ -359,7 +359,7 @@ TimerInitialize (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle;
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINTN TimerCtrlReg;
UINT32 TimerHypIntrNum;
@@ -408,7 +408,6 @@ TimerInitialize (
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status);
Handle = NULL;
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,

View File

@@ -2,7 +2,7 @@
Support a Semi Host file system over a debuggers JTAG
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -90,9 +90,8 @@ AllocateFCB (
VOID
)
{
SEMIHOST_FCB *Fcb;
SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
if (Fcb != NULL) {
CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));
Fcb->Signature = SEMIHOST_FCB_SIGNATURE;
@@ -123,7 +122,7 @@ VolumeOpen (
OUT EFI_FILE **Root
)
{
SEMIHOST_FCB *RootFcb;
SEMIHOST_FCB *RootFcb = NULL;
if (Root == NULL) {
return EFI_INVALID_PARAMETER;
@@ -197,8 +196,8 @@ FileOpen (
return EFI_INVALID_PARAMETER;
}
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
((Attributes & EFI_FILE_DIRECTORY) != 0)) {
if ((OpenMode & EFI_FILE_MODE_CREATE) &&
(Attributes & EFI_FILE_DIRECTORY) ) {
return EFI_WRITE_PROTECTED;
}
@@ -235,7 +234,7 @@ FileOpen (
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
if (RETURN_ERROR (Return)) {
if ((OpenMode & EFI_FILE_MODE_CREATE) != 0) {
if (OpenMode & EFI_FILE_MODE_CREATE) {
//
// In the create if does not exist case, if the opening in update
// mode failed, create it and open it in update mode. The update
@@ -278,8 +277,7 @@ FileOpen (
FileFcb->Info.FileSize = Length;
FileFcb->Info.PhysicalSize = Length;
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
Attributes : 0;
FileFcb->Info.Attribute = (OpenMode & EFI_FILE_MODE_CREATE) ? Attributes : 0;
InsertTailList (&gFileList, &FileFcb->Link);
@@ -760,13 +758,12 @@ GetFileInfo (
OUT VOID *Buffer
)
{
EFI_FILE_INFO *Info;
UINTN NameSize;
EFI_FILE_INFO *Info = NULL;
UINTN NameSize = 0;
UINTN ResultSize;
UINTN Index;
if (Fcb->IsRoot) {
NameSize = 0;
if (Fcb->IsRoot == TRUE) {
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
} else {
NameSize = AsciiStrLen (Fcb->FileName) + 1;
@@ -786,7 +783,7 @@ GetFileInfo (
// Fill in the structure
Info->Size = ResultSize;
if (Fcb->IsRoot) {
if (Fcb->IsRoot == TRUE) {
Info->FileName[0] = L'\0';
} else {
for (Index = 0; Index < NameSize; Index++) {

View File

@@ -112,10 +112,6 @@
#define ARM_VECTOR_LOW_A32_FIQ 0x700
#define ARM_VECTOR_LOW_A32_SERR 0x780
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
// build for ARMv8.0, we need to define the register here.
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \
.align 11; \

View File

@@ -1,44 +0,0 @@
/** @file
Header file for FF-A ABI's that will be used for
communication between S-EL0 and the Secure Partition
Manager(SPM)
Copyright (c) 2020, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- FF-A Version 1.0
**/
#ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
#define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0
#define ARM_FFA_SPM_RET_SUCCESS 0
#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
#define ARM_FFA_SPM_RET_NO_MEMORY -3
#define ARM_FFA_SPM_RET_BUSY -4
#define ARM_FFA_SPM_RET_INTERRUPTED -5
#define ARM_FFA_SPM_RET_DENIED -6
#define ARM_FFA_SPM_RET_RETRY -7
#define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added
// to get the endpoint id's dynamically
// This is the endpoint id used by the optee os's implementation
// of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_

View File

@@ -41,7 +41,4 @@
#define ARM_SVC_SPM_RET_DENIED -3
#define ARM_SVC_SPM_RET_NO_MEMORY -5
#define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1
#endif

View File

@@ -1,13 +1,9 @@
/** @file
*
* Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
* Copyright (c) 2012-2017, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
* @par Revision Reference:
* - SMC Calling Convention version 1.2
* (https://developer.arm.com/documentation/den0028/c/?lang=en)
**/
#ifndef __ARM_STD_SMC_H__
@@ -56,18 +52,6 @@
#define ARM_SMC_MM_RET_DENIED -3
#define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls
#define SMCCC_VERSION 0x80000000
#define SMCCC_ARCH_FEATURES 0x80000001
#define SMCCC_ARCH_SOC_ID 0x80000002
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
#define SMC_ARCH_CALL_NOT_REQUIRED -2
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
/*
* Power State Coordination Interface (PSCI) calls cover a subset of the
* Standard Service Call range.

View File

@@ -208,15 +208,6 @@ ArmGicSetPriorityMask (
IN INTN PriorityMask
);
VOID
EFIAPI
ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
);
VOID
EFIAPI
ArmGicEnableInterrupt (

View File

@@ -2,7 +2,6 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -109,10 +108,6 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
// The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL 7
UINTN
EFIAPI
ArmDataCacheLineLength (
@@ -137,6 +132,18 @@ ArmIsArchTimerImplemented (
VOID
);
UINTN
EFIAPI
ArmReadIdPfr0 (
VOID
);
UINTN
EFIAPI
ArmReadIdPfr1 (
VOID
);
UINTN
EFIAPI
ArmCacheInfo (
@@ -708,49 +715,4 @@ ArmGetPhysicalAddressBits (
VOID
);
///
/// ID Register Helper functions
///
/**
Check whether the CPU supports the GIC system register interface (any version)
@return Whether GIC System Register Interface is supported
**/
BOOLEAN
EFIAPI
ArmHasGicSystemRegisters (
VOID
);
/** Checks if CCIDX is implemented.
@retval TRUE CCIDX is implemented.
@retval FALSE CCIDX is not implemented.
**/
BOOLEAN
EFIAPI
ArmHasCcidx (
VOID
);
#ifdef MDE_CPU_ARM
///
/// AArch32-only ID Register Helper functions
///
/**
Check whether the CPU supports the Security extensions
@return Whether the Security extensions are implemented
**/
BOOLEAN
EFIAPI
ArmHasSecurityExtensions (
VOID
);
#endif // MDE_CPU_ARM
#endif // __ARM_LIB__

View File

@@ -27,16 +27,10 @@ typedef struct {
/**
Trigger an SVC call
SVC calls can take up to 8 arguments and return up to 8 return values.
Therefore, the 8 first fields in the ARM_SVC_ARGS structure are used
SVC calls can take up to 7 arguments and return up to 4 return values.
Therefore, the 4 first fields in the ARM_SVC_ARGS structure are used
for both input and output values.
@param[in, out] Args Arguments to be passed as part of the SVC call
The return values of the SVC call are also placed
in the same structure
@retval None
**/
VOID
ArmCallSvc (

View File

@@ -1,165 +0,0 @@
/** @file
*
* Copyright (c) 2021, NUVIA Inc. All rights reserved.
* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
* Copyright (c) 2015, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef OEM_MISC_LIB_H_
#define OEM_MISC_LIB_H_
#include <Uefi.h>
#include <IndustryStandard/SmBios.h>
typedef enum
{
CpuCacheL1 = 1,
CpuCacheL2,
CpuCacheL3,
CpuCacheL4,
CpuCacheL5,
CpuCacheL6,
CpuCacheL7,
CpuCacheLevelMax
} OEM_MISC_CPU_CACHE_LEVEL;
typedef struct
{
UINT8 Voltage; ///< Processor voltage
UINT16 CurrentSpeed; ///< Current clock speed in MHz
UINT16 MaxSpeed; ///< Maximum clock speed in MHz
UINT16 ExternalClock; ///< External clock speed in MHz
UINT16 CoreCount; ///< Number of cores available
UINT16 CoresEnabled; ///< Number of cores enabled
UINT16 ThreadCount; ///< Number of threads per processor
} OEM_MISC_PROCESSOR_DATA;
typedef enum
{
ProductNameType01,
SerialNumType01,
UuidType01,
SystemManufacturerType01,
SkuNumberType01,
FamilyType01,
AssertTagType02,
SerialNumberType02,
BoardManufacturerType02,
SkuNumberType02,
ChassisLocationType02,
AssetTagType03,
SerialNumberType03,
VersionType03,
ChassisTypeType03,
ManufacturerType03,
SkuNumberType03,
SmbiosHiiStringFieldMax
} OEM_MISC_SMBIOS_HII_STRING_FIELD;
/*
* The following are functions that the each platform needs to
* implement in its OemMiscLib library.
*/
/** Gets the CPU frequency of the specified processor.
@param ProcessorIndex Index of the processor to get the frequency for.
@return CPU frequency in Hz
**/
UINTN
EFIAPI
OemGetCpuFreq (
IN UINT8 ProcessorIndex
);
/** Gets information about the specified processor and stores it in
the structures provided.
@param ProcessorIndex Index of the processor to get the information for.
@param ProcessorStatus Processor status.
@param ProcessorCharacteristics Processor characteritics.
@param MiscProcessorData Miscellaneous processor information.
@return TRUE on success, FALSE on failure.
**/
BOOLEAN
EFIAPI
OemGetProcessorInformation (
IN UINTN ProcessorIndex,
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
);
/** Gets information about the cache at the specified cache level.
@param ProcessorIndex The processor to get information for.
@param CacheLevel The cache level to get information for.
@param DataCache Whether the cache is a data cache.
@param UnifiedCache Whether the cache is a unified cache.
@param SmbiosCacheTable The SMBIOS Type7 cache information structure.
@return TRUE on success, FALSE on failure.
**/
BOOLEAN
EFIAPI
OemGetCacheInformation (
IN UINT8 ProcessorIndex,
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
);
/** Gets the maximum number of processors supported by the platform.
@return The maximum number of processors.
**/
UINT8
EFIAPI
OemGetMaxProcessors (
VOID
);
/** Gets the type of chassis for the system.
@retval The type of the chassis.
**/
MISC_CHASSIS_TYPE
EFIAPI
OemGetChassisType (
VOID
);
/** Returns whether the specified processor is present or not.
@param ProcessIndex The processor index to check.
@return TRUE is the processor is present, FALSE otherwise.
**/
BOOLEAN
EFIAPI
OemIsProcessorPresent (
IN UINTN ProcessorIndex
);
/** Updates the HII string for the specified field.
@param HiiHandle The HII handle.
@param TokenToUpdate The string to update.
@param Field The field to get information about.
**/
VOID
EFIAPI
OemUpdateSmbiosInfo (
IN EFI_HII_HANDLE HiiHandle,
IN EFI_STRING_ID TokenToUpdate,
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);
#endif // OEM_MISC_LIB_H_

View File

@@ -56,7 +56,7 @@ TimerConstructor (
// If the security extension is not implemented, set Timer Frequency
// here.
//
if (ArmHasSecurityExtensions ()) {
if ((ArmReadIdPfr1 () & ARM_PFR1_SEC) == 0x0) {
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
}
#endif

View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,14 +20,11 @@ CacheRangeOperation (
IN UINTN LineLength
)
{
UINTN ArmCacheLineAlignmentMask;
// Align address (rounding down)
UINTN AlignedAddress;
UINTN EndAddress;
UINTN ArmCacheLineAlignmentMask = LineLength - 1;
ArmCacheLineAlignmentMask = LineLength - 1;
AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
EndAddress = (UINTN)Start + Length;
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {

View File

@@ -2,7 +2,6 @@
Default exception handler
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -158,7 +157,7 @@ DisassembleArmInstruction (
IN BOOLEAN Extended
)
{
UINT32 OpCode;
UINT32 OpCode = **OpCodePtr;
CHAR8 *Type, *Root;
BOOLEAN I, P, U, B, W, L, S, H;
UINT32 Rn, Rd, Rm;
@@ -166,8 +165,6 @@ DisassembleArmInstruction (
UINT32 Index;
UINT32 shift_imm, shift;
OpCode = **OpCodePtr;
I = (OpCode & BIT25) == BIT25;
P = (OpCode & BIT24) == BIT24;
U = (OpCode & BIT23) == BIT23;
@@ -243,7 +240,7 @@ DisassembleArmInstruction (
if (shift_imm == 0) {
shift_imm = 32;
}
} else if (shift == 0x2) {
} else if (shift == 0x12) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
@@ -273,7 +270,7 @@ DisassembleArmInstruction (
if (shift_imm == 0) {
shift_imm = 32;
}
} else if (shift == 0x2) {
} else if (shift == 0x12) {
Type = "ASR";
} else if (shift_imm == 0) {
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
@@ -370,11 +367,7 @@ DisassembleArmInstruction (
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
imode = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
(imode == 3) ? "ID":"IE",
((OpCode & BIT8) != 0) ? "A":"",
((OpCode & BIT7) != 0) ? "I":"",
((OpCode & BIT6) != 0) ? "F":"");
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":"");
if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
}

View File

@@ -19,8 +19,7 @@ EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] =
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
#define EL0_STACK_PAGES 2
VOID
RegisterEl0Stack (
@@ -32,11 +31,14 @@ RETURN_STATUS ArchVectorConfig(
)
{
UINTN HcrReg;
UINT8 *Stack;
// Round down sp by 16 bytes alignment
RegisterEl0Stack (
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
);
Stack = AllocatePages (EL0_STACK_PAGES);
if (Stack == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
RegisterEl0Stack ((UINT8 *)Stack + EFI_PAGES_TO_SIZE (EL0_STACK_PAGES));
if (ArmReadCurrentEL() == AARCH64_EL2) {
HcrReg = ArmReadHcr();

View File

@@ -2,7 +2,7 @@
* Main file supporting the SEC Phase for Versatile Express
*
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
* Copyright (c) 2016 HP Development Company, L.P.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -253,8 +253,7 @@ RETURN_STATUS
RegisterCpuInterruptHandler(
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
)
{
) {
if (ExceptionType > gMaxExceptionNumber) {
return RETURN_UNSUPPORTED;
}

View File

@@ -25,7 +25,7 @@ ArmGicArchLibInitialize (
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmHasGicSystemRegisters ()) {
if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need

View File

@@ -0,0 +1,60 @@
/** @file
*
* Copyright (c) 2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS
EFIAPI
ArmGicArchLibInitialize (
VOID
)
{
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
if (!(IccSre & ICC_SRE_EL2_SRE)) {
ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done;
}
}
mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
Done:
return RETURN_SUCCESS;
}
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
VOID
)
{
return mGicArchRevision;
}

View File

@@ -14,8 +14,11 @@
LIBRARY_CLASS = ArmGicArchLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
CONSTRUCTOR = ArmGicArchLibInitialize
[Sources]
ArmGicArchLib.c
[Sources.ARM]
Arm/ArmGicArchLib.c
[Sources.AARCH64]
AArch64/ArmGicArchLib.c
[Packages]
MdePkg/MdePkg.dec

View File

@@ -23,7 +23,7 @@ ArmGicGetSupportedArchRevision (
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmHasGicSystemRegisters ()) {
if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need

View File

@@ -0,0 +1,45 @@
/** @file
*
* Copyright (c) 2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
VOID
)
{
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
if (!(IccSre & ICC_SRE_EL2_SRE)) {
ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
return ARM_GIC_ARCH_REVISION_2;
}

View File

@@ -13,8 +13,11 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmGicArchLib|SEC
[Sources]
ArmGicArchLib.c
[Sources.ARM]
Arm/ArmGicArchLib.c
[Sources.AARCH64]
AArch64/ArmGicArchLib.c
[Packages]
MdePkg/MdePkg.dec

View File

@@ -2,7 +2,6 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -72,35 +71,3 @@ ArmCleanDataCache (
ArmDataSynchronizationBarrier ();
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
/**
Check whether the CPU supports the GIC system register interface (any version)
@return Whether GIC System Register Interface is supported
**/
BOOLEAN
EFIAPI
ArmHasGicSystemRegisters (
VOID
)
{
return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) != 0);
}
/** Checks if CCIDX is implemented.
@retval TRUE CCIDX is implemented.
@retval FALSE CCIDX is not implemented.
**/
BOOLEAN
EFIAPI
ArmHasCcidx (
VOID
)
{
UINTN Mmfr2;
Mmfr2 = ArmReadIdAA64Mmfr2 ();
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
}

View File

@@ -2,7 +2,6 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -36,21 +35,5 @@ ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINTN SetWayFormat
);
UINTN
EFIAPI
ArmReadIdAA64Pfr0 (
VOID
);
/** Reads the ID_AA64MMFR2_EL1 register.
@return The contents of the ID_AA64MMFR2_EL1 register.
**/
UINTN
EFIAPI
ArmReadIdAA64Mmfr2 (
VOID
);
#endif // __AARCH64_LIB_H__

View File

@@ -3,7 +3,6 @@
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
# Copyright (c) 2020, NUVIA Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -396,7 +395,7 @@ ASM_FUNC(ArmReadVBar)
ASM_FUNC(ArmEnableVFP)
// Check whether floating-point is implemented in the processor.
mov x1, x30 // Save LR
bl ArmReadIdAA64Pfr0 // Read EL1 Processor Feature Register (PFR0)
bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)
mov x30, x1 // Restore LR
ubfx x0, x0, #16, #4 // Extract the FP bits 16:19
cmp x0, #0xF // Check if FP bits are '1111b',
@@ -425,9 +424,6 @@ ASM_FUNC(ArmCallWFI)
wfi
ret
ASM_FUNC(ArmReadIdAA64Mmfr2)
mrs x0, ID_AA64MMFR2_EL1 // read EL1 MMFR2
ret
ASM_FUNC(ArmReadMpidr)
mrs x0, mpidr_el1 // read EL1 MPIDR
@@ -452,11 +448,19 @@ ASM_FUNC(ArmIsArchTimerImplemented)
ret
ASM_FUNC(ArmReadIdAA64Pfr0)
ASM_FUNC(ArmReadIdPfr0)
mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
ret
// Q: id_aa64pfr1_el1 not defined yet. What does this function want to access?
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
// See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
// Not defined yet, but stick in here for now, should read all zeros.
ASM_FUNC(ArmReadIdPfr1)
mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register
ret
// VOID ArmWriteHcr(UINTN Hcr)
ASM_FUNC(ArmWriteHcr)
msr hcr_el2, x0 // Write the passed HCR value

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@@ -84,7 +84,7 @@ ASM_FUNC(ArmDisableAllExceptions)
ret
// UINTN
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )

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@@ -60,11 +60,7 @@ ASM_FUNC(ArmDisableInterrupts)
isb
bx LR
ASM_FUNC(ArmReadIdMmfr4)
mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register
bx lr
// UINTN
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
@@ -74,16 +70,6 @@ ASM_FUNC(ReadCCSIDR)
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCCSIDR2 (
// IN UINT32 CSSELR
// )
ASM_FUNC(ReadCCSIDR2)
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSIDR2)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR

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@@ -64,11 +64,7 @@
isb
bx LR
RVCT_ASM_EXPORT ArmReadIdMmfr4
mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register
bx LR
// UINTN
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
@@ -78,16 +74,6 @@
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCCSIDR2 (
// IN UINT32 CSSELR
// )
RVCT_ASM_EXPORT ReadCCSIDR2
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR

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@@ -2,7 +2,6 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -72,50 +71,3 @@ ArmCleanDataCache (
ArmDataSynchronizationBarrier ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
/**
Check whether the CPU supports the GIC system register interface (any version)
@return Whether GIC System Register Interface is supported
**/
BOOLEAN
EFIAPI
ArmHasGicSystemRegisters (
VOID
)
{
return ((ArmReadIdPfr1 () & ARM_PFR1_GIC) != 0);
}
/**
Check whether the CPU supports the Security extensions
@return Whether the Security extensions are implemented
**/
BOOLEAN
EFIAPI
ArmHasSecurityExtensions (
VOID
)
{
return ((ArmReadIdPfr1 () & ARM_PFR1_SEC) != 0);
}
/** Checks if CCIDX is implemented.
@retval TRUE CCIDX is implemented.
@retval FALSE CCIDX is not implemented.
**/
BOOLEAN
EFIAPI
ArmHasCcidx (
VOID
)
{
UINTN Mmfr4;
Mmfr4 = ArmReadIdMmfr4 ();
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;
}

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@@ -48,21 +48,5 @@ ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINTN SetWayFormat
);
/** Reads the ID_MMFR4 register.
@return The contents of the ID_MMFR4 register.
**/
UINT32
EFIAPI
ArmReadIdMmfr4 (
VOID
);
UINTN
EFIAPI
ArmReadIdPfr1 (
VOID
);
#endif // __ARM_V7_LIB_H__

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@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2021, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -19,7 +19,9 @@ ArmSetAuxCrBit (
IN UINT32 Bits
)
{
ArmWriteAuxCr(ArmReadAuxCr() | Bits);
UINT32 val = ArmReadAuxCr();
val |= Bits;
ArmWriteAuxCr(val);
}
VOID
@@ -28,7 +30,9 @@ ArmUnsetAuxCrBit (
IN UINT32 Bits
)
{
ArmWriteAuxCr(ArmReadAuxCr() & ~Bits);
UINT32 val = ArmReadAuxCr();
val &= ~Bits;
ArmWriteAuxCr(val);
}
//
@@ -41,7 +45,10 @@ ArmSetCpuActlrBit (
IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () | Bits);
UINTN Value;
Value = ArmReadCpuActlr ();
Value |= Bits;
ArmWriteCpuActlr (Value);
}
VOID
@@ -50,7 +57,10 @@ ArmUnsetCpuActlrBit (
IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits);
UINTN Value;
Value = ArmReadCpuActlr ();
Value &= ~Bits;
ArmWriteCpuActlr (Value);
}
UINTN

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@@ -1,7 +1,5 @@
/** @file
ArmLibPrivate.h
Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -52,101 +50,6 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
UINT32 InD :1; ///< Instruction not Data bit
UINT32 Level :3; ///< Cache level (zero based)
UINT32 TnD :1; ///< Allocation not Data bit
UINT32 Reserved :27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
typedef enum
{
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
CsselrCacheTypeInstruction,
CsselrCacheTypeMax
} CSSELR_CACHE_TYPE;
/// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :10; ///< Associativity - 1
UINT64 NumSets :15; ///< Number of sets in the cache -1
UINT64 Unknown :4; ///< Reserved, UNKNOWN
UINT64 Reserved :32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :21; ///< Associativity - 1
UINT64 Reserved1 :8; ///< Reserved, RES0
UINT64 NumSets :24; ///< Number of sets in the cache -1
UINT64 Reserved2 :8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
UINT64 LineSize : 3;
UINT64 Associativity : 21;
UINT64 Reserved : 8;
UINT64 Unallocated : 32;
} BitsCcidxAA32;
UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
UINT32 NumSets :24; ///< Number of sets in the cache - 1
UINT32 Reserved :8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
*
* The lower 32 bits are the same for both AARCH32 and AARCH64
* so we can use the same structure for both.
**/
typedef union {
struct {
UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
typedef enum {
/// No cache is present
ClidrCacheTypeNone = 0,
/// There is only an instruction cache
ClidrCacheTypeInstructionOnly,
/// There is only a data cache
ClidrCacheTypeDataOnly,
/// There are separate data and instruction caches
ClidrCacheTypeSeparate,
/// There is a unified cache
ClidrCacheTypeUnified,
ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
VOID
CPSRMaskInsert (
IN UINT32 Mask,
@@ -158,26 +61,8 @@ CPSRRead (
VOID
);
/** Reads the CCSIDR register for the specified cache.
@param CSSELR The CSSELR cache selection register value.
@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
Returns the contents of the CCSIDR register in AARCH32 mode.
**/
UINTN
ReadCCSIDR (
IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@param CSSELR The CSSELR cache selection register value
@return The contents of the CCSIDR2 register for the specified cache.
**/
UINT32
ReadCCSIDR2 (
ReadCCSIDR (
IN UINT32 CSSELR
);

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@@ -294,7 +294,7 @@ UpdateRegionMapping (
{
UINTN T0SZ;
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
if (((RegionStart | RegionLength) & EFI_PAGE_MASK)) {
return EFI_INVALID_PARAMETER;
}
@@ -649,7 +649,7 @@ ArmMmuBaseLibConstructor (
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
WriteBackDataCacheRange (ArmReplaceLiveTranslationEntry,
ArmReplaceLiveTranslationEntrySize);
return RETURN_SUCCESS;

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@@ -1,10 +1,10 @@
/** @file
Copyright (c) 2016, Linaro Limited. All rights reserved.
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
*/
#/* @file
#
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#*/
#include <Base.h>
@@ -47,7 +47,7 @@ ArmMmuPeiLibConstructor (
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
WriteBackDataCacheRange (ArmReplaceLiveTranslationEntry,
ArmReplaceLiveTranslationEntrySize);
}

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@@ -225,7 +225,7 @@ FillTranslationTable (
return;
}
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;
PhysicalBase = MemoryRegion->PhysicalBase;
RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
switch (MemoryRegion->Attributes) {
@@ -291,7 +291,7 @@ FillTranslationTable (
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
} else {
PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
(PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));
// Case: Physical address aligned on the Section Size (1MB) && the length

View File

@@ -1,7 +1,7 @@
/** @file
* File managing the MMU for ARMv7 architecture
*
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2011-2016, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -105,7 +105,7 @@ UpdatePageEntries (
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask
EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;
if ((Attributes & EFI_MEMORY_XP) != 0) {
if (Attributes & EFI_MEMORY_XP) {
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
} else {
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
@@ -116,33 +116,33 @@ UpdatePageEntries (
// is irrelevant. If no memory attribute is specified, we preserve whatever
// memory type is set in the page tables, and update the permission attributes
// only.
if ((Attributes & EFI_MEMORY_UC) != 0) {
if (Attributes & EFI_MEMORY_UC) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
} else if (Attributes & EFI_MEMORY_WC) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// map to normal non-cachable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
} else if (Attributes & EFI_MEMORY_WT) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// write through with no-allocate
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
} else if ((Attributes & EFI_MEMORY_WB) != 0) {
} else if (Attributes & EFI_MEMORY_WB) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// write back (with allocate)
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
} else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {
} else if (Attributes & CACHE_ATTRIBUTE_MASK) {
// catch unsupported memory type attributes
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
if ((Attributes & EFI_MEMORY_RO) != 0) {
if (Attributes & EFI_MEMORY_RO) {
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
} else {
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
@@ -152,7 +152,7 @@ UpdatePageEntries (
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// Calculate number of 4KB page table entries to change
NumPageEntries = (UINT32)(Length / TT_DESCRIPTOR_PAGE_SIZE);
NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
// Iterate for the number of 4KB pages to change
Offset = 0;
@@ -220,7 +220,7 @@ UpdateSectionEntries (
IN UINT64 Attributes
)
{
EFI_STATUS Status;
EFI_STATUS Status = EFI_SUCCESS;
UINT32 EntryMask;
UINT32 EntryValue;
UINT32 FirstLevelIdx;
@@ -231,8 +231,6 @@ UpdateSectionEntries (
VOID *Mva;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
Status = EFI_SUCCESS;
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask
@@ -246,39 +244,39 @@ UpdateSectionEntries (
// is irrelevant. If no memory attribute is specified, we preserve whatever
// memory type is set in the page tables, and update the permission attributes
// only.
if ((Attributes & EFI_MEMORY_UC) != 0) {
if (Attributes & EFI_MEMORY_UC) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// map to strongly ordered
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
} else if (Attributes & EFI_MEMORY_WC) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// map to normal non-cachable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
} else if (Attributes & EFI_MEMORY_WT) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// write through with no-allocate
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
} else if ((Attributes & EFI_MEMORY_WB) != 0) {
} else if (Attributes & EFI_MEMORY_WB) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// write back (with allocate)
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
} else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) {
} else if (Attributes & CACHE_ATTRIBUTE_MASK) {
// catch unsupported memory type attributes
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
if ((Attributes & EFI_MEMORY_RO) != 0) {
if (Attributes & EFI_MEMORY_RO) {
EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
} else {
EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
}
if ((Attributes & EFI_MEMORY_XP) != 0) {
if (Attributes & EFI_MEMORY_XP) {
EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
}
@@ -290,7 +288,7 @@ UpdateSectionEntries (
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// calculate number of 1MB first level entries this applies to
NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);
NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
// iterate through each descriptor
for(i=0; i<NumSections; i++) {

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@@ -1,5 +1,5 @@
//
// Copyright (c) 2012 - 2020, ARM Limited. All rights reserved.
// Copyright (c) 2012 - 2017, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -25,19 +25,14 @@ ASM_PFX(ArmCallSvc):
ldp x0, x1, [x0, #0]
svc #0
// Prevent speculative execution beyond svc instruction
dsb nsh
isb
// Pop the ARM_SVC_ARGS structure address from the stack into x9
ldr x9, [sp, #16]
// Store the SVC returned values into the ARM_SVC_ARGS structure.
// A SVC call can return up to 8 values
// A SVC call can return up to 4 values - we do not need to store back x4-x7.
stp x0, x1, [x9, #0]
stp x2, x3, [x9, #16]
stp x4, x5, [x9, #32]
stp x6, x7, [x9, #48]
mov x0, x9

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@@ -1,5 +1,5 @@
//
// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.
// Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -18,9 +18,6 @@ ASM_PFX(ArmCallSvc):
ldm r0, {r0-r7}
svc #0
// Prevent speculative execution beyond svc instruction
dsb nsh
isb
// Load the ARM_SVC_ARGS structure address from the stack into r8
ldr r8, [sp]

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@@ -1,5 +1,5 @@
//
// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.
// Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -16,9 +16,6 @@
ldm r0, {r0-r7}
svc #0
// Prevent speculative execution beyond svc instruction
dsb nsh
isb
// Load the ARM_SVC_ARGS structure address from the stack into r8
ldr r8, [sp]

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -18,13 +17,10 @@ int memcmp(void *, void *, size_t);
#pragma function(memcmp)
int memcmp(const void *s1, const void *s2, size_t n)
{
unsigned char const *t1;
unsigned char const *t2;
unsigned char const *t1 = s1;
unsigned char const *t2 = s2;
t1 = s1;
t2 = s2;
while (n-- != 0) {
while (n--) {
if (*t1 != *t2)
return (int)*t1 - (int)*t2;
t1++;

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -11,15 +10,11 @@ typedef __SIZE_TYPE__ size_t;
static void __memcpy(void *dest, const void *src, size_t n)
{
unsigned char *d;
unsigned char const *s;
unsigned char *d = dest;
unsigned char const *s = src;
d = dest;
s = src;
while (n-- != 0) {
while (n--)
*d++ = *s++;
}
}
void *memcpy(void *dest, const void *src, size_t n)

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -18,15 +17,11 @@ void* memcpy(void *, const void *, size_t);
#pragma function(memcpy)
void* memcpy(void *dest, const void *src, size_t n)
{
unsigned char *d;
unsigned char const *s;
unsigned char *d = dest;
unsigned char const *s = src;
d = dest;
s = src;
while (n-- != 0) {
while (n--)
*d++ = *s++;
}
return dest;
}

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -18,22 +17,17 @@ void* memmove(void *, const void *, size_t);
#pragma function(memmove)
void* memmove(void *dest, const void *src, size_t n)
{
unsigned char *d;
unsigned char const *s;
d = dest;
s = src;
unsigned char *d = dest;
unsigned char const *s = src;
if (d < s) {
while (n-- != 0) {
while (n--)
*d++ = *s++;
}
} else {
d += n;
s += n;
while (n-- != 0) {
while (n--)
*--d = *--s;
}
}
return dest;

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -12,13 +11,10 @@ typedef __SIZE_TYPE__ size_t;
static __attribute__((__used__))
void *__memset(void *s, int c, size_t n)
{
unsigned char *d;
unsigned char *d = s;
d = s;
while (n-- != 0) {
while (n--)
*d++ = c;
}
return s;
}

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@@ -1,7 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -18,13 +17,10 @@ void* memset(void *, int, size_t);
#pragma function(memset)
void *memset(void *s, int c, size_t n)
{
unsigned char *d;
unsigned char *d = s;
d = s;
while (n-- != 0) {
while (n--)
*d++ = (unsigned char)c;
}
return s;
}

View File

@@ -2,7 +2,7 @@
Default exception handler
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2012 - 2021, Arm Ltd. All rights reserved.<BR>
Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -34,20 +34,6 @@ typedef struct {
CHAR8 Char;
} CPSR_CHAR;
STATIC CONST CPSR_CHAR mCpsrChar[] = {
{ 31, 'n' },
{ 30, 'z' },
{ 29, 'c' },
{ 28, 'v' },
{ 9, 'e' },
{ 8, 'a' },
{ 7, 'i' },
{ 6, 'f' },
{ 5, 't' },
{ 0, '?' }
};
CHAR8 *
GetImageName (
IN UINTN FaultAddress,
@@ -59,7 +45,7 @@ GetImageName (
Convert the Current Program Status Register (CPSR) to a string. The string is
a defacto standard in the ARM world.
It is possible to add extra bits by adding them to mCpsrChar array.
It is possible to add extra bits by adding them to CpsrChar array.
@param Cpsr ARM CPSR register value
@param ReturnStr CPSR_STRING_SIZE byte string that contains string
@@ -75,12 +61,25 @@ CpsrString (
UINTN Index;
CHAR8* Str;
CHAR8* ModeStr;
CPSR_CHAR CpsrChar[] = {
{ 31, 'n' },
{ 30, 'z' },
{ 29, 'c' },
{ 28, 'v' },
{ 9, 'e' },
{ 8, 'a' },
{ 7, 'i' },
{ 6, 'f' },
{ 5, 't' },
{ 0, '?' }
};
Str = ReturnStr;
for (Index = 0; mCpsrChar[Index].BIT != 0; Index++, Str++) {
*Str = mCpsrChar[Index].Char;
if ((Cpsr & (1 << mCpsrChar[Index].BIT)) != 0) {
for (Index = 0; CpsrChar[Index].BIT != 0; Index++, Str++) {
*Str = CpsrChar[Index].Char;
if ((Cpsr & (1 << CpsrChar[Index].BIT)) != 0) {
// Concert to upper case if bit is set
*Str &= ~0x20;
}
@@ -187,9 +186,7 @@ DefaultExceptionHandler (
UINT32 DfsrStatus;
UINT32 IfsrStatus;
BOOLEAN DfsrWrite;
UINT32 PcAdjust;
PcAdjust = 0;
UINT32 PcAdjust = 0;
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n%a Exception PC at 0x%08x CPSR 0x%08x ",
gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);

View File

@@ -3,7 +3,6 @@
secure monitor calls.
Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -228,7 +227,7 @@ OpteeOpenSession (
MessageArg->NumParams = 2;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
if (OpteeCallWithArg ((UINTN)MessageArg)) {
MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
@@ -432,7 +431,7 @@ OpteeInvokeFunction (
MessageArg->NumParams = OPTEE_MAX_CALL_PARAMS;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
if (OpteeCallWithArg ((UINTN)MessageArg)) {
MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
@@ -441,7 +440,7 @@ OpteeInvokeFunction (
InvokeFunctionArg->Params,
OPTEE_MAX_CALL_PARAMS,
MessageArg->Params
) != 0) {
)) {
MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}

View File

@@ -23,12 +23,10 @@
#include <Protocol/EsrtManagement.h>
#include <Protocol/GraphicsOutput.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/NonDiscoverableDevice.h>
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PlatformBootManager.h>
#include <Guid/EventGroup.h>
#include <Guid/NonDiscoverableDevice.h>
#include <Guid/TtyTerm.h>
#include <Guid/SerialPortLibVendor.h>
@@ -256,37 +254,6 @@ IsPciDisplay (
}
/**
This FILTER_FUNCTION checks if a handle corresponds to a non-discoverable
USB host controller.
**/
STATIC
BOOLEAN
EFIAPI
IsUsbHost (
IN EFI_HANDLE Handle,
IN CONST CHAR16 *ReportText
)
{
NON_DISCOVERABLE_DEVICE *Device;
EFI_STATUS Status;
Status = gBS->HandleProtocol (Handle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
(VOID **)&Device);
if (EFI_ERROR (Status)) {
return FALSE;
}
if (CompareGuid (Device->Type, &gEdkiiNonDiscoverableUhciDeviceGuid) ||
CompareGuid (Device->Type, &gEdkiiNonDiscoverableEhciDeviceGuid) ||
CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid)) {
return TRUE;
}
return FALSE;
}
/**
This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
the matching driver to produce all first-level child handles.
@@ -357,8 +324,7 @@ VOID
PlatformRegisterFvBootOption (
CONST EFI_GUID *FileGuid,
CHAR16 *Description,
UINT32 Attributes,
EFI_INPUT_KEY *Key
UINT32 Attributes
)
{
EFI_STATUS Status;
@@ -410,9 +376,6 @@ PlatformRegisterFvBootOption (
if (OptionIndex == -1) {
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
ASSERT_EFI_ERROR (Status);
Status = EfiBootManagerAddKeyOptionVariable (NULL,
(UINT16)NewOption.OptionNumber, 0, Key, NULL);
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
}
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
@@ -611,15 +574,6 @@ PlatformBootManagerBeforeConsole (
//
FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
//
// The core BDS code connects short-form USB device paths by explicitly
// looking for handles with PCI I/O installed, and checking the PCI class
// code whether it matches the one for a USB host controller. This means
// non-discoverable USB host controllers need to have the non-discoverable
// PCI driver attached first.
//
FilterAndProcess (&gEdkiiNonDiscoverableDeviceProtocolGuid, IsUsbHost, Connect);
//
// Add the hardcoded short-form USB keyboard device path to ConIn.
//
@@ -629,13 +583,7 @@ PlatformBootManagerBeforeConsole (
//
// Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
//
STATIC_ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4,
"PcdDefaultTerminalType must be TTYTERM");
STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultParity) != 0,
"PcdUartDefaultParity must be set to an actual value, not 'default'");
STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultStopBits) != 0,
"PcdUartDefaultStopBits must be set to an actual value, not 'default'");
ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4);
CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
EfiBootManagerUpdateConsoleVariable (ConIn,
@@ -725,7 +673,6 @@ PlatformBootManagerAfterConsole (
UINTN FirmwareVerLength;
UINTN PosX;
UINTN PosY;
EFI_INPUT_KEY Key;
FirmwareVerLength = StrLen (PcdGetPtr (PcdFirmwareVersionString));
@@ -753,6 +700,11 @@ PlatformBootManagerAfterConsole (
}
}
//
// Connect the rest of the devices.
//
EfiBootManagerConnectAll ();
//
// On ARM, there is currently no reason to use the phased capsule
// update approach where some capsules are dispatched before EndOfDxe
@@ -762,12 +714,17 @@ PlatformBootManagerAfterConsole (
//
HandleCapsules ();
//
// Enumerate all possible boot options.
//
EfiBootManagerRefreshAllBootOption ();
//
// Register UEFI Shell
//
Key.ScanCode = SCAN_NULL;
Key.UnicodeChar = L's';
PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key);
PlatformRegisterFvBootOption (
&gUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE
);
}
/**
@@ -818,53 +775,5 @@ PlatformBootManagerUnableToBoot (
VOID
)
{
EFI_STATUS Status;
EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;
EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
UINTN OldBootOptionCount;
UINTN NewBootOptionCount;
//
// Record the total number of boot configured boot options
//
BootOptions = EfiBootManagerGetLoadOptions (&OldBootOptionCount,
LoadOptionTypeBoot);
EfiBootManagerFreeLoadOptions (BootOptions, OldBootOptionCount);
//
// Connect all devices, and regenerate all boot options
//
EfiBootManagerConnectAll ();
EfiBootManagerRefreshAllBootOption ();
//
// Record the updated number of boot configured boot options
//
BootOptions = EfiBootManagerGetLoadOptions (&NewBootOptionCount,
LoadOptionTypeBoot);
EfiBootManagerFreeLoadOptions (BootOptions, NewBootOptionCount);
//
// If the number of configured boot options has changed, reboot
// the system so the new boot options will be taken into account
// while executing the ordinary BDS bootflow sequence.
// *Unless* persistent varstore is being emulated, since we would
// then end up in an endless reboot loop.
//
if (!PcdGetBool (PcdEmuVariableNvModeEnable)) {
if (NewBootOptionCount != OldBootOptionCount) {
DEBUG ((DEBUG_WARN, "%a: rebooting after refreshing all boot options\n",
__FUNCTION__));
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
}
}
Status = EfiBootManagerGetBootManagerMenu (&BootManagerMenu);
if (EFI_ERROR (Status)) {
return;
}
for (;;) {
EfiBootManagerBoot (&BootManagerMenu);
}
return;
}

View File

@@ -55,7 +55,6 @@
gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
@@ -67,9 +66,6 @@
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
[Guids]
gEdkiiNonDiscoverableEhciDeviceGuid
gEdkiiNonDiscoverableUhciDeviceGuid
gEdkiiNonDiscoverableXhciDeviceGuid
gEfiFileInfoGuid
gEfiFileSystemInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
@@ -78,7 +74,6 @@
gUefiShellFileGuid
[Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
gEfiLoadedImageProtocolGuid

View File

@@ -2,7 +2,6 @@
Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -56,13 +55,10 @@ SerialPortWrite (
)
{
UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
UINTN SourceIndex;
UINTN DestinationIndex;
UINTN SourceIndex = 0;
UINTN DestinationIndex = 0;
UINT8 CurrentCharacter;
SourceIndex = 0;
DestinationIndex = 0;
while (SourceIndex < NumberOfBytes)
{
CurrentCharacter = Buffer[SourceIndex++];

View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2013 - 2021, Arm Limited. All rights reserved.<BR>
Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -135,7 +135,9 @@ SemihostFileClose (
IN UINTN FileHandle
)
{
if (Semihost_SYS_CLOSE (&FileHandle) == -1) {
INT32 Result = Semihost_SYS_CLOSE(&FileHandle);
if (Result == -1) {
return RETURN_INVALID_PARAMETER;
} else {
return RETURN_SUCCESS;

View File

@@ -1,149 +1,21 @@
/** @file
File managing the MMU for ARMv8 architecture in S-EL0
Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
- [1] SPM based on the MM interface.
(https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager-mm.html)
- [2] Arm Firmware Framework for Armv8-A, DEN0077A, version 1.0
(https://developer.arm.com/documentation/den0077/a)
* File managing the MMU for ARMv8 architecture in S-EL0
*
* Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <IndustryStandard/ArmMmSvc.h>
#include <IndustryStandard/ArmFfaSvc.h>
#include <Library/ArmLib.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
/** Send memory permission request to target.
@param [in, out] SvcArgs Pointer to SVC arguments to send. On
return it contains the response parameters.
@param [out] RetVal Pointer to return the response value.
@retval EFI_SUCCESS Request successfull.
@retval EFI_INVALID_PARAMETER A parameter is invalid.
@retval EFI_NOT_READY Callee is busy or not in a state to handle
this request.
@retval EFI_UNSUPPORTED This function is not implemented by the
callee.
@retval EFI_ABORTED Message target ran into an unexpected error
and has aborted.
@retval EFI_ACCESS_DENIED Access denied.
@retval EFI_OUT_OF_RESOURCES Out of memory to perform operation.
**/
STATIC
EFI_STATUS
SendMemoryPermissionRequest (
IN OUT ARM_SVC_ARGS *SvcArgs,
OUT INT32 *RetVal
)
{
if ((SvcArgs == NULL) || (RetVal == NULL)) {
return EFI_INVALID_PARAMETER;
}
ArmCallSvc (SvcArgs);
if (FeaturePcdGet (PcdFfaEnable)) {
// Get/Set memory attributes is an atomic call, with
// StandaloneMm at S-EL0 being the caller and the SPM
// core being the callee. Thus there won't be a
// FFA_INTERRUPT or FFA_SUCCESS response to the Direct
// Request sent above. This will have to be considered
// for other Direct Request calls which are not atomic
// We therefore check only for Direct Response by the
// callee.
if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
// A Direct Response means FF-A success
// Now check the payload for errors
// The callee sends back the return value
// in Arg3
*RetVal = SvcArgs->Arg3;
} else {
// If Arg0 is not a Direct Response, that means we
// have an FF-A error. We need to check Arg2 for the
// FF-A error code.
// See [2], Table 10.8: FFA_ERROR encoding.
*RetVal = SvcArgs->Arg2;
switch (*RetVal) {
case ARM_FFA_SPM_RET_INVALID_PARAMETERS:
return EFI_INVALID_PARAMETER;
case ARM_FFA_SPM_RET_DENIED:
return EFI_ACCESS_DENIED;
case ARM_FFA_SPM_RET_NOT_SUPPORTED:
return EFI_UNSUPPORTED;
case ARM_FFA_SPM_RET_BUSY:
return EFI_NOT_READY;
case ARM_FFA_SPM_RET_ABORTED:
return EFI_ABORTED;
default:
// Undefined error code received.
ASSERT (0);
return EFI_INVALID_PARAMETER;
}
}
} else {
*RetVal = SvcArgs->Arg0;
}
// Check error response from Callee.
if (*RetVal & BIT31) {
// Bit 31 set means there is an error retured
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and
// Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
switch (*RetVal) {
case ARM_SVC_SPM_RET_NOT_SUPPORTED:
return EFI_UNSUPPORTED;
case ARM_SVC_SPM_RET_INVALID_PARAMS:
return EFI_INVALID_PARAMETER;
case ARM_SVC_SPM_RET_DENIED:
return EFI_ACCESS_DENIED;
case ARM_SVC_SPM_RET_NO_MEMORY:
return EFI_OUT_OF_RESOURCES;
default:
// Undefined error code received.
ASSERT (0);
return EFI_INVALID_PARAMETER;
}
}
return EFI_SUCCESS;
}
/** Request the permission attributes of a memory region from S-EL0.
@param [in] BaseAddress Base address for the memory region.
@param [out] MemoryAttributes Pointer to return the memory attributes.
@retval EFI_SUCCESS Request successfull.
@retval EFI_INVALID_PARAMETER A parameter is invalid.
@retval EFI_NOT_READY Callee is busy or not in a state to handle
this request.
@retval EFI_UNSUPPORTED This function is not implemented by the
callee.
@retval EFI_ABORTED Message target ran into an unexpected error
and has aborted.
@retval EFI_ACCESS_DENIED Access denied.
@retval EFI_OUT_OF_RESOURCES Out of memory to perform operation.
**/
STATIC
EFI_STATUS
GetMemoryPermissions (
@@ -151,89 +23,70 @@ GetMemoryPermissions (
OUT UINT32 *MemoryAttributes
)
{
EFI_STATUS Status;
INT32 Ret;
ARM_SVC_ARGS SvcArgs;
ARM_SVC_ARGS GetMemoryPermissionsSvcArgs = {0};
if (MemoryAttributes == NULL) {
GetMemoryPermissionsSvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
GetMemoryPermissionsSvcArgs.Arg1 = BaseAddress;
GetMemoryPermissionsSvcArgs.Arg2 = 0;
GetMemoryPermissionsSvcArgs.Arg3 = 0;
ArmCallSvc (&GetMemoryPermissionsSvcArgs);
if (GetMemoryPermissionsSvcArgs.Arg0 == ARM_SVC_SPM_RET_INVALID_PARAMS) {
*MemoryAttributes = 0;
return EFI_INVALID_PARAMETER;
}
// Prepare the message parameters.
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64.
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg4 = BaseAddress;
} else {
SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = 0;
}
Status = SendMemoryPermissionRequest (&SvcArgs, &Ret);
if (EFI_ERROR (Status)) {
*MemoryAttributes = 0;
return Status;
}
*MemoryAttributes = Ret;
return Status;
*MemoryAttributes = GetMemoryPermissionsSvcArgs.Arg0;
return EFI_SUCCESS;
}
/** Set the permission attributes of a memory region from S-EL0.
@param [in] BaseAddress Base address for the memory region.
@param [in] Length Length of the memory region.
@param [in] Permissions Memory access controls attributes.
@retval EFI_SUCCESS Request successfull.
@retval EFI_INVALID_PARAMETER A parameter is invalid.
@retval EFI_NOT_READY Callee is busy or not in a state to handle
this request.
@retval EFI_UNSUPPORTED This function is not implemented by the
callee.
@retval EFI_ABORTED Message target ran into an unexpected error
and has aborted.
@retval EFI_ACCESS_DENIED Access denied.
@retval EFI_OUT_OF_RESOURCES Out of memory to perform operation.
**/
STATIC
EFI_STATUS
RequestMemoryPermissionChange (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT32 Permissions
IN UINTN Permissions
)
{
INT32 Ret;
ARM_SVC_ARGS SvcArgs;
EFI_STATUS Status;
ARM_SVC_ARGS ChangeMemoryPermissionsSvcArgs = {0};
// Prepare the message parameters.
// See [1], Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg4 = BaseAddress;
SvcArgs.Arg5 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg6 = Permissions;
} else {
SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg3 = Permissions;
ChangeMemoryPermissionsSvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
ChangeMemoryPermissionsSvcArgs.Arg1 = BaseAddress;
ChangeMemoryPermissionsSvcArgs.Arg2 = EFI_SIZE_TO_PAGES(Length);
ChangeMemoryPermissionsSvcArgs.Arg3 = Permissions;
ArmCallSvc (&ChangeMemoryPermissionsSvcArgs);
Status = ChangeMemoryPermissionsSvcArgs.Arg0;
switch (Status) {
case ARM_SVC_SPM_RET_SUCCESS:
Status = EFI_SUCCESS;
break;
case ARM_SVC_SPM_RET_NOT_SUPPORTED:
Status = EFI_UNSUPPORTED;
break;
case ARM_SVC_SPM_RET_INVALID_PARAMS:
Status = EFI_INVALID_PARAMETER;
break;
case ARM_SVC_SPM_RET_DENIED:
Status = EFI_ACCESS_DENIED;
break;
case ARM_SVC_SPM_RET_NO_MEMORY:
Status = EFI_BAD_BUFFER_SIZE;
break;
default:
Status = EFI_ACCESS_DENIED;
ASSERT (0);
}
return SendMemoryPermissionRequest (&SvcArgs, &Ret);
return Status;
}
EFI_STATUS
@@ -247,7 +100,7 @@ ArmSetMemoryRegionNoExec (
UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
if (Status != EFI_INVALID_PARAMETER) {
CodePermission = SET_MEM_ATTR_CODE_PERM_XN << SET_MEM_ATTR_CODE_PERM_SHIFT;
return RequestMemoryPermissionChange (
BaseAddress,
@@ -255,7 +108,7 @@ ArmSetMemoryRegionNoExec (
MemoryAttributes | CodePermission
);
}
return Status;
return EFI_INVALID_PARAMETER;
}
EFI_STATUS
@@ -269,7 +122,7 @@ ArmClearMemoryRegionNoExec (
UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
if (Status != EFI_INVALID_PARAMETER) {
CodePermission = SET_MEM_ATTR_CODE_PERM_XN << SET_MEM_ATTR_CODE_PERM_SHIFT;
return RequestMemoryPermissionChange (
BaseAddress,
@@ -277,7 +130,7 @@ ArmClearMemoryRegionNoExec (
MemoryAttributes & ~CodePermission
);
}
return Status;
return EFI_INVALID_PARAMETER;
}
EFI_STATUS
@@ -291,7 +144,7 @@ ArmSetMemoryRegionReadOnly (
UINT32 DataPermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
if (Status != EFI_INVALID_PARAMETER) {
DataPermission = SET_MEM_ATTR_DATA_PERM_RO << SET_MEM_ATTR_DATA_PERM_SHIFT;
return RequestMemoryPermissionChange (
BaseAddress,
@@ -299,7 +152,7 @@ ArmSetMemoryRegionReadOnly (
MemoryAttributes | DataPermission
);
}
return Status;
return EFI_INVALID_PARAMETER;
}
EFI_STATUS
@@ -313,7 +166,7 @@ ArmClearMemoryRegionReadOnly (
UINT32 PermissionRequest;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
if (Status != EFI_INVALID_PARAMETER) {
PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (SET_MEM_ATTR_DATA_PERM_RW,
MemoryAttributes);
return RequestMemoryPermissionChange (
@@ -322,5 +175,5 @@ ArmClearMemoryRegionReadOnly (
PermissionRequest
);
}
return Status;
return EFI_INVALID_PARAMETER;
}

View File

@@ -23,9 +23,6 @@
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable
[LibraryClasses]
ArmLib
CacheMaintenanceLib

View File

@@ -1,141 +0,0 @@
/** @file
* OemMiscLib.c
*
* Copyright (c) 2021, NUVIA Inc. All rights reserved.
* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
* Copyright (c) 2018, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HiiLib.h>
#include <Library/OemMiscLib.h>
/** Gets the CPU frequency of the specified processor.
@param ProcessorIndex Index of the processor to get the frequency for.
@return CPU frequency in Hz
**/
UINTN
EFIAPI
OemGetCpuFreq (
IN UINT8 ProcessorIndex
)
{
ASSERT (FALSE);
return 0;
}
/** Gets information about the specified processor and stores it in
the structures provided.
@param ProcessorIndex Index of the processor to get the information for.
@param ProcessorStatus Processor status.
@param ProcessorCharacteristics Processor characteritics.
@param MiscProcessorData Miscellaneous processor information.
@return TRUE on success, FALSE on failure.
**/
BOOLEAN
EFIAPI
OemGetProcessorInformation (
IN UINTN ProcessorIndex,
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
)
{
ASSERT (FALSE);
return TRUE;
}
/** Gets information about the cache at the specified cache level.
@param ProcessorIndex The processor to get information for.
@param CacheLevel The cache level to get information for.
@param DataCache Whether the cache is a data cache.
@param UnifiedCache Whether the cache is a unified cache.
@param SmbiosCacheTable The SMBIOS Type7 cache information structure.
@return TRUE on success, FALSE on failure.
**/
BOOLEAN
EFIAPI
OemGetCacheInformation (
IN UINT8 ProcessorIndex,
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
)
{
ASSERT (FALSE);
return TRUE;
}
/** Gets the maximum number of processors supported by the platform.
@return The maximum number of processors.
**/
UINT8
EFIAPI
OemGetMaxProcessors (
VOID
)
{
ASSERT (FALSE);
return 1;
}
/** Gets the type of chassis for the system.
@retval The type of the chassis.
**/
MISC_CHASSIS_TYPE
EFIAPI
OemGetChassisType (
VOID
)
{
ASSERT (FALSE);
return MiscChassisTypeUnknown;
}
/** Returns whether the specified processor is present or not.
@param ProcessIndex The processor index to check.
@return TRUE is the processor is present, FALSE otherwise.
**/
BOOLEAN
EFIAPI
OemIsProcessorPresent (
IN UINTN ProcessorIndex
)
{
ASSERT (FALSE);
return FALSE;
}
/** Updates the HII string for the specified field.
@param HiiHandle The HII handle.
@param TokenToUpdate The string to update.
@param Field The field to get information about.
**/
VOID
EFIAPI
OemUpdateSmbiosInfo (
IN EFI_HII_HANDLE HiiHandle,
IN EFI_STRING_ID TokenToUpdate,
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
)
{
ASSERT (FALSE);
}

View File

@@ -1,31 +0,0 @@
#/** @file
# OemMiscLib.inf
#
# Copyright (c) 2021, NUVIA Inc. All rights reserved.
# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
# Copyright (c) 2018, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 1.29
BASE_NAME = OemMiscLibNull
FILE_GUID = e80b8e6b-fffb-4c39-b433-41de67c9d7b8
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = OemMiscLib
[Sources.common]
OemMiscLib.c
[Packages]
ArmPkg/ArmPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib

View File

@@ -1,752 +0,0 @@
/** @file
ProcessorSubClass.c
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.
Copyright (c) 2015, Linaro Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Protocol/Smbios.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmSmcLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HiiLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/OemMiscLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include "SmbiosProcessor.h"
extern UINT8 ProcessorSubClassStrings[];
#define CACHE_SOCKETED_SHIFT 3
#define CACHE_LOCATION_SHIFT 5
#define CACHE_ENABLED_SHIFT 7
#define CACHE_OPERATION_MODE_SHIFT 8
typedef enum {
CacheModeWriteThrough = 0, ///< Cache is write-through
CacheModeWriteBack, ///< Cache is write-back
CacheModeVariesWithAddress, ///< Cache mode varies by address
CacheModeUnknown, ///< Cache mode is unknown
CacheModeMax
} CACHE_OPERATION_MODE;
typedef enum {
CacheLocationInternal = 0, ///< Cache is internal to the processor
CacheLocationExternal, ///< Cache is external to the processor
CacheLocationReserved, ///< Reserved
CacheLocationUnknown, ///< Cache location is unknown
CacheLocationMax
} CACHE_LOCATION;
EFI_HII_HANDLE mHiiHandle;
EFI_SMBIOS_PROTOCOL *mSmbios;
SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = {
{ // Hdr
EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type
sizeof (SMBIOS_TABLE_TYPE4), // Length
0 // Handle
},
1, // Socket
CentralProcessor, // ProcessorType
ProcessorFamilyIndicatorFamily2, // ProcessorFamily
2, // ProcessorManufacture
{ // ProcessorId
{ // Signature
0
},
{ // FeatureFlags
0
}
},
3, // ProcessorVersion
{ // Voltage
0
},
0, // ExternalClock
0, // MaxSpeed
0, // CurrentSpeed
0, // Status
ProcessorUpgradeUnknown, // ProcessorUpgrade
0xFFFF, // L1CacheHandle
0xFFFF, // L2CacheHandle
0xFFFF, // L3CacheHandle
4, // SerialNumber
5, // AssetTag
6, // PartNumber
0, // CoreCount
0, //EnabledCoreCount
0, // ThreadCount
0, // ProcessorCharacteristics
ProcessorFamilyARM, // ProcessorFamily2
0, // CoreCount2
0, // EnabledCoreCount2
0 // ThreadCount2
};
/** Sets the HII variable `StringId` is `Pcd` isn't empty.
@param Pcd The FixedAtBuild PCD that contains the string to fetch.
@param StringId The string identifier to set.
**/
#define SET_HII_STRING_IF_PCD_NOT_EMPTY(Pcd, StringId) \
do { \
CHAR16 *Str; \
Str = (CHAR16*)PcdGetPtr (Pcd); \
if (StrLen (Str) > 0) { \
HiiSetString (mHiiHandle, StringId, Str, NULL); \
} \
} while (0)
/** Fetches the specified processor's frequency in Hz.
@param ProcessorNumber The processor number
@return The clock frequency in MHz
**/
UINT16
GetCpuFrequency (
IN UINT8 ProcessorNumber
)
{
return (UINT16)(OemGetCpuFreq (ProcessorNumber) / 1000 / 1000);
}
/** Gets a description of the specified cache.
@param[in] CacheLevel Zero-based cache level (e.g. L1 cache is 0).
@param[in] DataCache Cache is a data cache.
@param[in] UnifiedCache Cache is a unified cache.
@param[out] CacheSocketStr The description of the specified cache
@return The number of Unicode characters in CacheSocketStr not including the
terminating NUL.
**/
UINTN
GetCacheSocketStr (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
OUT CHAR16 *CacheSocketStr
)
{
UINTN CacheSocketStrLen;
if (CacheLevel == CpuCacheL1 && !DataCache && !UnifiedCache) {
CacheSocketStrLen = UnicodeSPrint (
CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Instruction Cache",
CacheLevel);
} else if (CacheLevel == CpuCacheL1 && DataCache) {
CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Data Cache",
CacheLevel);
} else {
CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Cache",
CacheLevel);
}
return CacheSocketStrLen;
}
/** Fills in the Type 7 record with the cache architecture information
read from the CPU registers.
@param[in] CacheLevel Cache level (e.g. L1, L2).
@param[in] DataCache Cache is a data cache.
@param[in] UnifiedCache Cache is a unified cache.
@param[out] Type7Record The Type 7 record to fill in.
**/
VOID
ConfigureCacheArchitectureInformation (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
OUT SMBIOS_TABLE_TYPE7 *Type7Record
)
{
UINT8 Associativity;
UINT32 CacheSize32;
UINT16 CacheSize16;
UINT64 CacheSize64;
if (!DataCache && !UnifiedCache) {
Type7Record->SystemCacheType = CacheTypeInstruction;
} else if (DataCache) {
Type7Record->SystemCacheType = CacheTypeData;
} else if (UnifiedCache) {
Type7Record->SystemCacheType = CacheTypeUnified;
} else {
ASSERT(FALSE);
}
CacheSize64 = SmbiosProcessorGetCacheSize (CacheLevel,
DataCache,
UnifiedCache
);
Associativity = SmbiosProcessorGetCacheAssociativity (CacheLevel,
DataCache,
UnifiedCache
);
CacheSize64 /= 1024; // Minimum granularity is 1K
// Encode the cache size into the format SMBIOS wants
if (CacheSize64 < MAX_INT16) {
CacheSize16 = CacheSize64;
CacheSize32 = CacheSize16;
} else if ((CacheSize64 / 64) < MAX_INT16) {
CacheSize16 = (1 << 15) | (CacheSize64 / 64);
CacheSize32 = CacheSize16;
} else {
if ((CacheSize64 / 1024) <= 2047) {
CacheSize32 = CacheSize64;
} else {
CacheSize32 = (1 << 31) | (CacheSize64 / 64);
}
CacheSize16 = -1;
}
Type7Record->MaximumCacheSize = CacheSize16;
Type7Record->InstalledSize = CacheSize16;
Type7Record->MaximumCacheSize2 = CacheSize32;
Type7Record->InstalledSize2 = CacheSize32;
switch (Associativity) {
case 2:
Type7Record->Associativity = CacheAssociativity2Way;
break;
case 4:
Type7Record->Associativity = CacheAssociativity4Way;
break;
case 8:
Type7Record->Associativity = CacheAssociativity8Way;
break;
case 12:
Type7Record->Associativity = CacheAssociativity12Way;
break;
case 16:
Type7Record->Associativity = CacheAssociativity16Way;
break;
case 20:
Type7Record->Associativity = CacheAssociativity20Way;
break;
case 24:
Type7Record->Associativity = CacheAssociativity24Way;
break;
case 32:
Type7Record->Associativity = CacheAssociativity32Way;
break;
case 48:
Type7Record->Associativity = CacheAssociativity48Way;
break;
case 64:
Type7Record->Associativity = CacheAssociativity64Way;
break;
default:
Type7Record->Associativity = CacheAssociativityOther;
break;
}
Type7Record->CacheConfiguration = (CacheModeUnknown << CACHE_OPERATION_MODE_SHIFT) |
(1 << CACHE_ENABLED_SHIFT) |
(CacheLocationUnknown << CACHE_LOCATION_SHIFT) |
(0 << CACHE_SOCKETED_SHIFT) |
(CacheLevel - 1);
}
/** Allocates and initializes an SMBIOS_TABLE_TYPE7 structure.
@param[in] CacheLevel The cache level (L1-L7).
@param[in] DataCache Cache is a data cache.
@param[in] UnifiedCache Cache is a unified cache.
@return A pointer to the Type 7 structure. Returns NULL on failure.
**/
SMBIOS_TABLE_TYPE7 *
AllocateAndInitCacheInformation (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
)
{
SMBIOS_TABLE_TYPE7 *Type7Record;
EFI_STRING CacheSocketStr;
UINTN CacheSocketStrLen;
UINTN StringBufferSize;
CHAR8 *OptionalStrStart;
UINTN TableSize;
// Allocate and fetch the cache description
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;
CacheSocketStr = AllocateZeroPool (StringBufferSize);
if (CacheSocketStr == NULL) {
return NULL;
}
CacheSocketStrLen = GetCacheSocketStr (CacheLevel,
DataCache,
UnifiedCache,
CacheSocketStr);
TableSize = sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;
Type7Record = AllocateZeroPool (TableSize);
if (Type7Record == NULL) {
FreePool(CacheSocketStr);
return NULL;
}
Type7Record->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
Type7Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE7);
Type7Record->Hdr.Handle = SMBIOS_HANDLE_PI_RESERVED;
Type7Record->SocketDesignation = 1;
Type7Record->SupportedSRAMType.Unknown = 1;
Type7Record->CurrentSRAMType.Unknown = 1;
Type7Record->CacheSpeed = 0;
Type7Record->ErrorCorrectionType = CacheErrorUnknown;
OptionalStrStart = (CHAR8 *)(Type7Record + 1);
UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrLen + 1);
FreePool (CacheSocketStr);
return Type7Record;
}
/**
Add Type 7 SMBIOS Record for Cache Information.
@param[in] ProcessorIndex Processor number of specified processor.
@param[out] L1CacheHandle Pointer to the handle of the L1 Cache SMBIOS record.
@param[out] L2CacheHandle Pointer to the handle of the L2 Cache SMBIOS record.
@param[out] L3CacheHandle Pointer to the handle of the L3 Cache SMBIOS record.
**/
VOID
AddSmbiosCacheTypeTable (
IN UINTN ProcessorIndex,
OUT EFI_SMBIOS_HANDLE *L1CacheHandle,
OUT EFI_SMBIOS_HANDLE *L2CacheHandle,
OUT EFI_SMBIOS_HANDLE *L3CacheHandle
)
{
EFI_STATUS Status;
SMBIOS_TABLE_TYPE7 *Type7Record;
EFI_SMBIOS_HANDLE SmbiosHandle;
UINT8 CacheLevel;
UINT8 MaxCacheLevel;
BOOLEAN DataCacheType;
BOOLEAN SeparateCaches;
Status = EFI_SUCCESS;
MaxCacheLevel = 0;
// See if there's an L1 cache present.
MaxCacheLevel = SmbiosProcessorGetMaxCacheLevel ();
if (MaxCacheLevel < 1) {
return;
}
for (CacheLevel = 1; CacheLevel <= MaxCacheLevel; CacheLevel++) {
Type7Record = NULL;
SeparateCaches = SmbiosProcessorHasSeparateCaches (CacheLevel);
// At each level of cache, we can have a single type (unified, instruction or data),
// or two types - separate data and instruction caches. If we have separate
// instruction and data caches, then on the first iteration (CacheSubLevel = 0)
// process the instruction cache.
for (DataCacheType = 0; DataCacheType <= 1; DataCacheType++) {
// If there's no separate data/instruction cache, skip the second iteration
if (DataCacheType == 1 && !SeparateCaches) {
continue;
}
Type7Record = AllocateAndInitCacheInformation (CacheLevel,
DataCacheType,
!SeparateCaches
);
if (Type7Record == NULL) {
continue;
}
ConfigureCacheArchitectureInformation(CacheLevel,
DataCacheType,
!SeparateCaches,
Type7Record
);
// Allow the platform to fill in other information such as speed, SRAM type etc.
if (!OemGetCacheInformation (ProcessorIndex, CacheLevel,
DataCacheType, !SeparateCaches, Type7Record)) {
continue;
}
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
// Finally, install the table
Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,
(EFI_SMBIOS_TABLE_HEADER *)Type7Record);
if (EFI_ERROR (Status)) {
continue;
}
// Config L1/L2/L3 Cache Handle
switch (CacheLevel) {
case CpuCacheL1:
*L1CacheHandle = SmbiosHandle;
break;
case CpuCacheL2:
*L2CacheHandle = SmbiosHandle;
break;
case CpuCacheL3:
*L3CacheHandle = SmbiosHandle;
break;
default:
break;
}
}
}
}
/** Allocates a Type 4 Processor Information structure and sets the
strings following the data fields.
@param[out] Type4Record The Type 4 structure to allocate and initialize
@param[in] ProcessorIndex The index of the processor
@param[in] Populated Whether the specified processor is
populated.
@retval EFI_SUCCESS The Type 4 structure was successfully
allocated and the strings initialized.
@retval EFI_OUT_OF_RESOURCES Could not allocate memory needed.
**/
EFI_STATUS
AllocateType4AndSetProcessorInformationStrings (
SMBIOS_TABLE_TYPE4 **Type4Record,
UINT8 ProcessorIndex,
BOOLEAN Populated
)
{
EFI_STATUS Status;
EFI_STRING_ID ProcessorManu;
EFI_STRING_ID ProcessorVersion;
EFI_STRING_ID SerialNumber;
EFI_STRING_ID AssetTag;
EFI_STRING_ID PartNumber;
EFI_STRING ProcessorStr;
EFI_STRING ProcessorManuStr;
EFI_STRING ProcessorVersionStr;
EFI_STRING SerialNumberStr;
EFI_STRING AssetTagStr;
EFI_STRING PartNumberStr;
CHAR8 *OptionalStrStart;
CHAR8 *StrStart;
UINTN ProcessorStrLen;
UINTN ProcessorManuStrLen;
UINTN ProcessorVersionStrLen;
UINTN SerialNumberStrLen;
UINTN AssetTagStrLen;
UINTN PartNumberStrLen;
UINTN TotalSize;
UINTN StringBufferSize;
Status = EFI_SUCCESS;
ProcessorManuStr = NULL;
ProcessorVersionStr = NULL;
SerialNumberStr = NULL;
AssetTagStr = NULL;
PartNumberStr = NULL;
ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);
ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);
SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);
AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);
PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorManufacturer, ProcessorManu);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorVersion, ProcessorVersion);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorSerialNumber, SerialNumber);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorAssetTag, AssetTag);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorPartNumber, PartNumber);
// Processor Designation
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;
ProcessorStr = AllocateZeroPool (StringBufferSize);
if (ProcessorStr == NULL) {
return EFI_OUT_OF_RESOURCES;
}
ProcessorStrLen = UnicodeSPrint (ProcessorStr, StringBufferSize,
L"CPU%02d", ProcessorIndex + 1);
// Processor Manufacture
ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);
ProcessorManuStrLen = StrLen (ProcessorManuStr);
// Processor Version
ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);
ProcessorVersionStrLen = StrLen (ProcessorVersionStr);
// Serial Number
SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);
SerialNumberStrLen = StrLen (SerialNumberStr);
// Asset Tag
AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);
AssetTagStrLen = StrLen (AssetTagStr);
// Part Number
PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);
PartNumberStrLen = StrLen (PartNumberStr);
TotalSize = sizeof (SMBIOS_TABLE_TYPE4) +
ProcessorStrLen + 1 +
ProcessorManuStrLen + 1 +
ProcessorVersionStrLen + 1 +
SerialNumberStrLen + 1 +
AssetTagStrLen + 1 +
PartNumberStrLen + 1 + 1;
*Type4Record = AllocateZeroPool (TotalSize);
if (*Type4Record == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
CopyMem (*Type4Record, &mSmbiosProcessorTableTemplate, sizeof (SMBIOS_TABLE_TYPE4));
OptionalStrStart = (CHAR8 *)(*Type4Record + 1);
UnicodeStrToAsciiStrS (
ProcessorStr,
OptionalStrStart,
ProcessorStrLen + 1
);
StrStart = OptionalStrStart + ProcessorStrLen + 1;
UnicodeStrToAsciiStrS (
ProcessorManuStr,
StrStart,
ProcessorManuStrLen + 1
);
StrStart += ProcessorManuStrLen + 1;
UnicodeStrToAsciiStrS (
ProcessorVersionStr,
StrStart,
ProcessorVersionStrLen + 1
);
StrStart += ProcessorVersionStrLen + 1;
UnicodeStrToAsciiStrS (
SerialNumberStr,
StrStart,
SerialNumberStrLen + 1
);
StrStart += SerialNumberStrLen + 1;
UnicodeStrToAsciiStrS (
AssetTagStr,
StrStart,
AssetTagStrLen + 1
);
StrStart += AssetTagStrLen + 1;
UnicodeStrToAsciiStrS (
PartNumberStr,
StrStart,
PartNumberStrLen + 1
);
Exit:
FreePool (ProcessorStr);
FreePool (ProcessorManuStr);
FreePool (ProcessorVersionStr);
FreePool (SerialNumberStr);
FreePool (AssetTagStr);
FreePool (PartNumberStr);
return Status;
}
/**
Add Type 4 SMBIOS Record for Processor Information.
@param[in] ProcessorIndex Processor index of specified processor.
**/
EFI_STATUS
AddSmbiosProcessorTypeTable (
IN UINTN ProcessorIndex
)
{
EFI_STATUS Status;
SMBIOS_TABLE_TYPE4 *Type4Record;
EFI_SMBIOS_HANDLE SmbiosHandle;
EFI_SMBIOS_HANDLE L1CacheHandle;
EFI_SMBIOS_HANDLE L2CacheHandle;
EFI_SMBIOS_HANDLE L3CacheHandle;
UINT8 *LegacyVoltage;
PROCESSOR_STATUS_DATA ProcessorStatus;
UINT64 *ProcessorId;
PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics;
OEM_MISC_PROCESSOR_DATA MiscProcessorData;
BOOLEAN ProcessorPopulated;
Type4Record = NULL;
MiscProcessorData.Voltage = 0;
MiscProcessorData.CurrentSpeed = 0;
MiscProcessorData.CoreCount = 0;
MiscProcessorData.CoresEnabled = 0;
MiscProcessorData.ThreadCount = 0;
MiscProcessorData.MaxSpeed = 0;
L1CacheHandle = 0xFFFF;
L2CacheHandle = 0xFFFF;
L3CacheHandle = 0xFFFF;
ProcessorPopulated = OemIsProcessorPresent (ProcessorIndex);
Status = AllocateType4AndSetProcessorInformationStrings (
&Type4Record,
ProcessorIndex,
ProcessorPopulated
);
if (EFI_ERROR (Status)) {
return Status;
}
OemGetProcessorInformation (ProcessorIndex,
&ProcessorStatus,
(PROCESSOR_CHARACTERISTIC_FLAGS*)
&Type4Record->ProcessorCharacteristics,
&MiscProcessorData);
if (ProcessorPopulated) {
AddSmbiosCacheTypeTable (ProcessorIndex, &L1CacheHandle,
&L2CacheHandle, &L3CacheHandle);
}
LegacyVoltage = (UINT8*)&Type4Record->Voltage;
*LegacyVoltage = MiscProcessorData.Voltage;
Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
Type4Record->Status = ProcessorStatus.Data;
Type4Record->L1CacheHandle = L1CacheHandle;
Type4Record->L2CacheHandle = L2CacheHandle;
Type4Record->L3CacheHandle = L3CacheHandle;
Type4Record->CoreCount = MiscProcessorData.CoreCount;
Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;
Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);
Type4Record->ExternalClock =
(UINT16)(SmbiosGetExternalClockFrequency () / 1000 / 1000);
ProcessorId = (UINT64*)&Type4Record->ProcessorId;
*ProcessorId = SmbiosGetProcessorId ();
ProcessorCharacteristics = SmbiosGetProcessorCharacteristics ();
Type4Record->ProcessorCharacteristics |= *((UINT64*)&ProcessorCharacteristics);
Type4Record->ProcessorFamily = SmbiosGetProcessorFamily ();
Type4Record->ProcessorFamily2 = SmbiosGetProcessorFamily2 ();
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,
(EFI_SMBIOS_TABLE_HEADER *)Type4Record);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n",
__FUNCTION__, __LINE__, Status));
}
FreePool (Type4Record);
return Status;
}
/**
Standard EFI driver point.
@param ImageHandle Handle for the image of this driver
@param SystemTable Pointer to the EFI System Table
@retval EFI_SUCCESS The data was successfully stored.
**/
EFI_STATUS
EFIAPI
ProcessorSubClassEntryPoint(
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINT32 ProcessorIndex;
//
// Locate dependent protocols
//
Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status));
return Status;
}
//
// Add our default strings to the HII database. They will be modified later.
//
mHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,
NULL,
ProcessorSubClassStrings,
NULL,
NULL
);
if (mHiiHandle == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Add SMBIOS tables for populated sockets.
//
for (ProcessorIndex = 0; ProcessorIndex < OemGetMaxProcessors (); ProcessorIndex++) {
Status = AddSmbiosProcessorTypeTable (ProcessorIndex);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Add Processor Type Table Failed! %r.\n", Status));
return Status;
}
}
return Status;
}

View File

@@ -1,66 +0,0 @@
#/** @file
# ProcessorSubClassDxe.inf
#
# Copyright (c) 2021, NUVIA Inc. All rights reserved.
# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
# Copyright (c) 2015, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 1.29
BASE_NAME = ProcessorSubClass
FILE_GUID = f3fe0e33-ea38-4069-9fb5-be23407207c7
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = ProcessorSubClassEntryPoint
[Sources]
SmbiosProcessorArmCommon.c
ProcessorSubClass.c
ProcessorSubClassStrings.uni
SmbiosProcessor.h
[Sources.AARCH64]
SmbiosProcessorAArch64.c
[Sources.ARM]
SmbiosProcessorArm.c
[Packages]
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
ArmSmcLib
BaseLib
BaseMemoryLib
DebugLib
HiiLib
IoLib
MemoryAllocationLib
OemMiscLib
PcdLib
PrintLib
UefiDriverEntryPoint
[Protocols]
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Pcd]
gArmTokenSpaceGuid.PcdProcessorManufacturer
gArmTokenSpaceGuid.PcdProcessorVersion
gArmTokenSpaceGuid.PcdProcessorSerialNumber
gArmTokenSpaceGuid.PcdProcessorAssetTag
gArmTokenSpaceGuid.PcdProcessorPartNumber
[Guids]
[Depex]
gEfiSmbiosProtocolGuid

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@@ -1,24 +0,0 @@
/** @file
SMBIOS Type 4 strings
Copyright (c) 2021, NUVIA Inc. All rights reserved.
Copyright (c) 2015, Hisilicon Limited. All rights reserved.
Copyright (c) 2015, Linaro Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
/=#
#langdef en-US "English"
//
// Processor Information
//
#string STR_PROCESSOR_SOCKET_DESIGNATION #language en-US "Not Specified"
#string STR_PROCESSOR_MANUFACTURE #language en-US "Not Specified"
#string STR_PROCESSOR_VERSION #language en-US "Not Specified"
#string STR_PROCESSOR_SERIAL_NUMBER #language en-US "Not Specified"
#string STR_PROCESSOR_ASSET_TAG #language en-US "Not Specified"
#string STR_PROCESSOR_PART_NUMBER #language en-US "Not Specified"
#string STR_PROCESSOR_UNKNOWN #language en-US "Unknown"

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@@ -1,102 +0,0 @@
/** @file
SMBIOS Processor Related Functions.
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef SMBIOS_PROCESSOR_H_
#define SMBIOS_PROCESSOR_H_
#include <Uefi.h>
#include <IndustryStandard/SmBios.h>
/** Returns the maximum cache level implemented by the current CPU.
@return The maximum cache level implemented.
**/
UINT8
SmbiosProcessorGetMaxCacheLevel (
VOID
);
/** Returns whether or not the specified cache level has separate I/D caches.
@param CacheLevel The cache level (L1, L2 etc.).
@return TRUE if the cache level has separate I/D caches, FALSE otherwise.
**/
BOOLEAN
SmbiosProcessorHasSeparateCaches (
UINT8 CacheLevel
);
/** Gets the size of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache size.
**/
UINT64
SmbiosProcessorGetCacheSize (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
);
/** Gets the associativity of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache associativity.
**/
UINT32
SmbiosProcessorGetCacheAssociativity (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
);
/** Returns a value for the Processor ID field that conforms to SMBIOS
requirements.
@return Processor ID.
**/
UINT64
SmbiosGetProcessorId (VOID);
/** Returns the external clock frequency.
@return The external CPU clock frequency.
**/
UINTN
SmbiosGetExternalClockFrequency (VOID);
/** Returns the SMBIOS ProcessorFamily field value.
@return The value for the ProcessorFamily field.
**/
UINT8
SmbiosGetProcessorFamily (VOID);
/** Returns the ProcessorFamily2 field value.
@return The value for the ProcessorFamily2 field.
**/
UINT16
SmbiosGetProcessorFamily2 (VOID);
/** Returns the SMBIOS Processor Characteristics.
@return Processor Characteristics bitfield.
**/
PROCESSOR_CHARACTERISTIC_FLAGS
SmbiosGetProcessorCharacteristics (VOID);
#endif // SMBIOS_PROCESSOR_H_

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@@ -1,93 +0,0 @@
/** @file
Functions for AARCH64 processor information
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include "SmbiosProcessor.h"
/** Gets the size of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache size.
**/
UINT64
SmbiosProcessorGetCacheSize (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
CSSELR_DATA Csselr;
BOOLEAN CcidxSupported;
UINT64 CacheSize;
Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
CcidxSupported = ArmHasCcidx ();
if (CcidxSupported) {
CacheSize = (1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) *
(Ccsidr.BitsCcidxAA64.Associativity + 1) *
(Ccsidr.BitsCcidxAA64.NumSets + 1);
} else {
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
(Ccsidr.BitsNonCcidx.Associativity + 1) *
(Ccsidr.BitsNonCcidx.NumSets + 1);
}
return CacheSize;
}
/** Gets the associativity of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache associativity.
**/
UINT32
SmbiosProcessorGetCacheAssociativity (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
CSSELR_DATA Csselr;
BOOLEAN CcidxSupported;
UINT32 Associativity;
Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
CcidxSupported = ArmHasCcidx ();
if (CcidxSupported) {
Associativity = Ccsidr.BitsCcidxAA64.Associativity + 1;
} else {
Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;
}
return Associativity;
}

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@@ -1,97 +0,0 @@
/** @file
Functions for ARM processor information
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include "SmbiosProcessor.h"
/** Gets the size of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache size.
**/
UINT64
SmbiosProcessorGetCacheSize (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
CCSIDR2_DATA Ccsidr2;
CSSELR_DATA Csselr;
BOOLEAN CcidxSupported;
UINT64 CacheSize;
// Read the CCSIDR register to get the cache architecture
Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
CcidxSupported = ArmHasCcidx ();
if (CcidxSupported) {
Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);
CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
(Ccsidr.BitsCcidxAA32.Associativity + 1) *
(Ccsidr2.Bits.NumSets + 1);
} else {
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
(Ccsidr.BitsNonCcidx.Associativity + 1) *
(Ccsidr.BitsNonCcidx.NumSets + 1);
}
return CacheSize;
}
/** Gets the associativity of the specified cache.
@param CacheLevel The cache level (L1, L2 etc.).
@param DataCache Whether the cache is a dedicated data cache.
@param UnifiedCache Whether the cache is a unified cache.
@return The cache associativity.
**/
UINT32
SmbiosProcessorGetCacheAssociativity (
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
CSSELR_DATA Csselr;
BOOLEAN CcidxSupported;
UINT32 Associativity;
// Read the CCSIDR register to get the cache architecture
Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
CcidxSupported = ArmHasCcidx ();
if (CcidxSupported) {
Associativity = Ccsidr.BitsCcidxAA32.Associativity + 1;
} else {
Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;
}
return Associativity;
}

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@@ -1,249 +0,0 @@
/** @file
Functions for processor information common to ARM and AARCH64.
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>
#include "SmbiosProcessor.h"
/** Returns the maximum cache level implemented by the current CPU.
@return The maximum cache level implemented.
**/
UINT8
SmbiosProcessorGetMaxCacheLevel (
VOID
)
{
CLIDR_DATA Clidr;
UINT8 CacheLevel;
UINT8 MaxCacheLevel;
MaxCacheLevel = 0;
// Read the CLIDR register to find out what caches are present.
Clidr.Data = ReadCLIDR ();
// Get the cache type for the L1 cache. If it's 0, there are no caches.
if (CLIDR_GET_CACHE_TYPE (Clidr.Data, 1) == ClidrCacheTypeNone) {
return 0;
}
for (CacheLevel = 1; CacheLevel <= MAX_ARM_CACHE_LEVEL; CacheLevel++) {
if (CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel) == ClidrCacheTypeNone) {
MaxCacheLevel = CacheLevel;
break;
}
}
return MaxCacheLevel;
}
/** Returns whether or not the specified cache level has separate I/D caches.
@param CacheLevel The cache level (L1, L2 etc.).
@return TRUE if the cache level has separate I/D caches, FALSE otherwise.
**/
BOOLEAN
SmbiosProcessorHasSeparateCaches (
UINT8 CacheLevel
)
{
CLIDR_CACHE_TYPE CacheType;
CLIDR_DATA Clidr;
BOOLEAN SeparateCaches;
SeparateCaches = FALSE;
Clidr.Data = ReadCLIDR ();
CacheType = CLIDR_GET_CACHE_TYPE (Clidr.Data, CacheLevel - 1);
if (CacheType == ClidrCacheTypeSeparate) {
SeparateCaches = TRUE;
}
return SeparateCaches;
}
/** Checks if ther ARM64 SoC ID SMC call is supported
@return Whether the ARM64 SoC ID call is supported.
**/
BOOLEAN
HasSmcArm64SocId (
VOID
)
{
ARM_SMC_ARGS Args;
INT32 SmcCallStatus;
BOOLEAN Arm64SocIdSupported;
Arm64SocIdSupported = FALSE;
Args.Arg0 = SMCCC_VERSION;
ArmCallSmc (&Args);
SmcCallStatus = (INT32)Args.Arg0;
if (SmcCallStatus < 0 || (SmcCallStatus >> 16) >= 1) {
Args.Arg0 = SMCCC_ARCH_FEATURES;
Args.Arg1 = SMCCC_ARCH_SOC_ID;
ArmCallSmc (&Args);
if (Args.Arg0 >= 0) {
Arm64SocIdSupported = TRUE;
}
}
return Arm64SocIdSupported;
}
/** Fetches the JEP106 code and SoC Revision.
@param Jep106Code JEP 106 code.
@param SocRevision SoC revision.
@retval EFI_SUCCESS Succeeded.
@retval EFI_UNSUPPORTED Failed.
**/
EFI_STATUS
SmbiosGetSmcArm64SocId (
OUT INT32 *Jep106Code,
OUT INT32 *SocRevision
)
{
ARM_SMC_ARGS Args;
INT32 SmcCallStatus;
EFI_STATUS Status;
Status = EFI_SUCCESS;
Args.Arg0 = SMCCC_ARCH_SOC_ID;
Args.Arg1 = 0;
ArmCallSmc (&Args);
SmcCallStatus = (INT32)Args.Arg0;
if (SmcCallStatus >= 0) {
*Jep106Code = (INT32)Args.Arg0;
} else {
Status = EFI_UNSUPPORTED;
}
Args.Arg0 = SMCCC_ARCH_SOC_ID;
Args.Arg1 = 1;
ArmCallSmc (&Args);
SmcCallStatus = (INT32)Args.Arg0;
if (SmcCallStatus >= 0) {
*SocRevision = (INT32)Args.Arg0;
} else {
Status = EFI_UNSUPPORTED;
}
return Status;
}
/** Returns a value for the Processor ID field that conforms to SMBIOS
requirements.
@return Processor ID.
**/
UINT64
SmbiosGetProcessorId (
VOID
)
{
INT32 Jep106Code;
INT32 SocRevision;
UINT64 ProcessorId;
if (HasSmcArm64SocId ()) {
SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);
ProcessorId = ((UINT64)Jep106Code << 32) | SocRevision;
} else {
ProcessorId = ArmReadMidr ();
}
return ProcessorId;
}
/** Returns the external clock frequency.
@return The external clock frequency.
**/
UINTN
SmbiosGetExternalClockFrequency (
VOID
)
{
return ArmReadCntFrq ();
}
/** Returns the SMBIOS ProcessorFamily field value.
@return The value for the ProcessorFamily field.
**/
UINT8
SmbiosGetProcessorFamily (
VOID
)
{
return ProcessorFamilyIndicatorFamily2;
}
/** Returns the ProcessorFamily2 field value.
@return The value for the ProcessorFamily2 field.
**/
UINT16
SmbiosGetProcessorFamily2 (
VOID
)
{
UINTN MainIdRegister;
UINT16 ProcessorFamily2;
MainIdRegister = ArmReadMidr ();
if (((MainIdRegister >> 16) & 0xF) < 8) {
ProcessorFamily2 = ProcessorFamilyARM;
} else {
if (sizeof (VOID*) == 4) {
ProcessorFamily2 = ProcessorFamilyARMv7;
} else {
ProcessorFamily2 = ProcessorFamilyARMv8;
}
}
return ProcessorFamily2;
}
/** Returns the SMBIOS Processor Characteristics.
@return Processor Characteristics bitfield.
**/
PROCESSOR_CHARACTERISTIC_FLAGS
SmbiosGetProcessorCharacteristics (
VOID
)
{
PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;
ZeroMem (&Characteristics, sizeof (Characteristics));
Characteristics.ProcessorArm64SocId = HasSmcArm64SocId ();
return Characteristics;
}

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@@ -1,134 +0,0 @@
/** @file
Header file for the SmbiosMisc Driver.
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef SMBIOS_MISC_H_
#define SMBIOS_MISC_H_
#include <Protocol/Smbios.h>
#include <IndustryStandard/SmBios.h>
//
// Data table entry update function.
//
typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION) (
IN VOID *RecordData,
IN EFI_SMBIOS_PROTOCOL *Smbios
);
//
// Data table entry definition.
//
typedef struct {
//
// intermediate input data for SMBIOS record
//
VOID *RecordData;
SMBIOS_MISC_DATA_FUNCTION *Function;
} SMBIOS_MISC_DATA_TABLE;
//
// SMBIOS table extern definitions
//
#define SMBIOS_MISC_TABLE_EXTERNS(NAME1, NAME2, NAME3) \
extern NAME1 NAME2 ## Data; \
extern SMBIOS_MISC_DATA_FUNCTION NAME3 ## Function;
//
// SMBIOS data table entries
//
// This is used to define a pair of table structure pointer and functions
// in order to iterate through the list of tables, populate them and add
// them into the system.
#define SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \
{ \
& NAME1 ## Data, \
NAME2 ## Function \
}
//
// Global definition macros.
//
#define SMBIOS_MISC_TABLE_DATA(NAME1, NAME2) \
NAME1 NAME2 ## Data
#define SMBIOS_MISC_TABLE_FUNCTION(NAME2) \
EFI_STATUS EFIAPI NAME2 ## Function( \
IN VOID *RecordData, \
IN EFI_SMBIOS_PROTOCOL *Smbios \
)
//
// Data Table Array Entries
//
extern EFI_HII_HANDLE mSmbiosMiscHiiHandle;
typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{
UINT8 *LanguageSignature;
EFI_STRING_ID InstallableLanguageLongString;
EFI_STRING_ID InstallableLanguageAbbreviateString;
} SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING;
/**
Adds an SMBIOS record.
@param Buffer The data for the SMBIOS record.
The format of the record is determined by
EFI_SMBIOS_TABLE_HEADER.Type. The size of the
formatted area is defined by EFI_SMBIOS_TABLE_HEADER.Length
and either followed by a double-null (0x0000) or a set
of null terminated strings and a null.
@param SmbiosHandle A unique handle will be assigned to the SMBIOS record
if not NULL.
@retval EFI_SUCCESS Record was added.
@retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources.
@retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in use.
**/
EFI_STATUS
SmbiosMiscAddRecord (
IN UINT8 *Buffer,
IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL
);
/**
Get Link Type Handle.
@param [in] SmbiosType Get this Type from SMBIOS table
@param [out] HandleArray Pointer to handle array which will be freed by caller
@param [out] HandleCount Pointer to handle count
**/
VOID
SmbiosMiscGetLinkTypeHandle(
IN UINT8 SmbiosType,
OUT UINT16 **HandleArray,
OUT UINTN *HandleCount
);
//
// Data Table Array
//
extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[];
//
// Data Table Array Entries
//
extern UINTN mSmbiosMiscDataTableEntries;
extern UINT8 mSmbiosMiscDxeStrings[];
#endif // SMBIOS_MISC_H_

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@@ -1,62 +0,0 @@
/** @file
This file provides SMBIOS Misc Type.
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent\
**/
#include "SmbiosMisc.h"
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE0,
MiscBiosVendor,
MiscBiosVendor)
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE1,
MiscSystemManufacturer,
MiscSystemManufacturer)
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE3,
MiscChassisManufacturer,
MiscChassisManufacturer)
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE2,
MiscBaseBoardManufacturer,
MiscBaseBoardManufacturer)
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE13,
MiscNumberOfInstallableLanguages,
MiscNumberOfInstallableLanguages)
SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE32,
MiscBootInformation,
MiscBootInformation)
SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[] = {
// Type0
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBiosVendor,
MiscBiosVendor),
// Type1
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscSystemManufacturer,
MiscSystemManufacturer),
// Type3
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscChassisManufacturer,
MiscChassisManufacturer),
// Type2
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBaseBoardManufacturer,
MiscBaseBoardManufacturer),
// Type13
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscNumberOfInstallableLanguages,
MiscNumberOfInstallableLanguages),
// Type32
SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBootInformation,
MiscBootInformation),
};
//
// Number of Data Table entries.
//
UINTN mSmbiosMiscDataTableEntries =
(sizeof (mSmbiosMiscDataTable)) / sizeof (SMBIOS_MISC_DATA_TABLE);

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@@ -1,89 +0,0 @@
#/** @file
# Component description file for SmbiosMisc instance.
#
# Parses the MiscSubclassDataTable and reports any generated data to the DataHub.
# All .uni file who tagged with "ToolCode="DUMMY"" in following file list is included by
# MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclassDriver.uni file
# and parse all .uni file.
#
# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
# Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
#**/
[Defines]
INF_VERSION = 1.29
BASE_NAME = SmbiosMiscDxe
FILE_GUID = 7e5e26d4-0be9-401f-b5e1-1c2bda7ca777
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = SmbiosMiscEntryPoint
[Sources]
SmbiosMisc.h
SmbiosMiscDataTable.c
SmbiosMiscEntryPoint.c
SmbiosMiscDxeStrings.uni
Type00/MiscBiosVendorData.c
Type00/MiscBiosVendorFunction.c
Type01/MiscSystemManufacturerData.c
Type01/MiscSystemManufacturerFunction.c
Type02/MiscBaseBoardManufacturerData.c
Type02/MiscBaseBoardManufacturerFunction.c
Type03/MiscChassisManufacturerData.c
Type03/MiscChassisManufacturerFunction.c
Type13/MiscNumberOfInstallableLanguagesData.c
Type13/MiscNumberOfInstallableLanguagesFunction.c
Type32/MiscBootInformationData.c
Type32/MiscBootInformationFunction.c
[Packages]
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
DebugLib
DevicePathLib
PcdLib
HiiLib
HobLib
MemoryAllocationLib
OemMiscLib
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiLib
UefiRuntimeServicesTableLib
[Protocols]
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[Pcd]
gArmTokenSpaceGuid.PcdFdSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gArmTokenSpaceGuid.PcdSystemBiosRelease
gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease
gArmTokenSpaceGuid.PcdSystemProductName
gArmTokenSpaceGuid.PcdSystemVersion
gArmTokenSpaceGuid.PcdBaseBoardManufacturer
gArmTokenSpaceGuid.PcdBaseBoardProductName
gArmTokenSpaceGuid.PcdBaseBoardVersion
gArmTokenSpaceGuid.PcdFdBaseAddress
[Guids]
gEfiGenericVariableGuid
[Depex]
gEfiSmbiosProtocolGuid

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@@ -1,22 +0,0 @@
/** @file
* Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
*
* Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
* Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
* Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
* Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
*
**/
/=#
#langdef en-US "English"
#include "Type00/MiscBiosVendor.uni"
#include "Type01/MiscSystemManufacturer.uni"
#include "Type02/MiscBaseBoardManufacturer.uni"
#include "Type03/MiscChassisManufacturer.uni"
#include "Type13/MiscNumberOfInstallableLanguages.uni"

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@@ -1,223 +0,0 @@
/** @file
This driver parses the mSmbiosMiscDataTable structure and reports
any generated data using SMBIOS protocol.
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HiiLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include "SmbiosMisc.h"
STATIC EFI_HANDLE mSmbiosMiscImageHandle;
STATIC EFI_SMBIOS_PROTOCOL *mSmbiosMiscSmbios = NULL;
EFI_HII_HANDLE mSmbiosMiscHiiHandle;
/**
Standard EFI driver point. This driver parses the mSmbiosMiscDataTable
structure and reports any generated data using SMBIOS protocol.
@param ImageHandle Handle for the image of this driver
@param SystemTable Pointer to the EFI System Table
@retval EFI_SUCCESS The data was successfully stored.
**/
EFI_STATUS
EFIAPI
SmbiosMiscEntryPoint(
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
UINTN Index;
EFI_STATUS EfiStatus;
mSmbiosMiscImageHandle = ImageHandle;
EfiStatus = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL,
(VOID**)&mSmbiosMiscSmbios);
if (EFI_ERROR (EfiStatus)) {
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus));
return EfiStatus;
}
mSmbiosMiscHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,
mSmbiosMiscImageHandle,
SmbiosMiscDxeStrings,
NULL
);
if (mSmbiosMiscHiiHandle == NULL) {
return EFI_OUT_OF_RESOURCES;
}
for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index) {
//
// If the entry have a function pointer, just log the data.
//
if (mSmbiosMiscDataTable[Index].Function != NULL) {
EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(mSmbiosMiscDataTable[Index].RecordData,
mSmbiosMiscSmbios
);
if (EFI_ERROR(EfiStatus)) {
DEBUG ((DEBUG_ERROR, "Misc smbios store error. Index=%d,"
"ReturnStatus=%r\n", Index, EfiStatus));
return EfiStatus;
}
}
}
return EfiStatus;
}
/**
Adds an SMBIOS record.
@param Buffer The data for the SMBIOS record.
The format of the record is determined by
EFI_SMBIOS_TABLE_HEADER.Type. The size of the
formatted area is defined by EFI_SMBIOS_TABLE_HEADER.Length
and either followed by a double-null (0x0000) or a set
of null terminated strings and a null.
@param SmbiosHandle A unique handle will be assigned to the SMBIOS record
if not NULL.
@retval EFI_SUCCESS Record was added.
@retval EFI_OUT_OF_RESOURCES Record was not added due to lack of system resources.
@retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in use.
**/
EFI_STATUS
SmbiosMiscAddRecord (
IN UINT8 *Buffer,
IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL
)
{
EFI_STATUS Status;
EFI_SMBIOS_HANDLE Handle;
Handle = SMBIOS_HANDLE_PI_RESERVED;
if (SmbiosHandle != NULL) {
Handle = *SmbiosHandle;
}
Status = mSmbiosMiscSmbios->Add (
mSmbiosMiscSmbios,
NULL,
&Handle,
(EFI_SMBIOS_TABLE_HEADER *)Buffer
);
if (SmbiosHandle != NULL) {
*SmbiosHandle = Handle;
}
return Status;
}
/** Fetches the number of handles of the specified SMBIOS type.
*
* @param SmbiosType The type of SMBIOS record to look for.
*
* @return The number of handles
*
**/
STATIC
UINTN
GetHandleCount (
IN UINT8 SmbiosType
)
{
UINTN HandleCount;
EFI_STATUS Status;
EFI_SMBIOS_HANDLE SmbiosHandle;
EFI_SMBIOS_TABLE_HEADER *Record;
HandleCount = 0;
// Iterate through entries to get the number
do {
Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,
&SmbiosHandle,
&SmbiosType,
&Record,
NULL
);
if (Status == EFI_SUCCESS) {
HandleCount++;
}
} while (!EFI_ERROR (Status));
return HandleCount;
}
/**
Fetches a list of the specified SMBIOS table types.
@param[in] SmbiosType The type of table to fetch
@param[out] **HandleArray The array of handles
@param[out] *HandleCount Number of handles in the array
**/
VOID
SmbiosMiscGetLinkTypeHandle(
IN UINT8 SmbiosType,
OUT SMBIOS_HANDLE **HandleArray,
OUT UINTN *HandleCount
)
{
UINTN Index;
EFI_STATUS Status;
EFI_SMBIOS_HANDLE SmbiosHandle;
EFI_SMBIOS_TABLE_HEADER *Record;
if (mSmbiosMiscSmbios == NULL) {
return;
}
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
*HandleCount = GetHandleCount (SmbiosType);
*HandleArray = AllocateZeroPool (sizeof (SMBIOS_HANDLE) * (*HandleCount));
if (*HandleArray == NULL) {
DEBUG ((DEBUG_ERROR, "HandleArray allocate memory resource failed.\n"));
*HandleCount = 0;
return;
}
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
for (Index = 0; Index < (*HandleCount); Index++) {
Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,
&SmbiosHandle,
&SmbiosType,
&Record,
NULL
);
if (!EFI_ERROR (Status)) {
(*HandleArray)[Index] = Record->Handle;
} else {
break;
}
}
}

View File

@@ -1,18 +0,0 @@
/** @file
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
/=#
#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified"
#string STR_MISC_BIOS_VERSION #language en-US "Not Specified"
#string STR_MISC_BIOS_RELEASE_DATE #language en-US "Not Specified"
#string STR_MISC_BIOS_VENDOR #language en-US "Not Specified"
#string STR_MISC_BIOS_RELEASE_DATE #language en-US "12/02/2020"

View File

@@ -1,93 +0,0 @@
/** @file
This file provides Smbios Type0 Data
Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SmbiosMisc.h"
//
// Static (possibly build generated) Bios Vendor data.
//
SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {
{ // Hdr
EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,
0, // Length,
0 // Handle
},
1, // Vendor
2, // BiosVersion
0xE000, // BiosSegment
3, // BiosReleaseDate
0, // BiosSize
{ // BiosCharacteristics
0, // Reserved :2
0, // Unknown :1
0, // BiosCharacteristicsNotSupported :1
0, // IsaIsSupported :1
0, // McaIsSupported :1
0, // EisaIsSupported :1
1, // PciIsSupported :1
0, // PcmciaIsSupported :1
1, // PlugAndPlayIsSupported :1
0, // ApmIsSupported :1
1, // BiosIsUpgradable :1
1, // BiosShadowingAllowed :1
0, // VlVesaIsSupported :1
0, // EscdSupportIsAvailable :1
1, // BootFromCdIsSupported :1
1, // SelectableBootIsSupported :1
0, // RomBiosIsSocketed :1
0, // BootFromPcmciaIsSupported :1
0, // EDDSpecificationIsSupported :1
0, // JapaneseNecFloppyIsSupported :1
0, // JapaneseToshibaFloppyIsSupported :1
0, // Floppy525_360IsSupported :1
0, // Floppy525_12IsSupported :1
0, // Floppy35_720IsSupported :1
0, // Floppy35_288IsSupported :1
0, // PrintScreenIsSupported :1
0, // Keyboard8042IsSupported :1
0, // SerialIsSupported :1
0, // PrinterIsSupported :1
0, // CgaMonoIsSupported :1
0, // NecPc98 :1
0 // ReservedForVendor :32
},
{
0x01, // BIOSCharacteristicsExtensionBytes[0]
// { // BiosReserved
// 1, // AcpiIsSupported :1
// 0, // UsbLegacyIsSupported :1
// 0, // AgpIsSupported :1
// 0, // I20BootIsSupported :1
// 0, // Ls120BootIsSupported :1
// 0, // AtapiZipDriveBootIsSupported :1
// 0, // Boot1394IsSupported :1
// 0 // SmartBatteryIsSupported :1
// },
0x0C //BIOSCharacteristicsExtensionBytes[1]
// { //SystemReserved
// 0, //BiosBootSpecIsSupported :1
// 0, //FunctionKeyNetworkBootIsSupported :1
// 1, //TargetContentDistributionEnabled :1
// 1, //UefiSpecificationSupported :1
// 0, //VirtualMachineSupported :1
// 0 //ExtensionByte2Reserved :3
// },
},
0xFF, // SystemBiosMajorRelease;
0xFF, // SystemBiosMinorRelease;
0xFF, // EmbeddedControllerFirmwareMajorRelease;
0xFF // EmbeddedControllerFirmwareMinorRelease;
};

View File

@@ -1,296 +0,0 @@
/** @file
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HiiLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include "SmbiosMisc.h"
typedef struct {
CONST CHAR8* MonthStr;
UINT32 MonthInt;
} MONTH_DESCRIPTION;
STATIC CONST
MONTH_DESCRIPTION mMonthDescription[] = {
{ "Jan", 1 },
{ "Feb", 2 },
{ "Mar", 3 },
{ "Apr", 4 },
{ "May", 5 },
{ "Jun", 6 },
{ "Jul", 7 },
{ "Aug", 8 },
{ "Sep", 9 },
{ "Oct", 10 },
{ "Nov", 11 },
{ "Dec", 12 },
{ "???", 1 }, // Use 1 as default month
};
/**
Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k'
as the unit.
@param Value Pointer to Base2_Data
@retval
**/
UINT8
Base2ToByteWith64KUnit (
IN UINTN Value
)
{
UINT8 Size;
Size = ((Value + (SIZE_64KB - 1)) >> 16);
return Size;
}
/**
Returns the date and time this file (and firmware) was built.
@param[out] *Time Pointer to the EFI_TIME structure to fill in.
**/
VOID
GetReleaseTime (
OUT EFI_TIME *Time
)
{
CONST CHAR8 *ReleaseDate = __DATE__;
CONST CHAR8 *ReleaseTime = __TIME__;
UINTN i;
for (i = 0; i < 12; i++) {
if (AsciiStrnCmp (ReleaseDate, mMonthDescription[i].MonthStr, 3) == 0) {
break;
}
}
Time->Month = mMonthDescription[i].MonthInt;
Time->Day = AsciiStrDecimalToUintn (ReleaseDate + 4);
Time->Year = AsciiStrDecimalToUintn (ReleaseDate + 7);
Time->Hour = AsciiStrDecimalToUintn (ReleaseTime);
Time->Minute = AsciiStrDecimalToUintn (ReleaseTime + 3);
Time->Second = AsciiStrDecimalToUintn (ReleaseTime + 6);
}
/**
Fetches the firmware ('BIOS') release date from the
FirmwareVersionInfo HOB.
@return The release date as a UTF-16 string
**/
CHAR16 *
GetBiosReleaseDate (
VOID
)
{
CHAR16 *ReleaseDate;
EFI_TIME BuildTime;
ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
if (ReleaseDate == NULL) {
return NULL;
}
GetReleaseTime (&BuildTime);
(VOID)UnicodeSPrintAsciiFormat (ReleaseDate,
(sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,
"%02d/%02d/%4d",
BuildTime.Month,
BuildTime.Day,
BuildTime.Year
);
return ReleaseDate;
}
/**
Fetches the firmware ('BIOS') version from the
FirmwareVersionInfo HOB.
@return The version as a UTF-16 string
**/
CHAR16 *
GetBiosVersion (
VOID
)
{
CHAR16 *ReleaseString;
ReleaseString = (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString);
return ReleaseString;
}
/**
This function makes boot time changes to the contents of the
MiscBiosVendor (Type 0) record.
@param RecordData Pointer to SMBIOS table with default values.
@param Smbios SMBIOS protocol.
@retval EFI_SUCCESS The SMBIOS table was successfully added.
@retval EFI_INVALID_PARAMETER Invalid parameter was found.
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor)
{
CHAR8 *OptionalStrStart;
CHAR8 *StrStart;
UINTN VendorStrLen;
UINTN VerStrLen;
UINTN DateStrLen;
UINTN BiosPhysicalSize;
CHAR16 *Vendor;
CHAR16 *Version;
CHAR16 *ReleaseDate;
CHAR16 *Char16String;
EFI_STATUS Status;
EFI_STRING_ID TokenToUpdate;
EFI_STRING_ID TokenToGet;
SMBIOS_TABLE_TYPE0 *SmbiosRecord;
SMBIOS_TABLE_TYPE0 *InputData;
//
// First check for invalid parameters.
//
if (RecordData == NULL) {
return EFI_INVALID_PARAMETER;
}
InputData = (SMBIOS_TABLE_TYPE0 *)RecordData;
Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor);
if (StrLen (Vendor) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Vendor, NULL);
}
Version = GetBiosVersion();
if (StrLen (Version) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);
} else {
Version = (CHAR16 *) PcdGetPtr (PcdFirmwareVersionString);
if (StrLen (Version) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);
}
}
Char16String = GetBiosReleaseDate ();
if (StrLen(Char16String) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Char16String, NULL);
}
TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
Vendor = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
VendorStrLen = StrLen (Vendor);
TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
VerStrLen = StrLen (Version);
TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
ReleaseDate = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
DateStrLen = StrLen (ReleaseDate);
//
// Now update the BiosPhysicalSize
//
BiosPhysicalSize = FixedPcdGet32 (PcdFdSize);
//
// Two zeros following the last string.
//
SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 +
VerStrLen + 1 +
DateStrLen + 1 + 1);
if (SmbiosRecord == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
(VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0));
SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / SIZE_64KB);
if (BiosPhysicalSize < SIZE_16MB) {
SmbiosRecord->BiosSize = Base2ToByteWith64KUnit (BiosPhysicalSize) - 1;
SmbiosRecord->ExtendedBiosSize.Size = BiosPhysicalSize / SIZE_1MB;
SmbiosRecord->ExtendedBiosSize.Unit = 0; // Size is in MB
} else {
SmbiosRecord->BiosSize = 0xFF;
if (BiosPhysicalSize > 0x3FFF) {
SmbiosRecord->ExtendedBiosSize.Size = BiosPhysicalSize / SIZE_1GB;
SmbiosRecord->ExtendedBiosSize.Unit = 1; // Size is in GB
}
}
SmbiosRecord->SystemBiosMajorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) >> 8);
SmbiosRecord->SystemBiosMinorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) & 0xFF);
SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = (UINT16)
(PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8);
SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = (UINT16)
(PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF);
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1);
StrStart = OptionalStrStart + VendorStrLen + 1;
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);
StrStart += VerStrLen + 1;
UnicodeStrToAsciiStrS (ReleaseDate, StrStart, DateStrLen + 1);
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//
Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n",
__FUNCTION__, __LINE__, Status));
}
FreePool (SmbiosRecord);
Exit:
if (Vendor != NULL) {
FreePool (Vendor);
}
if (Version != NULL) {
FreePool (Version);
}
if (ReleaseDate != NULL) {
FreePool (ReleaseDate);
}
if (Char16String != NULL) {
FreePool (Char16String);
}
return Status;
}

View File

@@ -1,20 +0,0 @@
/** @file
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
/=#
#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Not Specified"
#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified"
#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "Not Specified"
#string STR_MISC_SYSTEM_VERSION #language en-US "Not Specified"
#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "Not Specified"
#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "Not Specified"
#string STR_MISC_SYSTEM_FAMILY #language en-US "Not Specified"

View File

@@ -1,36 +0,0 @@
/** @file
This file provides Smbios Type1 Data
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SmbiosMisc.h"
//
// Static (possibly build generated) System Manufacturer data.
//
SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {
{ // Hdr
EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
0, // Length,
0 // Handle
},
1, // Manufacturer
2, // ProductName
3, // Version
4, // SerialNumber
{ // Uuid
0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
SystemWakeupTypePowerSwitch, // SystemWakeupType
5, // SKUNumber,
6 // Family
};

View File

@@ -1,196 +0,0 @@
/** @file
This driver parses the mMiscSubclassDataTable structure and reports
any generated data to smbios.
Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HiiLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/OemMiscLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include "SmbiosMisc.h"
/**
This function makes boot time changes to the contents of the
MiscSystemManufacturer (Type 1) record.
@param RecordData Pointer to SMBIOS table with default values.
@param Smbios SMBIOS protocol.
@retval EFI_SUCCESS The SMBIOS table was successfully added.
@retval EFI_INVALID_PARAMETER Invalid parameter was found.
@retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer)
{
CHAR8 *OptionalStrStart;
CHAR8 *StrStart;
UINTN ManuStrLen;
UINTN VerStrLen;
UINTN PdNameStrLen;
UINTN SerialNumStrLen;
UINTN SKUNumStrLen;
UINTN FamilyStrLen;
UINTN RecordLength;
EFI_STRING Manufacturer;
EFI_STRING ProductName;
EFI_STRING Version;
EFI_STRING SerialNumber;
EFI_STRING SKUNumber;
EFI_STRING Family;
EFI_STRING_ID TokenToGet;
SMBIOS_TABLE_TYPE1 *SmbiosRecord;
SMBIOS_TABLE_TYPE1 *InputData;
EFI_STATUS Status;
EFI_STRING_ID TokenToUpdate;
CHAR16 *Product;
CHAR16 *pVersion;
Status = EFI_SUCCESS;
//
// First check for invalid parameters.
//
if (RecordData == NULL) {
return EFI_INVALID_PARAMETER;
}
InputData = (SMBIOS_TABLE_TYPE1 *)RecordData;
Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName);
if (StrLen (Product) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Product, NULL);
}
pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion);
if (StrLen (pVersion) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, pVersion, NULL);
}
OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER),
SerialNumType01);
OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER),
SystemManufacturerType01);
OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER),
SkuNumberType01);
OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_SYSTEM_FAMILY),
FamilyType01);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
Manufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
ManuStrLen = StrLen (Manufacturer);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
ProductName = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
PdNameStrLen = StrLen (ProductName);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
VerStrLen = StrLen (Version);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER);
SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
SerialNumStrLen = StrLen (SerialNumber);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);
SKUNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
SKUNumStrLen = StrLen (SKUNumber);
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY);
Family = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
FamilyStrLen = StrLen (Family);
//
// Two zeros following the last string.
//
RecordLength = sizeof (SMBIOS_TABLE_TYPE1) +
ManuStrLen + 1 +
PdNameStrLen + 1 +
VerStrLen + 1 +
SerialNumStrLen + 1 +
SKUNumStrLen + 1 +
FamilyStrLen + 1 + 1;
SmbiosRecord = AllocateZeroPool (RecordLength);
if (SmbiosRecord == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
}
(VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1));
SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
CopyGuid(&SmbiosRecord->Uuid, &InputData->Uuid);
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1);
StrStart = OptionalStrStart + ManuStrLen + 1;
UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1);
StrStart += PdNameStrLen + 1;
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);
StrStart += VerStrLen + 1;
UnicodeStrToAsciiStrS (SerialNumber, StrStart, SerialNumStrLen + 1);
StrStart += SerialNumStrLen + 1;
UnicodeStrToAsciiStrS (SKUNumber, StrStart, SKUNumStrLen + 1);
StrStart += SKUNumStrLen + 1;
UnicodeStrToAsciiStrS (Family, StrStart, FamilyStrLen + 1);
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//
Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n",
__FUNCTION__, __LINE__, Status));
}
FreePool (SmbiosRecord);
Exit:
if (Manufacturer != NULL) {
FreePool (Manufacturer);
}
if (ProductName != NULL) {
FreePool (ProductName);
}
if (Version != NULL) {
FreePool (Version);
}
if (SerialNumber != NULL) {
FreePool (SerialNumber);
}
if (SKUNumber != NULL) {
FreePool (SKUNumber);
}
if (Family != NULL) {
FreePool (Family);
}
return Status;
}

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