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100 Commits

Author SHA1 Message Date
9ca522ba15 New fallout vault boy logo 2024-10-06 16:59:55 -04:00
3005ff4237 Change logo to fallout vault boy 2024-10-06 16:59:55 -04:00
d3bcf7e60e Add stylized name as logo 2024-10-06 16:59:55 -04:00
85f3fc6654 Only check webcam status on laptops 2024-08-30 12:35:45 -06:00
88f5720e16 MdeModulePkg/UsbBusDxe: fix NOOPT build error
gcc-11 (fedora 35):

/home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c: In function ?UsbIoBulkTransfer?:
/home/kraxel/projects/edk2/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBus.c:277:12: error: ?UsbHcBulkTransfer? accessing 80 bytes in a region of size 8 [-Werror=stringop-overflow=]

Upstream commit ae8272ef78

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2024-02-21 09:11:18 -07:00
27585e73da Update DBX to 2023-05-09
Ref: https://uefi.org/revocationlistfile
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-06-27 08:16:14 -06:00
42a443d5cd SecurityPkg: Fix debug build
For some reason only DEBUG builds fail because of the unused variable.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-06-22 13:41:43 -06:00
c466cc2ca5 Add System76 Secure Boot keys
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 18:10:00 -07:00
5c49aca613 Update DBX to 2022-09-07
Ref: https://uefi.org/revocationlistfile
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 18:10:00 -07:00
99891bd41e SecureBootConfig: Remove blank line
Remove the blank between "Delete..." and "Restore...".

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
3485d55709 SecureBootConfig: Split long strings
firmware-setup does not wrap long lines, so manually split long strings.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
c1a7127e01 SecureBootConfig: Clear PK and reset
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
2f21eddfb8 SecureBootConfig: Restore keys and reset
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
860c29c923 SecureBootConfig: Update variable and perform reset
Update the `SecureBootEnable` variable and perform a platform reset when
the enable/disable button is pressed.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
8cfead2839 SecureBootConfig: Add text key to perform the actions
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
30f6b2f3c7 SecureBootConfig: Modify UI
Rewrite the UI based on feedback from enabling the module.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
4de32568fa UiApp: Link to SecureBootConfig
Shoehorn in logic from Device Manager to show only the Secure Boot
Config entry under the firmware config form.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-07 10:10:35 -07:00
ff91020528 Notify System76 security callback prior to loading boot options 2023-03-06 15:01:34 -07:00
943773983d BaseTools: Fix DevicePath tool build failure issue
Fix the DevicePath tool build failure that was introduced by
the fixes: 22130dcd98 ("Basetools: turn off gcc12 warning").
Failure cases are:
1. clang 13.1.6 on macOS
2. gcc5.4

Reported-by: Rebecca Cran <rebecca@bsdio.com>
Reported-by: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
2022-08-17 11:40:12 -06:00
e91ea5561d Basetools: turn off gcc12 warning
In function ?SetDevicePathEndNode?,
    inlined from ?FileDevicePath? at DevicePathUtilities.c:857:5:
DevicePathUtilities.c:321:3: error: writing 4 bytes into a region of size 1 [-Werror=stringop-overflow=]
  321 |   memcpy (Node, &mUefiDevicePathLibEndDevicePath, sizeof (mUefiDevicePathLibEndDevicePath));
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from UefiDevicePathLib.h:22,
                 from DevicePathUtilities.c:16:
../Include/Protocol/DevicePath.h: In function ?FileDevicePath?:
../Include/Protocol/DevicePath.h:51:9: note: destination object ?Type? of size 1
   51 |   UINT8 Type;       ///< 0x01 Hardware Device Path.
      |         ^~~~

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
5e86b202de BaseTools: fix gcc12 warning
Sdk/C/LzmaEnc.c: In function ?LzmaEnc_CodeOneMemBlock?:
Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*p.rc.outStream? [-Werror=dangling-pointer=]
 2828 |   p->rc.outStream = &outStream.vt;
      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
      |                            ^~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*(CLzmaEnc *)pp.rc.outStream? [-Werror=dangling-pointer=]
 2828 |   p->rc.outStream = &outStream.vt;
      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
      |                            ^~~~~~~~~
Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
cc1: all warnings being treated as errors

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
b764882195 BaseTools: fix gcc12 warning
GenFfs.c:545:5: error: pointer ?InFileHandle? used after ?fclose? [-Werror=use-after-free]
  545 |     Error(NULL, 0, 4001, "Resource", "memory cannot be allocated  of %s", InFileHandle);
      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GenFfs.c:544:5: note: call to ?fclose? here
  544 |     fclose (InFileHandle);
      |     ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-17 11:40:12 -06:00
a2abc5e15f UefiPayloadPkg: Add Pop!_OS Recovery to boot text
Preserve existing UI and add the note about pressing Space to go to
the systemd-boot menu for Pop!_OS Recovery.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-12-21 15:25:08 -07:00
a618e43977 MdeModulePkg/BmBootDesciption: Remove device prefixes
Remove the device prefixes to match current System76 firmware UI in the
One Time Boot menu.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-16 10:10:20 -07:00
bbc04972bc UefiPayloadPkg: Add PCI support from DuetPkg
In coreboot, we mark GPU prefmem above 4GB, because NVIDIA wants a lot
(16GB region on the 30 series), otherwise coreboot will obviously fail
to allocate the resources.

In EDK2, we then end up hitting this assert:

    InitRootBridge: populated root bus 0, with room for 36 subordinate bus(es)
    RootBridge: PciRoot(0x0)
      Support/Attr: 7001F / 7001F
        DmaAbove4G: No
    NoExtConfSpace: No
         AllocAttr: 0 ()
               Bus: 0 - 24 Translation=0
                Io: 1000 - EFFF Translation=0
               Mem: 80400000 - 1001FFFFFF Translation=0
        MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
              PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
       PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
    ASSERT [PciHostBridgeDxe] .../edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c(120): Bridge->Mem.Limit < 0x0000000100000000ULL

So, bring back Pci*NoEnumerationDxe from the deleted DuetPkg, which
doesn't check anything and let's us boot.

Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
61a7f360d9 UefiPayloadPkg: Add Intel GOP driver 2021-11-11 17:49:07 -07:00
fc1c47ccad UefiPayloadPkg: Add System76 Setup menu 2021-11-11 17:49:07 -07:00
fec64b04eb Update brotli to fix compiling with GCC 11 2021-11-11 17:49:07 -07:00
05aa27ef23 MdeModulePkg/BM: Update boot options on device change
Register an event to trigger when a block device is added or removed
that will update the list of boot options. Use a refreshguid to force
the form to display the changes if it already open.
2021-11-11 17:49:07 -07:00
06cc698885 MdeModulePkg/Core: Signal notify events on protocol removal
In order for BootManager to maintain a valid list of boot options, it
must know when the BlockIo protocol is also removed, not just added.
2021-11-11 17:49:07 -07:00
cb870a1ce9 UiApp: Dynamically generated firmware configuration information page
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
90e04a7e31 MdeModulePkg/BMM: Unregister F9 and F10 hotkeys 2021-11-11 17:49:07 -07:00
1d01d2a9a7 MdeModulePkg/BMM: Remove Commit/Discard buttons 2021-11-11 17:49:07 -07:00
70e9b22f5c MdeModulePkg/BMM: Save BootOrder on list update 2021-11-11 17:49:07 -07:00
e9d6369050 MdeModulePkg/BMM: Add some debug logging 2021-11-11 17:49:07 -07:00
58d6aae969 MdeModulePkg/UiApp: Add warning if no bootable options found 2021-11-11 17:49:07 -07:00
4e0fcaba18 MdeModulePkg/BootMaintenanceManagerUiLib: Make it look like current BMM 2021-11-11 17:49:07 -07:00
2d04a62512 MdeModulePkg/UiApp: Make it look like current FrontPage
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-11 17:49:07 -07:00
8a0955dfa8 MdeModulePkg/BM: Make it look like current BootMngr 2021-11-11 17:49:07 -07:00
06f4583ea5 UefiPayloadPkg: Disable EFI shell 2021-11-02 19:24:49 -06:00
9daa69a59e UefiPayloadPkg: Add library for logging to EC
Make use of the SMFI command interface to forward logs from edk2 to
System76 EC.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-11-02 19:24:49 -06:00
9030464a1b fix secureboot
TODO: Proper integration
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bcfe7a54aa UefiPayloadPkg/Include/Coreboot.h: Remove __packed
The keyword is not defined and will end as public variable beeing declared
in every source that includes the header.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
600c565eb2 Revert "UefiPayloadPkg: Add FV Guid for DXEFV and PLDFV"
This reverts commit 4bac086e8e.
Breaks coreboot integration.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
aae506ce44 UefiPayloadPkg/BlSMMStoreDxe: Support Secureboot
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bf2ca74bb6 UefiPayloadPkg: Update APRIORI
Make sure that:
* FaultTolerantDxe is started before VariableRuntimeDxe
  This ensures that FailedTolerantPei is not required and faults when writing
  the variable store are discovered
* SMBUSConfigLoader is started right after VariableRuntimeDxe
  This ensured that the board specific variables are updated as soon as possible
* Start SmbiosDxe and BlSupportDxeSmbios early to install board specific NULL protocols
* Start SecureBootConfigDxe right after VariableRuntimeDxe to update SecureBootKeys before
  Tcg2Dxe starts

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
654e5958cd Fix TPM detection
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
9657bbe08f MdeModulePkg: Be more verbose about SecureBoot and the reason why the boot failed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
10cbbe06d3 [HACK]UefiPayloadPkg: Fix TPM2 support without PEI
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
802391f1fe UefiPayloadPkg/SecureBootEnrollDefaultKeys: Make SecureBoot configurable
Signed-off-by: Christian Walter <christian.walter@9elements.com>
2021-11-02 19:24:49 -06:00
db04386fd9 UefiPayloadPkg: Check TPM PPI requests in PlatformBootManager
Test if the user need to confirm TPM Physical presence commands.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
7d5abcd016 UefiPayloadPkg: Parse coreboot's TPM PPI handoff buffer
Read the coreboot table containing the TPM PPI handoff buffer and
place it in gEfiTcgPhysicalPresenceInfoHob.

coreboot uses the same PPI interface as QEMU does and installs the
corresponding ACPI code to provide a full PPI interface to the OS.
The OS must reboot in order to execute the requests.

The corresponding coreboot patch can be found here:
https://review.coreboot.org/c/coreboot/+/45568

In a follow up commit the OvmfPkg PhysicalPresence library will be used
to confirm TPM PPI request. This is necessary as coreboot doesn't have
input drivers or a graphical UI that could be used.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d296a36cc4 OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu: Add timeout
Instead of waiting and infinite time, abort the TPM PPI request after
3 minutes. This allow to boot headless platforms where no keyboard is
attached or the user didn't made it in time.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bdb15bf9ba OvmfPkg: Introduce Tcg2PhysicalPresencePlatformLib
Put the PPI configuration retriveal into an own library.
That will allow to reuse the code in the UefipayloadPkg, where the
firmware provides the ACPI tables, like QEMU does on OvmfPkg.

However one major difference is that the PPI interface in UefiPayloadPkg
is not backed by a MMIO device, but resides in DRAM and is shared with ACPI code.

Add an additional parameter to provide the location of the PPI and
test if the memory region has the correct attributes.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
25af751320 UefiPayloadPkg: Add TPM support
* Add support for TPM1.2 and TPM2.

This adds measured boot support and will be extended with Secureboot.

Signed-off-by: Christian Walter <christian.walter@9elements.com>
2021-11-02 19:24:49 -06:00
7f99fae217 UefiPayloadPkg: Advertise TPM support in BlSupportDxe
In BlSupportDxe read the AcpiBoardInfo and set PcdTpmInstanceGuid
to indicate that a TPM is likely present as TPM tables had been installed
by the bootloader.

The Tcg*Dxes will probe for the TPM, so no need to do it here as well.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
c134065066 UefiPayloadPkg: Check more ACPI tables
Probe for ACPI tables
* TPM2
* TCPA
and store the result in AcpiBoardInfo.

Will be used to determine if a TPM1.2 or TPM2.0 is present.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
eec38fd383 UefiPayloadPkg: Add Secureboot support
Must use RuntimeVariableDxe instead of EmuVariableDxe.
Currently doesn't boot on qemu.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
b9564773f1 UefiPayloadPkg: Scan for Option ROMs
Install the gPciPlatformProtocol to scan for Option ROMs.

For every device we probe the Option ROM and provide a pointer
to the activated BAR if found.

It's safe to assume that all ROM bars have been enumerated,
reserved in the bridge resources and are disabled by default.
This is made a mandatory bootloader requirement in the next commit.

Enabling them and leaving them enabled will do no harm.

This can easily be tested on qemu, where it will start finding Option ROMs
for VGA and network cards.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
2021-11-02 19:24:49 -06:00
8c767bb014 Ps2KbdCtrller: Make wait for SUCCESS after BAT non-fatal
Recent model Chromebooks only return ACK, but not
BAT_SUCCESS, which causes hanging and failed ps2k init.
To mitigate this, make the absence of BAT_SUCCESS reply
non-fatal, and reduce the no-reply timeout from 4s to 1s.

Tested on google/dracia and purism/librem_14

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
7386ad5ae3 UefiPayloadPkg: don't set PcdDebugPropertyMask for release builds
Don't set PcdDebugPropertyMask for release builds, and properly set it
for debug builds based on SOURCE_DEBUG_ENABLE.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
e727453a97 SdMmcPciDxe: Reduce timeout for SD card reset
Previous 1s timeout causeed stalls on boot splash with no benefit.
Reduced to 100ms and no interruptions to boot when no SD card inserted.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
553bda4d8e BaseTools: array.fromstring and array.tostring removed in python 3.9
array.fromstring and array.tostring deprecated, and alias for
array.frombytes and array.tobytes. Deprecated since version 3.2,
have been removed in version python 3.9.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yunhua Feng <fengyunhua@byosoft.com.cn>
2021-11-02 19:24:49 -06:00
3e7febc83c BlSMMStoreDxe: make error msgs unique
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
b664a5352c UefiPayloadPkg: Allow boot timeout to be set via cmd line
Allows for devices w/o internal display to set a longer timeout
via coreboot Kconfig

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
b376a7d60f ShellPkg: disable startup script, show welcome banner
Startup script does nothing other than confuse users.
Show a welcome banner and tell users how to exit.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
3fb944f925 UefiPayloadPkg: Update APRIORI
Make sure that:
* FaultTolerantDxe is started before VariableRuntimeDxe
  This ensures that FailedTolerantPei is not required and faults when writing
  the variable store are discovered
* Start BlSupportDxeSmbios early to install board specific NULL protocols

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
1d70aa7a9b UefiCpuPkg: Disable MTRR programming for UefiPayloadPkg
The MTRRs have already been programmed by FSB.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
0bef9ccd43 UefiPayloadPkg: Add support for Firmware Volume Block Protocol
This adds support for FVB in order to support a platform independent
and non-volatile variable store on UefiPayloadPkg. It is required for
non-volatile variable support, TPM support, Secureboot support and more.

Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports
the SMMSTORE v2 feature. It implements a SMI handler that is able to
write, read and erase pages in the boot media (SPI flash).
The communication is done using a fixed communication buffer that is
allocated in CBMEM. The existence of this optional feature is advertised
by a coreboot table.
When the SMMSTORE feature is not available the variable emulation is used
by setting PcdEmuVariableNvModeEnable to TRUE.

Add a library for SMMStore to be used in DXE.

The DXE component provides runtime services and takes care of virtual to
physical mapping the communication buffers between SMM and OS.

Make use of the APRIORI DXE to initialize an empty store on the first boot
and set the PCDs to sane values before the variable driver is loaded.

Tests on Intel(R) Xeon(R) E-2288G CPU @ 3.70G showed that the SMI isn't
triggered with a probability of 1:40 of all cases when called in a tight
loop. The CPU continues running and the SMI is triggeres asynchronously
a few clock cycles later. coreboot only handels synchronous APM request
and does nothing on asynchronous APM triggers.

As there's no livesign from SMM it's impossible to tell if the handler
has run. Just wait a bit and try again to trigger a synchronous SMI.

Tests confirmed that out of 5 million tries the SMI is now always handled.

Tested on Linux and Windows 10 on real hardware.
Currently this cannot be tested on coreboot and qemu as it doesn't support
the SMMSTORE on qemu.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d3b38ea28a UefiPayloadPkg/Library/PlatformBootManagerLib: Remove broken VGA detection
This fixes an issue where the framebuffer provided by coreboot or
slimbootloader will only work on the primary VGA device. If the
framebuffer corresponds to a different device the screen will stay black.
In addition, the code doesn't work for multiple graphic cards, has
reference to non existing functions, and is a duplication of common code.

Call EfiBootManagerConnectVideoController on every display device found,
not only the legacy VGA device. This is the same as OvmfPkg does.

Allows to display output on the framebuffer set up by firmware, which might
not be the VGA device.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
69ae47ba5d UefiPayloadPkg: Add RNG support
Uses the RDRAND instruction if available and install EfiRngProtocol.
The protocol may be used by iPXE or the Linux kernel to gather entropy.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
95c492569f UefiPayloadPkg: Use new filesystem drivers
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
d996a4bc9f Add filesystem drivers
Add EXT2/EXT4, exFAT, NTFS filesystem drivers.
Do not add ISO9115 drivers as it breaks El Torito boot.
2021-11-02 19:24:49 -06:00
9f528fb4c0 MdeModulePkg/Usb/Keyboard.c: don't request protocol before setting
No need to check the interface protocol then conditionally setting,
just set it to BOOT_PROTOCOL and check for error.

This is what Linux does for HID devices as some don't follow the USB spec.
One example is the Aspeed BMC HID keyboard device, which adds a massive
boot delay without this patch as it doesn't respond to 'GetProtocolRequest'.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-11-02 19:24:49 -06:00
bbab5b95b4 MdeModulePkg/Usb/Keyboard.c: remove Get/SetConfig calls
SetConfig is already called during device enumeration,
no need to do it again here.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:49 -06:00
5e84cc0714 UefiPayloadPkg: Reduce timeout to 2s
Current firmware does not honor PcdPlatformBootTimeOut and hard-codes a
timeout of 2s.
2021-11-02 19:24:48 -06:00
2af54dd5bd UefiPayloadPkg: Stall before connecting devices
USB devices are not being detected when booting. Pause a bit for them to
be initialized and detected by EfiBootManagerConnectAll().
2021-11-02 19:24:48 -06:00
00283317d8 MdeModulePkg/BdsDxe: Forward any key for booting
Pressing escape will bring a user to the boot manager. Pressing any
other key will continue booting, forwarding the key to systemd-boot.
2021-11-02 19:24:48 -06:00
232f661f99 MdeModulePkg: Wait for input after boot failure
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
552ca5cc88 UefiPayloadPkg: Clear screen on boot error 2021-11-02 19:24:48 -06:00
94e7cfc7e7 UefiPayloadPkg: Copy PlatformBootManagerUnableToBoot() from OvmfPkg 2021-11-02 19:24:48 -06:00
de7030ed26 UefiPayloadPkg: Set ResetOnMemoryTypeInformationChange to FALSE
the default value, TRUE, causes reboots if a device boots to the
shell, exits, and then attempts to boot from another source.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
587653cd8b MdeModulePkg/SdMmcPciHcDxe: add Bayhub support
Add support for Bayhub eMMC controller found on AMD
Stoneyridge Chromebooks.

Test: build/boot various google/kahlee-based devices

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
e167ed1a3d MdeModulePkg/GraphicsConsole: don't draw cursor at 0,0
Prevents cursor from flashing on screen when
changing modes or clearing the screen.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
003534f8f0 MdeModulePkg/BmBootDesciption: Improve device descriptions
Add device type prefixes for USB, IDE, SATA, and NVMe drives.
Remove UEFI prefix, remove serial numbers.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
a363907bc9 MdeModulePkg/BmBoot: skip secondary eMMC entries
Internal eMMC devices often show multiple entries, so skip
any after the initial entry.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
530cc53f96 MdeModulePkg/Frontpage: get SMBIOS Data from table directly
rather than getting it from the EFI SMBIOS protocol

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
112268c70d MdeModulePkg/GraphicsConsole: Don't re-set video output mode
Fixes display resolution issues with booting OS X

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
726280b214 UefiPayloadPkg: Disable Device Manager 2021-11-02 19:24:48 -06:00
b1ab82d4c8 BmpSupportLib: fix BMP validation
BMP files by tools other than MS paint can have a
variable number of padding bytes, which results in
the DataSize being less than (ImageSize - HeaderSize).
Fix the check to be less stringent.

Test: use BMP created by/saved by Photoshop

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
2e16857f3d MdeModulePkg: load boot logo into BGRT table
This is a shoehorned-in implementation of an ACPI BGRT
table, ported pretty much directly from the version used
under CorebootPayloadPkg.

EDK2 provides a facility to do this already, but it assumes
the ACPI tables already exist as EFI structures, so would need
to write code to populate those using the tables already in RAM
created by coreboot. This seemed like the easier option ATM.

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
308f9a49b0 MdeModulePkg/BootLogoLib: Center logo 38.2% from top of screen
Use Microsoft's recommended positioning [1] for the boot logo.

> We recommend that the logo is placed with its center at 38.2% from the
> screen's top edge. This positioning is based on the golden ratio's
> visual aesthetics and matches the Windows 10 design proportions.

[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/boot-screen-components#position-the-logo-during-post
2021-11-02 19:24:48 -06:00
7ab09015b1 MdeModulePkg/Logo: Use System76 boot logo 2021-11-02 19:24:48 -06:00
d1c0828262 UefiPayloadPkg: Enable boot logo 2021-11-02 19:24:48 -06:00
b4dd94c217 UefiPayloadPkg: Show boot message as progress text
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-02 19:24:48 -06:00
f428f538b6 UefiPayloadPkg: Map ESC to Boot Manager
Change menu key from F2 to ESC, remove extranous text
2021-11-02 19:24:48 -06:00
75b91c0b9f UefiPayloadPkg: Enable PS2 keyboard by default 2021-10-21 21:32:54 -06:00
9f1dd0acb1 UefiPayloadPkg: Default to coreboot 2021-10-21 21:32:54 -06:00
6db1a5555a UefiPayloadPkg: Increase FV size
The following commits need additional space.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2021-10-21 21:24:56 -06:00
72f8b9d80b UefiPayloadPkg: Fix the build error when enable Core ci for UefiPayloadPkg
V1: Add quotes when using $(ARCH) in .dsc and .fdf file.
The quotes are added due to the way by which Core ci parse the .dsc file.
Add UINTN in Hob.c to fix cast from pointer to integer of different size error.
V2: Delete lines which reference ShellBinPkg.The pkg doesn't exist in edk2.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: DunTan <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I18c2027f57a4fbf291925a11226ed620b808a970
2021-10-21 21:24:48 -06:00
4723 changed files with 347607 additions and 386101 deletions

View File

@ -17,7 +17,7 @@ parameters:
jobs:
- job: Build_${{ parameters.tool_chain_tag }}
timeoutInMinutes: 120
#Use matrix to speed up the build process
strategy:
matrix:
@ -48,9 +48,6 @@ jobs:
TARGET_SECURITY:
Build.Pkgs: 'SecurityPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
TARGET_UEFIPAYLOAD:
Build.Pkgs: 'UefiPayloadPkg'
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
TARGET_PLATFORMS:
# For Platforms only check code. Leave it to Platform CI
# to build them.

View File

@ -67,8 +67,7 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
"CryptoPkg",
"UnitTestFrameworkPkg",
"OvmfPkg",
"RedfishPkg",
"UefiPayloadPkg"
"RedfishPkg"
)
def GetArchitecturesSupported(self):

View File

@ -30,6 +30,7 @@ class EccCheck(ICiBuildPlugin):
},
"""
ReModifyFile = re.compile(r'[B-Q,S-Z]+[\d]*\t(.*)')
FindModifyFile = re.compile(r'\+\+\+ b\/(.*)')
LineScopePattern = (r'@@ -\d*\,*\d* \+\d*\,*\d* @@.*')
LineNumRange = re.compile(r'@@ -\d*\,*\d* \+(\d*)\,*(\d*) @@.*')
@ -68,174 +69,77 @@ class EccCheck(ICiBuildPlugin):
env.set_shell_var('WORKSPACE', workspace_path)
env.set_shell_var('PACKAGES_PATH', os.pathsep.join(Edk2pathObj.PackagePathList))
self.ECC_PASS = True
# Create temp directory
temp_path = os.path.join(workspace_path, 'Build', '.pytool', 'Plugin', 'EccCheck')
try:
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
# Copy package being scanned to temp_path
shutil.copytree (
os.path.join(workspace_path, packagename),
os.path.join(temp_path, packagename),
symlinks=True
)
# Copy exception.xml to temp_path
shutil.copyfile (
os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml"),
os.path.join(temp_path, "exception.xml")
)
# Output file to use for git diff operations
temp_diff_output = os.path.join (temp_path, 'diff.txt')
self.ApplyConfig(pkgconfig, temp_path, packagename)
modify_dir_list = self.GetModifyDir(packagename, temp_diff_output)
patch = self.GetDiff(packagename, temp_diff_output)
ecc_diff_range = self.GetDiffRange(patch, packagename, temp_path)
#
# Use temp_path as working directory when running ECC tool
#
self.GenerateEccReport(modify_dir_list, ecc_diff_range, temp_path, basetools_path)
ecc_log = os.path.join(temp_path, "Ecc.log")
if self.ECC_PASS:
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
tc.SetSuccess()
return 0
else:
with open(ecc_log, encoding='utf8') as output:
ecc_output = output.readlines()
for line in ecc_output:
logging.error(line.strip())
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
tc.SetFailed("EccCheck failed for {0}".format(packagename), "CHECK FAILED")
return 1
except KeyboardInterrupt:
# If EccCheck is interrupted by keybard interrupt, then return failure
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
tc.SetFailed("EccCheck interrupted for {0}".format(packagename), "CHECK FAILED")
return 1
self.ApplyConfig(pkgconfig, workspace_path, basetools_path, packagename)
modify_dir_list = self.GetModifyDir(packagename)
patch = self.GetDiff(packagename)
ecc_diff_range = self.GetDiffRange(patch, packagename, workspace_path)
self.GenerateEccReport(modify_dir_list, ecc_diff_range, workspace_path, basetools_path)
ecc_log = os.path.join(workspace_path, "Ecc.log")
self.RevertCode()
if self.ECC_PASS:
tc.SetSuccess()
self.RemoveFile(ecc_log)
return 0
else:
# If EccCheck fails for any other exception type, raise the exception
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
tc.SetFailed("EccCheck exception for {0}".format(packagename), "CHECK FAILED")
raise
with open(ecc_log, encoding='utf8') as output:
ecc_output = output.readlines()
for line in ecc_output:
logging.error(line.strip())
self.RemoveFile(ecc_log)
tc.SetFailed("EccCheck failed for {0}".format(packagename), "Ecc detected issues")
return 1
def GetDiff(self, pkg: str, temp_diff_output: str) -> List[str]:
patch = []
#
# Generate unified diff between origin/master and HEAD.
#
params = "diff --output={} --unified=0 origin/master HEAD".format(temp_diff_output)
RunCmd("git", params)
with open(temp_diff_output) as file:
patch = file.read().strip().split('\n')
def RevertCode(self) -> None:
submoudle_params = "submodule update --init"
RunCmd("git", submoudle_params)
reset_params = "reset HEAD --hard"
RunCmd("git", reset_params)
def GetDiff(self, pkg: str) -> List[str]:
return_buffer = StringIO()
params = "diff --unified=0 origin/master HEAD"
RunCmd("git", params, outstream=return_buffer)
p = return_buffer.getvalue().strip()
patch = p.split("\n")
return_buffer.close()
return patch
def GetModifyDir(self, pkg: str, temp_diff_output: str) -> List[str]:
#
# Generate diff between origin/master and HEAD using --diff-filter to
# exclude deleted and renamed files that do not need to be scanned by
# ECC. Also use --name-status to only generate the names of the files
# with differences. The output format of this git diff command is a
# list of files with the change status and the filename. The filename
# is always at the end of the line. Examples:
#
# M MdeModulePkg/Application/CapsuleApp/CapsuleApp.h
# M MdeModulePkg/Application/UiApp/FrontPage.h
#
params = "diff --output={} --diff-filter=dr --name-status origin/master HEAD".format(temp_diff_output)
RunCmd("git", params)
dir_list = []
with open(temp_diff_output) as file:
dir_list = file.read().strip().split('\n')
def RemoveFile(self, file: str) -> None:
if os.path.exists(file):
os.remove(file)
return
def GetModifyDir(self, pkg: str) -> List[str]:
return_buffer = StringIO()
params = "diff --name-status" + ' HEAD' + ' origin/master'
RunCmd("git", params, outstream=return_buffer)
p1 = return_buffer.getvalue().strip()
dir_list = p1.split("\n")
return_buffer.close()
modify_dir_list = []
for modify_dir in dir_list:
#
# Parse file name from the end of the line
#
file_path = modify_dir.strip().split()
#
# Skip lines that do not have at least 2 elements (status and file name)
#
if len(file_path) < 2:
file_path = self.ReModifyFile.findall(modify_dir)
if file_path:
file_dir = os.path.dirname(file_path[0])
else:
continue
#
# Parse the directory name from the file name
#
file_dir = os.path.dirname(file_path[-1])
#
# Skip directory names that do not start with the package being scanned.
#
if file_dir.split('/')[0] != pkg:
if pkg in file_dir and file_dir != pkg:
modify_dir_list.append('%s' % file_dir)
else:
continue
#
# Skip directory names that are identical to the package being scanned.
# The assumption here is that there are no source files at the package
# root. Instead, the only expected files in the package root are
# EDK II meta data files (DEC, DSC, FDF).
#
if file_dir == pkg:
continue
#
# Skip directory names that are already in the modified dir list
#
if file_dir in modify_dir_list:
continue
#
# Add the candidate directory to scan to the modified dir list
#
modify_dir_list.append(file_dir)
#
# Remove duplicates from modify_dir_list
# Given a folder path, ECC performs a recursive scan of that folder.
# If a parent and child folder are both present in modify_dir_list,
# then ECC will perform redudanct scans of source files. In order
# to prevent redundant scans, if a parent and child folder are both
# present, then remove all the child folders.
#
# For example, if modified_dir_list contains the following elements:
# MdeModulePkg/Core/Dxe
# MdeModulePkg/Core/Dxe/Hand
# MdeModulePkg/Core/Dxe/Mem
#
# Then MdeModulePkg/Core/Dxe/Hand and MdeModulePkg/Core/Dxe/Mem should
# be removed because the files in those folders are covered by a scan
# of MdeModulePkg/Core/Dxe.
#
filtered_list = []
for dir1 in modify_dir_list:
Append = True
for dir2 in modify_dir_list:
if dir1 == dir2:
continue
common = os.path.commonpath([dir1, dir2])
if os.path.normpath(common) == os.path.normpath(dir2):
Append = False
break
if Append and dir1 not in filtered_list:
filtered_list.append(dir1)
return filtered_list
modify_dir_list = list(set(modify_dir_list))
return modify_dir_list
def GetDiffRange(self, patch_diff: List[str], pkg: str, temp_path: str) -> Dict[str, List[Tuple[int, int]]]:
def GetDiffRange(self, patch_diff: List[str], pkg: str, workingdir: str) -> Dict[str, List[Tuple[int, int]]]:
IsDelete = True
StartCheck = False
range_directory: Dict[str, List[Tuple[int, int]]] = {}
for line in patch_diff:
modify_file = self.FindModifyFile.findall(line)
if modify_file and pkg in modify_file[0] and not StartCheck and os.path.isfile(modify_file[0]):
modify_file_comment_dic = self.GetCommentRange(modify_file[0], temp_path)
modify_file_comment_dic = self.GetCommentRange(modify_file[0], workingdir)
IsDelete = False
StartCheck = True
modify_file_dic = modify_file[0]
@ -254,13 +158,11 @@ class EccCheck(ICiBuildPlugin):
range_directory[modify_file_dic].append(i)
return range_directory
def GetCommentRange(self, modify_file: str, temp_path: str) -> List[Tuple[int, int]]:
comment_range: List[Tuple[int, int]] = []
modify_file_path = os.path.join(temp_path, modify_file)
if not os.path.exists (modify_file_path):
return comment_range
def GetCommentRange(self, modify_file: str, workingdir: str) -> List[Tuple[int, int]]:
modify_file_path = os.path.join(workingdir, modify_file)
with open(modify_file_path) as f:
line_no = 1
comment_range: List[Tuple[int, int]] = []
Start = False
for line in f:
if line.startswith('/**'):
@ -277,33 +179,35 @@ class EccCheck(ICiBuildPlugin):
return comment_range
def GenerateEccReport(self, modify_dir_list: List[str], ecc_diff_range: Dict[str, List[Tuple[int, int]]],
temp_path: str, basetools_path: str) -> None:
workspace_path: str, basetools_path: str) -> None:
ecc_need = False
ecc_run = True
config = os.path.normpath(os.path.join(basetools_path, "Source", "Python", "Ecc", "config.ini"))
exception = os.path.normpath(os.path.join(temp_path, "exception.xml"))
report = os.path.normpath(os.path.join(temp_path, "Ecc.csv"))
config = os.path.join(basetools_path, "Source", "Python", "Ecc", "config.ini")
exception = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
report = os.path.join(workspace_path, "Ecc.csv")
for modify_dir in modify_dir_list:
target = os.path.normpath(os.path.join(temp_path, modify_dir))
target = os.path.join(workspace_path, modify_dir)
logging.info('Run ECC tool for the commit in %s' % modify_dir)
ecc_need = True
ecc_params = "-c {0} -e {1} -t {2} -r {3}".format(config, exception, target, report)
return_code = RunCmd("Ecc", ecc_params, workingdir=temp_path)
return_code = RunCmd("Ecc", ecc_params, workingdir=workspace_path)
if return_code != 0:
ecc_run = False
break
if not ecc_run:
logging.error('Fail to run ECC tool')
self.ParseEccReport(ecc_diff_range, temp_path)
self.ParseEccReport(ecc_diff_range, workspace_path)
if not ecc_need:
logging.info("Doesn't need run ECC check")
revert_params = "checkout -- {}".format(exception)
RunCmd("git", revert_params)
return
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], temp_path: str) -> None:
ecc_log = os.path.join(temp_path, "Ecc.log")
ecc_csv = os.path.join(temp_path, "Ecc.csv")
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], workspace_path: str) -> None:
ecc_log = os.path.join(workspace_path, "Ecc.log")
ecc_csv = os.path.join(workspace_path, "Ecc.csv")
row_lines = []
ignore_error_code = self.GetIgnoreErrorCode()
if os.path.exists(ecc_csv):
@ -332,16 +236,16 @@ class EccCheck(ICiBuildPlugin):
log.writelines(all_line)
return
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], temp_path: str, pkg: str) -> None:
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], workspace_path: str, basetools_path: str, pkg: str) -> None:
if "IgnoreFiles" in pkgconfig:
for a in pkgconfig["IgnoreFiles"]:
a = os.path.join(temp_path, pkg, a)
a = os.path.join(workspace_path, pkg, a)
a = a.replace(os.sep, "/")
logging.info("Ignoring Files {0}".format(a))
if os.path.exists(a):
if os.path.isfile(a):
os.remove(a)
self.RemoveFile(a)
elif os.path.isdir(a):
shutil.rmtree(a)
else:
@ -349,7 +253,7 @@ class EccCheck(ICiBuildPlugin):
if "ExceptionList" in pkgconfig:
exception_list = pkgconfig["ExceptionList"]
exception_xml = os.path.join(temp_path, "exception.xml")
exception_xml = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
try:
logging.info("Appending exceptions")
self.AppendException(exception_list, exception_xml)

View File

@ -5,7 +5,6 @@
##
import os
import shutil
import logging
import re
from io import StringIO
@ -62,19 +61,12 @@ class LicenseCheck(ICiBuildPlugin):
# - Junit Logger
# - output_stream the StringIO output stream from this plugin via logging
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
# Create temp directory
temp_path = os.path.join(Edk2pathObj.WorkspacePath, 'Build', '.pytool', 'Plugin', 'LicenseCheck')
if not os.path.exists(temp_path):
os.makedirs(temp_path)
# Output file to use for git diff operations
temp_diff_output = os.path.join (temp_path, 'diff.txt')
params = "diff --output={} --unified=0 origin/master HEAD".format(temp_diff_output)
RunCmd("git", params)
with open(temp_diff_output) as file:
patch = file.read().strip().split("\n")
# Delete temp directory
if os.path.exists(temp_path):
shutil.rmtree(temp_path)
return_buffer = StringIO()
params = "diff --unified=0 origin/master HEAD"
RunCmd("git", params, outstream=return_buffer)
p = return_buffer.getvalue().strip()
patch = p.split("\n")
return_buffer.close()
ignore_files = []
if "IgnoreFiles" in pkgconfig:

View File

@ -1,120 +0,0 @@
# UncrustifyCheck Plugin
This CiBuildPlugin scans all the files in a given package and checks for coding standard compliance issues.
This plugin is enabled by default. If a package would like to prevent the plugin from reporting errors, it can do
so by enabling [`AuditOnly`](#auditonly) mode.
This plugin requires the directory containing the Uncrustify executable that should be used for this plugin to
be specified in an environment variable named `UNCRUSTIFY_CI_PATH`. This unique variable name is used to avoid confusion
with other paths to Uncrustify which might not be the expected build for use by this plugin.
By default, an Uncrustify configuration file named "uncrustify.cfg" located in the same directory as the plugin is
used. The value can be overridden to a package-specific path with the `ConfigFilePath` configuration file option.
* Uncrustify source code and documentation: https://github.com/uncrustify/uncrustify
* Project Mu Uncrustify fork source code and documentation: https://dev.azure.com/projectmu/Uncrustify
## Files Checked in a Package
By default, this plugin will discover all files in the package with the following default paths:
```python
[
# C source
"*.c",
"*.h"
]
```
From this list of files, any files ignored by Git or residing in a Git submodule will be removed. If Git is not
found, submodules are not found, or ignored files are not found no changes are made to the list of discovered files.
To control the paths checked in a given package, review the configuration options described in this file.
## Configuration
The plugin can be configured with a few optional configuration options.
``` yaml
"UncrustifyCheck": {
"AdditionalIncludePaths": [], # Additional paths to check formatting (wildcards supported).
"AuditOnly": False, # Don't fail the build if there are errors. Just log them.
"ConfigFilePath": "", # Custom path to an Uncrustify config file.
"IgnoreStandardPaths": [], # Standard Plugin defined paths that should be ignored.
"OutputFileDiffs": False, # Output chunks of formatting diffs in the test case log.
# This can significantly slow down the plugin on very large packages.
"SkipGitExclusions": False # Don't exclude git ignored files and files in git submodules.
}
```
### `AdditionalIncludePaths`
A package configuration file can specify any additional paths to be included with this option.
At this time, it is recommended all files run against the plugin be written in the C or C++ language.
### `AuditOnly`
`Boolean` - Default is `False`.
If `True`, run the test in an "audit only mode" which will log all errors but instead of failing the build, it will set
the test as skipped. This allows visibility into the failures without breaking the build.
### `ConfigFilePath`
`String` - Default is `"uncrustify.cfg"`
When specified in the config file, this is a package relative path to the Uncrustify configuration file.
### `IgnoreStandardPaths`
This plugin by default will check the below standard paths. A package configuration file can specify any of these paths
to be ignored.
```python
[
# C source
"*.c",
"*.h"
]
```
### `OutputFileDiffs`
`Boolean` - Default is `False`.
If `True`, output diffs of formatting changes into the test case log. This is helpful to exactly understand what changes
need to be made to the source code in order to fix a coding standard compliance issue.
Note that calculating the file diffs on a very large set of of results (e.g. >100 files) can significantly slow down
plugin execution.
### `SkipGitExclusions`
`Boolean` - Default is `False`.
By default, files in paths matched in a .gitignore file or a recognized git submodule are excluded. If this option
is `True`, the plugin will not attempt to recognize these files and exclude them.
## High-Level Plugin Operation
This plugin generates two main sets of temporary files:
1. A working directory in the directory `Build/.pytool/Plugin/Uncrustify`
2. For each source file with formatting errors, a sibling file with the `.uncrustify_plugin` extension
The working directory contains temporary files unique to operation of the plugin. All of these files are removed on
exit of the plugin including successful or unsuccessful execution (such as a Python exception occurring). If for any
reason, any files in the package exist prior to running the plugin with the `.uncrustify_plugin` extension, the plugin
will inform the user to remove these files and exit before running Uncrustify. This is to ensure the accuracy of the
results reported from each execution instance of the plugin.
The plugin determines the list of relevant files to check with Uncrustify and then invokes Uncrustify with that file
list. For any files not compliant to the configuration file provided, Uncrustify will generate a corresponding file
with the `.uncrustify_plugin` extension. The plugin discovers all of these files. If any such files are present, this
indicates a formatting issue was found and the test is marked failed (unless `AuditOnly` mode is enabled).
The test case log will contain a report of which files failed to format properly, allowing the user to run Uncrustify
against the file locally to fix the issue. If the `OutputFileDiffs` configuration option is set to `True`, the plugin
will output diff chunks for all code formatting issues in the test case log.

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@ -1,618 +0,0 @@
# @file UncrustifyCheck.py
#
# An edk2-pytool based plugin wrapper for Uncrustify
#
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import configparser
import difflib
import errno
import logging
import os
import pathlib
import shutil
import timeit
from edk2toolext.environment import version_aggregator
from edk2toolext.environment.plugin_manager import PluginManager
from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
from edk2toolext.environment.plugintypes.uefi_helper_plugin import HelperFunctions
from edk2toolext.environment.var_dict import VarDict
from edk2toollib.log.junit_report_format import JunitReportTestCase
from edk2toollib.uefi.edk2.path_utilities import Edk2Path
from edk2toollib.utility_functions import RunCmd
from io import StringIO
from typing import Any, Dict, List, Tuple
#
# Provide more user friendly messages for certain scenarios
#
class UncrustifyException(Exception):
def __init__(self, message, exit_code):
super().__init__(message)
self.exit_code = exit_code
class UncrustifyAppEnvVarNotFoundException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -101)
class UncrustifyAppVersionErrorException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -102)
class UncrustifyAppExecutionException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -103)
class UncrustifyStalePluginFormattedFilesException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -120)
class UncrustifyInputFileCreationErrorException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -121)
class UncrustifyInvalidIgnoreStandardPathsException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -122)
class UncrustifyGitIgnoreFileException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -140)
class UncrustifyGitSubmoduleException(UncrustifyException):
def __init__(self, message):
super().__init__(message, -141)
class UncrustifyCheck(ICiBuildPlugin):
"""
A CiBuildPlugin that uses Uncrustify to check the source files in the
package being tested for coding standard issues.
By default, the plugin runs against standard C source file extensions but
its configuration can be modified through its configuration file.
Configuration options:
"UncrustifyCheck": {
"AdditionalIncludePaths": [], # Additional paths to check formatting (wildcards supported).
"AuditOnly": False, # Don't fail the build if there are errors. Just log them.
"ConfigFilePath": "", # Custom path to an Uncrustify config file.
"IgnoreStandardPaths": [], # Standard Plugin defined paths that should be ignored.
"OutputFileDiffs": False, # Output chunks of formatting diffs in the test case log.
# This can significantly slow down the plugin on very large packages.
"SkipGitExclusions": False # Don't exclude git ignored files and files in git submodules.
}
"""
#
# By default, use an "uncrustify.cfg" config file in the plugin directory
# A package can override this path via "ConfigFilePath"
#
# Note: Values specified via "ConfigFilePath" are relative to the package
#
DEFAULT_CONFIG_FILE_PATH = os.path.join(
pathlib.Path(__file__).parent.resolve(), "uncrustify.cfg")
#
# The extension used for formatted files produced by this plugin
#
FORMATTED_FILE_EXTENSION = ".uncrustify_plugin"
#
# A package can add any additional paths with "AdditionalIncludePaths"
# A package can remove any of these paths with "IgnoreStandardPaths"
#
STANDARD_PLUGIN_DEFINED_PATHS = ("*.c", "*.h")
#
# The Uncrustify application path should set in this environment variable
#
UNCRUSTIFY_PATH_ENV_KEY = "UNCRUSTIFY_CI_PATH"
def GetTestName(self, packagename: str, environment: VarDict) -> Tuple:
""" Provide the testcase name and classname for use in reporting
Args:
packagename: string containing name of package to build
environment: The VarDict for the test to run in
Returns:
A tuple containing the testcase name and the classname
(testcasename, classname)
testclassname: a descriptive string for the testcase can include whitespace
classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
"""
return ("Check file coding standard compliance in " + packagename, packagename + ".UncrustifyCheck")
def RunBuildPlugin(self, package_rel_path: str, edk2_path: Edk2Path, package_config: Dict[str, List[str]], environment_config: Any, plugin_manager: PluginManager, plugin_manager_helper: HelperFunctions, tc: JunitReportTestCase, output_stream=None) -> int:
"""
External function of plugin. This function is used to perform the task of the CiBuild Plugin.
Args:
- package_rel_path: edk2 workspace relative path to the package
- edk2_path: Edk2Path object with workspace and packages paths
- package_config: Dictionary with the package configuration
- environment_config: Environment configuration
- plugin_manager: Plugin Manager Instance
- plugin_manager_helper: Plugin Manager Helper Instance
- tc: JUnit test case
- output_stream: The StringIO output stream from this plugin (logging)
Returns
>0 : Number of errors found
0 : Passed successfully
-1 : Skipped for missing prereq
"""
try:
# Initialize plugin and check pre-requisites.
self._initialize_environment_info(
package_rel_path, edk2_path, package_config, tc)
self._initialize_configuration()
self._check_for_preexisting_formatted_files()
# Log important context information.
self._log_uncrustify_app_info()
# Get template file contents if specified
self._get_template_file_contents()
# Create meta input files & directories
self._create_temp_working_directory()
self._create_uncrustify_file_list_file()
self._run_uncrustify()
# Post-execution actions.
self._process_uncrustify_results()
except UncrustifyException as e:
self._tc.LogStdError(
f"Uncrustify error {e.exit_code}. Details:\n\n{str(e)}")
logging.warning(
f"Uncrustify error {e.exit_code}. Details:\n\n{str(e)}")
return -1
else:
if self._formatted_file_error_count > 0:
if self._audit_only_mode:
logging.info(
"Setting test as skipped since AuditOnly is enabled")
self._tc.SetSkipped()
return -1
else:
self._tc.SetFailed(
f"{self._plugin_name} failed due to {self._formatted_file_error_count} incorrectly formatted files.", "CHECK_FAILED")
else:
self._tc.SetSuccess()
return self._formatted_file_error_count
finally:
self._cleanup_temporary_formatted_files()
self._cleanup_temporary_directory()
def _initialize_configuration(self) -> None:
"""
Initializes plugin configuration.
"""
self._initialize_app_info()
self._initialize_config_file_info()
self._initialize_file_to_format_info()
self._initialize_test_case_output_options()
def _check_for_preexisting_formatted_files(self) -> None:
"""
Checks if any formatted files from prior execution are present.
Existence of such files is an unexpected condition. This might result
from an error that occurred during a previous run or a premature exit from a debug scenario. In any case, the package should be clean before starting a new run.
"""
pre_existing_formatted_file_count = len(
[str(path.resolve()) for path in pathlib.Path(self._abs_package_path).rglob(f'*{UncrustifyCheck.FORMATTED_FILE_EXTENSION}')])
if pre_existing_formatted_file_count > 0:
raise UncrustifyStalePluginFormattedFilesException(
f"{pre_existing_formatted_file_count} formatted files already exist. To prevent overwriting these files, please remove them before running this plugin.")
def _cleanup_temporary_directory(self) -> None:
"""
Cleans up the temporary directory used for this execution instance.
This removes the directory and all files created during this instance.
"""
if hasattr(self, '_working_dir'):
self._remove_tree(self._working_dir)
def _cleanup_temporary_formatted_files(self) -> None:
"""
Cleans up the temporary formmatted files produced by Uncrustify.
This will recursively remove all formatted files generated by Uncrustify
during this execution instance.
"""
if hasattr(self, '_abs_package_path'):
formatted_files = [str(path.resolve()) for path in pathlib.Path(
self._abs_package_path).rglob(f'*{UncrustifyCheck.FORMATTED_FILE_EXTENSION}')]
for formatted_file in formatted_files:
os.remove(formatted_file)
def _create_temp_working_directory(self) -> None:
"""
Creates the temporary directory used for this execution instance.
"""
self._working_dir = os.path.join(
self._abs_workspace_path, "Build", ".pytool", "Plugin", f"{self._plugin_name}")
try:
pathlib.Path(self._working_dir).mkdir(parents=True, exist_ok=True)
except OSError as e:
raise UncrustifyInputFileCreationErrorException(
f"Error creating plugin directory {self._working_dir}.\n\n{repr(e)}.")
def _create_uncrustify_file_list_file(self) -> None:
"""
Creates the file with the list of source files for Uncrustify to process.
"""
self._app_input_file_path = os.path.join(
self._working_dir, "uncrustify_file_list.txt")
with open(self._app_input_file_path, 'w', encoding='utf8') as f:
f.writelines(f"\n".join(self._abs_file_paths_to_format))
def _execute_uncrustify(self) -> None:
"""
Executes Uncrustify with the initialized configuration.
"""
output = StringIO()
self._app_exit_code = RunCmd(
self._app_path,
f"-c {self._app_config_file} -F {self._app_input_file_path} --if-changed --suffix {UncrustifyCheck.FORMATTED_FILE_EXTENSION}", outstream=output)
self._app_output = output.getvalue().strip().splitlines()
def _get_git_ignored_paths(self) -> List[str]:
""""
Returns a list of file absolute path strings to all files ignored in this git repository.
If git is not found, an empty list will be returned.
"""
if not shutil.which("git"):
logging.warn(
"Git is not found on this system. Git submodule paths will not be considered.")
return []
outstream_buffer = StringIO()
exit_code = RunCmd("git", "ls-files --other",
workingdir=self._abs_workspace_path, outstream=outstream_buffer, logging_level=logging.NOTSET)
if (exit_code != 0):
raise UncrustifyGitIgnoreFileException(
f"An error occurred reading git ignore settings. This will prevent Uncrustify from running against the expected set of files.")
# Note: This will potentially be a large list, but at least sorted
return outstream_buffer.getvalue().strip().splitlines()
def _get_git_submodule_paths(self) -> List[str]:
"""
Returns a list of directory absolute path strings to the root of each submodule in the workspace repository.
If git is not found, an empty list will be returned.
"""
if not shutil.which("git"):
logging.warn(
"Git is not found on this system. Git submodule paths will not be considered.")
return []
if os.path.isfile(os.path.join(self._abs_workspace_path, ".gitmodules")):
logging.info(
f".gitmodules file found. Excluding submodules in {self._package_name}.")
outstream_buffer = StringIO()
exit_code = RunCmd("git", "config --file .gitmodules --get-regexp path", workingdir=self._abs_workspace_path, outstream=outstream_buffer, logging_level=logging.NOTSET)
if (exit_code != 0):
raise UncrustifyGitSubmoduleException(
f".gitmodule file detected but an error occurred reading the file. Cannot proceed with unknown submodule paths.")
submodule_paths = []
for line in outstream_buffer.getvalue().strip().splitlines():
submodule_paths.append(
os.path.normpath(os.path.join(self._abs_workspace_path, line.split()[1])))
return submodule_paths
else:
return []
def _get_template_file_contents(self) -> None:
"""
Gets the contents of Uncrustify template files if they are specified
in the Uncrustify configuration file.
"""
self._file_template_contents = None
self._func_template_contents = None
# Allow no value to allow "set" statements in the config file which do
# not specify value assignment
parser = configparser.ConfigParser(allow_no_value=True)
with open(self._app_config_file, 'r') as cf:
parser.read_string("[dummy_section]\n" + cf.read())
try:
file_template_name = parser["dummy_section"]["cmt_insert_file_header"]
file_template_path = pathlib.Path(file_template_name)
if not file_template_path.is_file():
file_template_path = pathlib.Path(os.path.join(self._plugin_path, file_template_name))
self._file_template_contents = file_template_path.read_text()
except KeyError:
logging.warn("A file header template is not specified in the config file.")
except FileNotFoundError:
logging.warn("The specified file header template file was not found.")
try:
func_template_name = parser["dummy_section"]["cmt_insert_func_header"]
func_template_path = pathlib.Path(func_template_name)
if not func_template_path.is_file():
func_template_path = pathlib.Path(os.path.join(self._plugin_path, func_template_name))
self._func_template_contents = func_template_path.read_text()
except KeyError:
logging.warn("A function header template is not specified in the config file.")
except FileNotFoundError:
logging.warn("The specified function header template file was not found.")
def _initialize_app_info(self) -> None:
"""
Initialize Uncrustify application information.
This function will determine the application path and version.
"""
# Verify Uncrustify is specified in the environment.
if UncrustifyCheck.UNCRUSTIFY_PATH_ENV_KEY not in os.environ:
raise UncrustifyAppEnvVarNotFoundException(
f"Uncrustify environment variable {UncrustifyCheck.UNCRUSTIFY_PATH_ENV_KEY} is not present.")
self._app_path = shutil.which('uncrustify', path=os.environ[UncrustifyCheck.UNCRUSTIFY_PATH_ENV_KEY])
if self._app_path is None:
raise FileNotFoundError(
errno.ENOENT, os.strerror(errno.ENOENT), self._app_path)
self._app_path = os.path.normcase(os.path.normpath(self._app_path))
if not os.path.isfile(self._app_path):
raise FileNotFoundError(
errno.ENOENT, os.strerror(errno.ENOENT), self._app_path)
# Verify Uncrustify is present at the expected path.
return_buffer = StringIO()
ret = RunCmd(self._app_path, "--version", outstream=return_buffer)
if (ret != 0):
raise UncrustifyAppVersionErrorException(
f"Error occurred executing --version: {ret}.")
# Log Uncrustify version information.
self._app_version = return_buffer.getvalue().strip()
self._tc.LogStdOut(f"Uncrustify version: {self._app_version}")
version_aggregator.GetVersionAggregator().ReportVersion(
"Uncrustify", self._app_version, version_aggregator.VersionTypes.INFO)
def _initialize_config_file_info(self) -> None:
"""
Initialize Uncrustify configuration file info.
The config file path is relative to the package root.
"""
self._app_config_file = UncrustifyCheck.DEFAULT_CONFIG_FILE_PATH
if "ConfigFilePath" in self._package_config:
self._app_config_file = self._package_config["ConfigFilePath"].strip()
self._app_config_file = os.path.normpath(
os.path.join(self._abs_package_path, self._app_config_file))
if not os.path.isfile(self._app_config_file):
raise FileNotFoundError(
errno.ENOENT, os.strerror(errno.ENOENT), self._app_config_file)
def _initialize_environment_info(self, package_rel_path: str, edk2_path: Edk2Path, package_config: Dict[str, List[str]], tc: JunitReportTestCase) -> None:
"""
Initializes plugin environment information.
"""
self._abs_package_path = edk2_path.GetAbsolutePathOnThisSytemFromEdk2RelativePath(
package_rel_path)
self._abs_workspace_path = edk2_path.WorkspacePath
self._package_config = package_config
self._package_name = os.path.basename(
os.path.normpath(package_rel_path))
self._plugin_name = self.__class__.__name__
self._plugin_path = os.path.dirname(os.path.realpath(__file__))
self._rel_package_path = package_rel_path
self._tc = tc
def _initialize_file_to_format_info(self) -> None:
"""
Forms the list of source files for Uncrustify to process.
"""
# Create a list of all the package relative file paths in the package to run against Uncrustify.
rel_file_paths_to_format = list(
UncrustifyCheck.STANDARD_PLUGIN_DEFINED_PATHS)
# Allow the ci.yaml to remove any of the pre-defined standard paths
if "IgnoreStandardPaths" in self._package_config:
for a in self._package_config["IgnoreStandardPaths"]:
if a.strip() in rel_file_paths_to_format:
self._tc.LogStdOut(
f"Ignoring standard path due to ci.yaml ignore: {a}")
rel_file_paths_to_format.remove(a.strip())
else:
raise UncrustifyInvalidIgnoreStandardPathsException(f"Invalid IgnoreStandardPaths value: {a}")
# Allow the ci.yaml to specify additional include paths for this package
if "AdditionalIncludePaths" in self._package_config:
rel_file_paths_to_format.extend(
self._package_config["AdditionalIncludePaths"])
self._abs_file_paths_to_format = []
for path in rel_file_paths_to_format:
self._abs_file_paths_to_format.extend(
[str(path.resolve()) for path in pathlib.Path(self._abs_package_path).rglob(path)])
if not "SkipGitExclusions" in self._package_config or not self._package_config["SkipGitExclusions"]:
# Remove files ignored by git
logging.info(
f"{self._package_name} file count before git ignore file exclusion: {len(self._abs_file_paths_to_format)}")
ignored_paths = self._get_git_ignored_paths()
self._abs_file_paths_to_format = list(
set(self._abs_file_paths_to_format).difference(ignored_paths))
logging.info(
f"{self._package_name} file count after git ignore file exclusion: {len(self._abs_file_paths_to_format)}")
# Remove files in submodules
logging.info(
f"{self._package_name} file count before submodule exclusion: {len(self._abs_file_paths_to_format)}")
submodule_paths = tuple(self._get_git_submodule_paths())
for path in submodule_paths:
logging.info(f" submodule path: {path}")
self._abs_file_paths_to_format = [
f for f in self._abs_file_paths_to_format if not f.startswith(submodule_paths)]
logging.info(
f"{self._package_name} file count after submodule exclusion: {len(self._abs_file_paths_to_format)}")
# Sort the files for more consistent results
self._abs_file_paths_to_format.sort()
def _initialize_test_case_output_options(self) -> None:
"""
Initializes options that influence test case output.
"""
self._audit_only_mode = False
self._output_file_diffs = False
if "AuditOnly" in self._package_config and self._package_config["AuditOnly"]:
self._audit_only_mode = True
if "OutputFileDiffs" in self._package_config and self._package_config["OutputFileDiffs"]:
self._output_file_diffs = True
def _log_uncrustify_app_info(self) -> None:
"""
Logs Uncrustify application information.
"""
self._tc.LogStdOut(f"Found Uncrustify at {self._app_path}")
self._tc.LogStdOut(f"Uncrustify version: {self._app_version}")
self._tc.LogStdOut('\n')
logging.info(f"Found Uncrustify at {self._app_path}")
logging.info(f"Uncrustify version: {self._app_version}")
logging.info('\n')
def _process_uncrustify_results(self) -> None:
"""
Process the results from Uncrustify.
Determines whether formatting errors are present and logs failures.
"""
formatted_files = [str(path.resolve()) for path in pathlib.Path(
self._abs_package_path).rglob(f'*{UncrustifyCheck.FORMATTED_FILE_EXTENSION}')]
self._formatted_file_error_count = len(formatted_files)
if self._formatted_file_error_count > 0:
self._tc.LogStdError("Files with formatting errors:\n")
if self._output_file_diffs:
logging.info("Calculating file diffs. This might take a while...")
for formatted_file in formatted_files:
pre_formatted_file = formatted_file[:-
len(UncrustifyCheck.FORMATTED_FILE_EXTENSION)]
logging.error(pre_formatted_file)
if (self._output_file_diffs or
self._file_template_contents is not None or
self._func_template_contents is not None):
self._tc.LogStdError(
f"Formatting errors in {os.path.relpath(pre_formatted_file, self._abs_package_path)}\n")
with open(formatted_file) as ff:
formatted_file_text = ff.read()
if (self._file_template_contents is not None and
self._file_template_contents in formatted_file_text):
self._tc.LogStdError(f"File header is missing in {os.path.relpath(pre_formatted_file, self._abs_package_path)}\n")
if (self._func_template_contents is not None and
self._func_template_contents in formatted_file_text):
self._tc.LogStdError(f"A function header is missing in {os.path.relpath(pre_formatted_file, self._abs_package_path)}\n")
if self._output_file_diffs:
with open(pre_formatted_file) as pf:
pre_formatted_file_text = pf.read()
for line in difflib.unified_diff(pre_formatted_file_text.split('\n'), formatted_file_text.split('\n'), fromfile=pre_formatted_file, tofile=formatted_file, n=3):
self._tc.LogStdError(line)
self._tc.LogStdError('\n')
else:
self._tc.LogStdError(pre_formatted_file)
def _remove_tree(self, dir_path: str, ignore_errors: bool = False) -> None:
"""
Helper for removing a directory. Over time there have been
many private implementations of this due to reliability issues in the
shutil implementations. To consolidate on a single function this helper is added.
On error try to change file attributes. Also add retry logic.
This function is temporarily borrowed from edk2toollib.utility_functions
since the version used in edk2 is not recent enough to include the
function.
This function should be replaced by "RemoveTree" when it is available.
Args:
- dir_path: Path to directory to remove.
- ignore_errors: Whether to ignore errors during removal
"""
def _remove_readonly(func, path, _):
"""
Private function to attempt to change permissions on file/folder being deleted.
"""
os.chmod(path, os.stat.S_IWRITE)
func(path)
for _ in range(3): # retry up to 3 times
try:
shutil.rmtree(dir_path, ignore_errors=ignore_errors, onerror=_remove_readonly)
except OSError as err:
logging.warning(f"Failed to fully remove {dir_path}: {err}")
else:
break
else:
raise RuntimeError(f"Failed to remove {dir_path}")
def _run_uncrustify(self) -> None:
"""
Runs Uncrustify for this instance of plugin execution.
"""
logging.info("Executing Uncrustify. This might take a while...")
start_time = timeit.default_timer()
self._execute_uncrustify()
end_time = timeit.default_timer() - start_time
execution_summary = f"Uncrustify executed against {len(self._abs_file_paths_to_format)} files in {self._package_name} in {end_time:.2f} seconds.\n"
self._tc.LogStdOut(execution_summary)
logging.info(execution_summary)
if self._app_exit_code != 0 and self._app_exit_code != 1:
raise UncrustifyAppExecutionException(
f"Error {str(self._app_exit_code)} returned from Uncrustify:\n\n{str(self._app_output)}")

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@ -1,9 +0,0 @@
/** @file
Brief description of the file's purpose.
Detailed description of the file's contents and other useful
information for a person viewing the file for the first time.
<<Copyright>>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

View File

@ -1,15 +0,0 @@
/**
Brief description of this function's purpose.
Follow it immediately with the detailed description.
@param[in] Arg1 Description of Arg1.
@param[in] Arg2 Description of Arg2 This is complicated and requires
multiple lines to describe.
@param[out] Arg3 Description of Arg3.
@param[in, out] Arg4 Description of Arg4.
@retval VAL_ONE Description of what VAL_ONE signifies.
@retval OTHER This is the only other return value. If there were other
return values, they would be listed.
**/

View File

@ -1,462 +0,0 @@
## @file
# Uncrustify Configuration File for EDK II C Code
#
# Coding Standard: https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
#
# This configuration file is meant to be a "best attempt" to align with the
# definitions in the EDK II C Coding Standards Specification.
#
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
# Force UTF-8 encoding (no UTF-16)
enable_digraphs = false
utf8_byte = false
utf8_force = true
# Code width / line splitting
#code_width =120 # TODO: This causes non-deterministic behaviour in some cases when code wraps
ls_code_width =false
ls_for_split_full =true
ls_func_split_full =true
pos_comma =trail
# 5.1.7 All files must end with CRLF
newlines = crlf
# 5.1.2 Do not use tab characters
cmt_convert_tab_to_spaces = true # Whether to convert all tabs to spaces in comments. If false, tabs in
# comments are left alone, unless used for indenting.
indent_columns = 2 # Number of spaces for indentation
indent_with_tabs = 0 # Do not use TAB characters
string_replace_tab_chars = true # Replace TAB with SPACE
# Note: This will break .robot files but is needed for edk2 style
# 5.2.1.1 There shall be only one statement on a line (statement ends with ;)
nl_multi_line_cond = true # Add a newline between ')' and '{' if the ')' is on a different line than
# the if/for/etc.
nl_after_semicolon = true # Whether to add a newline after semicolons, except in 'for' statements.
# 5.2.1.3 An open brace '{' goes on the same line as the closing parenthesis ')' of simple predicate expressions
mod_full_brace_do = add # Add or remove braces on a single-line 'do' statement.
mod_full_brace_for = add
mod_full_brace_function = add # Add or remove braces on a single-line function definition.
mod_full_brace_if = add # Add or remove braces on a single-line 'if' statement. Braces will not be
# removed if the braced statement contains an 'else'.
mod_full_brace_if_chain = false
mod_full_brace_while = add
# 5.2.1.4 A close brace '}' always goes at the beginning of the last line of the body
eat_blanks_after_open_brace = true
eat_blanks_before_close_brace = true # Whether to remove blank lines before '}'.
# 5.2.2.2 Always put space before and after binary operators.
sp_assign = add # Add or remove space around assignment operator '=', '+=', etc.
sp_assign_default = add
sp_bool = add # Add or remove space around boolean operators '&&' and '||'.
sp_compare = add # Add or remove space around compare operator '<', '>', '==', etc.
# 5.2.2.3 Do not put space between unary operators and their object
sp_addr = remove # A or remove space after the '&' (address-of) unary operator.
sp_incdec = remove # Add or remove space between '++' and '--' the word to which it is being
# applied, as in '(--x)' or 'y++;'.
sp_inv = remove # Add or remove space after the '~' (invert) unary operator.
sp_not = remove # Add or remove space after the '!' (not) unary operator.
sp_sign = remove # Add or remove space after '+' or '-', as in 'x = -5' or 'y = +7'.
# 5.2.2.4 Subsequent lines of multi-line function calls should line up two spaces from the beginning of the function
# name
nl_func_call_args_multi_line = true # Whether to add a newline after each ',' in a function call if '(' and ')'
# are in different lines.
nl_func_call_args_multi_line_ignore_closures = false
# - Indent each argument 2 spaces from the start of the function name. If a
# function is called through a structure or union member, of type
# pointer-to-function, then indent each argument 2 spaces from the start of the
# member name.
indent_func_call_edk2_style = true # Use EDK2 indentation style for function calls (**CUSTOM SETTING**)
indent_paren_after_func_call = true # Whether to indent the open parenthesis of a function call, if the
# parenthesis is on its own line.
# - Align the close parenthesis with the start of the last argument
indent_paren_close = 0 # How to indent a close parenthesis after a newline.
# (0: Body, 1: Openparenthesis, 2: Brace level)
# 5.2.2.5 Always put space after commas or semicolons that separate items
sp_after_comma = force # Add or remove space after ',', i.e. 'a,b' vs. 'a, b'.
sp_before_comma = remove # Add or remove space before ','.
# 5.2.2.6 Always put space before an open parenthesis
sp_after_sparen = add # Add or remove space after ')' of control statements.
sp_attribute_paren = add # Add or remove space between '__attribute__' and '('.
sp_before_sparen = force # Add or remove space before '(' of control statements
# ('if', 'for', 'switch', 'while', etc.).
sp_defined_paren = force # Add or remove space between 'defined' and '(' in '#if defined (FOO)'.
sp_func_call_paren = force # Add or remove space between function name and '(' on function calls.
sp_func_call_paren_empty = force # Add or remove space between function name and '()' on function calls
# without parameters. If set to ignore (the default), sp_func_call_paren is
# used.
sp_func_def_paren = add # Add or remove space between alias name and '(' of a non-pointer function
# type typedef.
sp_func_proto_paren = add # Add or remove space between function name and '()' on function declaration
sp_sizeof_paren = force # Add or remove space between 'sizeof' and '('.
sp_type_func = add # Add or remove space between return type and function name. A minimum of 1
# is forced except for pointer return types.
# Not specified, but also good style to remove spaces inside parentheses (Optional)
sp_cparen_oparen = remove # Add or remove space between back-to-back parentheses, i.e. ')(' vs. ') ('.
sp_inside_fparen = remove # Add or remove space inside function '(' and ')'.
sp_inside_fparens = remove # Add or remove space inside empty function '()'.
sp_inside_paren = remove # Add or remove space inside '(' and ')'.
sp_inside_paren_cast = remove # Add or remove spaces inside cast parentheses. '(int)x'
sp_inside_square = remove # Add or remove space inside a non-empty '[' and ']'.
sp_paren_paren = remove # Add or remove space between nested parentheses, i.e. '((' vs. ') )'.
sp_square_fparen = remove # Add or remove space between ']' and '(' when part of a function call.
# 5.2.2.7 Put a space before an open brace if it is not on its own line
sp_do_brace_open = force # Add or remove space between 'do' and '{'.
sp_paren_brace = force # Add or remove space between ')' and '{'.
sp_sparen_brace = force # Add or remove space between ')' and '{' of of control statements.
# 5.2.2.8 Do not put spaces around structure member and pointer operators
sp_after_byref = remove # Add or remove space after reference sign '&', if followed by a word.
sp_before_byref = add # Add or remove space before a reference sign '&'.
sp_deref = remove # Add or remove space after the '*' (dereference) unary operator. This does
# not affect the spacing after a '*' that is part of a type.
sp_member = remove # Add or remove space around the '.' or '->' operators.
# 5.2.2.9 Do not put spaces before open brackets of array subscripts
sp_before_square = remove # Add or remove space before '[' (except '[]').
sp_before_squares = remove # Add or remove space before '[]'.
sp_before_vardef_square = remove # Add or remove space before '[' for a variable definition.
# 5.2.2.10 Use extra parentheses rather than depending on in-depth knowledge of the order of precedence of C
mod_full_paren_if_bool = true # Whether to fully parenthesize Boolean expressions in 'while' and 'if'
# statement, as in 'if (a && b > c)' => 'if (a && (b > c))'.
# 5.2.2.11 Align a continuation line with the part of the line that it continues.
use_indent_continue_only_once = true
# Additional '{}' bracing rules (Optional)
# NOTE - The style guide specifies two different styles for braces,
# so these are ignored for now to allow developers some flexibility.
nl_after_brace_close = true # Whether to add a newline after '}'. Does not apply if followed by a
# necessary ';'.
nl_brace_else = remove # Add or remove newline between '}' and 'else'.
nl_brace_while = remove # Add or remove newline between '}' and 'while' of 'do' statement.
nl_do_brace = remove # Add or remove newline between 'do' and '{'.
nl_else_brace = remove # Add or remove newline between 'else' and '{'.
nl_else_if = remove # Add or remove newline between 'else' and 'if'.
nl_elseif_brace = remove # Add or remove newline between 'else if' and '{'.
nl_enum_brace = remove # Add or remove newline between 'enum' and '{'.
nl_fcall_brace = remove # Add or remove newline between a function call's ')' and '{',
# as in 'list_for_each(item, &list) { }'.
nl_for_brace = remove # Add or remove newline between 'for' and '{'.
nl_if_brace = remove # Add or remove newline between 'if' and '{'.
nl_struct_brace = remove # Add or remove newline between 'struct and '{'.
nl_switch_brace = remove # Add or remove newline between 'switch' and '{'.
nl_union_brace = remove # Add or remove newline between 'union' and '{'.
nl_while_brace = remove # Add or remove newline between 'while' and '{'.
# Additional whitespace rules (Optional)
sp_after_ptr_star = remove # Add or remove space after pointer star '*', if followed by a word.
# Useful when paired with align_var_def_star_style==2
sp_after_ptr_star_func = remove # Add or remove space after a pointer star '*', if followed by a function
# prototype or function definition.
sp_after_semi = remove # Add or remove space after ';', except when followed by a comment.
sp_before_case_colon = remove # Add or remove space before case ':'.
sp_before_ptr_star = add # Add or remove space before pointer star '*'.
sp_before_ptr_star_func = add # Add or remove space before a pointer star '*', if followed by a function
# prototype or function definition.
sp_before_semi = remove # Add or remove space before ';'
sp_before_semi_for = remove # Add or remove space before ';' in non-empty 'for' statements.
sp_before_semi_for_empty = add # Add or remove space before a semicolon of an empty part of a for statement
sp_between_ptr_star = remove # Add or remove space between pointer stars '*'. (ie, 'VOID **')
sp_brace_close_while = force # Add or remove space between '}' and 'while'.
sp_after_cast = remove
sp_after_type = add
sp_balance_nested_parens = false
sp_before_nl_cont = add
sp_before_square_asm_block = ignore
sp_before_unnamed_byref = add
sp_brace_brace = ignore
sp_brace_else = force
sp_brace_typedef = add
sp_case_label = force
sp_cmt_cpp_doxygen = true
sp_cond_colon = add
sp_cond_question = add
sp_cpp_cast_paren = force
sp_else_brace = force
sp_endif_cmt = force
sp_enum_assign = add
sp_inside_braces = force
sp_inside_braces_empty = force
sp_inside_braces_enum = force
sp_inside_braces_struct = force
sp_pp_concat = add
sp_pp_stringify = add
sp_return_paren = add
sp_special_semi = force
sp_while_paren_open = force
# Additional Indentation Rules
indent_access_spec = 1
indent_access_spec_body = false
indent_align_assign = true
indent_align_string = true
indent_bool_paren = true
indent_brace_parent = false
indent_braces = false
indent_braces_no_class = false
indent_braces_no_func = true
indent_braces_no_struct = false
indent_class = false
indent_class_colon = false
indent_cmt_with_tabs = false # Whether to indent comments that are not at a brace level with tabs on
# a tabstop. Requires indent_with_tabs=2. If false, will use spaces.
indent_col1_comment = true
indent_col1_multi_string_literal= true
indent_comma_paren = true
indent_else_if = true
indent_extern = false
indent_first_bool_expr = true
indent_func_def_param_paren_pos_threshold = 0
indent_func_param_double = false
indent_func_proto_param = true
indent_ignore_asm_block = true
indent_label = 1
indent_member = 2
indent_namespace = false
indent_param = 2
indent_paren_nl = false
indent_paren_open_brace = false
indent_preserve_sql = false
indent_relative_single_line_comments = false
indent_sing_line_comments = 0
indent_single_newlines = false
indent_square_nl = false
indent_switch_case = 2
indent_template_param = true
indent_var_def_blk = 0
indent_var_def_cont = false
# Tidy-up rules (Optional)
mod_move_case_break = true # Whether to move a 'break' that appears after a fully braced 'case'
# before the close brace, as in 'case X: { ... } break;' =>
# 'case X: { ... break; }'.
mod_pawn_semicolon = false
mod_remove_empty_return = false # Whether to remove a void 'return;' that appears as the last statement
# in a function.
mod_remove_extra_semicolon = true
mod_sort_import = false
mod_sort_include = false
mod_sort_using = false
nl_after_case = false # Whether to add a newline after a 'case' statement.
nl_end_of_file = force # Add or remove newline at the end of the file.
nl_end_of_file_min = 1 # The minimum number of newlines at the end of the file
nl_max = 2 # The maximum number of consecutive newlines (3 = 2 blank lines).
nl_start_of_file = remove # Add or remove newlines at the start of the file.
# Code alignment rules (Optional)
align_asm_colon = false
align_assign_span = 1 # The span for aligning on '=' in assignments.
align_assign_thresh = 0
align_edk2_style = true # Whether to apply edk2-specific alignment formatting
align_enum_equ_span = 1 # The span for aligning on '=' in enums.
align_func_params = true # Whether to align variable definitions in prototypes and functions.
align_func_params_gap = 2
align_func_params_span = 2 # The span for aligning parameter definitions in function on parameter name.
align_func_params_thresh = 0
align_func_proto_span = 0
align_keep_tabs = false
align_left_shift = false
align_mix_var_proto = false
align_nl_cont = false
align_oc_decl_colon = false
align_on_operator = false
align_on_tabstop = false
align_pp_define_gap = 2
align_pp_define_span = 1
align_right_cmt_at_col = 0 # Align trailing comment at or beyond column N; 'pulls in' comments as
# a bonus side effect (0=ignore)
align_right_cmt_gap = 0 # If a trailing comment is more than this number of columns away from the
# text it follows,
# it will qualify for being aligned. This has to be > 0 to do anything.
align_right_cmt_mix = false # If aligning comments, mix with comments after '}' and #endif with less
# than 3 spaces before the comment
align_right_cmt_same_level = true # Whether to only align trailing comments that are at the same brace level.
align_right_cmt_span = 2 # The span for aligning comments that end lines.
align_same_func_call_params = false
align_single_line_brace = true
align_single_line_func = true
align_struct_init_span = 1 # The span for aligning struct initializer values.
align_typedef_amp_style = 1
align_typedef_func = 1 # How to align typedef'd functions with other typedefs.
# (0: No align, 1: Align open paranthesis, 2: Align function type name)
align_typedef_gap = 2
align_typedef_span = 1 # The span for aligning single-line typedefs.
align_typedef_star_style = 1
align_var_def_amp_style = 1
align_var_def_attribute = true
align_var_def_colon = true # Whether to align the colon in struct bit fields.
align_var_def_gap = 2 # The gap (minimum spacing for aligned items) for variable definitions.
align_var_def_inline = false
align_var_def_span = 1 # The span (lines needed to align) for aligning variable definitions.
align_var_def_star_style = 1 # How to consider (or treat) the '*' in the alignment of variable
# definitions.
# 0: Part of the type 'void * foo;' (default)
# 1: Part of the variable 'void *foo;'
# 2: Dangling 'void *foo;'
# (Note - should also set sp_after_ptr_star=remove)
align_var_struct_gap = 4
align_var_struct_span = 8 # The span for aligning struct/union member definitions.
align_var_struct_thresh = 0
align_with_tabs = false
# Comment formatting
cmt_align_doxygen_javadoc_tags = true # Whether to align doxygen javadoc-style tags ('@param', '@return', etc.)
# TODO: Eats '[' in '[in]'
cmt_c_group = false
cmt_c_nl_end = true # Whether to add a newline before the closing '*/' of the combined c-comment.
cmt_c_nl_start = true
cmt_cpp_group = false
cmt_cpp_nl_end = true
cmt_cpp_nl_start = true
cmt_cpp_to_c = false
cmt_indent_multi = false # Whether to apply changes to multi-line comments, including cmt_width,
# keyword substitution and leading chars.
cmt_insert_before_preproc = false
#cmt_insert_file_header = default_file_header.txt
#cmt_insert_func_header = default_function_header.txt
cmt_multi_check_last = false
cmt_multi_first_len_minimum = 2
cmt_reflow_mode = 1 # How to reflow comments.
# (0:No reflow, 1:No touching at all, 2: Full reflow)
cmt_sp_after_star_cont = 0 # The number of spaces to insert after the star on subsequent comment lines.
cmt_sp_before_star_cont = 0 # The number of spaces to insert at the start of subsequent comment lines.
cmt_star_cont = false # Whether to put a star on subsequent comment lines.
cmt_width = 120 # Try to wrap comments at N columns.
sp_cmt_cpp_start = add # Add or remove space after the opening of a C++ comment, as in
# '// <here> A'. NOTE: Breaks indentation within comments.
# Function definitions / declarations
indent_func_call_param = false # Whether to indent continued function call parameters one indent level,
# rather than aligning parameters under the open parenthesis.
indent_func_class_param = false # Whether to indent continued function call declaration one indent level,
# rather than aligning parameters under the open parenthesis.
indent_func_ctor_var_param = false # Whether to indent continued class variable constructors one indent level,
# rather than aligning parameters under the open parenthesis.
indent_func_def_param = true # Whether to indent continued function definition parameters one indent
# level, rather than aligning parameters under the open parenthesis.
nl_fdef_brace = add # Add or remove newline between function signature and '{'.
nl_func_call_end_multi_line = true # Whether to add a newline before ')' in a function call if '(' and ')' are
# in different lines.
nl_func_call_paren = remove # Add or remove newline between a function name and the opening '(' in the
# call.
nl_func_call_start_multi_line = true # Whether to add a newline after '(' in a function call if '(' and ')' are
# in different lines.
nl_func_decl_args = force # Add or remove newline after each ',' in a function declaration.
nl_func_decl_empty = add # Add or remove newline between '()' in a function declaration.
nl_func_def_args = force # Add or remove newline after each ',' in a function definition.
nl_func_def_empty = add # Add or remove newline between '()' in a function definition.
nl_func_def_paren = remove # Add or remove newline between a function name and the opening '('
# in the definition.
nl_func_paren = remove # Add or remove newline between a function name and the opening '(' in
# the declaration.
nl_func_type_name = add # Add or remove newline between return type and function name in a function
# definition.
sp_fparen_brace = force # Add or remove space between ')' and '{' of function.
use_indent_func_call_param = true # indent_func_call_param will be used
# Additional Newline Rules
nl_after_brace_open = true # Whether to add a newline after '{'. This also adds a newline
# before the matching '}'.
nl_after_brace_open_cmt = true # Whether to add a newline between the open brace and a
# trailing single-line comment.
# Requires nl_after_brace_open = true.
nl_after_do = add # Add or remove blank line after 'do/while' statement.
nl_after_for = add # Add or remove blank line after 'for' statement.
nl_after_func_body = 2 # The number of newlines after '}' of a multi-line function body
nl_after_func_body_one_liner = 2
nl_after_func_proto = 2
nl_after_func_proto_group = 2
nl_after_if = add
nl_after_multiline_comment = false
nl_after_return = false
nl_after_struct = 2
nl_after_switch = add
nl_after_vbrace_close = true
nl_after_vbrace_open = true
nl_after_vbrace_open_empty = true
nl_after_while = add
nl_assign_leave_one_liners = true
nl_before_block_comment = 2
nl_before_case = false
nl_before_do = ignore
nl_before_for = ignore
nl_before_if = ignore
nl_before_switch = ignore
nl_before_while = ignore
nl_before_whole_file_ifdef = 2
nl_brace_brace = force
nl_brace_struct_var = remove
nl_case_colon_brace = add
nl_class_leave_one_liners = false
nl_collapse_empty_body = false
nl_comment_func_def = 1
nl_create_for_one_liner = false
nl_create_if_one_liner = false
nl_create_while_one_liner = false
nl_define_macro = false
nl_ds_struct_enum_close_brace = true
nl_ds_struct_enum_cmt = false
nl_enum_leave_one_liners = false
nl_func_decl_end = add
nl_func_decl_start = add
nl_func_def_end = add
nl_func_def_start = add
nl_func_leave_one_liners = false
nl_func_proto_type_name = add
nl_func_var_def_blk = 1
nl_getset_leave_one_liners = false
nl_if_leave_one_liners = false
nl_multi_line_define = false
nl_squeeze_ifdef = false
nl_var_def_blk_end = 0
nl_var_def_blk_start = 0
# Preprocessor Rules
pp_define_at_level = true
pp_if_indent_code = false
pp_indent_func_def = false
pp_indent_extern = false
pp_ignore_define_body = true # Workaround: Turn off processing for #define body
# (current rules do not work for some defines)
pp_indent = add
pp_indent_at_level = true
pp_indent_count = 2
pp_indent_if = 2
pp_indent_region = 2
pp_region_indent_code = false
pp_space = remove
#
# The tokens below are assigned specific types so they are always recognized properly.
#
# Explicitly define EDK II qualifiers
set QUALIFIER CONST
set QUALIFIER EFIAPI
set QUALIFIER IN
set QUALIFIER OPTIONAL
set QUALIFIER OUT
# Explicitly define EDK II types
set TYPE EFI_STATUS
set TYPE VOID

View File

@ -1,16 +0,0 @@
## @file
# Downloads the Uncrustify application from a Project Mu NuGet package.
#
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
"id": "uncrustify-ci-1",
"scope": "cibuild",
"type": "nuget",
"name": "mu-uncrustify-release",
"source": "https://pkgs.dev.azure.com/projectmu/Uncrustify/_packaging/mu_uncrustify/nuget/v3/index.json",
"version": "73.0.3",
"flags": ["set_shell_var", "host_specific"],
"var_name": "UNCRUSTIFY_CI_PATH"
}

View File

@ -1,11 +0,0 @@
## @file
# CiBuildPlugin used to check coding standard compliance of EDK II style C source code
#
# Copyright (c) Microsoft Corporation.
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
"scope": "cibuild",
"name": "Uncrustify Coding Standard Test",
"module": "UncrustifyCheck"
}

View File

@ -264,10 +264,6 @@ BSD-2-Clause-Patent.
Run the Ecc tool on the package. The Ecc tool is available in the BaseTools
package. It checks that the code complies to the EDKII coding standard.
### Coding Standard Compliance - UncrustifyCheck
Runs the Uncrustify application to check for coding standard compliance issues.
## PyTool Scopes
Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning

View File

@ -19,10 +19,7 @@
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
"Library/ArmSoftFloatLib/berkeley-softfloat-3",
"Library/ArmSoftFloatLib/ArmSoftFloatLib.c",
"Library/CompilerIntrinsicsLib",
"Universal/Smbios/SmbiosMiscDxe"
"Library/ArmSoftFloatLib/berkeley-softfloat-3"
]
},

View File

@ -3,7 +3,6 @@
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -338,9 +337,9 @@
# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
#
# gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
# gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
# gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
#
# because (a) the target address space (ie. the cpu-physical space) is
# 64-bit, and (b) the translation values are meant as offsets for *modular*
@ -357,11 +356,11 @@
# UINT64 TranslatedMmio64Address; // output parameter
#
# TranslatedIoAddress = UntranslatedIoAddress +
# gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
# PcdPciIoTranslation;
# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
# gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
# PcdPciMmio32Translation;
# TranslatedMmio64Address = UntranslatedMmio64Address +
# gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
# PcdPciMmio64Translation;
#
# The modular arithmetic performed in UINT64 ensures that the translation
# works correctly regardless of the relation between IoCpuBase and
@ -370,20 +369,16 @@
#
gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
#
# Inclusive range of allowed PCI buses.
#
gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
[PcdsDynamicEx]
#
# This dynamic PCD hold the GUID of a firmware FFS which contains
# the LinuxBoot payload.
#
gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C

View File

@ -5,7 +5,6 @@
# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation.<BR>
# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -151,7 +150,6 @@
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBootManagerLib.inf
ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf

View File

@ -12,23 +12,21 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Cpu.h>
STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
EFI_STATUS
EFIAPI
ArmCrashDumpDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
ASSERT_EFI_ERROR (Status);
ASSERT_EFI_ERROR(Status);
return mCpu->RegisterInterruptHandler (
mCpu,
EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
&DefaultExceptionHandler
);
return mCpu->RegisterInterruptHandler (mCpu,
EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
&DefaultExceptionHandler);
}

View File

@ -11,8 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
VOID
@ -26,13 +26,14 @@ ExitBootServicesEvent (
EFI_HANDLE gHardwareInterruptHandle = NULL;
// Notifications
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts
UINTN mGicNumInterrupts = 0;
UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
/**
Calculate GICD_ICFGRn base address and corresponding bit
field Int_config[1] of the GIC distributor register.
@ -46,21 +47,21 @@ HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
**/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
)
{
UINTN RegIndex;
UINTN Field;
UINTN RegIndex;
UINTN Field;
if (Source >= mGicNumInterrupts) {
ASSERT (Source < mGicNumInterrupts);
ASSERT(Source < mGicNumInterrupts);
return EFI_UNSUPPORTED;
}
RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
*RegAddress = PcdGet64 (PcdGicDistributorBase)
+ ARM_GIC_ICDICFR
+ (ARM_GIC_ICDICFR_BYTES * RegIndex);
@ -70,6 +71,8 @@ GicGetDistributorIcfgBaseAndBit (
return EFI_SUCCESS;
}
/**
Register Handler for the specified interrupt source.
@ -84,13 +87,13 @@ GicGetDistributorIcfgBaseAndBit (
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -105,25 +108,25 @@ RegisterInterruptSource (
gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler) {
if (NULL == Handler){
return This->DisableInterruptSource (This, Source);
} else {
return This->EnableInterruptSource (This, Source);
}
}
STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC
VOID
EFIAPI
CpuArchEventProtocolNotify (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
// Get the CPU protocol that this driver requires.
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
@ -134,28 +137,17 @@ CpuArchEventProtocolNotify (
// Unregister the default exception handler.
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
return;
}
// Register to receive interrupts
Status = Cpu->RegisterInterruptHandler (
Cpu,
ARM_ARCH_EXCEPTION_IRQ,
Context
);
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ,
Context);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__,
Status
));
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
}
gBS->CloseEvent (Event);
@ -165,13 +157,13 @@ EFI_STATUS
InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
)
{
EFI_STATUS Status;
CONST UINTN RihArraySize =
(sizeof (HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
EFI_STATUS Status;
CONST UINTN RihArraySize =
(sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
@ -199,8 +191,7 @@ InstallAndRegisterInterruptService (
TPL_CALLBACK,
CpuArchEventProtocolNotify,
InterruptHandler,
&mCpuArchProtocolNotifyEventRegistration
);
&mCpuArchProtocolNotifyEventRegistration);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (

View File

@ -32,12 +32,12 @@ Abstract:
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
ARM_GIC_ARCH_REVISION Revision;
EFI_STATUS Status;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();

View File

@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Protocol/HardwareInterrupt.h>
#include <Protocol/HardwareInterrupt2.h>
extern UINTN mGicNumInterrupts;
extern UINTN mGicNumInterrupts;
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
// Common API
@ -29,32 +29,33 @@ EFI_STATUS
InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EFI_EVENT_NOTIFY ExitBootServicesEvent
);
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
);
// GicV2 API
EFI_STATUS
GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
// GicV3 API
EFI_STATUS
GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
// Shared code
/**
@ -70,9 +71,9 @@ GicV3DxeInitialize (
**/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT UINTN *RegAddress,
OUT UINTN *Config1Bit
);
#endif // ARM_GIC_DXE_H_

View File

@ -24,13 +24,13 @@
+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
#define ISENABLER_ADDRESS(base, offset) ((base) +\
#define ISENABLER_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
#define ICENABLER_ADDRESS(base, offset) ((base) +\
#define ICENABLER_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
#define IPRIORITY_ADDRESS(base, offset) ((base) +\
#define IPRIORITY_ADDRESS(base,offset) ((base) + \
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
/**
@ -57,15 +57,15 @@ SourceIsSpi (
STATIC
UINTN
GicGetCpuRedistributorBase (
IN UINTN GicRedistributorBase,
IN ARM_GIC_ARCH_REVISION Revision
IN UINTN GicRedistributorBase,
IN ARM_GIC_ARCH_REVISION Revision
)
{
UINTN MpId;
UINTN CpuAffinity;
UINTN Affinity;
UINTN GicCpuRedistributorBase;
UINT64 TypeRegister;
UINTN MpId;
UINTN CpuAffinity;
UINTN Affinity;
UINTN GicCpuRedistributorBase;
UINT64 TypeRegister;
MpId = ArmReadMpidr ();
// Define CPU affinity as:
@ -83,7 +83,7 @@ GicGetCpuRedistributorBase (
do {
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
if (Affinity == CpuAffinity) {
return GicCpuRedistributorBase;
}
@ -107,7 +107,7 @@ GicGetCpuRedistributorBase (
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
// Read the GIC Identification Register
@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification (
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
UINTN ItLines;
UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts (
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
)
{
MmioWrite32 (
@ -162,12 +162,12 @@ ArmGicSendSgiTo (
UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
)
{
UINTN Value;
ARM_GIC_ARCH_REVISION Revision;
UINTN Value;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt (
VOID
EFIAPI
ArmGicEndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -212,26 +212,25 @@ ArmGicEndOfInterrupt (
VOID
EFIAPI
ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate register offset and bit position
RegOffset = Source / 4;
RegShift = (Source % 4) * 8;
RegShift = (Source % 4) * 8;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source))
{
SourceIsSpi (Source)) {
MmioAndThenOr32 (
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
@ -257,25 +256,24 @@ ArmGicSetInterruptPriority (
VOID
EFIAPI
ArmGicEnableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source))
{
SourceIsSpi (Source)) {
// Write set-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
@ -293,7 +291,7 @@ ArmGicEnableInterrupt (
// Write set-enable register
MmioWrite32 (
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@ -302,25 +300,24 @@ ArmGicEnableInterrupt (
VOID
EFIAPI
ArmGicDisableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source))
{
SourceIsSpi (Source)) {
// Write clear-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
@ -328,16 +325,16 @@ ArmGicDisableInterrupt (
);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
Revision
);
GicRedistributorBase,
Revision
);
if (GicCpuRedistributorBase == 0) {
return;
}
// Write clear-enable register
MmioWrite32 (
ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@ -346,30 +343,29 @@ ArmGicDisableInterrupt (
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
)
{
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 Interrupts;
UINT32 RegOffset;
UINTN RegShift;
ARM_GIC_ARCH_REVISION Revision;
UINTN GicCpuRedistributorBase;
UINT32 Interrupts;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source))
{
SourceIsSpi (Source)) {
Interrupts = ((MmioRead32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
)
& (1 << RegShift)) != 0);
& (1 << RegShift)) != 0);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
@ -381,7 +377,7 @@ ArmGicIsInterruptEnabled (
// Read set-enable register
Interrupts = MmioRead32 (
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
);
}
@ -391,7 +387,7 @@ ArmGicIsInterruptEnabled (
VOID
EFIAPI
ArmGicDisableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
// Disable Gic Distributor
@ -401,10 +397,10 @@ ArmGicDisableDistributor (
VOID
EFIAPI
ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@ -419,10 +415,10 @@ ArmGicEnableInterruptInterface (
VOID
EFIAPI
ArmGicDisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {

View File

@ -13,10 +13,10 @@
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
)
{
ARM_GIC_ARCH_REVISION Revision;
ARM_GIC_ARCH_REVISION Revision;
/*
* Enable GIC distributor in Non-Secure world.

View File

@ -22,11 +22,11 @@ Abstract:
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
STATIC UINT32 mGicInterruptInterfaceBase;
STATIC UINT32 mGicDistributorBase;
STATIC UINT32 mGicInterruptInterfaceBase;
STATIC UINT32 mGicDistributorBase;
/**
Enable interrupt source Source.
@ -42,12 +42,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -70,12 +70,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -99,13 +99,13 @@ STATIC
EFI_STATUS
EFIAPI
GicV2GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -129,12 +129,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV2EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -158,8 +158,8 @@ STATIC
VOID
EFIAPI
GicV2IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@ -185,7 +185,7 @@ GicV2IrqInterruptHandler (
}
// The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
RegisterInterruptSource,
GicV2EnableInterruptSource,
GicV2DisableInterruptSource,
@ -208,28 +208,28 @@ EFI_STATUS
EFIAPI
GicV2GetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_SOURCE Source,
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
Source,
&RegAddress,
&Config1Bit
);
Source,
&RegAddress,
&Config1Bit
);
if (EFI_ERROR (Status)) {
return Status;
}
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@ -254,22 +254,18 @@ GicV2SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
{
DEBUG ((
DEBUG_ERROR,
"Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
TriggerType));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@ -283,7 +279,7 @@ GicV2SetTriggerType (
}
Status = GicV2GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source,
&SourceEnabled
);
@ -300,7 +296,7 @@ GicV2SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV2DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source
);
}
@ -314,7 +310,7 @@ GicV2SetTriggerType (
// Restore interrupt state
if (SourceEnabled) {
GicV2EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source
);
}
@ -322,7 +318,7 @@ GicV2SetTriggerType (
return EFI_SUCCESS;
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
@ -349,8 +345,8 @@ GicV2ExitBootServicesEvent (
IN VOID *Context
)
{
UINTN Index;
UINT32 GicInterrupt;
UINTN Index;
UINT32 GicInterrupt;
// Disable all the interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
@ -386,30 +382,30 @@ GicV2ExitBootServicesEvent (
**/
EFI_STATUS
GicV2DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT32 CpuTarget;
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
UINT32 CpuTarget;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),

View File

@ -12,7 +12,7 @@
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
IN UINTN GicInterruptInterfaceBase
)
{
// Read the Interrupt Acknowledge Register
@ -22,8 +22,8 @@ ArmGicV2AcknowledgeInterrupt (
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
)
{
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);

View File

@ -10,10 +10,11 @@
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
/*
@ -26,7 +27,7 @@ ArmGicV2EnableInterruptInterface (
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
)
{
// Disable Gic Interface

View File

@ -12,11 +12,11 @@
#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
STATIC UINTN mGicDistributorBase;
STATIC UINTN mGicRedistributorsBase;
STATIC UINTN mGicDistributorBase;
STATIC UINTN mGicRedistributorsBase;
/**
Enable interrupt source Source.
@ -32,12 +32,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -60,12 +60,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -89,13 +89,13 @@ STATIC
EFI_STATUS
EFIAPI
GicV3GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -123,12 +123,12 @@ STATIC
EFI_STATUS
EFIAPI
GicV3EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
ASSERT (FALSE);
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
@ -152,8 +152,8 @@ STATIC
VOID
EFIAPI
GicV3IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@ -179,7 +179,7 @@ GicV3IrqInterruptHandler (
}
// The protocol instance produced by this driver
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
RegisterInterruptSource,
GicV3EnableInterruptSource,
GicV3DisableInterruptSource,
@ -206,9 +206,9 @@ GicV3GetTriggerType (
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
UINTN RegAddress;
UINTN Config1Bit;
EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
Source,
@ -221,9 +221,9 @@ GicV3GetTriggerType (
}
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
*TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@ -248,22 +248,18 @@ GicV3SetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
UINTN RegAddress;
UINTN Config1Bit;
UINT32 Value;
EFI_STATUS Status;
BOOLEAN SourceEnabled;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
{
DEBUG ((
DEBUG_ERROR,
"Invalid interrupt trigger type: %d\n", \
TriggerType
));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
&& (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
TriggerType));
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@ -277,7 +273,7 @@ GicV3SetTriggerType (
}
Status = GicV3GetInterruptSourceState (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source,
&SourceEnabled
);
@ -294,7 +290,7 @@ GicV3SetTriggerType (
// otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV3DisableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source
);
}
@ -307,7 +303,7 @@ GicV3SetTriggerType (
// Restore interrupt state
if (SourceEnabled) {
GicV3EnableInterruptSource (
(EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
(EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
Source
);
}
@ -315,7 +311,7 @@ GicV3SetTriggerType (
return EFI_SUCCESS;
}
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
@ -341,13 +337,17 @@ GicV3ExitBootServicesEvent (
IN VOID *Context
)
{
UINTN Index;
UINTN Index;
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
}
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);
}
// Disable Gic Interface
ArmGicV3DisableInterruptInterface ();
@ -368,14 +368,14 @@ GicV3ExitBootServicesEvent (
**/
EFI_STATUS
GicV3DxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT64 CpuTarget;
UINT64 MpId;
EFI_STATUS Status;
UINTN Index;
UINT64 CpuTarget;
UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
@ -428,14 +428,14 @@ GicV3DxeInitialize (
}
}
} else {
MpId = ArmReadMpidr ();
MpId = ArmReadMpidr ();
CpuTarget = MpId &
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
if ((MmioRead32 (
mGicDistributorBase + ARM_GIC_ICDDCR
) & ARM_GIC_ICDDCR_DS) != 0)
{
) & ARM_GIC_ICDDCR_DS) != 0) {
// If the Disable Security (DS) control bit is set, we are dealing with a
// GIC that has only one security state. In this case, let's assume we are
// executing in non-secure state (which is appropriate for DXE modules)

View File

@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#define MAX_IO_PORT_ADDRESS 0xFFFF
#define MAX_IO_PORT_ADDRESS 0xFFFF
//
// Handle for the CPU I/O 2 Protocol
@ -28,7 +28,7 @@ STATIC EFI_HANDLE mHandle = NULL;
//
// Lookup table for increment values based on transfer widths
//
STATIC CONST UINT8 mInStride[] = {
STATIC CONST UINT8 mInStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@ -46,7 +46,7 @@ STATIC CONST UINT8 mInStride[] = {
//
// Lookup table for increment values based on transfer widths
//
STATIC CONST UINT8 mOutStride[] = {
STATIC CONST UINT8 mOutStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@ -117,14 +117,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access,
// so treat Count as 1
//
if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
Count = 1;
}
//
// Check to see if Width is in the valid range for I/O Port operations
//
Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER;
}
@ -161,7 +161,6 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@ -241,9 +240,9 @@ CpuMemoryServiceRead (
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address);
@ -255,7 +254,6 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
}
}
return EFI_SUCCESS;
}
@ -323,9 +321,9 @@ CpuMemoryServiceWrite (
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@ -337,7 +335,6 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
}
}
return EFI_SUCCESS;
}
@ -407,9 +404,9 @@ CpuIoServiceRead (
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@ -493,9 +490,9 @@ CpuIoServiceWrite (
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@ -513,7 +510,7 @@ CpuIoServiceWrite (
//
// CPU I/O 2 Protocol instance
//
STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
@ -524,6 +521,7 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
}
};
/**
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
@ -541,13 +539,12 @@ ArmPciCpuIo2Initialize (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle,
&gEfiCpuIo2ProtocolGuid,
&mCpuIo2,
&gEfiCpuIo2ProtocolGuid, &mCpuIo2,
NULL
);
ASSERT_EFI_ERROR (Status);

View File

@ -38,7 +38,7 @@
UefiBootServicesTableLib
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
gArmTokenSpaceGuid.PcdPciIoTranslation
[Protocols]
gEfiCpuIo2ProtocolGuid ## PRODUCES

View File

@ -14,7 +14,7 @@
// Return values of BASE_DISCOVER_LIST_PROTOCOLS command.
typedef struct {
UINT32 NumProtocols;
UINT32 NumProtocols;
// Array of four protocols in each element
// Total elements = 1 + (NumProtocols-1)/4
@ -22,7 +22,7 @@ typedef struct {
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
UINT8 Protocols[1];
UINT8 Protocols[1];
} BASE_DISCOVER_LIST;
/** Initialize Base protocol and install protocol on a given handle.
@ -34,7 +34,7 @@ typedef struct {
**/
EFI_STATUS
ScmiBaseProtocolInit (
IN OUT EFI_HANDLE *Handle
IN OUT EFI_HANDLE* Handle
);
#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */

View File

@ -16,56 +16,57 @@
// Clock rate in two 32bit words.
typedef struct {
UINT32 Low;
UINT32 High;
UINT32 Low;
UINT32 High;
} CLOCK_RATE_DWORD;
// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12]
#define RATE_FORMAT_SHIFT 12
#define RATE_FORMAT_MASK 0x0001
#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
#define RATE_FORMAT_SHIFT 12
#define RATE_FORMAT_MASK 0x0001
#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
& RATE_FORMAT_MASK)
// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16]
#define NUM_REMAIN_RATES_SHIFT 16
#define NUM_REMAIN_RATES_SHIFT 16
#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT))
// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0]
#define NUM_RATES_MASK 0x0FFF
#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
#define NUM_RATES_MASK 0x0FFF
#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
// Return values for the CLOCK_DESCRIBER_RATE command.
typedef struct {
UINT32 NumRatesFlags;
UINT32 NumRatesFlags;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
CLOCK_RATE_DWORD Rates[1];
CLOCK_RATE_DWORD Rates[1];
} CLOCK_DESCRIBE_RATES;
#define CLOCK_SET_DEFAULT_FLAGS 0
#define CLOCK_SET_DEFAULT_FLAGS 0
// Message parameters for CLOCK_RATE_SET command.
typedef struct {
UINT32 Flags;
UINT32 ClockId;
CLOCK_RATE_DWORD Rate;
UINT32 Flags;
UINT32 ClockId;
CLOCK_RATE_DWORD Rate;
} CLOCK_RATE_SET_ATTRIBUTES;
// Message parameters for CLOCK_CONFIG_SET command.
typedef struct {
UINT32 ClockId;
UINT32 Attributes;
UINT32 ClockId;
UINT32 Attributes;
} CLOCK_CONFIG_SET_ATTRIBUTES;
// if ClockAttr Bit[0] is set then clock device is enabled.
#define CLOCK_ENABLE_MASK 0x1
#define CLOCK_ENABLE_MASK 0x1
#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1)
typedef struct {
UINT32 Attributes;
UINT8 ClockName[SCMI_MAX_STR_LEN];
UINT32 Attributes;
UINT8 ClockName[SCMI_MAX_STR_LEN];
} CLOCK_ATTRIBUTES;
#pragma pack()
@ -78,7 +79,7 @@ typedef struct {
**/
EFI_STATUS
ScmiClockProtocolInit (
IN EFI_HANDLE *Handle
IN EFI_HANDLE *Handle
);
#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */

View File

@ -15,23 +15,23 @@
#include <Protocol/ArmScmiPerformanceProtocol.h>
// Number of performance levels returned by a call to the SCP, Lvls Bits[11:0]
#define NUM_PERF_LEVELS_MASK 0x0FFF
#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
#define NUM_PERF_LEVELS_MASK 0x0FFF
#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
// Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16]
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
/** Return values for ScmiMessageIdPerformanceDescribeLevels command.
SCMI Spec section 4.5.2.5
**/
typedef struct {
UINT32 NumLevels;
UINT32 NumLevels;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
} PERF_DESCRIBE_LEVELS;
/** Initialize performance management protocol and install on a given Handle.
@ -43,7 +43,7 @@ typedef struct {
**/
EFI_STATUS
ScmiPerformanceProtocolInit (
IN EFI_HANDLE *Handle
IN EFI_HANDLE* Handle
);
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */

View File

@ -29,7 +29,7 @@
**/
EFI_STATUS
ScmiCommandGetPayload (
OUT UINT32 **Payload
OUT UINT32** Payload
)
{
EFI_STATUS Status;
@ -76,7 +76,7 @@ EFI_STATUS
ScmiCommandExecute (
IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength,
OUT UINT32 **ReturnValues OPTIONAL
OUT UINT32 **ReturnValues OPTIONAL
)
{
EFI_STATUS Status;
@ -121,12 +121,10 @@ ScmiCommandExecute (
return EFI_DEVICE_ERROR;
}
Response = (SCMI_MESSAGE_RESPONSE *)MtlGetChannelPayload (Channel);
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
if (Response->Status != ScmiSuccess) {
DEBUG ((
DEBUG_ERROR,
"SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
Command->ProtocolId,
Command->MessageId,
Response->Status
@ -165,7 +163,7 @@ ScmiProtocolDiscoveryCommon (
SCMI_COMMAND Command;
UINT32 PayloadLength;
PayloadLength = 0;
PayloadLength = 0;
Command.ProtocolId = ProtocolId;
Command.MessageId = MessageId;
@ -192,13 +190,13 @@ ScmiGetProtocolVersion (
OUT UINT32 *Version
)
{
EFI_STATUS Status;
UINT32 *ProtocolVersion;
EFI_STATUS Status;
UINT32 *ProtocolVersion;
Status = ScmiProtocolDiscoveryCommon (
ProtocolId,
ScmiMessageIdProtocolVersion,
(UINT32 **)&ProtocolVersion
(UINT32**)&ProtocolVersion
);
if (EFI_ERROR (Status)) {
return Status;

View File

@ -106,9 +106,9 @@ BaseDiscoverVendorDetails (
}
AsciiStrCpyS (
(CHAR8 *)VendorIdentifier,
(CHAR8*)VendorIdentifier,
SCMI_MAX_STR_LEN,
(CONST CHAR8 *)ReturnValues
(CONST CHAR8*)ReturnValues
);
return EFI_SUCCESS;
@ -256,6 +256,7 @@ BaseDiscoverListProtocols (
Skip = 0;
while (Skip < TotalProtocols) {
*MessageParams = Skip;
// Note PayloadLength is a IN/OUT parameter.
@ -264,7 +265,7 @@ BaseDiscoverListProtocols (
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&DiscoverList
(UINT32**)&DiscoverList
);
if (EFI_ERROR (Status)) {
return Status;
@ -281,7 +282,7 @@ BaseDiscoverListProtocols (
}
// Instance of the SCMI Base protocol.
STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
BaseGetVersion,
BaseGetTotalProtocols,
BaseDiscoverVendor,
@ -299,7 +300,7 @@ STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
**/
EFI_STATUS
ScmiBaseProtocolInit (
IN OUT EFI_HANDLE *Handle
IN OUT EFI_HANDLE* Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (

View File

@ -28,11 +28,11 @@
STATIC
UINT64
ConvertTo64Bit (
IN UINT32 Low,
IN UINT32 High
IN UINT32 Low,
IN UINT32 High
)
{
return (Low | ((UINT64)High << 32));
return (Low | ((UINT64)High << 32));
}
/** Return version of the clock management protocol supported by SCP firmware.
@ -74,7 +74,7 @@ ClockGetTotalClocks (
)
{
EFI_STATUS Status;
UINT32 *ReturnValues;
UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
if (EFI_ERROR (Status)) {
@ -108,12 +108,12 @@ ClockGetClockAttributes (
OUT CHAR8 *ClockAsciiName
)
{
EFI_STATUS Status;
EFI_STATUS Status;
UINT32 *MessageParams;
CLOCK_ATTRIBUTES *ClockAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
UINT32 *MessageParams;
CLOCK_ATTRIBUTES *ClockAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@ -130,19 +130,18 @@ ClockGetClockAttributes (
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&ClockAttributes
(UINT32**)&ClockAttributes
);
if (EFI_ERROR (Status)) {
return Status;
}
// TRUE if bit 0 of ClockAttributes->Attributes is set.
// TRUE if bit 0 of ClockAttributes->Attributes is set.
*Enabled = CLOCK_ENABLED (ClockAttributes->Attributes);
AsciiStrCpyS (
ClockAsciiName,
SCMI_MAX_STR_LEN,
(CONST CHAR8 *)ClockAttributes->ClockName
(CONST CHAR8*)ClockAttributes->ClockName
);
return EFI_SUCCESS;
@ -175,29 +174,29 @@ STATIC
EFI_STATUS
ClockDescribeRates (
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
OUT UINT32 *TotalRates,
IN OUT UINT32 *RateArraySize,
OUT SCMI_CLOCK_RATE *RateArray
)
{
EFI_STATUS Status;
EFI_STATUS Status;
UINT32 PayloadLength;
SCMI_COMMAND Cmd;
UINT32 *MessageParams;
CLOCK_DESCRIBE_RATES *DescribeRates;
CLOCK_RATE_DWORD *Rate;
UINT32 PayloadLength;
SCMI_COMMAND Cmd;
UINT32 *MessageParams;
CLOCK_DESCRIBE_RATES *DescribeRates;
CLOCK_RATE_DWORD *Rate;
UINT32 RequiredArraySize;
UINT32 RateIndex;
UINT32 RateNo;
UINT32 RateOffset;
UINT32 RequiredArraySize;
UINT32 RateIndex;
UINT32 RateNo;
UINT32 RateOffset;
*TotalRates = 0;
*TotalRates = 0;
RequiredArraySize = 0;
RateIndex = 0;
RateIndex = 0;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@ -207,19 +206,20 @@ ClockDescribeRates (
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockDescribeRates;
*MessageParams++ = ClockId;
*MessageParams++ = ClockId;
do {
*MessageParams = RateIndex;
// Set Payload length, note PayloadLength is a IN/OUT parameter.
PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
// Execute and wait for response on a SCMI channel.
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&DescribeRates
(UINT32**)&DescribeRates
);
if (EFI_ERROR (Status)) {
return Status;
@ -237,10 +237,10 @@ ClockDescribeRates (
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
if (*Format == ScmiClockRateFormatDiscrete) {
RequiredArraySize = (*TotalRates) * sizeof (UINT64);
RequiredArraySize = (*TotalRates) * sizeof (UINT64);
} else {
// We need to return triplet of 64 bit value for each rate
RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
// We need to return triplet of 64 bit value for each rate
RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
}
if (RequiredArraySize > (*RateArraySize)) {
@ -262,7 +262,7 @@ ClockDescribeRates (
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
// Linear clock rates from minimum to maximum in steps
// Minimum clock rate.
Rate = &DescribeRates->Rates[RateOffset++];
Rate = &DescribeRates->Rates[RateOffset++];
RateArray[RateIndex].ContinuousRate.Min =
ConvertTo64Bit (Rate->Low, Rate->High);
@ -304,13 +304,13 @@ ClockRateGet (
OUT UINT64 *Rate
)
{
EFI_STATUS Status;
EFI_STATUS Status;
UINT32 *MessageParams;
CLOCK_RATE_DWORD *ClockRate;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@ -318,10 +318,10 @@ ClockRateGet (
}
// Fill arguments for clock protocol command.
*MessageParams = ClockId;
*MessageParams = ClockId;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateGet;
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateGet;
PayloadLength = sizeof (ClockId);
@ -329,7 +329,7 @@ ClockRateGet (
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&ClockRate
(UINT32**)&ClockRate
);
if (EFI_ERROR (Status)) {
return Status;
@ -358,21 +358,21 @@ ClockRateSet (
IN UINT64 Rate
)
{
EFI_STATUS Status;
CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
EFI_STATUS Status;
CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
Status = ScmiCommandGetPayload ((UINT32 **)&ClockRateSetAttributes);
Status = ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes);
if (EFI_ERROR (Status)) {
return Status;
}
// Fill arguments for clock protocol command.
ClockRateSetAttributes->ClockId = ClockId;
ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
ClockRateSetAttributes->ClockId = ClockId;
ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateSet;
@ -402,17 +402,17 @@ ClockRateSet (
STATIC
EFI_STATUS
ClockEnable (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN BOOLEAN Enable
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN BOOLEAN Enable
)
{
EFI_STATUS Status;
CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
EFI_STATUS Status;
CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
SCMI_COMMAND Cmd;
UINT32 PayloadLength;
Status = ScmiCommandGetPayload ((UINT32 **)&ClockConfigSetAttributes);
Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes);
if (EFI_ERROR (Status)) {
return Status;
}
@ -437,17 +437,17 @@ ClockEnable (
}
// Instance of the SCMI clock management protocol.
STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
ClockGetVersion,
ClockGetTotalClocks,
ClockGetClockAttributes,
ClockDescribeRates,
ClockRateGet,
ClockRateSet
};
};
// Instance of the SCMI clock management protocol.
STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
(SCMI_CLOCK2_GET_VERSION)ClockGetVersion,
(SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks,
(SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes,
@ -456,7 +456,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
(SCMI_CLOCK2_RATE_SET)ClockRateSet,
SCMI_CLOCK2_PROTOCOL_VERSION,
ClockEnable
};
};
/** Initialize clock management protocol and install protocol on a given handle.
@ -466,7 +466,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
**/
EFI_STATUS
ScmiClockProtocolInit (
IN EFI_HANDLE *Handle
IN EFI_HANDLE* Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (

View File

@ -23,10 +23,10 @@
#include "ScmiDxe.h"
#include "ScmiPrivate.h"
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
{ ScmiProtocolIdBase, ScmiBaseProtocolInit },
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
{ ScmiProtocolIdBase, ScmiBaseProtocolInit },
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
{ ScmiProtocolIdClock, ScmiClockProtocolInit }
{ ScmiProtocolIdClock, ScmiClockProtocolInit }
};
/** ARM SCMI driver entry point function.
@ -47,8 +47,8 @@ STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
EFI_STATUS
EFIAPI
ArmScmiDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@ -72,7 +72,7 @@ ArmScmiDxeEntryPoint (
Status = gBS->LocateProtocol (
&gArmScmiBaseProtocolGuid,
NULL,
(VOID **)&BaseProtocol
(VOID**)&BaseProtocol
);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
@ -88,8 +88,7 @@ ArmScmiDxeEntryPoint (
// Accept any version between SCMI v1.0 and SCMI v2.0
if ((Version < BASE_PROTOCOL_VERSION_V1) ||
(Version > BASE_PROTOCOL_VERSION_V2))
{
(Version > BASE_PROTOCOL_VERSION_V2)) {
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@ -97,7 +96,7 @@ ArmScmiDxeEntryPoint (
// Apart from Base protocol, SCMI may implement various other protocols,
// query total protocols implemented by the SCP firmware.
NumProtocols = 0;
Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
return Status;
@ -110,7 +109,7 @@ ArmScmiDxeEntryPoint (
Status = gBS->AllocatePool (
EfiBootServicesData,
SupportedListSize,
(VOID **)&SupportedList
(VOID**)&SupportedList
);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
@ -131,8 +130,7 @@ ArmScmiDxeEntryPoint (
// Install supported protocol on ImageHandle.
for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols);
ProtocolIndex++)
{
ProtocolIndex++) {
for (Index = 0; Index < NumProtocols; Index++) {
if (Protocols[ProtocolIndex].Id == SupportedList[Index]) {
Status = Protocols[ProtocolIndex].InitFn (&ImageHandle);
@ -140,7 +138,6 @@ ArmScmiDxeEntryPoint (
ASSERT_EFI_ERROR (Status);
return Status;
}
break;
}
}

View File

@ -8,13 +8,12 @@
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
**/
#ifndef SCMI_DXE_H_
#define SCMI_DXE_H_
#include "ScmiPrivate.h"
#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
/** Pointer to protocol initialization function.
@ -30,8 +29,8 @@ EFI_STATUS
);
typedef struct {
SCMI_PROTOCOL_ID Id; // Protocol Id.
SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
SCMI_PROTOCOL_ID Id; // Protocol Id.
SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
} SCMI_PROTOCOL_ENTRY;
#endif /* SCMI_DXE_H_ */

View File

@ -51,12 +51,12 @@ PerformanceGetVersion (
STATIC
EFI_STATUS
PerformanceGetAttributes (
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
)
{
EFI_STATUS Status;
UINT32 *ReturnValues;
UINT32* ReturnValues;
Status = ScmiGetProtocolAttributes (
ScmiProtocolIdPerformance,
@ -90,7 +90,7 @@ STATIC
EFI_STATUS
PerformanceDomainAttributes (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
)
{
@ -160,21 +160,21 @@ PerformanceDescribeLevels (
EFI_STATUS Status;
UINT32 PayloadLength;
SCMI_COMMAND Cmd;
UINT32 *MessageParams;
UINT32* MessageParams;
UINT32 LevelIndex;
UINT32 RequiredSize;
UINT32 LevelNo;
UINT32 ReturnNumLevels;
UINT32 ReturnRemainNumLevels;
PERF_DESCRIBE_LEVELS *Levels;
PERF_DESCRIBE_LEVELS *Levels;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
return Status;
}
LevelIndex = 0;
LevelIndex = 0;
RequiredSize = 0;
*MessageParams++ = DomainId;
@ -183,6 +183,7 @@ PerformanceDescribeLevels (
Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
do {
*MessageParams = LevelIndex;
// Note, PayloadLength is an IN/OUT parameter.
@ -191,13 +192,13 @@ PerformanceDescribeLevels (
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&Levels
(UINT32**)&Levels
);
if (EFI_ERROR (Status)) {
return Status;
}
ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels);
if (RequiredSize == 0) {
@ -212,12 +213,13 @@ PerformanceDescribeLevels (
}
for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) {
CopyMem (
&LevelArray[LevelIndex++],
&Levels->PerfLevel[LevelNo],
sizeof (SCMI_PERFORMANCE_LEVEL)
);
CopyMem (
&LevelArray[LevelIndex++],
&Levels->PerfLevel[LevelNo],
sizeof (SCMI_PERFORMANCE_LEVEL)
);
}
} while (ReturnRemainNumLevels != 0);
*LevelArraySize = RequiredSize;
@ -237,9 +239,9 @@ PerformanceDescribeLevels (
**/
EFI_STATUS
PerformanceLimitsSet (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits
)
{
EFI_STATUS Status;
@ -283,9 +285,9 @@ PerformanceLimitsSet (
**/
EFI_STATUS
PerformanceLimitsGet (
SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits
SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits
)
{
EFI_STATUS Status;
@ -310,7 +312,7 @@ PerformanceLimitsGet (
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
(UINT32 **)&ReturnValues
(UINT32**)&ReturnValues
);
if (EFI_ERROR (Status)) {
return Status;
@ -334,9 +336,9 @@ PerformanceLimitsGet (
**/
EFI_STATUS
PerformanceLevelSet (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 Level
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 Level
)
{
EFI_STATUS Status;
@ -379,9 +381,9 @@ PerformanceLevelSet (
**/
EFI_STATUS
PerformanceLevelGet (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *Level
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *Level
)
{
EFI_STATUS Status;
@ -417,7 +419,7 @@ PerformanceLevelGet (
}
// Instance of the SCMI performance management protocol.
STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
PerformanceGetVersion,
PerformanceGetAttributes,
PerformanceDomainAttributes,
@ -437,7 +439,7 @@ STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
**/
EFI_STATUS
ScmiPerformanceProtocolInit (
IN EFI_HANDLE *Handle
IN EFI_HANDLE* Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (

View File

@ -8,7 +8,6 @@
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
**/
#ifndef SCMI_PRIVATE_H_
#define SCMI_PRIVATE_H_
@ -53,21 +52,21 @@ typedef enum {
// Not defined in SCMI specification but will help to identify a message.
typedef struct {
SCMI_PROTOCOL_ID ProtocolId;
UINT32 MessageId;
SCMI_PROTOCOL_ID ProtocolId;
UINT32 MessageId;
} SCMI_COMMAND;
#pragma pack(1)
// Response to a SCMI command.
typedef struct {
INT32 Status;
UINT32 ReturnValues[];
INT32 Status;
UINT32 ReturnValues[];
} SCMI_MESSAGE_RESPONSE;
// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10]
#define MESSAGE_TYPE_SHIFT 8
#define PROTOCOL_ID_SHIFT 10
#define MESSAGE_TYPE_SHIFT 8
#define PROTOCOL_ID_SHIFT 10
#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \
MsgType << MESSAGE_TYPE_SHIFT | \
ProtocolId << PROTOCOL_ID_SHIFT | \
@ -75,7 +74,7 @@ typedef struct {
)
// SCMI message header.
typedef struct {
UINT32 MessageHeader;
UINT32 MessageHeader;
} SCMI_MESSAGE_HEADER;
#pragma pack()
@ -90,7 +89,7 @@ typedef struct {
**/
EFI_STATUS
ScmiCommandGetPayload (
OUT UINT32 **Payload
OUT UINT32** Payload
);
/** Execute a SCMI command and receive a response.
@ -116,7 +115,7 @@ EFI_STATUS
ScmiCommandExecute (
IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength,
OUT UINT32 **ReturnValues OPTIONAL
OUT UINT32 **ReturnValues OPTIONAL
);
/** Return protocol version from SCP for a given protocol ID.

View File

@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include "CpuDxe.h"
#define INVALID_ENTRY ((UINT32)~0)
#define INVALID_ENTRY ((UINT32)~0)
#define MIN_T0SZ 16
#define BITS_PER_LEVEL 9
@ -21,52 +21,49 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
STATIC
VOID
GetRootTranslationTableInfo (
IN UINTN T0SZ,
OUT UINTN *RootTableLevel,
OUT UINTN *RootTableEntryCount
IN UINTN T0SZ,
OUT UINTN *RootTableLevel,
OUT UINTN *RootTableEntryCount
)
{
*RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
*RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
*RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
*RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
}
STATIC
UINT64
PageAttributeToGcdAttribute (
IN UINT64 PageAttributes
IN UINT64 PageAttributes
)
{
UINT64 GcdAttributes;
switch (PageAttributes & TT_ATTR_INDX_MASK) {
case TT_ATTR_INDX_DEVICE_MEMORY:
GcdAttributes = EFI_MEMORY_UC;
break;
case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
GcdAttributes = EFI_MEMORY_WC;
break;
case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
GcdAttributes = EFI_MEMORY_WT;
break;
case TT_ATTR_INDX_MEMORY_WRITE_BACK:
GcdAttributes = EFI_MEMORY_WB;
break;
default:
DEBUG ((
DEBUG_ERROR,
"PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
PageAttributes
));
ASSERT (0);
// The Global Coherency Domain (GCD) value is defined as a bit set.
// Returning 0 means no attribute has been set.
GcdAttributes = 0;
case TT_ATTR_INDX_DEVICE_MEMORY:
GcdAttributes = EFI_MEMORY_UC;
break;
case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
GcdAttributes = EFI_MEMORY_WC;
break;
case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
GcdAttributes = EFI_MEMORY_WT;
break;
case TT_ATTR_INDX_MEMORY_WRITE_BACK:
GcdAttributes = EFI_MEMORY_WB;
break;
default:
DEBUG ((DEBUG_ERROR,
"PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
PageAttributes));
ASSERT (0);
// The Global Coherency Domain (GCD) value is defined as a bit set.
// Returning 0 means no attribute has been set.
GcdAttributes = 0;
}
// Determine protection attributes
if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||
((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO))
{
((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
// Read only cases map to write-protect
GcdAttributes |= EFI_MEMORY_RO;
}
@ -83,19 +80,19 @@ STATIC
UINT64
GetFirstPageAttribute (
IN UINT64 *FirstLevelTableAddress,
IN UINTN TableLevel
IN UINTN TableLevel
)
{
UINT64 FirstEntry;
UINT64 FirstEntry;
// Get the first entry of the table
FirstEntry = *FirstLevelTableAddress;
if ((TableLevel != 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
// Only valid for Levels 0, 1 and 2
// Get the attribute of the subsequent table
return GetFirstPageAttribute ((UINT64 *)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
} else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) ||
((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
{
@ -108,25 +105,25 @@ GetFirstPageAttribute (
STATIC
UINT64
GetNextEntryAttribute (
IN UINT64 *TableAddress,
IN UINT64 *TableAddress,
IN UINTN EntryCount,
IN UINTN TableLevel,
IN UINT64 BaseAddress,
IN OUT UINT32 *PrevEntryAttribute,
IN OUT UINT64 *StartGcdRegion
IN OUT UINT32 *PrevEntryAttribute,
IN OUT UINT64 *StartGcdRegion
)
{
UINTN Index;
UINT64 Entry;
UINT32 EntryAttribute;
UINT32 EntryType;
EFI_STATUS Status;
UINTN NumberOfDescriptors;
UINTN Index;
UINT64 Entry;
UINT32 EntryAttribute;
UINT32 EntryType;
EFI_STATUS Status;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
// Get the memory space map from GCD
MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
// We cannot get more than 3-level page table
@ -135,28 +132,24 @@ GetNextEntryAttribute (
// While the top level table might not contain TT_ENTRY_COUNT entries;
// the subsequent ones should be filled up
for (Index = 0; Index < EntryCount; Index++) {
Entry = TableAddress[Index];
EntryType = Entry & TT_TYPE_MASK;
Entry = TableAddress[Index];
EntryType = Entry & TT_TYPE_MASK;
EntryAttribute = Entry & TT_ATTR_INDX_MASK;
// If Entry is a Table Descriptor type entry then go through the sub-level table
if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||
((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
{
((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) {
if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {
if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
NumberOfDescriptors,
*StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute)
);
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
*StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute));
}
// Start of the new region
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
*PrevEntryAttribute = EntryAttribute;
} else {
continue;
@ -166,27 +159,20 @@ GetNextEntryAttribute (
ASSERT (TableLevel < 3);
// Increase the level number and scan the sub-level table
GetNextEntryAttribute (
(UINT64 *)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
TT_ENTRY_COUNT,
TableLevel + 1,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))),
PrevEntryAttribute,
StartGcdRegion
);
GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
TT_ENTRY_COUNT, TableLevel + 1,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))),
PrevEntryAttribute, StartGcdRegion);
} else {
if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
NumberOfDescriptors,
*StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute)
);
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
*StartGcdRegion,
(BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
PageAttributeToGcdAttribute (*PrevEntryAttribute));
// Start of the new region
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
*PrevEntryAttribute = INVALID_ENTRY;
}
}
@ -194,25 +180,25 @@ GetNextEntryAttribute (
FreePool (MemorySpaceMap);
return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL (TableLevel));
return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel));
}
EFI_STATUS
SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
)
{
EFI_STATUS Status;
UINT32 PageAttribute;
UINT64 *FirstLevelTableAddress;
UINTN TableLevel;
UINTN TableCount;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
UINTN Tcr;
UINTN T0SZ;
UINT64 BaseAddressGcdRegion;
UINT64 EndAddressGcdRegion;
EFI_STATUS Status;
UINT32 PageAttribute;
UINT64 *FirstLevelTableAddress;
UINTN TableLevel;
UINTN TableCount;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
UINTN Tcr;
UINTN T0SZ;
UINT64 BaseAddressGcdRegion;
UINT64 EndAddressGcdRegion;
// This code assumes MMU is enabled and filed with section translations
ASSERT (ArmMmuEnabled ());
@ -221,7 +207,7 @@ SyncCacheConfig (
// Get the memory space map from GCD
//
MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
@ -231,7 +217,7 @@ SyncCacheConfig (
// with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
// Obtain page table base
FirstLevelTableAddress = (UINT64 *)(ArmGetTTBR0BaseAddress ());
FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ());
// Get Translation Control Register value
Tcr = ArmGetTCR ();
@ -246,24 +232,17 @@ SyncCacheConfig (
// We scan from the start of the memory map (ie: at the address 0x0)
BaseAddressGcdRegion = 0x0;
EndAddressGcdRegion = GetNextEntryAttribute (
FirstLevelTableAddress,
TableCount,
TableLevel,
BaseAddressGcdRegion,
&PageAttribute,
&BaseAddressGcdRegion
);
EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress,
TableCount, TableLevel,
BaseAddressGcdRegion,
&PageAttribute, &BaseAddressGcdRegion);
// Update GCD with the last region if valid
if (PageAttribute != INVALID_ENTRY) {
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
NumberOfDescriptors,
BaseAddressGcdRegion,
EndAddressGcdRegion - BaseAddressGcdRegion,
PageAttributeToGcdAttribute (PageAttribute)
);
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
BaseAddressGcdRegion,
EndAddressGcdRegion - BaseAddressGcdRegion,
PageAttributeToGcdAttribute (PageAttribute));
}
FreePool (MemorySpaceMap);
@ -273,31 +252,30 @@ SyncCacheConfig (
UINT64
EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes
IN UINT64 EfiAttributes
)
{
UINT64 ArmAttributes;
UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC:
if (ArmReadCurrentEL () == AARCH64_EL2) {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
} else {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
}
break;
case EFI_MEMORY_WC:
ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
break;
case EFI_MEMORY_WT:
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
break;
case EFI_MEMORY_WB:
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
break;
default:
ArmAttributes = TT_ATTR_INDX_MASK;
case EFI_MEMORY_UC:
if (ArmReadCurrentEL () == AARCH64_EL2) {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
} else {
ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
}
break;
case EFI_MEMORY_WC:
ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
break;
case EFI_MEMORY_WT:
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
break;
case EFI_MEMORY_WB:
ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
break;
default:
ArmAttributes = TT_ATTR_INDX_MASK;
}
// Set the access flag to match the block attributes
@ -305,7 +283,7 @@ EfiAttributeToArmAttribute (
// Determine protection attributes
if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
ArmAttributes |= TT_AP_NO_RO;
ArmAttributes |= TT_AP_RO_RO;
}
// Process eXecute Never attribute
@ -320,19 +298,19 @@ EfiAttributeToArmAttribute (
// And then the function will identify the size of the region that has the same page table attribute.
EFI_STATUS
GetMemoryRegionRec (
IN UINT64 *TranslationTable,
IN UINTN TableLevel,
IN UINT64 *LastBlockEntry,
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
IN UINT64 *TranslationTable,
IN UINTN TableLevel,
IN UINT64 *LastBlockEntry,
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
)
{
EFI_STATUS Status;
UINT64 *NextTranslationTable;
UINT64 *BlockEntry;
UINT64 BlockEntryType;
UINT64 EntryType;
EFI_STATUS Status;
UINT64 *NextTranslationTable;
UINT64 *BlockEntry;
UINT64 BlockEntryType;
UINT64 EntryType;
if (TableLevel != 3) {
BlockEntryType = TT_TYPE_BLOCK_ENTRY;
@ -341,25 +319,22 @@ GetMemoryRegionRec (
}
// Find the block entry linked to the Base Address
BlockEntry = (UINT64 *)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
EntryType = *BlockEntry & TT_TYPE_MASK;
BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
EntryType = *BlockEntry & TT_TYPE_MASK;
if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {
NextTranslationTable = (UINT64 *)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
// The entry is a page table, so we go to the next level
Status = GetMemoryRegionRec (
NextTranslationTable, // Address of the next level page table
TableLevel + 1, // Next Page Table level
(UINTN *)TT_LAST_BLOCK_ADDRESS (NextTranslationTable, TT_ENTRY_COUNT),
BaseAddress,
RegionLength,
RegionAttributes
);
NextTranslationTable, // Address of the next level page table
TableLevel + 1, // Next Page Table level
(UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT),
BaseAddress, RegionLength, RegionAttributes);
// In case of 'Success', it means the end of the block region has been found into the upper
// level translation table
if (!EFI_ERROR (Status)) {
if (!EFI_ERROR(Status)) {
return EFI_SUCCESS;
}
@ -368,7 +343,7 @@ GetMemoryRegionRec (
} else if (EntryType == BlockEntryType) {
// We have found the BlockEntry attached to the address. We save its start address (the start
// address might be before the 'BaseAddress') and attributes
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL (TableLevel) - 1);
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);
*RegionLength = 0;
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;
} else {
@ -378,12 +353,11 @@ GetMemoryRegionRec (
while (BlockEntry <= LastBlockEntry) {
if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) {
*RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL (TableLevel);
*RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel);
} else {
// In case we have found the end of the region we return success
return EFI_SUCCESS;
}
BlockEntry++;
}
@ -395,13 +369,13 @@ GetMemoryRegionRec (
EFI_STATUS
GetMemoryRegion (
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
)
{
EFI_STATUS Status;
UINT64 *TranslationTable;
UINT64 *TranslationTable;
UINTN TableLevel;
UINTN EntryCount;
UINTN T0SZ;
@ -414,14 +388,9 @@ GetMemoryRegion (
// Get the Table info from T0SZ
GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount);
Status = GetMemoryRegionRec (
TranslationTable,
TableLevel,
(UINTN *)TT_LAST_BLOCK_ADDRESS (TranslationTable, EntryCount),
BaseAddress,
RegionLength,
RegionAttributes
);
Status = GetMemoryRegionRec (TranslationTable, TableLevel,
(UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount),
BaseAddress, RegionLength, RegionAttributes);
// If the region continues up to the end of the root table then GetMemoryRegionRec()
// will return EFI_NOT_FOUND

View File

@ -22,7 +22,7 @@ SectionToGcdAttributes (
*GcdAttributes = 0;
// determine cacheability attributes
switch (SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC;
break;
@ -49,9 +49,9 @@ SectionToGcdAttributes (
}
// determine protection attributes
switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
// *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
//*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break;
case TT_DESCRIPTOR_SECTION_AP_RW_NO:
@ -86,7 +86,7 @@ PageToGcdAttributes (
*GcdAttributes = 0;
// determine cacheability attributes
switch (PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC;
break;
@ -113,9 +113,9 @@ PageToGcdAttributes (
}
// determine protection attributes
switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
// *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
//*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break;
case TT_DESCRIPTOR_PAGE_AP_RW_NO:
@ -143,43 +143,43 @@ PageToGcdAttributes (
EFI_STATUS
SyncCacheConfigPage (
IN UINT32 SectionIndex,
IN UINT32 FirstLevelDescriptor,
IN UINTN NumberOfDescriptors,
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
IN OUT UINT64 *NextRegionLength,
IN OUT UINT32 *NextSectionAttributes
IN UINT32 SectionIndex,
IN UINT32 FirstLevelDescriptor,
IN UINTN NumberOfDescriptors,
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
IN OUT UINT64 *NextRegionLength,
IN OUT UINT32 *NextSectionAttributes
)
{
EFI_STATUS Status;
UINT32 i;
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
UINT32 NextPageAttributes;
UINT32 PageAttributes;
UINT32 BaseAddress;
UINT64 GcdAttributes;
EFI_STATUS Status;
UINT32 i;
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
UINT32 NextPageAttributes;
UINT32 PageAttributes;
UINT32 BaseAddress;
UINT64 GcdAttributes;
// Get the Base Address from FirstLevelDescriptor;
BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
// Convert SectionAttributes into PageAttributes
NextPageAttributes =
TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);
TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |
TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);
// obtain page table base
SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
// extract attributes (cacheability and permissions)
PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
if (NextPageAttributes == 0) {
// start on a new region
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes;
} else if (PageAttributes != NextPageAttributes) {
// Convert Section Attributes into GCD Attributes
@ -190,8 +190,8 @@ SyncCacheConfigPage (
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
// start on a new region
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes;
}
} else if (NextPageAttributes != 0) {
@ -202,37 +202,37 @@ SyncCacheConfigPage (
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
*NextRegionLength = 0;
*NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = 0;
}
*NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
}
// Convert back PageAttributes into SectionAttributes
*NextSectionAttributes =
TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);
TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);
return EFI_SUCCESS;
}
EFI_STATUS
SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
)
{
EFI_STATUS Status;
UINT32 i;
EFI_PHYSICAL_ADDRESS NextRegionBase;
UINT64 NextRegionLength;
UINT32 NextSectionAttributes;
UINT32 SectionAttributes;
UINT64 GcdAttributes;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
EFI_STATUS Status;
UINT32 i;
EFI_PHYSICAL_ADDRESS NextRegionBase;
UINT64 NextRegionLength;
UINT32 NextSectionAttributes;
UINT32 SectionAttributes;
UINT64 GcdAttributes;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));
@ -243,9 +243,10 @@ SyncCacheConfig (
// Get the memory space map from GCD
//
MemorySpaceMap = NULL;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
// GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
@ -260,15 +261,15 @@ SyncCacheConfig (
// iterate through each 1MB descriptor
NextRegionBase = NextRegionLength = 0;
for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// extract attributes (cacheability and permissions)
SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
if (NextSectionAttributes == 0) {
// start on a new region
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes;
} else if (SectionAttributes != NextSectionAttributes) {
// Convert Section Attributes into GCD Attributes
@ -279,27 +280,21 @@ SyncCacheConfig (
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
// start on a new region
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes;
}
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
} else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (FirstLevelTable[i])) {
} else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {
// In this case any bits set in the 'NextSectionAttributes' are garbage and were set from
// bits that are actually part of the pagetable address. We clear it out to zero so that
// the SyncCacheConfigPage will use the page attributes instead of trying to convert the
// section attributes into page attributes
NextSectionAttributes = 0;
Status = SyncCacheConfigPage (
i,
FirstLevelTable[i],
NumberOfDescriptors,
MemorySpaceMap,
&NextRegionBase,
&NextRegionLength,
&NextSectionAttributes
);
Status = SyncCacheConfigPage (
i,FirstLevelTable[i],
NumberOfDescriptors, MemorySpaceMap,
&NextRegionBase,&NextRegionLength,&NextSectionAttributes);
ASSERT_EFI_ERROR (Status);
} else {
// We do not support yet 16MB sections
@ -314,11 +309,10 @@ SyncCacheConfig (
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextRegionLength = 0;
NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = 0;
}
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
}
} // section entry loop
@ -339,10 +333,10 @@ SyncCacheConfig (
UINT64
EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes
IN UINT64 EfiAttributes
)
{
UINT64 ArmAttributes;
UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC:
@ -388,15 +382,15 @@ EfiAttributeToArmAttribute (
EFI_STATUS
GetMemoryRegionPage (
IN UINT32 *PageTable,
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
IN UINT32 *PageTable,
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
)
{
UINT32 PageAttributes;
UINT32 TableIndex;
UINT32 PageDescriptor;
UINT32 PageAttributes;
UINT32 TableIndex;
UINT32 PageDescriptor;
// Convert the section attributes into page attributes
PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0);
@ -406,7 +400,7 @@ GetMemoryRegionPage (
ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT);
// Go through the page table to find the end of the section
for ( ; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
// Get the section at the given index
PageDescriptor = PageTable[TableIndex];
@ -422,7 +416,7 @@ GetMemoryRegionPage (
}
} else {
// We do not support Large Page yet. We return EFI_SUCCESS that means end of the region.
ASSERT (0);
ASSERT(0);
return EFI_SUCCESS;
}
}
@ -432,9 +426,9 @@ GetMemoryRegionPage (
EFI_STATUS
GetMemoryRegion (
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
)
{
EFI_STATUS Status;
@ -442,8 +436,8 @@ GetMemoryRegion (
UINT32 PageAttributes;
UINT32 PageTableIndex;
UINT32 SectionDescriptor;
ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINT32 *PageTable;
ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
UINT32 *PageTable;
// Initialize the arguments
*RegionLength = 0;
@ -465,32 +459,32 @@ GetMemoryRegion (
if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
{
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
*RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK;
} else {
// Otherwise, we round it to the page boundary
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK;
// Get the attribute at the page table level (Level 2)
PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Calculate index into first level translation table for start of modification
PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
*RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
}
for ( ; TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
// Get the section at the given index
SectionDescriptor = FirstLevelTable[TableIndex];
// If the entry is a level-2 page table then we scan it to find the end of the region
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) {
// Extract the page table location from the descriptor
PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Scan the page table to find the end of the region.
Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes);
@ -500,8 +494,7 @@ GetMemoryRegion (
break;
}
} else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
{
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) {
if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) {
// If the attributes of the section differ from the one targeted then we exit the loop
break;

View File

@ -11,7 +11,7 @@
#include <Guid/IdleLoopEvent.h>
BOOLEAN mIsFlushingGCD;
BOOLEAN mIsFlushingGCD;
/**
This function flushes the range of addresses from Start to Start+Length
@ -43,12 +43,13 @@ BOOLEAN mIsFlushingGCD;
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType
)
{
switch (FlushType) {
case EfiCpuFlushTypeWriteBack:
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
@ -66,6 +67,7 @@ CpuFlushCpuDataCache (
return EFI_SUCCESS;
}
/**
This function enables interrupt processing by the processor.
@ -78,7 +80,7 @@ CpuFlushCpuDataCache (
EFI_STATUS
EFIAPI
CpuEnableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This
IN EFI_CPU_ARCH_PROTOCOL *This
)
{
ArmEnableInterrupts ();
@ -86,6 +88,7 @@ CpuEnableInterrupt (
return EFI_SUCCESS;
}
/**
This function disables interrupt processing by the processor.
@ -98,7 +101,7 @@ CpuEnableInterrupt (
EFI_STATUS
EFIAPI
CpuDisableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This
IN EFI_CPU_ARCH_PROTOCOL *This
)
{
ArmDisableInterrupts ();
@ -106,6 +109,7 @@ CpuDisableInterrupt (
return EFI_SUCCESS;
}
/**
This function retrieves the processor's current interrupt state a returns it in
State. If interrupts are currently enabled, then TRUE is returned. If interrupts
@ -122,18 +126,19 @@ CpuDisableInterrupt (
EFI_STATUS
EFIAPI
CpuGetInterruptState (
IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State
IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State
)
{
if (State == NULL) {
return EFI_INVALID_PARAMETER;
}
*State = ArmGetInterruptState ();
*State = ArmGetInterruptState();
return EFI_SUCCESS;
}
/**
This function generates an INIT on the processor. If this function succeeds, then the
processor will be reset, and control will not be returned to the caller. If InitType is
@ -153,8 +158,8 @@ CpuGetInterruptState (
EFI_STATUS
EFIAPI
CpuInit (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType
)
{
return EFI_UNSUPPORTED;
@ -163,9 +168,9 @@ CpuInit (
EFI_STATUS
EFIAPI
CpuRegisterInterruptHandler (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterInterruptHandler (InterruptType, InterruptHandler);
@ -174,10 +179,10 @@ CpuRegisterInterruptHandler (
EFI_STATUS
EFIAPI
CpuGetTimerValue (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex,
OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL
IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex,
OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL
)
{
return EFI_UNSUPPORTED;
@ -194,8 +199,8 @@ CpuGetTimerValue (
VOID
EFIAPI
IdleLoopEventCallback (
IN EFI_EVENT Event,
IN VOID *Context
IN EFI_EVENT Event,
IN VOID *Context
)
{
CpuSleep ();
@ -204,8 +209,8 @@ IdleLoopEventCallback (
//
// Globals used to initialize the protocol
//
EFI_HANDLE mCpuHandle = NULL;
EFI_CPU_ARCH_PROTOCOL mCpu = {
EFI_HANDLE mCpuHandle = NULL;
EFI_CPU_ARCH_PROTOCOL mCpu = {
CpuFlushCpuDataCache,
CpuEnableInterrupt,
CpuDisableInterrupt,
@ -221,7 +226,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = {
STATIC
VOID
InitializeDma (
IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
)
{
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
@ -229,23 +234,22 @@ InitializeDma (
EFI_STATUS
CpuDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_EVENT IdleLoopEvent;
EFI_EVENT IdleLoopEvent;
InitializeExceptions (&mCpu);
InitializeDma (&mCpu);
Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle,
&gEfiCpuArchProtocolGuid,
&mCpu,
NULL
);
&mCpuHandle,
&gEfiCpuArchProtocolGuid, &mCpu,
NULL
);
//
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
@ -258,8 +262,8 @@ CpuDxeInitialize (
// If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
if (ArmIsMpCore ()) {
PublishArmProcessorTable ();
if (ArmIsMpCore()) {
PublishArmProcessorTable();
}
//

View File

@ -31,7 +31,7 @@
#include <Protocol/DebugSupport.h>
#include <Protocol/LoadedImage.h>
extern BOOLEAN mIsFlushingGCD;
extern BOOLEAN mIsFlushingGCD;
/**
This function registers and enables the handler specified by InterruptHandler for a processor
@ -55,10 +55,11 @@ extern BOOLEAN mIsFlushingGCD;
**/
EFI_STATUS
RegisterInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
/**
This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
@ -81,27 +82,28 @@ RegisterInterruptHandler (
**/
EFI_STATUS
RegisterDebuggerInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
);
EFI_STATUS
InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu
IN EFI_CPU_ARCH_PROTOCOL *Cpu
);
EFI_STATUS
SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
);
/**
@ -115,30 +117,30 @@ SyncCacheConfig (
**/
VOID
EFIAPI
PublishArmProcessorTable (
PublishArmProcessorTable(
VOID
);
// The ARM Attributes might be defined on 64-bit (case of the long format description table)
UINT64
EfiAttributeToArmAttribute (
IN UINT64 EfiAttributes
IN UINT64 EfiAttributes
);
EFI_STATUS
GetMemoryRegion (
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
IN OUT UINTN *BaseAddress,
OUT UINTN *RegionLength,
OUT UINTN *RegionAttributes
);
EFI_STATUS
SetGcdMemorySpaceAttributes (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
);
#endif // CPU_DXE_H_

View File

@ -29,36 +29,33 @@
**/
EFI_STATUS
SearchGcdMemorySpaces (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
OUT UINTN *StartIndex,
OUT UINTN *EndIndex
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
OUT UINTN *StartIndex,
OUT UINTN *EndIndex
)
{
UINTN Index;
UINTN Index;
*StartIndex = 0;
*EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
{
(BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
*StartIndex = Index;
}
if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) &&
((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
{
((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
*EndIndex = Index;
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
/**
Sets the attributes for a specified range in Gcd Memory Space Map.
@ -77,11 +74,11 @@ SearchGcdMemorySpaces (
**/
EFI_STATUS
SetGcdMemorySpaceAttributes (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
)
{
EFI_STATUS Status;
@ -91,21 +88,14 @@ SetGcdMemorySpaceAttributes (
EFI_PHYSICAL_ADDRESS RegionStart;
UINT64 RegionLength;
DEBUG ((
DEBUG_GCD,
"SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
BaseAddress,
BaseAddress + Length,
Attributes
));
DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
BaseAddress, BaseAddress + Length, Attributes));
// We do not support a smaller granularity than 4KB on ARM Architecture
if ((Length & EFI_PAGE_MASK) != 0) {
DEBUG ((
DEBUG_WARN,
"Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
Length
));
DEBUG ((DEBUG_WARN,
"Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
Length));
}
//
@ -130,7 +120,6 @@ SetGcdMemorySpaceAttributes (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue;
}
//
// Calculate the start and end address of the overlapping range
//
@ -139,13 +128,11 @@ SetGcdMemorySpaceAttributes (
} else {
RegionStart = MemorySpaceMap[Index].BaseAddress;
}
if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) {
RegionLength = BaseAddress + Length - RegionStart;
} else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
}
//
// Set memory attributes according to MTRR attribute and the original attribute of descriptor
//
@ -183,10 +170,10 @@ SetGcdMemorySpaceAttributes (
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 EfiAttributes
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 EfiAttributes
)
{
EFI_STATUS Status;
@ -210,7 +197,7 @@ CpuSetMemoryAttributes (
// Get the region starting from 'BaseAddress' and its 'Attribute'
RegionBaseAddress = BaseAddress;
Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
// Data & Instruction Caches are flushed when we set new memory attributes.
// So, we only set the attributes if the new region is different.

View File

@ -14,7 +14,7 @@
#include <Guid/ArmMpCoreInfo.h>
ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
{
EFI_ARM_PROCESSOR_TABLE_SIGNATURE,
0,
@ -26,7 +26,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,
{ 0 },
0
}, // ARM Processor table header
}, //ARM Processor table header
0, // Number of entries in ARM processor Table
NULL // ARM Processor Table
};
@ -45,48 +45,47 @@ PublishArmProcessorTable (
VOID
)
{
EFI_PEI_HOB_POINTERS Hob;
EFI_PEI_HOB_POINTERS Hob;
Hob.Raw = GetHobList ();
// Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
for ( ; !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {
for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
// Check for Correct HOB type
if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
// Check for correct GUID type
if (CompareGuid (&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
ARM_PROCESSOR_TABLE *ArmProcessorTable;
EFI_STATUS Status;
if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
ARM_PROCESSOR_TABLE *ArmProcessorTable;
EFI_STATUS Status;
// Allocate Runtime memory for ARM processor table
ArmProcessorTable = (ARM_PROCESSOR_TABLE *)AllocateRuntimePool (sizeof (ARM_PROCESSOR_TABLE));
ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));
// Check if the memory allocation is successful or not
ASSERT (NULL != ArmProcessorTable);
ASSERT(NULL != ArmProcessorTable);
// Set ARM processor table to default values
CopyMem (ArmProcessorTable, &mArmProcessorTableTemplate, sizeof (ARM_PROCESSOR_TABLE));
CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE));
// Fill in Length fields of ARM processor table
ArmProcessorTable->Header.Length = sizeof (ARM_PROCESSOR_TABLE);
ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE (Hob);
ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE);
ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob);
// Fill in Identifier(ARM processor table GUID)
ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;
// Set Number of ARM core entries in the Table
ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE (Hob)/sizeof (ARM_CORE_INFO);
ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
// Allocate runtime memory for ARM processor Table entries
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO *)AllocateRuntimePool (
ArmProcessorTable->NumberOfEntries * sizeof (ARM_CORE_INFO)
);
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (
ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));
// Check if the memory allocation is successful or not
ASSERT (NULL != ArmProcessorTable->ArmCpus);
ASSERT(NULL != ArmProcessorTable->ArmCpus);
// Copy ARM Processor Table data from HOB list to newly allocated memory
CopyMem (ArmProcessorTable->ArmCpus, GET_GUID_HOB_DATA (Hob), ArmProcessorTable->Header.DataLen);
CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen);
// Install the ARM Processor table into EFI system configuration table
Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);

View File

@ -13,23 +13,23 @@
EFI_STATUS
InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu
IN EFI_CPU_ARCH_PROTOCOL *Cpu
)
{
EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
BOOLEAN IrqEnabled;
BOOLEAN FiqEnabled;
EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
BOOLEAN IrqEnabled;
BOOLEAN FiqEnabled;
VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL;
Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
VectorInfo = VectorInfoList;
}
// initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
InitializeCpuExceptionHandlers (VectorInfo);
InitializeCpuExceptionHandlers(VectorInfo);
Status = EFI_SUCCESS;
@ -64,7 +64,7 @@ InitializeExceptions (
//
DEBUG_CODE (
ArmEnableAsynchronousAbort ();
);
);
return Status;
}
@ -90,11 +90,11 @@ previously installed.
**/
EFI_STATUS
RegisterInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
RegisterInterruptHandler(
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
// pass down to CpuExceptionHandlerLib
return (EFI_STATUS)RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
}

View File

@ -16,6 +16,8 @@ Abstract:
**/
//
// The package level header files this module uses
//
@ -56,10 +58,10 @@ InitializeCpuPeim (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
EFI_STATUS Status;
ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
UINTN ArmCoreCount;
ARM_CORE_INFO *ArmCoreInfoTable;
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
@ -68,12 +70,12 @@ InitializeCpuPeim (
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID **)&ArmMpCoreInfoPpi);
if (!EFI_ERROR (Status)) {
Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);
if (!EFI_ERROR(Status)) {
// Build the MP Core Info Table
ArmCoreCount = 0;
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
// Build MPCore Info HOB
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
}

View File

@ -5,21 +5,20 @@
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef GENERIC_WATCHDOG_H_
#define GENERIC_WATCHDOG_H_
// Refresh Frame:
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
// Control Frame:
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
// Values of bit 0 of the Control/Status Register
#define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0
#define GENERIC_WDOG_ENABLED 1
#define GENERIC_WDOG_DISABLED 0
#endif // GENERIC_WATCHDOG_H_
#endif // GENERIC_WATCHDOG_H_

View File

@ -25,18 +25,18 @@
/* The number of 100ns periods (the unit of time passed to these functions)
in a second */
#define TIME_UNITS_PER_SECOND 10000000
#define TIME_UNITS_PER_SECOND 10000000
// Tick frequency of the generic timer basis of the generic watchdog.
STATIC UINTN mTimerFrequencyHz = 0;
STATIC UINTN mTimerFrequencyHz = 0;
/* In cases where the compare register was set manually, information about
how long the watchdog was asked to wait cannot be retrieved from hardware.
It is therefore stored here. 0 means the timer is not running. */
STATIC UINT64 mNumTimerTicks = 0;
STATIC UINT64 mNumTimerTicks = 0;
STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
STATIC
VOID
@ -97,12 +97,12 @@ STATIC
VOID
EFIAPI
WatchdogInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
UINT64 TimerPeriod;
STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";
UINT64 TimerPeriod;
WatchdogDisable ();
@ -119,12 +119,8 @@ WatchdogInterruptHandler (
mWatchdogNotify (TimerPeriod + 1);
}
gRT->ResetSystem (
EfiResetCold,
EFI_TIMEOUT,
StrSize (ResetString),
(CHAR16 *)ResetString
);
gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString),
(CHAR16 *)ResetString);
// If we got here then the reset didn't work
ASSERT (FALSE);
@ -158,15 +154,15 @@ STATIC
EFI_STATUS
EFIAPI
WatchdogRegisterHandler (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
)
{
if ((mWatchdogNotify == NULL) && (NotifyFunction == NULL)) {
if (mWatchdogNotify == NULL && NotifyFunction == NULL) {
return EFI_INVALID_PARAMETER;
}
if ((mWatchdogNotify != NULL) && (NotifyFunction != NULL)) {
if (mWatchdogNotify != NULL && NotifyFunction != NULL) {
return EFI_ALREADY_STARTED;
}
@ -192,11 +188,11 @@ STATIC
EFI_STATUS
EFIAPI
WatchdogSetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod // In 100ns units
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod // In 100ns units
)
{
UINTN SystemCount;
UINTN SystemCount;
// if TimerPeriod is 0, this is a request to stop the watchdog.
if (TimerPeriod == 0) {
@ -248,8 +244,8 @@ STATIC
EFI_STATUS
EFIAPI
WatchdogGetTimerPeriod (
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
@ -293,29 +289,26 @@ WatchdogGetTimerPeriod (
Retrieves the period of the timer interrupt in 100ns units.
**/
STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
WatchdogRegisterHandler,
WatchdogSetTimerPeriod,
WatchdogGetTimerPeriod
};
STATIC EFI_EVENT mEfiExitBootServicesEvent;
STATIC EFI_EVENT mEfiExitBootServicesEvent;
EFI_STATUS
EFIAPI
GenericWatchdogEntry (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
EFI_STATUS Status;
EFI_HANDLE Handle;
Status = gBS->LocateProtocol (
&gHardwareInterrupt2ProtocolGuid,
NULL,
(VOID **)&mInterruptProtocol
);
Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL,
(VOID **)&mInterruptProtocol);
ASSERT_EFI_ERROR (Status);
/* Make sure the Watchdog Timer Architectural Protocol has not been installed
@ -327,44 +320,33 @@ GenericWatchdogEntry (
ASSERT (mTimerFrequencyHz != 0);
// Install interrupt handler
Status = mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
WatchdogInterruptHandler
);
WatchdogInterruptHandler);
if (EFI_ERROR (Status)) {
return Status;
}
Status = mInterruptProtocol->SetTriggerType (
mInterruptProtocol,
Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING
);
EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING);
if (EFI_ERROR (Status)) {
goto UnregisterHandler;
}
// Install the Timer Architectural Protocol onto a new handle
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiWatchdogTimerArchProtocolGuid,
&mWatchdogTimer,
NULL
);
Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
&gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer,
NULL);
if (EFI_ERROR (Status)) {
goto UnregisterHandler;
}
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (
EVT_SIGNAL_EXIT_BOOT_SERVICES,
TPL_NOTIFY,
WatchdogExitBootServicesEvent,
NULL,
&mEfiExitBootServicesEvent
);
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
WatchdogExitBootServicesEvent, NULL,
&mEfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
mNumTimerTicks = 0;
@ -374,10 +356,8 @@ GenericWatchdogEntry (
UnregisterHandler:
// Unregister the handler
mInterruptProtocol->RegisterInterruptSource (
mInterruptProtocol,
mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
NULL
);
NULL);
return Status;
}

View File

@ -9,14 +9,14 @@
#ifndef MM_COMMUNICATE_H_
#define MM_COMMUNICATE_H_
#define MM_MAJOR_VER_MASK 0xEFFF0000
#define MM_MINOR_VER_MASK 0x0000FFFF
#define MM_MAJOR_VER_SHIFT 16
#define MM_MAJOR_VER_MASK 0xEFFF0000
#define MM_MINOR_VER_MASK 0x0000FFFF
#define MM_MAJOR_VER_SHIFT 16
#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
#define MM_CALLER_MAJOR_VER 0x1UL
#define MM_CALLER_MINOR_VER 0x0
#define MM_CALLER_MAJOR_VER 0x1UL
#define MM_CALLER_MINOR_VER 0x0
#endif /* MM_COMMUNICATE_H_ */

View File

@ -41,21 +41,15 @@ STATIC EFI_HANDLE mMmCommunicateHandle;
This function provides a service to send and receive messages from a registered UEFI service.
@param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance.
@param[in, out] CommBufferPhysical Physical address of the MM communication buffer
@param[in, out] CommBufferVirtual Virtual address of the MM communication buffer
@param[in, out] CommSize The size of the data buffer being passed in. On input,
when not omitted, the buffer should cover EFI_MM_COMMUNICATE_HEADER
and the value of MessageLength field. On exit, the size
of data being returned. Zero if the handler does not
wish to reply with any data. This parameter is optional
and may be NULL.
@param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance.
@param[in] CommBufferPhysical Physical address of the MM communication buffer
@param[in] CommBufferVirtual Virtual address of the MM communication buffer
@param[in] CommSize The size of the data buffer being passed in. On exit, the size of data
being returned. Zero if the handler does not wish to reply with any data.
This parameter is optional and may be NULL.
@retval EFI_SUCCESS The message was successfully posted.
@retval EFI_INVALID_PARAMETER CommBufferPhysical or CommBufferVirtual was NULL, or
integer value pointed by CommSize does not cover
EFI_MM_COMMUNICATE_HEADER and the value of MessageLength
field.
@retval EFI_INVALID_PARAMETER CommBufferPhysical was NULL or CommBufferVirtual was NULL.
@retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation.
If this error is returned, the MessageLength field
in the CommBuffer header or the integer pointed by
@ -69,18 +63,18 @@ STATIC EFI_HANDLE mMmCommunicateHandle;
EFI_STATUS
EFIAPI
MmCommunication2Communicate (
IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
IN OUT VOID *CommBufferPhysical,
IN OUT VOID *CommBufferVirtual,
IN OUT UINTN *CommSize OPTIONAL
IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
IN OUT VOID *CommBufferPhysical,
IN OUT VOID *CommBufferVirtual,
IN OUT UINTN *CommSize OPTIONAL
)
{
EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
ARM_SMC_ARGS CommunicateSmcArgs;
EFI_STATUS Status;
UINTN BufferSize;
EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
ARM_SMC_ARGS CommunicateSmcArgs;
EFI_STATUS Status;
UINTN BufferSize;
Status = EFI_ACCESS_DENIED;
Status = EFI_ACCESS_DENIED;
BufferSize = 0;
ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));
@ -88,11 +82,10 @@ MmCommunication2Communicate (
//
// Check parameters
//
if ((CommBufferVirtual == NULL) || (CommBufferPhysical == NULL)) {
if (CommBufferVirtual == NULL) {
return EFI_INVALID_PARAMETER;
}
Status = EFI_SUCCESS;
CommunicateHeader = CommBufferVirtual;
// CommBuffer is a mandatory parameter. Hence, Rely on
// MessageLength + Header to ascertain the
@ -102,41 +95,33 @@ MmCommunication2Communicate (
sizeof (CommunicateHeader->HeaderGuid) +
sizeof (CommunicateHeader->MessageLength);
// If CommSize is not omitted, perform size inspection before proceeding.
if (CommSize != NULL) {
// If the length of the CommBuffer is 0 then return the expected length.
if (CommSize != 0) {
// This case can be used by the consumer of this driver to find out the
// max size that can be used for allocating CommBuffer.
if ((*CommSize == 0) ||
(*CommSize > mNsCommBuffMemRegion.Length))
{
(*CommSize > mNsCommBuffMemRegion.Length)) {
*CommSize = mNsCommBuffMemRegion.Length;
Status = EFI_BAD_BUFFER_SIZE;
return EFI_BAD_BUFFER_SIZE;
}
//
// CommSize should cover at least MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
// CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
//
if (*CommSize < BufferSize) {
Status = EFI_INVALID_PARAMETER;
if (*CommSize != BufferSize) {
return EFI_INVALID_PARAMETER;
}
}
//
// If the message length is 0 or greater than what can be tolerated by the MM
// If the buffer size is 0 or greater than what can be tolerated by the MM
// environment then return the expected size.
//
if ((CommunicateHeader->MessageLength == 0) ||
(BufferSize > mNsCommBuffMemRegion.Length))
{
if ((BufferSize == 0) ||
(BufferSize > mNsCommBuffMemRegion.Length)) {
CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length -
sizeof (CommunicateHeader->HeaderGuid) -
sizeof (CommunicateHeader->MessageLength);
Status = EFI_BAD_BUFFER_SIZE;
}
// MessageLength or CommSize check has failed, return here.
if (EFI_ERROR (Status)) {
return Status;
return EFI_BAD_BUFFER_SIZE;
}
// SMC Function ID
@ -158,41 +143,41 @@ MmCommunication2Communicate (
ArmCallSmc (&CommunicateSmcArgs);
switch (CommunicateSmcArgs.Arg0) {
case ARM_SMC_MM_RET_SUCCESS:
ZeroMem (CommBufferVirtual, BufferSize);
// On successful return, the size of data being returned is inferred from
// MessageLength + Header.
CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
BufferSize = CommunicateHeader->MessageLength +
sizeof (CommunicateHeader->HeaderGuid) +
sizeof (CommunicateHeader->MessageLength);
case ARM_SMC_MM_RET_SUCCESS:
ZeroMem (CommBufferVirtual, BufferSize);
// On successful return, the size of data being returned is inferred from
// MessageLength + Header.
CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
BufferSize = CommunicateHeader->MessageLength +
sizeof (CommunicateHeader->HeaderGuid) +
sizeof (CommunicateHeader->MessageLength);
CopyMem (
CommBufferVirtual,
(VOID *)mNsCommBuffMemRegion.VirtualBase,
BufferSize
);
Status = EFI_SUCCESS;
break;
CopyMem (
CommBufferVirtual,
(VOID *)mNsCommBuffMemRegion.VirtualBase,
BufferSize
);
Status = EFI_SUCCESS;
break;
case ARM_SMC_MM_RET_INVALID_PARAMS:
Status = EFI_INVALID_PARAMETER;
break;
case ARM_SMC_MM_RET_INVALID_PARAMS:
Status = EFI_INVALID_PARAMETER;
break;
case ARM_SMC_MM_RET_DENIED:
Status = EFI_ACCESS_DENIED;
break;
case ARM_SMC_MM_RET_DENIED:
Status = EFI_ACCESS_DENIED;
break;
case ARM_SMC_MM_RET_NO_MEMORY:
// Unexpected error since the CommSize was checked for zero length
// prior to issuing the SMC
Status = EFI_OUT_OF_RESOURCES;
ASSERT (0);
break;
case ARM_SMC_MM_RET_NO_MEMORY:
// Unexpected error since the CommSize was checked for zero length
// prior to issuing the SMC
Status = EFI_OUT_OF_RESOURCES;
ASSERT (0);
break;
default:
Status = EFI_ACCESS_DENIED;
ASSERT (0);
default:
Status = EFI_ACCESS_DENIED;
ASSERT (0);
}
return Status;
@ -224,7 +209,7 @@ VOID
EFIAPI
NotifySetVirtualAddressMap (
IN EFI_EVENT Event,
IN VOID *Context
IN VOID *Context
)
{
EFI_STATUS Status;
@ -234,23 +219,19 @@ NotifySetVirtualAddressMap (
(VOID **)&mNsCommBuffMemRegion.VirtualBase
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"NotifySetVirtualAddressMap():"
" Unable to convert MM runtime pointer. Status:0x%r\n",
Status
));
DEBUG ((DEBUG_ERROR, "NotifySetVirtualAddressMap():"
" Unable to convert MM runtime pointer. Status:0x%r\n", Status));
}
}
STATIC
EFI_STATUS
GetMmCompatibility (
)
GetMmCompatibility ()
{
EFI_STATUS Status;
UINT32 MmVersion;
ARM_SMC_ARGS MmVersionArgs;
EFI_STATUS Status;
UINT32 MmVersion;
ARM_SMC_ARGS MmVersionArgs;
// MM_VERSION uses SMC32 calling conventions
MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32;
@ -259,38 +240,27 @@ GetMmCompatibility (
MmVersion = MmVersionArgs.Arg0;
if ((MM_MAJOR_VER (MmVersion) == MM_CALLER_MAJOR_VER) &&
(MM_MINOR_VER (MmVersion) >= MM_CALLER_MINOR_VER))
{
DEBUG ((
DEBUG_INFO,
"MM Version: Major=0x%x, Minor=0x%x\n",
MM_MAJOR_VER (MmVersion),
MM_MINOR_VER (MmVersion)
));
if ((MM_MAJOR_VER(MmVersion) == MM_CALLER_MAJOR_VER) &&
(MM_MINOR_VER(MmVersion) >= MM_CALLER_MINOR_VER)) {
DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n",
MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion)));
Status = EFI_SUCCESS;
} else {
DEBUG ((
DEBUG_ERROR,
"Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
MM_MAJOR_VER (MmVersion),
MM_MINOR_VER (MmVersion),
MM_CALLER_MAJOR_VER,
MM_CALLER_MINOR_VER
));
DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER));
Status = EFI_UNSUPPORTED;
}
return Status;
}
STATIC EFI_GUID *CONST mGuidedEventGuid[] = {
STATIC EFI_GUID* CONST mGuidedEventGuid[] = {
&gEfiEndOfDxeEventGroupGuid,
&gEfiEventExitBootServicesGuid,
&gEfiEventReadyToBootGuid,
};
STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
/**
Event notification that is fired when GUIDed Event Group is signaled.
@ -307,15 +277,15 @@ MmGuidedEventNotify (
IN VOID *Context
)
{
EFI_MM_COMMUNICATE_HEADER Header;
UINTN Size;
EFI_MM_COMMUNICATE_HEADER Header;
UINTN Size;
//
// Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure
//
CopyGuid (&Header.HeaderGuid, Context);
Header.MessageLength = 1;
Header.Data[0] = 0;
Header.Data[0] = 0;
Size = sizeof (Header);
MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);
@ -338,23 +308,23 @@ MmGuidedEventNotify (
EFI_STATUS
EFIAPI
MmCommunication2Initialize (
IN EFI_HANDLE ImageHandle,
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
EFI_STATUS Status;
UINTN Index;
// Check if we can make the MM call
Status = GetMmCompatibility ();
if (EFI_ERROR (Status)) {
if (EFI_ERROR(Status)) {
goto ReturnErrorStatus;
}
mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);
// During boot , Virtual and Physical are same
mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;
mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0);
@ -369,11 +339,8 @@ MmCommunication2Initialize (
EFI_MEMORY_RUNTIME
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"MmCommunicateInitialize: "
"Failed to add MM-NS Buffer Memory Space\n"
));
DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
"Failed to add MM-NS Buffer Memory Space\n"));
goto ReturnErrorStatus;
}
@ -383,11 +350,8 @@ MmCommunication2Initialize (
EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"MmCommunicateInitialize: "
"Failed to set MM-NS Buffer Memory attributes\n"
));
DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
"Failed to set MM-NS Buffer Memory attributes\n"));
goto CleanAddedMemorySpace;
}
@ -398,12 +362,9 @@ MmCommunication2Initialize (
EFI_NATIVE_INTERFACE,
&mMmCommunication2
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"MmCommunicationInitialize: "
"Failed to install MM communication protocol\n"
));
if (EFI_ERROR(Status)) {
DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: "
"Failed to install MM communication protocol\n"));
goto CleanAddedMemorySpace;
}
@ -420,24 +381,17 @@ MmCommunication2Initialize (
ASSERT_EFI_ERROR (Status);
for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) {
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
MmGuidedEventNotify,
mGuidedEventGuid[Index],
mGuidedEventGuid[Index],
&mGuidedEvent[Index]
);
Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
MmGuidedEventNotify, mGuidedEventGuid[Index],
mGuidedEventGuid[Index], &mGuidedEvent[Index]);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
while (Index-- > 0) {
gBS->CloseEvent (mGuidedEvent[Index]);
}
goto UninstallProtocol;
}
}
return EFI_SUCCESS;
UninstallProtocol:

View File

@ -7,6 +7,7 @@
**/
#include <PiDxe.h>
#include <Library/ArmLib.h>
@ -23,18 +24,18 @@
#include <Protocol/HardwareInterrupt.h>
// The notification function to call on every timer interrupt.
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt
UINT64 mTimerPeriod = 0;
UINT64 mTimerPeriod = 0;
// The latest Timer Tick calculated for mTimerPeriod
UINT64 mTimerTicks = 0;
UINT64 mTimerTicks = 0;
// Number of elapsed period since the last Timer interrupt
UINT64 mElapsedPeriod = 1;
UINT64 mElapsedPeriod = 1;
// Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
/**
This function registers the handler NotifyFunction so it is called every time
@ -132,9 +133,9 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod
)
{
UINT64 CounterValue;
UINT64 TimerTicks;
EFI_TPL OriginalTPL;
UINT64 CounterValue;
UINT64 TimerTicks;
EFI_TPL OriginalTPL;
// Always disable the timer
ArmGenericTimerDisableTimer ();
@ -165,7 +166,7 @@ TimerDriverSetTimerPeriod (
ArmGenericTimerEnableTimer ();
} else {
// Save the new timer period
mTimerPeriod = TimerPeriod;
mTimerPeriod = TimerPeriod;
// Reset the elapsed period
mElapsedPeriod = 1;
}
@ -191,8 +192,8 @@ TimerDriverSetTimerPeriod (
EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
@ -261,7 +262,7 @@ TimerDriverGenerateSoftInterrupt (
a period of time.
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
@ -284,13 +285,13 @@ EFI_TIMER_ARCH_PROTOCOL gTimer = {
VOID
EFIAPI
TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EFI_TPL OriginalTPL;
UINT64 CurrentValue;
UINT64 CompareValue;
EFI_TPL OriginalTPL;
UINT64 CurrentValue;
UINT64 CompareValue;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
@ -304,7 +305,8 @@ TimerInterruptHandler (
gInterrupt->EndOfInterrupt (gInterrupt, Source);
// Check if the timer interrupt is active
if ((ArmGenericTimerGetTimerCtrlReg ()) & ARM_ARCH_TIMER_ISTATUS) {
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
if (mTimerNotifyFunction != 0) {
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
}
@ -336,6 +338,7 @@ TimerInterruptHandler (
gBS->RestoreTPL (OriginalTPL);
}
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
@ -352,8 +355,8 @@ TimerInterruptHandler (
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle;
@ -371,7 +374,7 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status);
// Disable the timer
TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
TimerCtrlReg |= ARM_ARCH_TIMER_IMASK;
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);
@ -402,18 +405,17 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32 (PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status);
Handle = NULL;
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces (
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,
&gEfiTimerArchProtocolGuid,
&gTimer,
&gEfiTimerArchProtocolGuid, &gTimer,
NULL
);
ASSERT_EFI_ERROR (Status);
ASSERT_EFI_ERROR(Status);
// Everything is ready, unmask and enable timer interrupts
TimerCtrlReg = ARM_ARCH_TIMER_ENABLE;

View File

@ -27,16 +27,16 @@
#include "SemihostFs.h"
#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"
#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"
STATIC CHAR16 *mSemihostFsLabel;
STATIC CHAR16 *mSemihostFsLabel;
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,
VolumeOpen
};
EFI_FILE gSemihostFsFile = {
EFI_FILE gSemihostFsFile = {
EFI_FILE_PROTOCOL_REVISION,
FileOpen,
FileClose,
@ -54,45 +54,43 @@ EFI_FILE gSemihostFsFile = {
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} SEMIHOST_DEVICE_PATH;
SEMIHOST_DEVICE_PATH gDevicePath = {
SEMIHOST_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }
},
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
}
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
};
typedef struct {
LIST_ENTRY Link;
UINT64 Signature;
EFI_FILE File;
CHAR8 *FileName;
UINT64 OpenMode;
UINT32 Position;
UINTN SemihostHandle;
BOOLEAN IsRoot;
EFI_FILE_INFO Info;
LIST_ENTRY Link;
UINT64 Signature;
EFI_FILE File;
CHAR8 *FileName;
UINT64 OpenMode;
UINT32 Position;
UINTN SemihostHandle;
BOOLEAN IsRoot;
EFI_FILE_INFO Info;
} SEMIHOST_FCB;
#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
EFI_HANDLE gInstallHandle = NULL;
LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
SEMIHOST_FCB *
AllocateFCB (
VOID
)
{
SEMIHOST_FCB *Fcb;
SEMIHOST_FCB *Fcb;
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
if (Fcb != NULL) {
@ -105,7 +103,7 @@ AllocateFCB (
VOID
FreeFCB (
IN SEMIHOST_FCB *Fcb
IN SEMIHOST_FCB *Fcb
)
{
// Remove Fcb from gFileList.
@ -117,13 +115,15 @@ FreeFCB (
FreePool (Fcb);
}
EFI_STATUS
VolumeOpen (
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root
)
{
SEMIHOST_FCB *RootFcb;
SEMIHOST_FCB *RootFcb;
if (Root == NULL) {
return EFI_INVALID_PARAMETER;
@ -134,7 +134,7 @@ VolumeOpen (
return EFI_OUT_OF_RESOURCES;
}
RootFcb->IsRoot = TRUE;
RootFcb->IsRoot = TRUE;
RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;
InsertTailList (&gFileList, &RootFcb->Link);
@ -191,33 +191,29 @@ FileOpen (
return EFI_INVALID_PARAMETER;
}
if ((OpenMode != EFI_FILE_MODE_READ) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)))
{
if ( (OpenMode != EFI_FILE_MODE_READ) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&
(OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)) ) {
return EFI_INVALID_PARAMETER;
}
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
((Attributes & EFI_FILE_DIRECTORY) != 0))
{
((Attributes & EFI_FILE_DIRECTORY) != 0)) {
return EFI_WRITE_PROTECTED;
}
Length = StrLen (FileName) + 1;
Length = StrLen (FileName) + 1;
AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES;
}
UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length);
// Opening '/', '\', '.', or the NULL pathname is trying to open the root directory
if ((AsciiStrCmp (AsciiFileName, "\\") == 0) ||
(AsciiStrCmp (AsciiFileName, "/") == 0) ||
(AsciiStrCmp (AsciiFileName, "") == 0) ||
(AsciiStrCmp (AsciiFileName, ".") == 0))
{
(AsciiStrCmp (AsciiFileName, ".") == 0) ) {
FreePool (AsciiFileName);
return (VolumeOpen (&gSemihostFs, NewHandle));
}
@ -236,7 +232,6 @@ FileOpen (
} else {
SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
}
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
if (RETURN_ERROR (Return)) {
@ -284,7 +279,7 @@ FileOpen (
FileFcb->Info.FileSize = Length;
FileFcb->Info.PhysicalSize = Length;
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
Attributes : 0;
Attributes : 0;
InsertTailList (&gFileList, &FileFcb->Link);
@ -313,7 +308,7 @@ STATIC
EFI_STATUS
TruncateFile (
IN CHAR8 *FileName,
IN UINTN Size
IN UINTN Size
)
{
EFI_STATUS Status;
@ -343,7 +338,7 @@ TruncateFile (
goto Error;
}
Read = 0;
Read = 0;
Remaining = Size;
while (Remaining > 0) {
ToRead = Remaining;
@ -351,12 +346,11 @@ TruncateFile (
if (RETURN_ERROR (Return)) {
goto Error;
}
Remaining -= ToRead;
Read += ToRead;
}
Return = SemihostFileClose (FileHandle);
Return = SemihostFileClose (FileHandle);
FileHandle = 0;
if (RETURN_ERROR (Return)) {
goto Error;
@ -385,12 +379,12 @@ Error:
if (FileHandle != 0) {
SemihostFileClose (FileHandle);
}
if (Buffer != NULL) {
FreePool (Buffer);
}
return (Status);
}
/**
@ -408,13 +402,13 @@ FileClose (
IN EFI_FILE *This
)
{
SEMIHOST_FCB *Fcb;
SEMIHOST_FCB *Fcb;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}
Fcb = SEMIHOST_FCB_FROM_THIS (This);
Fcb = SEMIHOST_FCB_FROM_THIS(This);
if (!Fcb->IsRoot) {
SemihostFileClose (Fcb->SemihostHandle);
@ -426,7 +420,6 @@ FileClose (
if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) {
TruncateFile (Fcb->FileName, Fcb->Info.FileSize);
}
FreePool (Fcb->FileName);
}
@ -448,7 +441,7 @@ FileClose (
**/
EFI_STATUS
FileDelete (
IN EFI_FILE *This
IN EFI_FILE *This
)
{
SEMIHOST_FCB *Fcb;
@ -478,7 +471,6 @@ FileDelete (
if (RETURN_ERROR (Return)) {
return EFI_WARN_DELETE_FAILURE;
}
return EFI_SUCCESS;
} else {
return EFI_WARN_DELETE_FAILURE;
@ -574,15 +566,14 @@ ExtendFile (
}
Remaining = Size;
SetMem (WriteBuffer, 0, sizeof (WriteBuffer));
SetMem (WriteBuffer, 0, sizeof(WriteBuffer));
while (Remaining > 0) {
WriteNb = MIN (Remaining, sizeof (WriteBuffer));
WriteNb = MIN (Remaining, sizeof(WriteBuffer));
WriteSize = WriteNb;
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
Remaining -= WriteNb;
}
@ -608,9 +599,9 @@ ExtendFile (
**/
EFI_STATUS
FileWrite (
IN EFI_FILE *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
IN EFI_FILE *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
)
{
SEMIHOST_FCB *Fcb;
@ -626,9 +617,8 @@ FileWrite (
Fcb = SEMIHOST_FCB_FROM_THIS (This);
// We cannot write a read-only file
if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
{
if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {
return EFI_ACCESS_DENIED;
}
@ -642,12 +632,11 @@ FileWrite (
if (EFI_ERROR (Status)) {
return Status;
}
Fcb->Info.FileSize = Fcb->Position;
}
WriteSize = *BufferSize;
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
@ -661,7 +650,6 @@ FileWrite (
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
Fcb->Info.PhysicalSize = Length;
return EFI_SUCCESS;
@ -680,17 +668,17 @@ FileWrite (
**/
EFI_STATUS
FileGetPosition (
IN EFI_FILE *This,
OUT UINT64 *Position
IN EFI_FILE *This,
OUT UINT64 *Position
)
{
SEMIHOST_FCB *Fcb;
SEMIHOST_FCB *Fcb;
if ((This == NULL) || (Position == NULL)) {
return EFI_INVALID_PARAMETER;
}
Fcb = SEMIHOST_FCB_FROM_THIS (This);
Fcb = SEMIHOST_FCB_FROM_THIS(This);
*Position = Fcb->Position;
@ -713,8 +701,8 @@ FileGetPosition (
**/
EFI_STATUS
FileSetPosition (
IN EFI_FILE *This,
IN UINT64 Position
IN EFI_FILE *This,
IN UINT64 Position
)
{
SEMIHOST_FCB *Fcb;
@ -730,7 +718,8 @@ FileSetPosition (
if (Position != 0) {
return EFI_UNSUPPORTED;
}
} else {
}
else {
//
// UEFI Spec section 12.5:
// "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to
@ -739,7 +728,6 @@ FileSetPosition (
if (Position == 0xFFFFFFFFFFFFFFFF) {
Position = Fcb->Info.FileSize;
}
Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize));
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
@ -772,14 +760,14 @@ GetFileInfo (
OUT VOID *Buffer
)
{
EFI_FILE_INFO *Info;
UINTN NameSize;
UINTN ResultSize;
UINTN Index;
EFI_FILE_INFO *Info;
UINTN NameSize;
UINTN ResultSize;
UINTN Index;
if (Fcb->IsRoot) {
NameSize = 0;
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof (CHAR16);
NameSize = 0;
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
} else {
NameSize = AsciiStrLen (Fcb->FileName) + 1;
ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);
@ -799,7 +787,7 @@ GetFileInfo (
Info->Size = ResultSize;
if (Fcb->IsRoot) {
Info->FileName[0] = L'\0';
Info->FileName[0] = L'\0';
} else {
for (Index = 0; Index < NameSize; Index++) {
Info->FileName[Index] = Fcb->FileName[Index];
@ -830,9 +818,9 @@ GetFileInfo (
STATIC
EFI_STATUS
GetFilesystemInfo (
IN SEMIHOST_FCB *Fcb,
IN OUT UINTN *BufferSize,
OUT VOID *Buffer
IN SEMIHOST_FCB *Fcb,
IN OUT UINTN *BufferSize,
OUT VOID *Buffer
)
{
EFI_FILE_SYSTEM_INFO *Info;
@ -894,19 +882,18 @@ FileGetInfo (
OUT VOID *Buffer
)
{
SEMIHOST_FCB *Fcb;
EFI_STATUS Status;
UINTN ResultSize;
SEMIHOST_FCB *Fcb;
EFI_STATUS Status;
UINTN ResultSize;
if ((This == NULL) ||
(InformationType == NULL) ||
(BufferSize == NULL) ||
((Buffer == NULL) && (*BufferSize > 0)))
{
((Buffer == NULL) && (*BufferSize > 0)) ) {
return EFI_INVALID_PARAMETER;
}
Fcb = SEMIHOST_FCB_FROM_THIS (This);
Fcb = SEMIHOST_FCB_FROM_THIS(This);
if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);
@ -976,12 +963,11 @@ SetFileInfo (
return EFI_ACCESS_DENIED;
}
Length = StrLen (Info->FileName) + 1;
Length = StrLen (Info->FileName) + 1;
AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES;
}
UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length);
FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize);
@ -999,8 +985,7 @@ SetFileInfo (
// description.
//
if ((Fcb->OpenMode == EFI_FILE_MODE_READ) ||
(Fcb->Info.Attribute & EFI_FILE_READ_ONLY))
{
(Fcb->Info.Attribute & EFI_FILE_READ_ONLY) ) {
if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) {
Status = EFI_ACCESS_DENIED;
goto Error;
@ -1021,7 +1006,6 @@ SetFileInfo (
if (EFI_ERROR (Status)) {
goto Error;
}
//
// The read/write position from the host file system point of view
// is at the end of the file. If the position from this module
@ -1032,14 +1016,12 @@ SetFileInfo (
FileSetPosition (&Fcb->File, Fcb->Position);
}
}
Fcb->Info.FileSize = FileSize;
Return = SemihostFileLength (Fcb->SemihostHandle, &Length);
if (RETURN_ERROR (Return)) {
goto Error;
}
Fcb->Info.PhysicalSize = Length;
}
@ -1066,7 +1048,6 @@ SetFileInfo (
if (RETURN_ERROR (Return)) {
goto Error;
}
FreePool (Fcb->FileName);
Fcb->FileName = AsciiFileName;
AsciiFileName = NULL;
@ -1138,24 +1119,19 @@ FileSetInfo (
if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) {
return EFI_INVALID_PARAMETER;
}
if (BufferSize < Info->Size) {
return EFI_BAD_BUFFER_SIZE;
}
return SetFileInfo (Fcb, Info);
} else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
SystemInfo = Buffer;
if (SystemInfo->Size <
(SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel)))
{
(SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel))) {
return EFI_INVALID_PARAMETER;
}
if (BufferSize < SystemInfo->Size) {
return EFI_BAD_BUFFER_SIZE;
}
Buffer = SystemInfo->VolumeLabel;
if (StrSize (Buffer) > 0) {
@ -1179,19 +1155,18 @@ FileSetInfo (
EFI_STATUS
FileFlush (
IN EFI_FILE *File
IN EFI_FILE *File
)
{
SEMIHOST_FCB *Fcb;
SEMIHOST_FCB *Fcb;
Fcb = SEMIHOST_FCB_FROM_THIS (File);
Fcb = SEMIHOST_FCB_FROM_THIS(File);
if (Fcb->IsRoot) {
return EFI_SUCCESS;
} else {
if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
{
if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
|| !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {
return EFI_ACCESS_DENIED;
} else {
return EFI_SUCCESS;
@ -1201,11 +1176,11 @@ FileFlush (
EFI_STATUS
SemihostFsEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_STATUS Status;
Status = EFI_NOT_FOUND;
@ -1217,14 +1192,12 @@ SemihostFsEntryPoint (
Status = gBS->InstallMultipleProtocolInterfaces (
&gInstallHandle,
&gEfiSimpleFileSystemProtocolGuid,
&gSemihostFs,
&gEfiDevicePathProtocolGuid,
&gDevicePath,
&gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,
&gEfiDevicePathProtocolGuid, &gDevicePath,
NULL
);
if (EFI_ERROR (Status)) {
if (EFI_ERROR(Status)) {
FreePool (mSemihostFsLabel);
}
}

View File

@ -12,8 +12,8 @@
EFI_STATUS
VolumeOpen (
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root
IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
OUT EFI_FILE **Root
);
/**
@ -79,7 +79,7 @@ FileClose (
**/
EFI_STATUS
FileDelete (
IN EFI_FILE *This
IN EFI_FILE *This
);
/**
@ -127,9 +127,9 @@ FileRead (
**/
EFI_STATUS
FileWrite (
IN EFI_FILE *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
IN EFI_FILE *This,
IN OUT UINTN *BufferSize,
IN VOID *Buffer
);
/**
@ -145,8 +145,8 @@ FileWrite (
**/
EFI_STATUS
FileGetPosition (
IN EFI_FILE *File,
OUT UINT64 *Position
IN EFI_FILE *File,
OUT UINT64 *Position
);
/**
@ -164,8 +164,8 @@ FileGetPosition (
**/
EFI_STATUS
FileSetPosition (
IN EFI_FILE *File,
IN UINT64 Position
IN EFI_FILE *File,
IN UINT64 Position
);
/**
@ -239,7 +239,8 @@ FileSetInfo (
EFI_STATUS
FileFlush (
IN EFI_FILE *File
IN EFI_FILE *File
);
#endif // SEMIHOST_FS_H_

View File

@ -9,6 +9,7 @@
**/
#ifndef ASM_MACRO_IO_LIB_H_
#define ASM_MACRO_IO_LIB_H_
@ -19,7 +20,7 @@
.p2align 2 ; \
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movw Reg, #(Val) & 0xffff ; \

View File

@ -9,6 +9,7 @@
**/
#ifndef ASM_MACRO_IO_LIBV8_H_
#define ASM_MACRO_IO_LIBV8_H_
@ -23,6 +24,7 @@
cbnz SAFE_XREG, 1f ;\
b . ;// We should never get here
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2 and EL3, else we die.
// Provide the Macro with a safe temp xreg to use.
@ -40,7 +42,7 @@
.type Name, %function ; \
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movz Reg, (Val) >> 16, lsl #16 ; \

View File

@ -13,108 +13,108 @@
#include <Chipset/AArch64Mmu.h>
// ARM Interrupt ID in Exception Table
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
// CPACR - Coprocessor Access Control Register definitions
#define CPACR_TTA_EN (1UL << 28)
#define CPACR_FPEN_EL1 (1UL << 20)
#define CPACR_FPEN_FULL (3UL << 20)
#define CPACR_CP_FULL_ACCESS 0x300000
#define CPACR_TTA_EN (1UL << 28)
#define CPACR_FPEN_EL1 (1UL << 20)
#define CPACR_FPEN_FULL (3UL << 20)
#define CPACR_CP_FULL_ACCESS 0x300000
// Coprocessor Trap Register (CPTR)
#define AARCH64_CPTR_TFP (1 << 10)
#define AARCH64_CPTR_TFP (1 << 10)
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
#define AARCH64_PFR0_FP (0xF << 16)
#define AARCH64_PFR0_GIC (0xF << 24)
#define AARCH64_PFR0_FP (0xF << 16)
#define AARCH64_PFR0_GIC (0xF << 24)
// SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3)
#define SCR_FW (1 << 4)
#define SCR_AW (1 << 5)
#define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3)
#define SCR_FW (1 << 4)
#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
// Hypervisor Configuration Register
#define ARM_HCR_FMO BIT3
#define ARM_HCR_IMO BIT4
#define ARM_HCR_AMO BIT5
#define ARM_HCR_TSC BIT19
#define ARM_HCR_TGE BIT27
#define ARM_HCR_FMO BIT3
#define ARM_HCR_IMO BIT4
#define ARM_HCR_AMO BIT5
#define ARM_HCR_TSC BIT19
#define ARM_HCR_TGE BIT27
// Exception Syndrome Register
#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
// AArch64 Exception Level
#define AARCH64_EL3 0xC
#define AARCH64_EL2 0x8
#define AARCH64_EL1 0x4
#define AARCH64_EL3 0xC
#define AARCH64_EL2 0x8
#define AARCH64_EL1 0x4
// Saved Program Status Register definitions
#define SPSR_A BIT8
#define SPSR_I BIT7
#define SPSR_F BIT6
#define SPSR_A BIT8
#define SPSR_I BIT7
#define SPSR_F BIT6
#define SPSR_AARCH32 BIT4
#define SPSR_AARCH32 BIT4
#define SPSR_AARCH32_MODE_USER 0x0
#define SPSR_AARCH32_MODE_FIQ 0x1
#define SPSR_AARCH32_MODE_IRQ 0x2
#define SPSR_AARCH32_MODE_SVC 0x3
#define SPSR_AARCH32_MODE_ABORT 0x7
#define SPSR_AARCH32_MODE_UNDEF 0xB
#define SPSR_AARCH32_MODE_SYS 0xF
#define SPSR_AARCH32_MODE_USER 0x0
#define SPSR_AARCH32_MODE_FIQ 0x1
#define SPSR_AARCH32_MODE_IRQ 0x2
#define SPSR_AARCH32_MODE_SVC 0x3
#define SPSR_AARCH32_MODE_ABORT 0x7
#define SPSR_AARCH32_MODE_UNDEF 0xB
#define SPSR_AARCH32_MODE_SYS 0xF
// Counter-timer Hypervisor Control register definitions
#define CNTHCTL_EL2_EL1PCTEN BIT0
#define CNTHCTL_EL2_EL1PCEN BIT1
#define CNTHCTL_EL2_EL1PCTEN BIT0
#define CNTHCTL_EL2_EL1PCEN BIT1
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
// Vector table offset definitions
#define ARM_VECTOR_CUR_SP0_SYNC 0x000
#define ARM_VECTOR_CUR_SP0_IRQ 0x080
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SP0_SYNC 0x000
#define ARM_VECTOR_CUR_SP0_IRQ 0x080
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480
#define ARM_VECTOR_LOW_A64_FIQ 0x500
#define ARM_VECTOR_LOW_A64_SERR 0x580
#define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480
#define ARM_VECTOR_LOW_A64_FIQ 0x500
#define ARM_VECTOR_LOW_A64_SERR 0x580
#define ARM_VECTOR_LOW_A32_SYNC 0x600
#define ARM_VECTOR_LOW_A32_IRQ 0x680
#define ARM_VECTOR_LOW_A32_FIQ 0x700
#define ARM_VECTOR_LOW_A32_SERR 0x780
#define ARM_VECTOR_LOW_A32_SYNC 0x600
#define ARM_VECTOR_LOW_A32_IRQ 0x680
#define ARM_VECTOR_LOW_A32_FIQ 0x700
#define ARM_VECTOR_LOW_A32_SERR 0x780
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
// build for ARMv8.0, we need to define the register here.
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \
@ -151,7 +151,7 @@ ArmReadTpidrurw (
VOID
EFIAPI
ArmWriteTpidrurw (
UINTN Value
UINTN Value
);
UINTN
@ -163,7 +163,7 @@ ArmGetTCR (
VOID
EFIAPI
ArmSetTCR (
UINTN Value
UINTN Value
);
UINTN
@ -175,7 +175,7 @@ ArmGetMAIR (
VOID
EFIAPI
ArmSetMAIR (
UINTN Value
UINTN Value
);
VOID
@ -210,7 +210,7 @@ ArmDisableAllExceptions (
VOID
ArmWriteHcr (
IN UINTN Hcr
IN UINTN Hcr
);
UINTN
@ -225,7 +225,7 @@ ArmReadCurrentEL (
UINTN
ArmWriteCptr (
IN UINT64 Cptr
IN UINT64 Cptr
);
UINT32
@ -235,7 +235,7 @@ ArmReadCntHctl (
VOID
ArmWriteCntHctl (
IN UINT32 CntHctl
IN UINT32 CntHctl
);
#endif // AARCH64_H_

View File

@ -12,12 +12,12 @@
//
// Memory Attribute Indirection register Definitions
//
#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
#define MAIR_ATTR(n, value) ((value) << (((n) >> 2)*8))
#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))
//
// Long-descriptor Translation Table format
@ -27,7 +27,7 @@
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
// Get the associated entry in the given Translation Table
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
@ -35,161 +35,164 @@
// Return the smallest address granularity from the table level.
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
// There are 512 entries per table when 4K Granularity
#define TT_ENTRY_COUNT 512
#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
#define TT_ENTRY_COUNT 512
#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
#define TT_TYPE_MASK 0x3
#define TT_TYPE_TABLE_ENTRY 0x3
#define TT_TYPE_BLOCK_ENTRY 0x1
#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
#define TT_TYPE_MASK 0x3
#define TT_TYPE_TABLE_ENTRY 0x3
#define TT_TYPE_BLOCK_ENTRY 0x1
#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
#define TT_ATTR_INDX_MASK (0x7 << 2)
#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
#define TT_ATTR_INDX_MASK (0x7 << 2)
#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
#define TT_AP_MASK (0x3UL << 6)
#define TT_AP_NO_RW (0x0UL << 6)
#define TT_AP_RW_RW (0x1UL << 6)
#define TT_AP_NO_RO (0x2UL << 6)
#define TT_AP_RO_RO (0x3UL << 6)
#define TT_AP_MASK (0x3UL << 6)
#define TT_AP_NO_RW (0x0UL << 6)
#define TT_AP_RW_RW (0x1UL << 6)
#define TT_AP_NO_RO (0x2UL << 6)
#define TT_AP_RO_RO (0x3UL << 6)
#define TT_NS BIT5
#define TT_AF BIT10
#define TT_NS BIT5
#define TT_AF BIT10
#define TT_SH_NON_SHAREABLE (0x0 << 8)
#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
#define TT_SH_INNER_SHAREABLE (0x3 << 8)
#define TT_SH_MASK (0x3 << 8)
#define TT_SH_NON_SHAREABLE (0x0 << 8)
#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
#define TT_SH_INNER_SHAREABLE (0x3 << 8)
#define TT_SH_MASK (0x3 << 8)
#define TT_PXN_MASK BIT53
#define TT_UXN_MASK BIT54 // EL1&0
#define TT_XN_MASK BIT54 // EL2 / EL3
#define TT_PXN_MASK BIT53
#define TT_UXN_MASK BIT54 // EL1&0
#define TT_XN_MASK BIT54 // EL2 / EL3
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
#define TT_TABLE_PXN BIT59
#define TT_TABLE_UXN BIT60 // EL1&0
#define TT_TABLE_XN BIT60 // EL2 / EL3
#define TT_TABLE_NS BIT63
#define TT_TABLE_PXN BIT59
#define TT_TABLE_UXN BIT60 // EL1&0
#define TT_TABLE_XN BIT60 // EL2 / EL3
#define TT_TABLE_NS BIT63
#define TT_TABLE_AP_MASK (BIT62 | BIT61)
#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
#define TT_TABLE_AP_MASK (BIT62 | BIT61)
#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
//
// Translation Control Register
//
#define TCR_T0SZ_MASK 0x3FUL
#define TCR_T0SZ_MASK 0x3FUL
#define TCR_PS_4GB (0UL << 16)
#define TCR_PS_64GB (1UL << 16)
#define TCR_PS_1TB (2UL << 16)
#define TCR_PS_4TB (3UL << 16)
#define TCR_PS_16TB (4UL << 16)
#define TCR_PS_256TB (5UL << 16)
#define TCR_PS_4GB (0UL << 16)
#define TCR_PS_64GB (1UL << 16)
#define TCR_PS_1TB (2UL << 16)
#define TCR_PS_4TB (3UL << 16)
#define TCR_PS_16TB (4UL << 16)
#define TCR_PS_256TB (5UL << 16)
#define TCR_TG0_4KB (0UL << 14)
#define TCR_TG1_4KB (2UL << 30)
#define TCR_TG0_4KB (0UL << 14)
#define TCR_TG1_4KB (2UL << 30)
#define TCR_IPS_4GB (0ULL << 32)
#define TCR_IPS_64GB (1ULL << 32)
#define TCR_IPS_1TB (2ULL << 32)
#define TCR_IPS_4TB (3ULL << 32)
#define TCR_IPS_16TB (4ULL << 32)
#define TCR_IPS_256TB (5ULL << 32)
#define TCR_IPS_4GB (0ULL << 32)
#define TCR_IPS_64GB (1ULL << 32)
#define TCR_IPS_1TB (2ULL << 32)
#define TCR_IPS_4TB (3ULL << 32)
#define TCR_IPS_16TB (4ULL << 32)
#define TCR_IPS_256TB (5ULL << 32)
#define TCR_EPD1 (1UL << 23)
#define TCR_EPD1 (1UL << 23)
#define TTBR_ASID_FIELD (48)
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
#define TTBR_ASID_FIELD (48)
#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
#define TCR_EL1_T0SZ_FIELD (0)
#define TCR_EL1_EPD0_FIELD (7)
#define TCR_EL1_IRGN0_FIELD (8)
#define TCR_EL1_ORGN0_FIELD (10)
#define TCR_EL1_SH0_FIELD (12)
#define TCR_EL1_TG0_FIELD (14)
#define TCR_EL1_T1SZ_FIELD (16)
#define TCR_EL1_A1_FIELD (22)
#define TCR_EL1_EPD1_FIELD (23)
#define TCR_EL1_IRGN1_FIELD (24)
#define TCR_EL1_ORGN1_FIELD (26)
#define TCR_EL1_SH1_FIELD (28)
#define TCR_EL1_TG1_FIELD (30)
#define TCR_EL1_IPS_FIELD (32)
#define TCR_EL1_AS_FIELD (36)
#define TCR_EL1_TBI0_FIELD (37)
#define TCR_EL1_TBI1_FIELD (38)
#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
#define TCR_EL1_T0SZ_FIELD (0)
#define TCR_EL1_EPD0_FIELD (7)
#define TCR_EL1_IRGN0_FIELD (8)
#define TCR_EL1_ORGN0_FIELD (10)
#define TCR_EL1_SH0_FIELD (12)
#define TCR_EL1_TG0_FIELD (14)
#define TCR_EL1_T1SZ_FIELD (16)
#define TCR_EL1_A1_FIELD (22)
#define TCR_EL1_EPD1_FIELD (23)
#define TCR_EL1_IRGN1_FIELD (24)
#define TCR_EL1_ORGN1_FIELD (26)
#define TCR_EL1_SH1_FIELD (28)
#define TCR_EL1_TG1_FIELD (30)
#define TCR_EL1_IPS_FIELD (32)
#define TCR_EL1_AS_FIELD (36)
#define TCR_EL1_TBI0_FIELD (37)
#define TCR_EL1_TBI1_FIELD (38)
#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
#define TCR_EL23_T0SZ_FIELD (0)
#define TCR_EL23_IRGN0_FIELD (8)
#define TCR_EL23_ORGN0_FIELD (10)
#define TCR_EL23_SH0_FIELD (12)
#define TCR_EL23_TG0_FIELD (14)
#define TCR_EL23_PS_FIELD (16)
#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
#define TCR_EL23_T0SZ_FIELD (0)
#define TCR_EL23_IRGN0_FIELD (8)
#define TCR_EL23_ORGN0_FIELD (10)
#define TCR_EL23_SH0_FIELD (12)
#define TCR_EL23_TG0_FIELD (14)
#define TCR_EL23_PS_FIELD (16)
#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
#define TCR_PASZ_32BITS_4GB (0x0UL)
#define TCR_PASZ_36BITS_64GB (0x1UL)
#define TCR_PASZ_40BITS_1TB (0x2UL)
#define TCR_PASZ_42BITS_4TB (0x3UL)
#define TCR_PASZ_44BITS_16TB (0x4UL)
#define TCR_PASZ_48BITS_256TB (0x5UL)
#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
#define TCR_PASZ_32BITS_4GB (0x0UL)
#define TCR_PASZ_36BITS_64GB (0x1UL)
#define TCR_PASZ_40BITS_1TB (0x2UL)
#define TCR_PASZ_42BITS_4TB (0x3UL)
#define TCR_PASZ_44BITS_16TB (0x4UL)
#define TCR_PASZ_48BITS_256TB (0x5UL)
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format
#endif // AARCH64_MMU_H_

View File

@ -12,7 +12,7 @@
//
// Cortex A5x feature bit definitions
//
#define A5X_FEATURE_SMP (1 << 6)
#define A5X_FEATURE_SMP (1 << 6)
//
// Helper functions to access CPU Extended Control Register
@ -26,19 +26,19 @@ ArmReadCpuExCr (
VOID
EFIAPI
ArmWriteCpuExCr (
IN UINT64 Val
IN UINT64 Val
);
VOID
EFIAPI
ArmSetCpuExCrBit (
IN UINT64 Bits
IN UINT64 Bits
);
VOID
EFIAPI
ArmUnsetCpuExCrBit (
IN UINT64 Bits
IN UINT64 Bits
);
#endif // ARM_CORTEX_A5X_H_

View File

@ -26,27 +26,28 @@
//
// Cortex A9 Watchdog
//
#define ARM_A9_WATCHDOG_REGION 0x600
#define ARM_A9_WATCHDOG_REGION 0x600
#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
#define ARM_A9_WATCHDOG_ENABLE 1
#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
#define ARM_A9_WATCHDOG_ENABLE 1
//
// SCU register offsets & masks
//
#define A9_SCU_CONTROL_OFFSET 0x0
#define A9_SCU_CONFIG_OFFSET 0x4
#define A9_SCU_INVALL_OFFSET 0xC
#define A9_SCU_FILT_START_OFFSET 0x40
#define A9_SCU_FILT_END_OFFSET 0x44
#define A9_SCU_SACR_OFFSET 0x50
#define A9_SCU_SSACR_OFFSET 0x54
#define A9_SCU_CONTROL_OFFSET 0x0
#define A9_SCU_CONFIG_OFFSET 0x4
#define A9_SCU_INVALL_OFFSET 0xC
#define A9_SCU_FILT_START_OFFSET 0x40
#define A9_SCU_FILT_END_OFFSET 0x44
#define A9_SCU_SACR_OFFSET 0x50
#define A9_SCU_SSACR_OFFSET 0x54
UINTN
EFIAPI
@ -55,3 +56,4 @@ ArmGetScuBaseAddress (
);
#endif // ARM_CORTEX_A9_H_

View File

@ -13,19 +13,19 @@
#include <Chipset/ArmV7Mmu.h>
// ARM Interrupt ID in Exception Table
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
// ID_PFR1 - ARM Processor Feature Register 1 definitions
#define ARM_PFR1_SEC (0xFUL << 4)
#define ARM_PFR1_TIMER (0xFUL << 16)
#define ARM_PFR1_GIC (0xFUL << 28)
#define ARM_PFR1_SEC (0xFUL << 4)
#define ARM_PFR1_TIMER (0xFUL << 16)
#define ARM_PFR1_GIC (0xFUL << 28)
// Domain Access Control Register
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
// CPSR - Coprocessor Status Register definitions
#define CPSR_MODE_USER 0x10
@ -41,47 +41,48 @@
#define CPSR_IRQ (1 << 7)
#define CPSR_FIQ (1 << 6)
// CPACR - Coprocessor Access Control Register definitions
#define CPACR_CP_DENIED(cp) 0x00
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_ASEDIS (1 << 31)
#define CPACR_D32DIS (1 << 30)
#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
#define CPACR_CP_DENIED(cp) 0x00
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
#define CPACR_ASEDIS (1 << 31)
#define CPACR_D32DIS (1 << 30)
#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
// NSACR - Non-Secure Access Control Register definitions
#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
#define NSACR_NSD32DIS (1 << 14)
#define NSACR_NSASEDIS (1 << 15)
#define NSACR_PLE (1 << 16)
#define NSACR_TL (1 << 17)
#define NSACR_NS_SMP (1 << 18)
#define NSACR_RFR (1 << 19)
#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
#define NSACR_NSD32DIS (1 << 14)
#define NSACR_NSASEDIS (1 << 15)
#define NSACR_PLE (1 << 16)
#define NSACR_TL (1 << 17)
#define NSACR_NS_SMP (1 << 18)
#define NSACR_RFR (1 << 19)
// SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3)
#define SCR_FW (1 << 4)
#define SCR_AW (1 << 5)
#define SCR_NS (1 << 0)
#define SCR_IRQ (1 << 1)
#define SCR_FIQ (1 << 2)
#define SCR_EA (1 << 3)
#define SCR_FW (1 << 4)
#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A12 0xC0D
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A12 0xC0D
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A7 0xC07
#define ARM_CPU_TYPE_A5 0xC05
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
VOID
EFIAPI
@ -104,7 +105,7 @@ ArmReadTpidrurw (
VOID
EFIAPI
ArmWriteTpidrurw (
UINTN Value
UINTN Value
);
UINT32
@ -116,7 +117,7 @@ ArmReadNsacr (
VOID
EFIAPI
ArmWriteNsacr (
IN UINT32 Nsacr
IN UINT32 Nsacr
);
#endif // ARM_V7_H_

View File

@ -9,182 +9,183 @@
#ifndef ARMV7_MMU_H_
#define ARMV7_MMU_H_
#define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
#define TTBR_SHAREABLE BIT1
#define TTBR_NON_SHAREABLE 0
#define TTBR_INNER_CACHEABLE BIT0
#define TTBR_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
#define TTBR_NOT_OUTER_SHAREABLE BIT5
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
#define TTBR_SHAREABLE BIT1
#define TTBR_NON_SHAREABLE 0
#define TTBR_INNER_CACHEABLE BIT0
#define TTBR_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TRANSLATION_TABLE_SECTION_COUNT 4096
#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
#define TRANSLATION_TABLE_PAGE_COUNT 256
#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
#define TRANSLATION_TABLE_SECTION_COUNT 4096
#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
#define TRANSLATION_TABLE_PAGE_COUNT 256
#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
// Translation table descriptor types
#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types
#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((IsLargePage)?\
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@ -192,7 +193,7 @@
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_XN_MASK | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@ -200,33 +201,33 @@
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// First Level Descriptors
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
// Second Level Descriptors
typedef UINT32 ARM_PAGE_TABLE_ENTRY;
typedef UINT32 ARM_PAGE_TABLE_ENTRY;
UINT32
ConvertSectionAttributesToPageAttributes (

View File

@ -9,50 +9,52 @@
#ifndef ARM_MP_CORE_INFO_GUID_H_
#define ARM_MP_CORE_INFO_GUID_H_
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
#define SCU_CONFIG_REG_OFFSET 0x04
#define MPIDR_U_BIT_MASK 0x40000000
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
#define SCU_CONFIG_REG_OFFSET 0x04
#define MPIDR_U_BIT_MASK 0x40000000
typedef struct {
UINT64 Mpidr;
UINT32 ClusterId;
UINT32 CoreId;
// MP Core Mailbox
EFI_PHYSICAL_ADDRESS MailboxSetAddress;
EFI_PHYSICAL_ADDRESS MailboxGetAddress;
EFI_PHYSICAL_ADDRESS MailboxClearAddress;
UINT64 MailboxClearValue;
EFI_PHYSICAL_ADDRESS MailboxSetAddress;
EFI_PHYSICAL_ADDRESS MailboxGetAddress;
EFI_PHYSICAL_ADDRESS MailboxClearAddress;
UINT64 MailboxClearValue;
} ARM_CORE_INFO;
typedef struct {
UINT64 Signature;
UINT32 Length;
UINT32 Revision;
UINT64 OemId;
UINT64 OemTableId;
UINTN OemRevision;
UINTN CreatorId;
UINTN CreatorRevision;
EFI_GUID Identifier;
UINTN DataLen;
typedef struct{
UINT64 Signature;
UINT32 Length;
UINT32 Revision;
UINT64 OemId;
UINT64 OemTableId;
UINTN OemRevision;
UINTN CreatorId;
UINTN CreatorRevision;
EFI_GUID Identifier;
UINTN DataLen;
} ARM_PROCESSOR_TABLE_HEADER;
typedef struct {
ARM_PROCESSOR_TABLE_HEADER Header;
UINTN NumberOfEntries;
ARM_CORE_INFO *ArmCpus;
ARM_PROCESSOR_TABLE_HEADER Header;
UINTN NumberOfEntries;
ARM_CORE_INFO *ArmCpus;
} ARM_PROCESSOR_TABLE;
#define ARM_MP_CORE_INFO_GUID \
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0
#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0
#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
extern EFI_GUID gArmMpCoreInfoGuid;
extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* ARM_MP_CORE_INFO_GUID_H_ */

View File

@ -13,21 +13,22 @@
// The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
#define MAX_ARM_CACHE_LEVEL 7
#define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
UINT32 InD : 1; ///< Instruction not Data bit
UINT32 Level : 3; ///< Cache level (zero based)
UINT32 TnD : 1; ///< Allocation not Data bit
UINT32 Reserved : 27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
UINT32 InD :1; ///< Instruction not Data bit
UINT32 Level :3; ///< Cache level (zero based)
UINT32 TnD :1; ///< Allocation not Data bit
UINT32 Reserved :27; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
typedef enum {
typedef enum
{
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
@ -38,35 +39,35 @@ typedef enum {
/// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity : 10; ///< Associativity - 1
UINT64 NumSets : 15; ///< Number of sets in the cache -1
UINT64 Unknown : 4; ///< Reserved, UNKNOWN
UINT64 Reserved : 32; ///< Reserved, RES0
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :10; ///< Associativity - 1
UINT64 NumSets :15; ///< Number of sets in the cache -1
UINT64 Unknown :4; ///< Reserved, UNKNOWN
UINT64 Reserved :32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity : 21; ///< Associativity - 1
UINT64 Reserved1 : 8; ///< Reserved, RES0
UINT64 NumSets : 24; ///< Number of sets in the cache -1
UINT64 Reserved2 : 8; ///< Reserved, RES0
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
UINT64 Associativity :21; ///< Associativity - 1
UINT64 Reserved1 :8; ///< Reserved, RES0
UINT64 NumSets :24; ///< Number of sets in the cache -1
UINT64 Reserved2 :8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
UINT64 LineSize : 3;
UINT64 Associativity : 21;
UINT64 Reserved : 8;
UINT64 Unallocated : 32;
UINT64 LineSize : 3;
UINT64 Associativity : 21;
UINT64 Reserved : 8;
UINT64 Unallocated : 32;
} BitsCcidxAA32;
UINT64 Data; ///< The entire 64-bit value
UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
UINT32 NumSets : 24; ///< Number of sets in the cache - 1
UINT32 Reserved : 8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
UINT32 NumSets :24; ///< Number of sets in the cache - 1
UINT32 Reserved :8; ///< Reserved, RES0
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
@ -76,19 +77,19 @@ typedef union {
**/
typedef union {
struct {
UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
UINT32 Ctype1 : 3; ///< Level 1 cache type
UINT32 Ctype2 : 3; ///< Level 2 cache type
UINT32 Ctype3 : 3; ///< Level 3 cache type
UINT32 Ctype4 : 3; ///< Level 4 cache type
UINT32 Ctype5 : 3; ///< Level 5 cache type
UINT32 Ctype6 : 3; ///< Level 6 cache type
UINT32 Ctype7 : 3; ///< Level 7 cache type
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
UINT32 LoC : 3; ///< Level of Coherency
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
UINT32 Icb : 3; ///< Inner Cache Boundary
} Bits; ///< Bitfield definition of the register
UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
@ -106,6 +107,6 @@ typedef enum {
ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */

View File

@ -16,34 +16,34 @@
#ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif
#define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0
#define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0
#define ARM_FFA_SPM_RET_SUCCESS 0
#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
#define ARM_FFA_SPM_RET_NO_MEMORY -3
#define ARM_FFA_SPM_RET_BUSY -4
#define ARM_FFA_SPM_RET_INTERRUPTED -5
#define ARM_FFA_SPM_RET_DENIED -6
#define ARM_FFA_SPM_RET_RETRY -7
#define ARM_FFA_SPM_RET_ABORTED -8
#define ARM_FFA_SPM_RET_SUCCESS 0
#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
#define ARM_FFA_SPM_RET_NO_MEMORY -3
#define ARM_FFA_SPM_RET_BUSY -4
#define ARM_FFA_SPM_RET_INTERRUPTED -5
#define ARM_FFA_SPM_RET_DENIED -6
#define ARM_FFA_SPM_RET_RETRY -7
#define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added
@ -51,6 +51,6 @@
// This is the endpoint id used by the optee os's implementation
// of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_

View File

@ -14,49 +14,49 @@
* delegated events and request the Secure partition manager to perform
* privileged operations on its behalf.
*/
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
#define SET_MEM_ATTR_DATA_PERM_RW 1
#define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
#define SET_MEM_ATTR_DATA_PERM_RW 1
#define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
#define SET_MEM_ATTR_CODE_PERM_X 0
#define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
#define SET_MEM_ATTR_CODE_PERM_X 0
#define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
/* MM SVC Return error codes */
#define ARM_SVC_SPM_RET_SUCCESS 0
#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
#define ARM_SVC_SPM_RET_DENIED -3
#define ARM_SVC_SPM_RET_NO_MEMORY -5
#define ARM_SVC_SPM_RET_SUCCESS 0
#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
#define ARM_SVC_SPM_RET_DENIED -3
#define ARM_SVC_SPM_RET_NO_MEMORY -5
#define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1
#define SPM_MAJOR_VERSION 0
#define SPM_MINOR_VERSION 1
#endif // ARM_MM_SVC_H_

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@ -17,64 +17,64 @@
* SMC function IDs for Standard Service queries
*/
#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
#define ARM_SMC_ID_STD_UID 0x8400ff01
#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
#define ARM_SMC_ID_STD_UID 0x8400ff01
/* 0x8400ff02 is reserved */
#define ARM_SMC_ID_STD_REVISION 0x8400ff03
#define ARM_SMC_ID_STD_REVISION 0x8400ff03
/*
* The 'Standard Service Call UID' is supposed to return the Standard
* Service UUID. This is a 128-bit value.
*/
#define ARM_SMC_STD_UUID0 0x108d905b
#define ARM_SMC_STD_UUID1 0x47e8f863
#define ARM_SMC_STD_UUID2 0xfbc02dae
#define ARM_SMC_STD_UUID3 0xe2f64156
#define ARM_SMC_STD_UUID0 0x108d905b
#define ARM_SMC_STD_UUID1 0x47e8f863
#define ARM_SMC_STD_UUID2 0xfbc02dae
#define ARM_SMC_STD_UUID3 0xe2f64156
/*
* ARM Standard Service Calls revision numbers
* The current revision is: 0.1
*/
#define ARM_SMC_STD_REVISION_MAJOR 0x0
#define ARM_SMC_STD_REVISION_MINOR 0x1
#define ARM_SMC_STD_REVISION_MAJOR 0x0
#define ARM_SMC_STD_REVISION_MINOR 0x1
/*
* Management Mode (MM) calls cover a subset of the Standard Service Call range.
* The list below is not exhaustive.
*/
#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
// Request service from secure standalone MM environment
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif
#ifdef MDE_CPU_ARM
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif
/* MM return error codes */
#define ARM_SMC_MM_RET_SUCCESS 0
#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
#define ARM_SMC_MM_RET_INVALID_PARAMS -2
#define ARM_SMC_MM_RET_DENIED -3
#define ARM_SMC_MM_RET_NO_MEMORY -4
#define ARM_SMC_MM_RET_SUCCESS 0
#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
#define ARM_SMC_MM_RET_INVALID_PARAMS -2
#define ARM_SMC_MM_RET_DENIED -3
#define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls
#define SMCCC_VERSION 0x80000000
#define SMCCC_ARCH_FEATURES 0x80000001
#define SMCCC_ARCH_SOC_ID 0x80000002
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMCCC_VERSION 0x80000000
#define SMCCC_ARCH_FEATURES 0x80000001
#define SMCCC_ARCH_SOC_ID 0x80000002
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
#define SMC_ARCH_CALL_NOT_REQUIRED -2
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
#define SMC_ARCH_CALL_NOT_REQUIRED -2
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
/*
* Power State Coordination Interface (PSCI) calls cover a subset of the
@ -101,15 +101,15 @@
((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
/* PSCI return error codes */
#define ARM_SMC_PSCI_RET_SUCCESS 0
#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
#define ARM_SMC_PSCI_RET_DENIED -3
#define ARM_SMC_PSCI_RET_ALREADY_ON -4
#define ARM_SMC_PSCI_RET_ON_PENDING -5
#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
#define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_RET_SUCCESS 0
#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
#define ARM_SMC_PSCI_RET_DENIED -3
#define ARM_SMC_PSCI_RET_ALREADY_ON -4
#define ARM_SMC_PSCI_RET_ON_PENDING -5
#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
#define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
@ -120,10 +120,10 @@
#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
@ -132,9 +132,9 @@
/*
* SMC function IDs for Trusted OS Service queries
*/
#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
#define ARM_SMC_ID_TOS_UID 0xbf00ff01
#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
#define ARM_SMC_ID_TOS_UID 0xbf00ff01
/* 0xbf00ff02 is reserved */
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif // ARM_STD_SMC_H_

View File

@ -26,12 +26,12 @@
**/
VOID
DisassembleInstruction (
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf,
OUT UINTN Size
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf,
OUT UINTN Size
);
#endif // ARM_DISASSEMBLER_LIB_H_

View File

@ -43,7 +43,7 @@ ArmGenericTimerGetTimerFreq (
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
IN UINTN Value
IN UINTN Value
);
UINTN
@ -67,7 +67,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
UINTN Value
UINTN Value
);
UINT64
@ -79,7 +79,7 @@ ArmGenericTimerGetCompareVal (
VOID
EFIAPI
ArmGenericTimerSetCompareVal (
IN UINT64 Value
IN UINT64 Value
);
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_

View File

@ -17,6 +17,7 @@ typedef enum {
ARM_GIC_ARCH_REVISION_3
} ARM_GIC_ARCH_REVISION;
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (

View File

@ -12,36 +12,36 @@
#include <Library/ArmGicArchLib.h>
// GIC Distributor
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
// Each reg base below repeats for Number of interrupts / 4
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
// Each reg base below repeats for Number of interrupts
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
// just one of these
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
// GICv3 specific registers
#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
// GICD_CTLR bits
#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
// GICD_ICDICFR bits
#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
@ -52,124 +52,125 @@
#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
// GIC Redistributor
#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
// GIC Redistributor Control frame
#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
// GIC Redistributor TYPER bit assignments
#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
// Selection Support
#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
ARM_GICR_TYPER_AFFINITY) >> 32)
// GIC SGI & PPI Redistributor frame
#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
// GIC Cpu interface
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
#define ARM_GIC_ICCIIDR 0xFC // Identification Register
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
#define ARM_GIC_ICCIIDR 0xFC // Identification Register
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
// Bit-masks to configure the CPU Interface Control register
#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
#define ARM_GIC_ICCICR_ENABLE_NS 0x02
#define ARM_GIC_ICCICR_ACK_CTL 0x04
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
#define ARM_GIC_ICCICR_USE_SBPR 0x10
#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
#define ARM_GIC_ICCICR_ENABLE_NS 0x02
#define ARM_GIC_ICCICR_ACK_CTL 0x04
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
#define ARM_GIC_ICCICR_USE_SBPR 0x10
// Bit Mask for GICC_IIDR
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
// Bit Mask for
#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
);
// GIC Secure interfaces
VOID
EFIAPI
ArmGicSetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicSetSecureInterrupts (
IN UINTN GicDistributorBase,
IN UINTN *GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
IN UINTN GicDistributorBase,
IN UINTN* GicSecureInterruptMask,
IN UINTN GicSecureInterruptMaskSize
);
VOID
EFIAPI
ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicDisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicDisableDistributor (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
);
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
IN INTN GicDistributorBase
IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList,
IN INTN SgiId
);
/*
@ -189,55 +190,55 @@ ArmGicSendSgiTo (
UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *InterruptId
);
VOID
EFIAPI
ArmGicEndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
);
UINTN
EFIAPI
ArmGicSetPriorityMask (
IN INTN GicInterruptInterfaceBase,
IN INTN PriorityMask
IN INTN GicInterruptInterfaceBase,
IN INTN PriorityMask
);
VOID
EFIAPI
ArmGicSetInterruptPriority (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source,
IN UINTN Priority
);
VOID
EFIAPI
ArmGicEnableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
);
VOID
EFIAPI
ArmGicDisableInterrupt (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
);
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
IN UINTN GicDistributorBase,
IN UINTN GicRedistributorBase,
IN UINTN Source
);
// GIC revision 2 specific declarations
@ -250,41 +251,41 @@ ArmGicIsInterruptEnabled (
VOID
EFIAPI
ArmGicV2SetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
IN INTN GicInterruptInterfaceBase
IN INTN GicInterruptInterfaceBase
);
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
IN UINTN GicInterruptInterfaceBase
IN UINTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
IN UINTN GicInterruptInterfaceBase,
IN UINTN Source
);
// GIC revision 3 specific declarations
#define ICC_SRE_EL2_SRE (1 << 0)
#define ICC_SRE_EL2_SRE (1 << 0)
#define ARM_GICD_IROUTER_IRM BIT31
#define ARM_GICD_IROUTER_IRM BIT31
UINT32
EFIAPI
@ -295,7 +296,7 @@ ArmGicV3GetControlSystemRegisterEnable (
VOID
EFIAPI
ArmGicV3SetControlSystemRegisterEnable (
IN UINT32 ControlSystemRegisterEnable
IN UINT32 ControlSystemRegisterEnable
);
VOID
@ -319,17 +320,17 @@ ArmGicV3AcknowledgeInterrupt (
VOID
EFIAPI
ArmGicV3EndOfInterrupt (
IN UINTN Source
IN UINTN Source
);
VOID
ArmGicV3SetBinaryPointer (
IN UINTN BinaryPoint
IN UINTN BinaryPoint
);
VOID
ArmGicV3SetPriorityMask (
IN UINTN Priority
IN UINTN Priority
);
#endif // ARMGIC_H_

View File

@ -14,14 +14,14 @@
* The native size is used for the arguments.
*/
typedef struct {
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
} ARM_HVC_ARGS;
/**
@ -34,7 +34,7 @@ typedef struct {
**/
VOID
ArmCallHvc (
IN OUT ARM_HVC_ARGS *Args
IN OUT ARM_HVC_ARGS *Args
);
#endif // ARM_HVC_LIB_H_

View File

@ -15,13 +15,13 @@
#ifdef MDE_CPU_ARM
#include <Chipset/ArmV7.h>
#elif defined (MDE_CPU_AARCH64)
#elif defined(MDE_CPU_AARCH64)
#include <Chipset/AArch64.h>
#else
#error "Unknown chipset."
#error "Unknown chipset."
#endif
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE)
@ -50,21 +50,17 @@ typedef enum {
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES;
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct {
EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase;
UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes;
EFI_PHYSICAL_ADDRESS PhysicalBase;
EFI_VIRTUAL_ADDRESS VirtualBase;
UINT64 Length;
ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
typedef VOID (*CACHE_OPERATION)(
VOID
);
typedef VOID (*LINE_OPERATION)(
UINTN
);
typedef VOID (*CACHE_OPERATION)(VOID);
typedef VOID (*LINE_OPERATION)(UINTN);
//
// ARM Processor Mode
@ -84,38 +80,34 @@ typedef enum {
//
// ARM Cpu IDs
//
#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
//
// ARM MP Core IDs
//
#define ARM_CORE_AFF0 0xFF
#define ARM_CORE_AFF1 (0xFF << 8)
#define ARM_CORE_AFF2 (0xFF << 16)
#define ARM_CORE_AFF3 (0xFFULL << 32)
#define ARM_CORE_AFF0 0xFF
#define ARM_CORE_AFF1 (0xFF << 8)
#define ARM_CORE_AFF2 (0xFF << 16)
#define ARM_CORE_AFF3 (0xFFULL << 32)
#define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
#define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache.
@ -126,7 +118,7 @@ typedef enum {
**/
UINTN
ReadCCSIDR (
IN UINT32 CSSELR
IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@ -137,7 +129,7 @@ ReadCCSIDR (
**/
UINT32
ReadCCSIDR2 (
IN UINT32 CSSELR
IN UINT32 CSSELR
);
/** Reads the Cache Level ID (CLIDR) register.
@ -191,6 +183,7 @@ ArmInvalidateDataCache (
VOID
);
VOID
EFIAPI
ArmCleanInvalidateDataCache (
@ -212,31 +205,31 @@ ArmInvalidateInstructionCache (
VOID
EFIAPI
ArmInvalidateDataCacheEntryByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryToPoUByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmInvalidateInstructionCacheEntryToPoUByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
IN UINTN Address
);
IN UINTN Address
);
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
IN UINTN Address
IN UINTN Address
);
VOID
@ -359,8 +352,8 @@ ArmInvalidateTlb (
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
IN VOID *TranslationTableEntry,
IN VOID *Mva
IN VOID *TranslationTableEntry,
IN VOID *Mva
);
VOID
@ -378,7 +371,7 @@ ArmSetTTBR0 (
VOID
EFIAPI
ArmSetTTBCR (
IN UINT32 Bits
IN UINT32 Bits
);
VOID *
@ -438,7 +431,7 @@ ArmInstructionSynchronizationBarrier (
VOID
EFIAPI
ArmWriteVBar (
IN UINTN VectorBase
IN UINTN VectorBase
);
UINTN
@ -450,7 +443,7 @@ ArmReadVBar (
VOID
EFIAPI
ArmWriteAuxCr (
IN UINT32 Bit
IN UINT32 Bit
);
UINT32
@ -462,13 +455,13 @@ ArmReadAuxCr (
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
IN UINT32 Bits
);
VOID
EFIAPI
ArmUnsetAuxCrBit (
IN UINT32 Bits
IN UINT32 Bits
);
VOID
@ -511,7 +504,7 @@ ArmReadCpacr (
VOID
EFIAPI
ArmWriteCpacr (
IN UINT32 Access
IN UINT32 Access
);
VOID
@ -541,7 +534,7 @@ ArmReadScr (
VOID
EFIAPI
ArmWriteScr (
IN UINT32 Value
IN UINT32 Value
);
UINT32
@ -553,7 +546,7 @@ ArmReadMVBar (
VOID
EFIAPI
ArmWriteMVBar (
IN UINT32 VectorMonitorBase
IN UINT32 VectorMonitorBase
);
UINT32
@ -565,7 +558,7 @@ ArmReadSctlr (
VOID
EFIAPI
ArmWriteSctlr (
IN UINT32 Value
IN UINT32 Value
);
UINTN
@ -577,9 +570,10 @@ ArmReadHVBar (
VOID
EFIAPI
ArmWriteHVBar (
IN UINTN HypModeVectorBase
IN UINTN HypModeVectorBase
);
//
// Helper functions for accessing CPU ACTLR
//
@ -593,28 +587,28 @@ ArmReadCpuActlr (
VOID
EFIAPI
ArmWriteCpuActlr (
IN UINTN Val
IN UINTN Val
);
VOID
EFIAPI
ArmSetCpuActlrBit (
IN UINTN Bits
IN UINTN Bits
);
VOID
EFIAPI
ArmUnsetCpuActlrBit (
IN UINTN Bits
IN UINTN Bits
);
//
// Accessors for the architected generic timer registers
//
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
#define ARM_ARCH_TIMER_IMASK (1 << 1)
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
UINTN
EFIAPI
@ -625,7 +619,7 @@ ArmReadCntFrq (
VOID
EFIAPI
ArmWriteCntFrq (
UINTN FreqInHz
UINTN FreqInHz
);
UINT64
@ -643,7 +637,7 @@ ArmReadCntkCtl (
VOID
EFIAPI
ArmWriteCntkCtl (
UINTN Val
UINTN Val
);
UINTN
@ -655,7 +649,7 @@ ArmReadCntpTval (
VOID
EFIAPI
ArmWriteCntpTval (
UINTN Val
UINTN Val
);
UINTN
@ -667,7 +661,7 @@ ArmReadCntpCtl (
VOID
EFIAPI
ArmWriteCntpCtl (
UINTN Val
UINTN Val
);
UINTN
@ -679,7 +673,7 @@ ArmReadCntvTval (
VOID
EFIAPI
ArmWriteCntvTval (
UINTN Val
UINTN Val
);
UINTN
@ -691,7 +685,7 @@ ArmReadCntvCtl (
VOID
EFIAPI
ArmWriteCntvCtl (
UINTN Val
UINTN Val
);
UINT64
@ -709,7 +703,7 @@ ArmReadCntpCval (
VOID
EFIAPI
ArmWriteCntpCval (
UINT64 Val
UINT64 Val
);
UINT64
@ -721,7 +715,7 @@ ArmReadCntvCval (
VOID
EFIAPI
ArmWriteCntvCval (
UINT64 Val
UINT64 Val
);
UINT64
@ -733,7 +727,7 @@ ArmReadCntvOff (
VOID
EFIAPI
ArmWriteCntvOff (
UINT64 Val
UINT64 Val
);
UINTN
@ -742,6 +736,7 @@ ArmGetPhysicalAddressBits (
VOID
);
///
/// ID Register Helper functions
///
@ -773,7 +768,6 @@ ArmHasCcidx (
///
/// AArch32-only ID Register Helper functions
///
/**
Check whether the CPU supports the Security extensions
@ -785,7 +779,6 @@ EFIAPI
ArmHasSecurityExtensions (
VOID
);
#endif // MDE_CPU_ARM
#endif // ARM_LIB_H_

View File

@ -24,29 +24,29 @@ ArmConfigureMmu (
EFI_STATUS
EFIAPI
ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
VOID
@ -59,9 +59,9 @@ ArmReplaceLiveTranslationEntry (
EFI_STATUS
ArmSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes
);
#endif // ARM_MMU_LIB_H_

View File

@ -18,37 +18,37 @@
#pragma pack(1)
typedef struct {
UINT32 Reserved1;
UINT32 ChannelStatus;
UINT64 Reserved2;
UINT32 Flags;
UINT32 Length;
UINT32 MessageHeader;
UINT32 Reserved1;
UINT32 ChannelStatus;
UINT64 Reserved2;
UINT32 Flags;
UINT32 Length;
UINT32 MessageHeader;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
UINT32 Payload[1]; // size less object gives offset to payload.
UINT32 Payload[1]; // size less object gives offset to payload.
} MTL_MAILBOX;
#pragma pack()
// Channel Type, Low-priority, and High-priority
typedef enum {
MTL_CHANNEL_TYPE_LOW = 0,
MTL_CHANNEL_TYPE_LOW = 0,
MTL_CHANNEL_TYPE_HIGH = 1
} MTL_CHANNEL_TYPE;
typedef struct {
UINT64 PhysicalAddress;
UINT32 ModifyMask;
UINT32 PreserveMask;
UINT64 PhysicalAddress;
UINT32 ModifyMask;
UINT32 PreserveMask;
} MTL_DOORBELL;
typedef struct {
MTL_CHANNEL_TYPE ChannelType;
MTL_MAILBOX *CONST MailBox;
MTL_DOORBELL DoorBell;
MTL_CHANNEL_TYPE ChannelType;
MTL_MAILBOX * CONST MailBox;
MTL_DOORBELL DoorBell;
} MTL_CHANNEL;
/** Wait until channel is free.
@ -71,7 +71,7 @@ MtlWaitUntilChannelFree (
@retval UINT32* Pointer to the payload.
**/
UINT32 *
UINT32*
MtlGetChannelPayload (
IN MTL_CHANNEL *Channel
);
@ -127,4 +127,5 @@ MtlReceiveMessage (
OUT UINT32 *PayloadLength
);
#endif /* ARM_MTL_LIB_H_ */
#endif /* ARM_MTL_LIB_H_ */

View File

@ -1,6 +1,5 @@
/** @file
*
* Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
* Copyright (c) 2012-2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@ -15,14 +14,14 @@
* The native size is used for the arguments.
*/
typedef struct {
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
} ARM_SMC_ARGS;
/**
@ -35,79 +34,7 @@ typedef struct {
**/
VOID
ArmCallSmc (
IN OUT ARM_SMC_ARGS *Args
);
/** Trigger an SMC call with 3 arguments.
@param Function The SMC function.
@param Arg1 Argument/result.
@param Arg2 Argument/result.
@param Arg3 Argument/result.
@return The SMC error code.
**/
UINTN
ArmCallSmc3 (
IN UINTN Function,
IN OUT UINTN *Arg1 OPTIONAL,
IN OUT UINTN *Arg2 OPTIONAL,
IN OUT UINTN *Arg3 OPTIONAL
);
/** Trigger an SMC call with 2 arguments.
@param Function The SMC function.
@param Arg1 Argument/result.
@param Arg2 Argument/result.
@param Arg3 Result.
@return The SMC error code.
**/
UINTN
ArmCallSmc2 (
IN UINTN Function,
IN OUT UINTN *Arg1 OPTIONAL,
IN OUT UINTN *Arg2 OPTIONAL,
OUT UINTN *Arg3 OPTIONAL
);
/** Trigger an SMC call with 1 argument.
@param Function The SMC function.
@param Arg1 Argument/result.
@param Arg2 Result.
@param Arg3 Result.
@return The SMC error code.
**/
UINTN
ArmCallSmc1 (
IN UINTN Function,
IN OUT UINTN *Arg1 OPTIONAL,
OUT UINTN *Arg2 OPTIONAL,
OUT UINTN *Arg3 OPTIONAL
);
/** Trigger an SMC call with 0 arguments.
@param Function The SMC function.
@param Arg1 Result.
@param Arg2 Result.
@param Arg3 Result.
@return The SMC error code.
**/
UINTN
ArmCallSmc0 (
IN UINTN Function,
OUT UINTN *Arg1 OPTIONAL,
OUT UINTN *Arg2 OPTIONAL,
OUT UINTN *Arg3 OPTIONAL
IN OUT ARM_SMC_ARGS *Args
);
#endif // ARM_SMC_LIB_H_

View File

@ -14,14 +14,14 @@
* The native size is used for the arguments.
*/
typedef struct {
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
UINTN Arg0;
UINTN Arg1;
UINTN Arg2;
UINTN Arg3;
UINTN Arg4;
UINTN Arg5;
UINTN Arg6;
UINTN Arg7;
} ARM_SVC_ARGS;
/**
@ -40,7 +40,7 @@ typedef struct {
**/
VOID
ArmCallSvc (
IN OUT ARM_SVC_ARGS *Args
IN OUT ARM_SVC_ARGS *Args
);
#endif // ARM_SVC_LIB_H_

View File

@ -18,8 +18,8 @@
**/
VOID
DefaultExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_

View File

@ -8,13 +8,15 @@
*
**/
#ifndef OEM_MISC_LIB_H_
#define OEM_MISC_LIB_H_
#include <Uefi.h>
#include <IndustryStandard/SmBios.h>
typedef enum {
typedef enum
{
CpuCacheL1 = 1,
CpuCacheL2,
CpuCacheL3,
@ -25,40 +27,37 @@ typedef enum {
CpuCacheLevelMax
} OEM_MISC_CPU_CACHE_LEVEL;
typedef struct {
UINT8 Voltage; ///< Processor voltage
UINT16 CurrentSpeed; ///< Current clock speed in MHz
UINT16 MaxSpeed; ///< Maximum clock speed in MHz
UINT16 ExternalClock; ///< External clock speed in MHz
UINT16 CoreCount; ///< Number of cores available
UINT16 CoresEnabled; ///< Number of cores enabled
UINT16 ThreadCount; ///< Number of threads per processor
typedef struct
{
UINT8 Voltage; ///< Processor voltage
UINT16 CurrentSpeed; ///< Current clock speed in MHz
UINT16 MaxSpeed; ///< Maximum clock speed in MHz
UINT16 ExternalClock; ///< External clock speed in MHz
UINT16 CoreCount; ///< Number of cores available
UINT16 CoresEnabled; ///< Number of cores enabled
UINT16 ThreadCount; ///< Number of threads per processor
} OEM_MISC_PROCESSOR_DATA;
typedef enum {
ProductNameType01,
SerialNumType01,
UuidType01,
SystemManufacturerType01,
VersionType01,
SkuNumberType01,
FamilyType01,
AssertTagType02,
SerialNumberType02,
BoardManufacturerType02,
ProductNameType02,
VersionType02,
SkuNumberType02,
ChassisLocationType02,
AssetTagType03,
SerialNumberType03,
VersionType03,
ChassisTypeType03,
ManufacturerType03,
SkuNumberType03,
ProcessorPartNumType04,
ProcessorSerialNumType04,
SmbiosHiiStringFieldMax
typedef enum
{
ProductNameType01,
SerialNumType01,
UuidType01,
SystemManufacturerType01,
SkuNumberType01,
FamilyType01,
AssertTagType02,
SerialNumberType02,
BoardManufacturerType02,
SkuNumberType02,
ChassisLocationType02,
AssetTagType03,
SerialNumberType03,
VersionType03,
ChassisTypeType03,
ManufacturerType03,
SkuNumberType03,
SmbiosHiiStringFieldMax
} OEM_MISC_SMBIOS_HII_STRING_FIELD;
/*
@ -75,7 +74,7 @@ typedef enum {
UINTN
EFIAPI
OemGetCpuFreq (
IN UINT8 ProcessorIndex
IN UINT8 ProcessorIndex
);
/** Gets information about the specified processor and stores it in
@ -91,10 +90,10 @@ OemGetCpuFreq (
BOOLEAN
EFIAPI
OemGetProcessorInformation (
IN UINTN ProcessorIndex,
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
IN UINTN ProcessorIndex,
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
);
/** Gets information about the cache at the specified cache level.
@ -110,11 +109,11 @@ OemGetProcessorInformation (
BOOLEAN
EFIAPI
OemGetCacheInformation (
IN UINT8 ProcessorIndex,
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
IN UINT8 ProcessorIndex,
IN UINT8 CacheLevel,
IN BOOLEAN DataCache,
IN BOOLEAN UnifiedCache,
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
);
/** Gets the maximum number of processors supported by the platform.
@ -146,7 +145,7 @@ OemGetChassisType (
BOOLEAN
EFIAPI
OemIsProcessorPresent (
IN UINTN ProcessorIndex
IN UINTN ProcessorIndex
);
/** Updates the HII string for the specified field.
@ -158,9 +157,9 @@ OemIsProcessorPresent (
VOID
EFIAPI
OemUpdateSmbiosInfo (
IN EFI_HII_HANDLE HiiHandle,
IN EFI_STRING_ID TokenToUpdate,
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
IN EFI_HII_HANDLE HiiHandle,
IN EFI_STRING_ID TokenToUpdate,
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);
/** Fetches the Type 32 boot information status.

View File

@ -15,24 +15,24 @@
* The 'Trusted OS Call UID' is supposed to return the following UUID for
* OP-TEE OS. This is a 128-bit value.
*/
#define OPTEE_OS_UID0 0x384fb3e0
#define OPTEE_OS_UID1 0xe7f811e3
#define OPTEE_OS_UID2 0xaf630002
#define OPTEE_OS_UID3 0xa5d5c51b
#define OPTEE_OS_UID0 0x384fb3e0
#define OPTEE_OS_UID1 0xe7f811e3
#define OPTEE_OS_UID2 0xaf630002
#define OPTEE_OS_UID3 0xa5d5c51b
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
#define OPTEE_SUCCESS 0x00000000
#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
#define OPTEE_SUCCESS 0x00000000
#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
typedef struct {
UINT64 BufferAddress;
@ -47,44 +47,44 @@ typedef struct {
} OPTEE_MESSAGE_PARAM_VALUE;
typedef union {
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
OPTEE_MESSAGE_PARAM_MEMORY Memory;
OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION;
typedef struct {
UINT64 Attribute;
OPTEE_MESSAGE_PARAM_UNION Union;
UINT64 Attribute;
OPTEE_MESSAGE_PARAM_UNION Union;
} OPTEE_MESSAGE_PARAM;
#define OPTEE_MAX_CALL_PARAMS 4
#define OPTEE_MAX_CALL_PARAMS 4
typedef struct {
UINT32 Command;
UINT32 Function;
UINT32 Session;
UINT32 CancelId;
UINT32 Pad;
UINT32 Return;
UINT32 ReturnOrigin;
UINT32 NumParams;
UINT32 Command;
UINT32 Function;
UINT32 Session;
UINT32 CancelId;
UINT32 Pad;
UINT32 Return;
UINT32 ReturnOrigin;
UINT32 NumParams;
// NumParams tells the actual number of element in Params
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
} OPTEE_MESSAGE_ARG;
typedef struct {
EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
UINT32 Session; // [out] Session id
UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value
EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
UINT32 Session; // [out] Session id
UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value
} OPTEE_OPEN_SESSION_ARG;
typedef struct {
UINT32 Function; // [in] Trusted Application function, specific to the TA
UINT32 Session; // [in] Session id
UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
UINT32 Function; // [in] Trusted Application function, specific to the TA
UINT32 Session; // [in] Session id
UINT32 Return; // [out] Return value
UINT32 ReturnOrigin; // [out] Origin of the return value
OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
} OPTEE_INVOKE_FUNCTION_ARG;
BOOLEAN
@ -102,19 +102,19 @@ OpteeInit (
EFI_STATUS
EFIAPI
OpteeOpenSession (
IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
);
EFI_STATUS
EFIAPI
OpteeCloseSession (
IN UINT32 Session
IN UINT32 Session
);
EFI_STATUS
EFIAPI
OpteeInvokeFunction (
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
);
#endif // OPTEE_LIB_H_

View File

@ -17,12 +17,12 @@
*
*/
#define SEMIHOST_FILE_MODE_READ (0 << 2)
#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
#define SEMIHOST_FILE_MODE_READ (0 << 2)
#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN
SemihostConnectionSupported (
@ -31,9 +31,9 @@ SemihostConnectionSupported (
RETURN_STATUS
SemihostFileOpen (
IN CHAR8 *FileName,
IN UINT32 Mode,
OUT UINTN *FileHandle
IN CHAR8 *FileName,
IN UINT32 Mode,
OUT UINTN *FileHandle
);
RETURN_STATUS
@ -81,7 +81,7 @@ SemihostFileLength (
**/
RETURN_STATUS
SemihostFileTmpName (
SemihostFileTmpName(
OUT VOID *Buffer,
IN UINT8 Identifier,
IN UINTN Length
@ -89,7 +89,7 @@ SemihostFileTmpName (
RETURN_STATUS
SemihostFileRemove (
IN CHAR8 *FileName
IN CHAR8 *FileName
);
/**
@ -104,7 +104,7 @@ SemihostFileRemove (
**/
RETURN_STATUS
SemihostFileRename (
SemihostFileRename(
IN CHAR8 *FileName,
IN CHAR8 *NewFileName
);
@ -116,17 +116,17 @@ SemihostReadCharacter (
VOID
SemihostWriteCharacter (
IN CHAR8 Character
IN CHAR8 Character
);
VOID
SemihostWriteString (
IN CHAR8 *String
IN CHAR8 *String
);
UINT32
SemihostSystem (
IN CHAR8 *CommandLine
IN CHAR8 *CommandLine
);
#endif // SEMIHOSTING_LIB_H_

View File

@ -11,26 +11,26 @@
EFI_STATUS
ArmSetMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionNoExec (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
ArmSetMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionReadOnly (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
#endif /* STANDALONE_MM_MMU_LIB_ */

View File

@ -32,10 +32,10 @@
**/
typedef
EFI_STATUS
(EFIAPI *ARM_MP_CORE_INFO_GET)(
(EFIAPI * ARM_MP_CORE_INFO_GET) (
OUT UINTN *ArmCoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
);
);
///
/// This service abstracts the ability to migrate contents of the platform early memory store.
@ -43,10 +43,10 @@ EFI_STATUS
/// This PPI was optional.
///
typedef struct {
ARM_MP_CORE_INFO_GET GetMpCoreInfo;
ARM_MP_CORE_INFO_GET GetMpCoreInfo;
} ARM_MP_CORE_INFO_PPI;
extern EFI_GUID gArmMpCoreInfoPpiGuid;
extern EFI_GUID gArmMpCoreInfoGuid;
extern EFI_GUID gArmMpCoreInfoPpiGuid;
extern EFI_GUID gArmMpCoreInfoGuid;
#endif // ARM_MP_CORE_INFO_PPI_H_

View File

@ -15,6 +15,7 @@
/* As per SCMI specification, maximum allowed ASCII string length
for various return values/parameters of a SCMI message.
*/
#define SCMI_MAX_STR_LEN 16
#define SCMI_MAX_STR_LEN 16
#endif /* ARM_SCMI_H_ */

View File

@ -17,24 +17,24 @@
#define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000
#define NUM_PROTOCOL_MASK 0xFFU
#define NUM_AGENT_MASK 0xFFU
#define NUM_PROTOCOL_MASK 0xFFU
#define NUM_AGENT_MASK 0xFFU
#define NUM_AGENT_SHIFT 0x8
#define NUM_AGENT_SHIFT 0x8
/** Returns total number of protocols that are
implemented (excluding the Base protocol)
*/
#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
// Returns total number of agents in the system.
#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
#define ARM_SCMI_BASE_PROTOCOL_GUID { \
0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \
}
extern EFI_GUID gArmScmiBaseProtocolGuid;
extern EFI_GUID gArmScmiBaseProtocolGuid;
typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
@ -50,7 +50,7 @@ typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_GET_VERSION)(
(EFIAPI *SCMI_BASE_GET_VERSION) (
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *Version
);
@ -67,7 +67,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS)(
(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) (
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *TotalProtocols
);
@ -85,7 +85,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_VENDOR)(
(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) (
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@ -103,7 +103,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR)(
(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) (
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@ -120,7 +120,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION)(
(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) (
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *ImplementationVersion
);
@ -141,7 +141,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS)(
(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) (
IN SCMI_BASE_PROTOCOL *This,
IN OUT UINT32 *ProtocolListSize,
OUT UINT8 *ProtocolList
@ -149,20 +149,20 @@ EFI_STATUS
// Base protocol.
typedef struct _SCMI_BASE_PROTOCOL {
SCMI_BASE_GET_VERSION GetVersion;
SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
SCMI_BASE_GET_VERSION GetVersion;
SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
} SCMI_BASE_PROTOCOL;
// SCMI Message IDs for Base protocol.
typedef enum {
ScmiMessageIdBaseDiscoverVendor = 0x3,
ScmiMessageIdBaseDiscoverSubVendor = 0x4,
ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
ScmiMessageIdBaseDiscoverListProtocols = 0x6
ScmiMessageIdBaseDiscoverVendor = 0x3,
ScmiMessageIdBaseDiscoverSubVendor = 0x4,
ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */

View File

@ -15,13 +15,13 @@
#include <Protocol/ArmScmi.h>
#include <Protocol/ArmScmiClockProtocol.h>
#define ARM_SCMI_CLOCK2_PROTOCOL_GUID {\
#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \
0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \
}
extern EFI_GUID gArmScmiClock2ProtocolGuid;
extern EFI_GUID gArmScmiClock2ProtocolGuid;
#define SCMI_CLOCK2_PROTOCOL_VERSION 1
#define SCMI_CLOCK2_PROTOCOL_VERSION 1
typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
@ -39,7 +39,7 @@ typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_VERSION)(
(EFIAPI *SCMI_CLOCK2_GET_VERSION) (
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *Version
);
@ -57,7 +57,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS)(
(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) (
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@ -77,7 +77,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)(
(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@ -109,7 +109,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES)(
(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@ -131,7 +131,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_RATE_GET)(
(EFIAPI *SCMI_CLOCK2_RATE_GET) (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@ -149,7 +149,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_RATE_SET)(
(EFIAPI *SCMI_CLOCK2_RATE_SET) (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
@ -168,24 +168,24 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK2_ENABLE)(
(EFIAPI *SCMI_CLOCK2_ENABLE) (
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN BOOLEAN Enable
);
typedef struct _SCMI_CLOCK2_PROTOCOL {
SCMI_CLOCK2_GET_VERSION GetVersion;
SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK2_RATE_GET RateGet;
SCMI_CLOCK2_RATE_SET RateSet;
SCMI_CLOCK2_GET_VERSION GetVersion;
SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK2_RATE_GET RateGet;
SCMI_CLOCK2_RATE_SET RateSet;
// Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL
// can be cast to SCMI_CLOCK_PROTOCOL
UINTN Version; // For future expandability
SCMI_CLOCK2_ENABLE Enable;
UINTN Version; // For future expandability
SCMI_CLOCK2_ENABLE Enable;
} SCMI_CLOCK2_PROTOCOL;
#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */

View File

@ -14,11 +14,11 @@
#include <Protocol/ArmScmi.h>
#define ARM_SCMI_CLOCK_PROTOCOL_GUID {\
#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \
0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \
}
extern EFI_GUID gArmScmiClockProtocolGuid;
extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol.
typedef enum {
@ -35,21 +35,21 @@ typedef enum {
} SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version.
#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
/** Total number of pending asynchronous clock rates changes
supported by the SCP, Attr Bits[23:16]
*/
#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
(Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \
SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)
// Total of clock devices supported by the SCP, Attr Bits[15:0]
#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
#pragma pack(1)
@ -57,18 +57,18 @@ typedef enum {
either Rate or Min/Max/Step triplet is valid.
*/
typedef struct {
UINT64 Min;
UINT64 Max;
UINT64 Step;
UINT64 Min;
UINT64 Max;
UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct {
UINT64 Rate;
UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE;
typedef union {
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE;
#pragma pack()
@ -89,7 +89,7 @@ typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL;
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_VERSION)(
(EFIAPI *SCMI_CLOCK_GET_VERSION) (
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *Version
);
@ -107,7 +107,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS)(
(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) (
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@ -127,7 +127,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES)(
(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) (
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@ -159,7 +159,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES)(
(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) (
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@ -181,7 +181,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_RATE_GET)(
(EFIAPI *SCMI_CLOCK_RATE_GET) (
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@ -199,19 +199,20 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_CLOCK_RATE_SET)(
(EFIAPI *SCMI_CLOCK_RATE_SET) (
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
);
typedef struct _SCMI_CLOCK_PROTOCOL {
SCMI_CLOCK_GET_VERSION GetVersion;
SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK_RATE_GET RateGet;
SCMI_CLOCK_RATE_SET RateSet;
SCMI_CLOCK_GET_VERSION GetVersion;
SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
SCMI_CLOCK_RATE_GET RateGet;
SCMI_CLOCK_RATE_SET RateSet;
} SCMI_CLOCK_PROTOCOL;
#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */

View File

@ -20,15 +20,15 @@
0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \
}
extern EFI_GUID gArmScmiPerformanceProtocolGuid;
extern EFI_GUID gArmScmiPerformanceProtocolGuid;
typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
#pragma pack(1)
#define POWER_IN_MW_SHIFT 16
#define POWER_IN_MW_MASK 0x1
#define NUM_PERF_DOMAINS_MASK 0xFFFF
#define POWER_IN_MW_SHIFT 16
#define POWER_IN_MW_MASK 0x1
#define NUM_PERF_DOMAINS_MASK 0xFFFF
// Total number of performance domains, Attr Bits [15:0]
#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)
@ -39,41 +39,41 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
// Performance protocol attributes return values.
typedef struct {
UINT32 Attributes;
UINT64 StatisticsAddress;
UINT32 StatisticsLen;
UINT32 Attributes;
UINT64 StatisticsAddress;
UINT32 StatisticsLen;
} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;
#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
// Performance protocol domain attributes.
typedef struct {
UINT32 Attributes;
UINT32 RateLimit;
UINT32 SustainedFreq;
UINT32 SustainedPerfLevel;
UINT8 Name[SCMI_MAX_STR_LEN];
UINT32 Attributes;
UINT32 RateLimit;
UINT32 SustainedFreq;
UINT32 SustainedPerfLevel;
UINT8 Name[SCMI_MAX_STR_LEN];
} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;
// Worst case latency in microseconds, Bits[15:0]
#define PERF_LATENCY_MASK 0xFFFF
#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
#define PERF_LATENCY_MASK 0xFFFF
#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
// Performance protocol performance level.
typedef struct {
UINT32 Level;
UINT32 PowerCost;
UINT32 Latency;
UINT32 Level;
UINT32 PowerCost;
UINT32 Latency;
} SCMI_PERFORMANCE_LEVEL;
// Performance protocol performance limit.
typedef struct {
UINT32 RangeMax;
UINT32 RangeMin;
UINT32 RangeMax;
UINT32 RangeMin;
} SCMI_PERFORMANCE_LIMITS;
#pragma pack()
@ -92,7 +92,7 @@ typedef struct {
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_VERSION)(
(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT UINT32 *Version
);
@ -109,7 +109,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES)(
(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
@ -128,7 +128,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES)(
(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
@ -153,7 +153,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS)(
(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *NumLevels,
@ -173,7 +173,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET)(
(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits
@ -192,7 +192,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET)(
(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) (
SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits
@ -210,7 +210,7 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET)(
(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 Level
@ -229,21 +229,21 @@ EFI_STATUS
**/
typedef
EFI_STATUS
(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET)(
(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) (
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *Level
);
typedef struct _SCMI_PERFORMANCE_PROTOCOL {
SCMI_PERFORMANCE_GET_VERSION GetVersion;
SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
SCMI_PERFORMANCE_LEVEL_SET LevelSet;
SCMI_PERFORMANCE_LEVEL_GET LevelGet;
SCMI_PERFORMANCE_GET_VERSION GetVersion;
SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
SCMI_PERFORMANCE_LEVEL_SET LevelSet;
SCMI_PERFORMANCE_LEVEL_GET LevelGet;
} SCMI_PERFORMANCE_PROTOCOL;
typedef enum {
@ -256,3 +256,4 @@ typedef enum {
} SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */

View File

@ -7,6 +7,7 @@
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
@ -15,15 +16,16 @@
#include <Library/PcdLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
// Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM
#define MULT_U64_X_N MultU64x32
#define MULT_U64_X_N MultU64x32
#else
#define MULT_U64_X_N MultU64x64
#define MULT_U64_X_N MultU64x64
#endif
RETURN_STATUS
EFIAPI
TimerConstructor (
@ -34,6 +36,7 @@ TimerConstructor (
// Check if the ARM Generic Timer Extension is implemented.
//
if (ArmIsArchTimerImplemented ()) {
//
// Check if Architectural Timer frequency is pre-determined by the platform
// (ie. nonzero).
@ -46,7 +49,7 @@ TimerConstructor (
//
ASSERT (TICKS_PER_MICRO_SEC);
#ifdef MDE_CPU_ARM
#ifdef MDE_CPU_ARM
//
// Only set the frequency for ARMv7. We expect the secure firmware to
// have already done it.
@ -56,8 +59,7 @@ TimerConstructor (
if (ArmHasSecurityExtensions ()) {
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
}
#endif
#endif
}
//
@ -66,8 +68,9 @@ TimerConstructor (
// If the reset value (0) is returned, just ASSERT.
//
ASSERT (ArmGenericTimerGetTimerFreq () != 0);
} else {
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));
ASSERT (0);
}
@ -87,16 +90,16 @@ EFIAPI
GetPlatformTimerFreq (
)
{
UINTN TimerFreq;
UINTN TimerFreq;
TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz);
if (TimerFreq == 0) {
TimerFreq = ArmGenericTimerGetTimerFreq ();
}
return TimerFreq;
}
/**
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@ -108,11 +111,11 @@ GetPlatformTimerFreq (
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
IN UINTN MicroSeconds
)
{
UINT64 TimerTicks64;
UINT64 SystemCounterVal;
UINT64 TimerTicks64;
UINT64 SystemCounterVal;
// Calculate counter ticks that represent requested delay:
// = MicroSeconds x TICKS_PER_MICRO_SEC
@ -138,6 +141,7 @@ MicroSecondDelay (
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
@ -154,13 +158,13 @@ MicroSecondDelay (
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
IN UINTN NanoSeconds
)
{
UINTN MicroSeconds;
// Round up to 1us Tick Number
MicroSeconds = NanoSeconds / 1000;
MicroSeconds = NanoSeconds / 1000;
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
MicroSecondDelay (MicroSeconds);
@ -215,13 +219,13 @@ GetPerformanceCounter (
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue OPTIONAL,
OUT UINT64 *EndValue OPTIONAL
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts at 0
*StartValue = (UINT64)0ULL;
*StartValue = (UINT64)0ULL ;
}
if (EndValue != NULL) {
@ -246,7 +250,7 @@ GetPerformanceCounterProperties (
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
IN UINT64 Ticks
)
{
UINT64 NanoSeconds;
@ -263,8 +267,7 @@ GetTimeInNanoSecond (
DivU64x32Remainder (
Ticks,
TimerFreq,
&Remainder
),
&Remainder),
1000000000U
);
@ -274,9 +277,8 @@ GetTimeInNanoSecond (
//
NanoSeconds += DivU64x32 (
MULT_U64_X_N (
(UINT64)Remainder,
1000000000U
),
(UINT64) Remainder,
1000000000U),
TimerFreq
);

View File

@ -20,21 +20,20 @@ CacheRangeOperation (
IN UINTN LineLength
)
{
UINTN ArmCacheLineAlignmentMask;
UINTN ArmCacheLineAlignmentMask;
// Align address (rounding down)
UINTN AlignedAddress;
UINTN EndAddress;
UINTN AlignedAddress;
UINTN EndAddress;
ArmCacheLineAlignmentMask = LineLength - 1;
AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
EndAddress = (UINTN)Start + Length;
AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation (AlignedAddress);
LineOperation(AlignedAddress);
AlignedAddress += LineLength;
}
ArmDataSynchronizationBarrier ();
}
@ -59,22 +58,15 @@ InvalidateDataCache (
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (
Address,
Length,
ArmCleanDataCacheEntryToPoUByMVA,
ArmDataCacheLineLength ()
);
CacheRangeOperation (
Address,
Length,
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,
ArmDataCacheLineLength ());
CacheRangeOperation (Address, Length,
ArmInvalidateInstructionCacheEntryToPoUByMVA,
ArmInstructionCacheLineLength ()
);
ArmInstructionCacheLineLength ());
ArmInstructionSynchronizationBarrier ();
@ -93,16 +85,12 @@ WriteBackInvalidateDataCache (
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (
Address,
Length,
ArmCleanInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ());
return Address;
}
@ -118,31 +106,23 @@ WriteBackDataCache (
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (
Address,
Length,
ArmCleanDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,
ArmDataCacheLineLength ());
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
IN VOID *Address,
IN UINTN Length
)
{
CacheRangeOperation (
Address,
Length,
ArmInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ()
);
CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,
ArmDataCacheLineLength ());
return Address;
}

View File

@ -26,12 +26,12 @@
**/
VOID
DisassembleInstruction (
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf,
OUT UINTN Size
IN UINT8 **OpCodePtr,
IN BOOLEAN Thumb,
IN BOOLEAN Extended,
IN OUT UINT32 *ItBlock,
OUT CHAR8 *Buf,
OUT UINTN Size
)
{
// Not yet supported for AArch64.

View File

@ -13,7 +13,7 @@
#include <Library/PrintLib.h>
#include <Library/ArmDisassemblerLib.h>
CHAR8 *gCondition[] = {
CHAR8 *gCondition[] = {
"EQ",
"NE",
"CS",
@ -34,7 +34,7 @@ CHAR8 *gCondition[] = {
#define COND(_a) gCondition[((_a) >> 28)]
CHAR8 *gReg[] = {
CHAR8 *gReg[] = {
"r0",
"r1",
"r2",
@ -53,36 +53,37 @@ CHAR8 *gReg[] = {
"pc"
};
CHAR8 *gLdmAdr[] = {
CHAR8 *gLdmAdr[] = {
"DA",
"IA",
"DB",
"IB"
};
CHAR8 *gLdmStack[] = {
CHAR8 *gLdmStack[] = {
"FA",
"FD",
"EA",
"ED"
};
#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
#define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
CHAR8 mMregListStr[4*15 + 1];
#define SIGN(_U) ((_U) ? "" : "-")
#define WRITE(_Write) ((_Write) ? "!" : "")
#define BYTE(_B) ((_B) ? "B":"")
#define USER(_B) ((_B) ? "^" : "")
CHAR8 mMregListStr[4*15 + 1];
CHAR8 *
MRegList (
UINT32 OpCode
)
{
UINTN Index, Start, End;
BOOLEAN First;
UINTN Index, Start, End;
BOOLEAN First;
mMregListStr[0] = '\0';
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
@ -109,11 +110,9 @@ MRegList (
}
}
}
if (First) {
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
}
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner
@ -130,13 +129,14 @@ FieldMask (
UINT32
RotateRight (
IN UINT32 Op,
IN UINT32 Shift
IN UINT32 Op,
IN UINT32 Shift
)
{
return (Op >> Shift) | (Op << (32 - Shift));
}
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@ -152,38 +152,39 @@ RotateRight (
**/
VOID
DisassembleArmInstruction (
IN UINT32 **OpCodePtr,
OUT CHAR8 *Buf,
OUT UINTN Size,
IN BOOLEAN Extended
IN UINT32 **OpCodePtr,
OUT CHAR8 *Buf,
OUT UINTN Size,
IN BOOLEAN Extended
)
{
UINT32 OpCode;
CHAR8 *Type;
CHAR8 *Root;
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
UINT32 Rn, Rd, Rm;
UINT32 IMod, Offset8, Offset12;
UINT32 Index;
UINT32 ShiftImm, Shift;
UINT32 OpCode;
CHAR8 *Type;
CHAR8 *Root;
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
UINT32 Rn, Rd, Rm;
UINT32 IMod, Offset8, Offset12;
UINT32 Index;
UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr;
Imm = (OpCode & BIT25) == BIT25; // I
Pre = (OpCode & BIT24) == BIT24; // P
Up = (OpCode & BIT23) == BIT23; // U
Imm = (OpCode & BIT25) == BIT25; // I
Pre = (OpCode & BIT24) == BIT24; // P
Up = (OpCode & BIT23) == BIT23; // U
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
Write = (OpCode & BIT21) == BIT21; // W
Load = (OpCode & BIT20) == BIT20; // L
Sign = (OpCode & BIT6) == BIT6; // S
Half = (OpCode & BIT5) == BIT5; // H
Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf);
Write = (OpCode & BIT21) == BIT21; // W
Load = (OpCode & BIT20) == BIT20; // L
Sign = (OpCode & BIT6) == BIT6; // S
Half = (OpCode & BIT5) == BIT5; // H
Rn = (OpCode >> 16) & 0xf;
Rd = (OpCode >> 12) & 0xf;
Rm = (OpCode & 0xf);
if (Extended) {
Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
Buf += Index;
Buf += Index;
Size -= Index;
}
@ -193,10 +194,9 @@ DisassembleArmInstruction (
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else {
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
}
return;
}
@ -206,25 +206,23 @@ DisassembleArmInstruction (
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
}
return;
}
// LDR/STR Address Mode 2
if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
Offset12 = OpCode & 0xfff;
if ((OpCode & 0xfd70f000) == 0xf550f000) {
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD");
} else {
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
}
if (Pre) {
if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>]
@ -238,7 +236,7 @@ DisassembleArmInstruction (
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3;
Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
} else if (Shift == 0x1) {
@ -257,8 +255,7 @@ DisassembleArmInstruction (
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
}
} else {
// !Pre
} else { // !Pre
if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
@ -268,7 +265,7 @@ DisassembleArmInstruction (
} else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
ShiftImm = (OpCode >> 7) & 0x1f;
Shift = (OpCode >> 5) & 0x3;
Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
@ -290,7 +287,6 @@ DisassembleArmInstruction (
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
}
}
return;
}
@ -317,31 +313,30 @@ DisassembleArmInstruction (
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
Sign = (OpCode & BIT6) == BIT6;
Half = (OpCode & BIT5) == BIT5;
Sign = (OpCode & BIT6) == BIT6;
Half = (OpCode & BIT5) == BIT5;
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (Pre & !Write) {
// Immediate offset/index
if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else {
// A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
}
} else {
// Register offset/index
if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else {
// A5.3.7 [<Rn>], +/-<Rm>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
}
}
return;
}
@ -375,21 +370,16 @@ DisassembleArmInstruction (
if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
IMod = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (
Buf,
Size,
"CPS%a %a%a%a",
(IMod == 3) ? "ID" : "IE",
((OpCode & BIT8) != 0) ? "A" : "",
((OpCode & BIT7) != 0) ? "I" : "",
((OpCode & BIT6) != 0) ? "F" : ""
);
IMod = (OpCode >> 18) & 0x3;
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
(IMod == 3) ? "ID":"IE",
((OpCode & BIT8) != 0) ? "A":"",
((OpCode & BIT7) != 0) ? "I":"",
((OpCode & BIT6) != 0) ? "F":"");
if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
}
}
return;
}
@ -405,16 +395,16 @@ DisassembleArmInstruction (
return;
}
if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else {
// MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
}
return;
}
@ -427,34 +417,35 @@ DisassembleArmInstruction (
if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) {
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
} else {
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
}
if (!Pre) {
if (!Write) {
// A5.5.5.5 [<Rn>], <option>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
}
} else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
}
}
if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return;
}
@ -463,3 +454,4 @@ DisassembleArmInstruction (
*OpCodePtr += 1;
return;
}

File diff suppressed because it is too large Load Diff

View File

@ -14,39 +14,39 @@
#include <Library/MemoryAllocationLib.h>
#include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION
UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
VOID
RegisterEl0Stack (
IN VOID *Stack
IN VOID *Stack
);
RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress
IN UINTN VectorBaseAddress
)
{
UINTN HcrReg;
UINTN HcrReg;
// Round down sp by 16 bytes alignment
RegisterEl0Stack (
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
);
if (ArmReadCurrentEL () == AARCH64_EL2) {
HcrReg = ArmReadHcr ();
if (ArmReadCurrentEL() == AARCH64_EL2) {
HcrReg = ArmReadHcr();
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
HcrReg |= ARM_HCR_TGE;
ArmWriteHcr (HcrReg);
ArmWriteHcr(HcrReg);
}
return RETURN_SUCCESS;

View File

@ -17,27 +17,28 @@
#include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION
UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
// Exception handler contains branch to vector location (jmp $) so no handler
// NOTE: This code assumes vectors are ARM and not Thumb code
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress
IN UINTN VectorBaseAddress
)
{
// if the vector address corresponds to high vectors
if (VectorBaseAddress == 0xFFFF0000) {
// set SCTLR.V to enable high vectors
ArmSetHighVectors ();
} else {
ArmSetHighVectors();
}
else {
// Set SCTLR.V to 0 to enable VBAR to be used
ArmSetLowVectors ();
ArmSetLowVectors();
}
return RETURN_SUCCESS;

View File

@ -22,38 +22,37 @@
STATIC
RETURN_STATUS
CopyExceptionHandlers (
IN PHYSICAL_ADDRESS BaseAddress
CopyExceptionHandlers(
IN PHYSICAL_ADDRESS BaseAddress
);
EFI_STATUS
EFIAPI
RegisterExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
RegisterExceptionHandler(
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
VOID
ExceptionHandlersStart (
ExceptionHandlersStart(
VOID
);
VOID
ExceptionHandlersEnd (
ExceptionHandlersEnd(
VOID
);
RETURN_STATUS
ArchVectorConfig (
IN UINTN VectorBaseAddress
RETURN_STATUS ArchVectorConfig(
IN UINTN VectorBaseAddress
);
// these globals are provided by the architecture specific source (Arm or AArch64)
extern UINTN gMaxExceptionNumber;
extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
extern UINTN gDebuggerNoHandlerValue;
extern UINTN gMaxExceptionNumber;
extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
extern UINTN gDebuggerNoHandlerValue;
// A compiler flag adjusts the compilation of this library to a variant where
// the vectors are relocated (copied) to another location versus using the
@ -61,12 +60,13 @@ extern UINTN gDebuggerNoHandlerValue;
// address this at library build time. Since this affects the build of the
// library we cannot represent this in a PCD since PCDs are evaluated on
// a per-module basis.
#if defined (ARM_RELOCATE_VECTORS)
STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
#if defined(ARM_RELOCATE_VECTORS)
STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
#else
STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
#endif
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
@ -85,21 +85,23 @@ with default exception handlers.
**/
EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
InitializeCpuExceptionHandlers(
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
RETURN_STATUS Status;
UINTN VectorBase;
RETURN_STATUS Status;
UINTN VectorBase;
Status = EFI_SUCCESS;
// if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) {
VectorBase = PcdGet64 (PcdCpuVectorBaseAddress);
Status = CopyExceptionHandlers (VectorBase);
} else {
// use VBAR to point to where our exception handlers are
VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
Status = CopyExceptionHandlers(VectorBase);
}
else { // use VBAR to point to where our exception handlers are
// The vector table must be aligned for the architecture. If this
// assertion fails ensure the appropriate FFS alignment is in effect,
@ -108,7 +110,7 @@ InitializeCpuExceptionHandlers (
// for AArch64 Align=4K is required. Align=Auto can be used but this
// is known to cause an issue with populating the reset vector area
// for encapsulated FVs.
ASSERT (((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector
// Base Address to point into CpuDxe code.
@ -117,12 +119,12 @@ InitializeCpuExceptionHandlers (
Status = RETURN_SUCCESS;
}
if (!RETURN_ERROR (Status)) {
if (!RETURN_ERROR(Status)) {
// call the architecture-specific routine to prepare for the new vector
// configuration to take effect
ArchVectorConfig (VectorBase);
ArchVectorConfig(VectorBase);
ArmWriteVBar (VectorBase);
ArmWriteVBar(VectorBase);
}
return RETURN_SUCCESS;
@ -146,14 +148,14 @@ with default exception handlers.
**/
STATIC
RETURN_STATUS
CopyExceptionHandlers (
IN PHYSICAL_ADDRESS BaseAddress
CopyExceptionHandlers(
IN PHYSICAL_ADDRESS BaseAddress
)
{
RETURN_STATUS Status;
UINTN Length;
UINTN Index;
UINT32 *VectorBase;
RETURN_STATUS Status;
UINTN Length;
UINTN Index;
UINT32 *VectorBase;
// ensure that the destination value specifies an address meeting the vector alignment requirements
ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0);
@ -165,35 +167,37 @@ CopyExceptionHandlers (
VectorBase = (UINT32 *)(UINTN)BaseAddress;
if (FeaturePcdGet (PcdDebuggerExceptionSupport) == TRUE) {
if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {
// Save existing vector table, in case debugger is already hooked in
CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
CopyMem((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
}
// Copy our assembly code into the page that contains the exception vectors.
CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
CopyMem((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
//
// Initialize the C entry points for interrupts
//
for (Index = 0; Index <= gMaxExceptionNumber; Index++) {
if (!FeaturePcdGet (PcdDebuggerExceptionSupport) ||
(gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue))
{
Status = RegisterExceptionHandler (Index, NULL);
ASSERT_EFI_ERROR (Status);
} else {
if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||
(gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue)) {
Status = RegisterExceptionHandler(Index, NULL);
ASSERT_EFI_ERROR(Status);
}
else {
// If the debugger has already hooked put its vector back
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
}
}
// Flush Caches since we updated executable stuff
InvalidateInstructionCacheRange ((VOID *)(UINTN)BaseAddress, Length);
InvalidateInstructionCacheRange((VOID *)(UINTN)BaseAddress, Length);
return RETURN_SUCCESS;
}
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
@ -212,9 +216,9 @@ with default interrupt/exception handlers.
**/
EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
InitializeCpuInterruptHandlers(
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
// not needed, this is what the CPU driver is for
return EFI_UNSUPPORTED;
@ -246,9 +250,9 @@ previously installed.
or this function is not supported.
**/
RETURN_STATUS
RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
RegisterCpuInterruptHandler(
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
)
{
if (ExceptionType > gMaxExceptionNumber) {
@ -283,19 +287,19 @@ If this parameter is NULL, then the handler will be uninstalled.
**/
EFI_STATUS
EFIAPI
RegisterExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
RegisterExceptionHandler(
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
return RegisterCpuInterruptHandler(ExceptionType, InterruptHandler);
}
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
CommonCExceptionHandler(
IN EFI_EXCEPTION_TYPE ExceptionType,
IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
if (ExceptionType <= gMaxExceptionNumber) {
@ -303,12 +307,13 @@ CommonCExceptionHandler (
gExceptionHandlers[ExceptionType](ExceptionType, SystemContext);
return;
}
} else {
DEBUG ((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
ASSERT (FALSE);
}
else {
DEBUG((EFI_D_ERROR, "Unknown exception type %d\n", ExceptionType));
ASSERT(FALSE);
}
DefaultExceptionHandler (ExceptionType, SystemContext);
DefaultExceptionHandler(ExceptionType, SystemContext);
}
/**
@ -336,9 +341,10 @@ CommonCExceptionHandler (
EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
}

View File

@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer (
VOID
)
{
UINTN TimerCtrlReg;
UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer (
VOID
)
{
UINTN TimerCtrlReg;
UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@ -71,10 +71,11 @@ ArmGenericTimerGetTimerVal (
return ArmReadCntpTval ();
}
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
IN UINTN Value
IN UINTN Value
)
{
ArmWriteCntpTval (Value);
@ -101,7 +102,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
UINTN Value
UINTN Value
)
{
ArmWriteCntpCtl (Value);
@ -119,7 +120,7 @@ ArmGenericTimerGetCompareVal (
VOID
EFIAPI
ArmGenericTimerSetCompareVal (
IN UINT64 Value
IN UINT64 Value
)
{
ArmWriteCntpCval (Value);

View File

@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer (
VOID
)
{
UINTN TimerCtrlReg;
UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer (
VOID
)
{
UINTN TimerCtrlReg;
UINTN TimerCtrlReg;
TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@ -71,10 +71,11 @@ ArmGenericTimerGetTimerVal (
return ArmReadCntvTval ();
}
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
IN UINTN Value
IN UINTN Value
)
{
ArmWriteCntvTval (Value);
@ -101,7 +102,7 @@ ArmGenericTimerGetTimerCtrlReg (
VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
UINTN Value
UINTN Value
)
{
ArmWriteCntvCtl (Value);
@ -119,7 +120,7 @@ ArmGenericTimerGetCompareVal (
VOID
EFIAPI
ArmGenericTimerSetCompareVal (
IN UINT64 Value
IN UINT64 Value
)
{
ArmWriteCntvCval (Value);

View File

@ -9,7 +9,7 @@
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS
EFIAPI
@ -17,7 +17,7 @@ ArmGicArchLibInitialize (
VOID
)
{
UINT32 IccSre;
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@ -38,7 +38,6 @@ ArmGicArchLibInitialize (
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done;

View File

@ -15,7 +15,7 @@ ArmGicGetSupportedArchRevision (
VOID
)
{
UINT32 IccSre;
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@ -36,7 +36,6 @@ ArmGicGetSupportedArchRevision (
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}

View File

@ -23,10 +23,10 @@ AArch64DataCacheOperation (
IN AARCH64_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmDisableInterrupts();
AArch64AllDataCachesOperation (DataCacheOperation);
@ -99,7 +99,7 @@ ArmHasCcidx (
VOID
)
{
UINTN Mmfr2;
UINTN Mmfr2;
Mmfr2 = ArmReadIdAA64Mmfr2 ();
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;

View File

@ -11,9 +11,7 @@
#ifndef AARCH64_LIB_H_
#define AARCH64_LIB_H_
typedef VOID (*AARCH64_CACHE_OPERATION)(
UINTN
);
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
VOID
AArch64AllDataCachesOperation (
@ -35,7 +33,7 @@ ArmCleanDataCacheEntryBySetWay (
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay (
IN UINTN SetWayFormat
IN UINTN SetWayFormat
);
UINTN
@ -55,3 +53,4 @@ ArmReadIdAA64Mmfr2 (
);
#endif // AARCH64_LIB_H_

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