UefiPayloadPkg: Enable ESRT

Signed-off-by: Tim Crawford <tcrawford@system76.com>

.azurepipelines/ReadMe.md

@@ -0,0 +1,50 @@
+# Azure DevOps Pipelines
+
+These yml files are used to provide CI builds using the Azure DevOps Pipeline Service.
+Most of the CI leverages edk2-pytools to support cross platform building and execution.
+
+## Core CI
+
+Focused on building and testing all packages in Edk2 without an actual target platform.
+
+See `.pytools/ReadMe.py` for more details
+
+## Platform CI
+
+Focused on building a single target platform and confirming functionality on that platform.
+
+## Conventions
+
+* Files extension should be *.yml.  *.yaml is also supported but in Edk2 we use those for our package configuration.
+* Platform CI files should be in the `<PlatformPkg>/.azurepipelines` folder.
+* Core CI files are in the root folder.
+* Shared templates are in the `templates` folder.
+* Top level CI files should be named `<host os>-<tool_chain_tag>.yml`
+
+## Links
+
+* Basic Azure Landing Site - https://docs.microsoft.com/en-us/azure/devops/pipelines/?view=azure-devops
+* Pipeline jobs - https://docs.microsoft.com/en-us/azure/devops/pipelines/process/phases?view=azure-devops&tabs=yaml
+* Pipeline yml scheme - https://docs.microsoft.com/en-us/azure/devops/pipelines/yaml-schema?view=azure-devops&tabs=schema%2Cparameter-schema
+* Pipeline expression - https://docs.microsoft.com/en-us/azure/devops/pipelines/process/expressions?view=azure-devops
+* PyTools - https://github.com/tianocore/edk2-pytool-extensions and https://github.com/tianocore/edk2-pytool-library
+
+## Lessons Learned
+
+### Templates and parameters
+
+They are great but evil.  If they are used as part of determining the steps of a build they must resolve before the build starts.  They can not use variables set in a yml or determined as part of a matrix.  If they are used in a step then they can be bound late.
+
+### File matching patterns
+
+On Linux this can hang if there are too many files in the search list.
+
+### Templates and file splitting
+
+Suggestion is to do one big yaml file that does what you want for one of your targets.  Then do the second one and find the deltas.  From that you can start to figure out the right split of files, steps, jobs.
+
+### Conditional steps
+
+If you want the step to show up in the log but not run, use a step conditional. This is great when a platform doesn't currently support a feature but you want the builders to know that the features exists and maybe someday it will.
+
+If you want the step to not show up use a template step conditional wrapper.  Beware this will be evaluated early (at build start).  This can hide things not needed on a given OS for example.

.azurepipelines/Ubuntu-GCC5.yml

@@ -2,17 +2,20 @@
 # Azure Pipeline build file for a build using ubuntu and GCC5
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 trigger:
 - master
+- stable/*
 pr:
 - master
+- stable/*
 
 jobs:
 - template: templates/pr-gate-build-job.yml
   parameters:
     tool_chain_tag: 'GCC5'
     vm_image: 'ubuntu-latest'
-    arch_list: "IA32,X64,ARM,AARCH64"
+    arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
 

.azurepipelines/Ubuntu-PatchCheck.yml

@@ -5,7 +5,7 @@
 # NOTE: This example monitors pull requests against the edk2-ci branch.  Most
 # environments would replace 'edk2-ci' with 'master'.
 #
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 # https://github.com/tianocore
@@ -16,6 +16,7 @@ trigger: none
 
 pr:
 - master
+- stable/*
 
 pool:
   vmImage: 'ubuntu-latest'

.azurepipelines/Windows-VS2019.yml

@@ -6,9 +6,11 @@
 ##
 trigger:
 - master
+- stable/*
 
 pr:
 - master
+- stable/*
 
 jobs:
 - template: templates/pr-gate-build-job.yml

.azurepipelines/templates/ReadMe.md

@@ -0,0 +1,59 @@
+# CI Templates
+
+This folder contains azure pipeline yml templates for "Core" and "Platform" Continuous Integration and PR validation.
+
+## Common CI templates
+
+### basetools-build-steps.yml
+
+This template compiles the Edk2 basetools from source.  The steps in this template are
+conditional and will only run if variable `pkg_count` is greater than 0.
+
+It also has two conditional steps only used when the toolchain contains GCC. These two steps
+use `apt` to update the system packages and add those necessary for Edk2 builds.
+
+## Core CI templates
+
+### pr-gate-build-job.yml
+
+This templates contains the jobs and most importantly the matrix of which packages and
+targets to run for Core CI.
+
+### pr-gate-steps.yml
+
+This template is the main Core CI template.  It controls all the steps run and is responsible for most functionality of the Core CI process.  This template sets
+the `pkg_count` variable using the `stuart_pr_eval` tool when the
+build type is "pull request"
+
+### spell-check-prereq-steps.yml
+
+This template installs the node based tools used by the spell checker plugin. The steps
+in this template are conditional and will only run if variable `pkg_count` is greater than 0.
+
+## Platform CI templates
+
+### platform-build-run-steps.yml
+
+This template makes heavy use of pytools to build and run a platform in the Edk2 repo
+
+Also uses basetools-build-steps.yml to compile basetools
+
+#### Special Notes
+
+* For a build type of pull request it will conditionally build if the patches change files that impact the platform.
+  * uses `stuart_pr_eval` to determine impact
+* For manual builds or CI builds it will always build the platform
+* It compiles basetools from source
+* Will use `stuart_build --FlashOnly` to attempt to run the built image if the `Run` parameter is set.
+* See the parameters block for expected configuration options
+* Parameter `extra_install_step` allows the caller to insert extra steps.  This is useful if additional dependencies, tools, or other things need to be installed.  Here is an example of installing qemu on Windows.
+
+    ``` yaml
+    steps:
+    - template: ../../.azurepipelines/templates/build-run-steps.yml
+      parameters:
+        extra_install_step:
+        - powershell: choco install qemu; Write-Host "##vso[task.prependpath]c:\Program Files\qemu"
+          displayName: Install QEMU and Set QEMU on path # friendly name displayed in the UI
+          condition: and(gt(variables.pkg_count, 0), succeeded())
+    ```

.azurepipelines/templates/platform-build-run-steps.yml

@@ -0,0 +1,140 @@
+
+## @file
+# File steps.yml
+#
+# template file containing the steps to build
+#
+# Copyright (c) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+parameters:
+- name: tool_chain_tag
+  type: string
+  default: ''
+- name: build_pkg
+  type: string
+  default: ''
+- name: build_target
+  type: string
+  default: ''
+- name: build_arch
+  type: string
+  default: ''
+- name: build_file
+  type: string
+  default: ''
+- name: build_flags
+  type: string
+  default: ''
+- name: run_flags
+  type: string
+  default: ''
+
+- name: extra_install_step
+  type: stepList
+  default: []
+
+steps:
+- checkout: self
+  clean: true
+  fetchDepth: 1
+
+- task: UsePythonVersion@0
+  inputs:
+    versionSpec: "3.8.x"
+    architecture: "x64"
+
+- script: pip install -r pip-requirements.txt --upgrade
+  displayName: 'Install/Upgrade pip modules'
+
+# Set default
+- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
+
+# Fetch the target branch so that pr_eval can diff them.
+# Seems like azure pipelines/github changed checkout process in nov 2020.
+- script: git fetch origin $(System.PullRequest.targetBranch)
+  displayName: fetch target branch
+  condition: eq(variables['Build.Reason'], 'PullRequest')
+
+# trim the package list if this is a PR
+- task: CmdLine@1
+  displayName: Check if ${{ parameters.build_pkg }} need testing
+  inputs:
+    filename: stuart_pr_eval
+    arguments: -c ${{ parameters.build_file }} -t ${{ parameters.build_target}} -a ${{ parameters.build_arch}} --pr-target origin/$(System.PullRequest.targetBranch) --output-count-format-string "##vso[task.setvariable variable=pkg_count;isOutpout=true]{pkgcount}"
+  condition: eq(variables['Build.Reason'], 'PullRequest')
+
+ # Setup repo
+- task: CmdLine@1
+  displayName: Setup
+  inputs:
+    filename: stuart_setup
+    arguments: -c ${{ parameters.build_file }} TOOL_CHAIN_TAG=${{ parameters.tool_chain_tag}} -t ${{ parameters.build_target}} -a ${{ parameters.build_arch}} ${{ parameters.build_flags}}
+  condition: and(gt(variables.pkg_count, 0), succeeded())
+
+# Stuart Update
+- task: CmdLine@1
+  displayName: Update
+  inputs:
+    filename: stuart_update
+    arguments: -c ${{ parameters.build_file }} TOOL_CHAIN_TAG=${{ parameters.tool_chain_tag}} -t ${{ parameters.build_target}} -a ${{ parameters.build_arch}} ${{ parameters.build_flags}}
+  condition: and(gt(variables.pkg_count, 0), succeeded())
+
+# build basetools
+#   do this after setup and update so that code base dependencies
+#   are all resolved.
+- template: basetools-build-steps.yml
+  parameters:
+    tool_chain_tag: ${{ parameters.tool_chain_tag }}
+
+# Potential Extra steps
+- ${{ parameters.extra_install_step }}
+
+# Build
+- task: CmdLine@1
+  displayName: Build
+  inputs:
+    filename: stuart_build
+    arguments: -c ${{ parameters.build_file }} TOOL_CHAIN_TAG=${{ parameters.tool_chain_tag}} TARGET=${{ parameters.build_target}} -a ${{ parameters.build_arch}} ${{ parameters.build_flags}}
+  condition: and(gt(variables.pkg_count, 0), succeeded())
+
+# Run
+- task: CmdLine@1
+  displayName: Run to shell
+  inputs:
+    filename: stuart_build
+    arguments: -c ${{ parameters.build_file }} TOOL_CHAIN_TAG=${{ parameters.tool_chain_tag}} TARGET=${{ parameters.build_target}} -a ${{ parameters.build_arch}} ${{ parameters.build_flags}} ${{ parameters.run_flags }} --FlashOnly
+  condition: and(and(gt(variables.pkg_count, 0), succeeded()), eq(variables['Run'], true))
+  timeoutInMinutes: 1
+
+# Copy the build logs to the artifact staging directory
+- task: CopyFiles@2
+  displayName: "Copy build logs"
+  inputs:
+    targetFolder: "$(Build.ArtifactStagingDirectory)"
+    SourceFolder: "Build"
+    contents: |
+      BUILDLOG_*.txt
+      BUILDLOG_*.md
+      CI_*.txt
+      CI_*.md
+      CISETUP.txt
+      SETUPLOG.txt
+      UPDATE_LOG.txt
+      PREVALLOG.txt
+      TestSuites.xml
+      **/BUILD_TOOLS_REPORT.html
+      **/OVERRIDELOG.TXT
+      BASETOOLS_BUILD*.*
+    flattenFolders: true
+  condition: succeededOrFailed()
+
+# Publish build artifacts to Azure Artifacts/TFS or a file share
+- task: PublishBuildArtifacts@1
+  continueOnError: true
+  displayName: "Publish build logs"
+  inputs:
+    pathtoPublish: "$(Build.ArtifactStagingDirectory)"
+    artifactName: "Build Logs $(System.JobName)"
+  condition: succeededOrFailed()

.azurepipelines/templates/pr-gate-build-job.yml

@@ -4,6 +4,7 @@
 # template file used to build supported packages.
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 
@@ -20,6 +21,9 @@ jobs:
   #Use matrix to speed up the build process
   strategy:
     matrix:
+      TARGET_ARM_ARMPLATFORM:
+        Build.Pkgs: 'ArmPkg,ArmPlatformPkg'
+        Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
       TARGET_MDE_CPU:
         Build.Pkgs: 'MdePkg,UefiCpuPkg'
         Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
@@ -30,20 +34,25 @@ jobs:
         Build.Pkgs: 'MdeModulePkg'
         Build.Targets: 'RELEASE,NO-TARGET'
       TARGET_NETWORK:
-        Build.Pkgs: 'NetworkPkg'
+        Build.Pkgs: 'NetworkPkg,RedfishPkg'
         Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
       TARGET_OTHER:
-        Build.Pkgs: 'PcAtChipsetPkg,ShellPkg'
+        Build.Pkgs: 'PcAtChipsetPkg,ShellPkg,StandaloneMmPkg'
         Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
       TARGET_FMP_FAT_TEST:
-        Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg'
+        Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg,DynamicTablesPkg'
         Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
       TARGET_CRYPTO:
         Build.Pkgs: 'CryptoPkg'
-        Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
+        Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
       TARGET_SECURITY:
         Build.Pkgs: 'SecurityPkg'
         Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
+      TARGET_PLATFORMS:
+        # For Platforms only check code. Leave it to Platform CI
+        # to build them.
+        Build.Pkgs: 'ArmVirtPkg,EmulatorPkg,OvmfPkg'
+        Build.Targets: 'NO-TARGET'
 
   workspace:
     clean: all
@@ -58,23 +67,3 @@ jobs:
       build_pkgs: $(Build.Pkgs)
       build_targets: $(Build.Targets)
       build_archs: ${{ parameters.arch_list }}
-
-- job: FINISHED
-  dependsOn: Build_${{ parameters.tool_chain_tag }}
-  condition: succeeded()
-  steps:
-  - checkout: none
-  - script: |
-      echo FINISHED
-      sleep 10
-    displayName: FINISHED
-
-- job: FAILED
-  dependsOn: Build_${{ parameters.tool_chain_tag }}
-  condition: failed()
-  steps:
-  - checkout: none
-  - script: |
-      echo FAILED
-      sleep 10
-    displayName: FAILED

.azurepipelines/templates/pr-gate-steps.yml

@@ -20,7 +20,7 @@ steps:
 
 - task: UsePythonVersion@0
   inputs:
-    versionSpec: '3.7.x'
+    versionSpec: '3.8.x'
     architecture: 'x64'
 
 - script: pip install -r pip-requirements.txt --upgrade
@@ -31,6 +31,12 @@ steps:
     echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
     echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
 
+# Fetch the target branch so that pr_eval can diff them.
+# Seems like azure pipelines/github changed checkout process in nov 2020.
+- script: git fetch origin $(System.PullRequest.targetBranch)
+  displayName: fetch target branch
+  condition: eq(variables['Build.Reason'], 'PullRequest')
+
 # trim the package list if this is a PR
 - task: CmdLine@1
   displayName: Check if ${{ parameters.build_pkgs }} need testing
@@ -39,11 +45,6 @@ steps:
     arguments: -c .pytool/CISettings.py -p ${{ parameters.build_pkgs }} --pr-target origin/$(System.PullRequest.targetBranch) --output-csv-format-string "##vso[task.setvariable variable=pkgs_to_build;isOutpout=true]{pkgcsv}" --output-count-format-string "##vso[task.setvariable variable=pkg_count;isOutpout=true]{pkgcount}"
   condition: eq(variables['Build.Reason'], 'PullRequest')
 
-# build basetools
-- template: basetools-build-steps.yml
-  parameters:
-    tool_chain_tag: ${{ parameters.tool_chain_tag }}
-
 # install spell check prereqs
 - template: spell-check-prereq-steps.yml
 
@@ -62,6 +63,13 @@ steps:
     arguments: -c .pytool/CISettings.py -p $(pkgs_to_build) -t ${{ parameters.build_targets}} -a ${{ parameters.build_archs}} TOOL_CHAIN_TAG=${{ parameters.tool_chain_tag}}
   condition: and(gt(variables.pkg_count, 0), succeeded())
 
+# build basetools
+#   do this after setup and update so that code base dependencies
+#   are all resolved.
+- template: basetools-build-steps.yml
+  parameters:
+    tool_chain_tag: ${{ parameters.tool_chain_tag }}
+
 - task: CmdLine@1
   displayName: Build and Test ${{ parameters.build_pkgs }} ${{ parameters.build_archs}}
   inputs:

.azurepipelines/templates/spell-check-prereq-steps.yml

@@ -13,7 +13,7 @@ parameters:
 steps:
 - task: NodeTool@0
   inputs:
-    versionSpec: '10.x'
+    versionSpec: '14.x'
     #checkLatest: false # Optional
   condition: and(gt(variables.pkg_count, 0), succeeded())
 

.gitmodules

@@ -6,4 +6,17 @@
 	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
 [submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
 	path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
-	url = https://git.cryptomilk.org/projects/cmocka.git
+	url = https://github.com/tianocore/edk2-cmocka.git
+[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
+	path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
+	url = https://github.com/kkos/oniguruma
+[submodule "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli"]
+	path = MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
+	url = https://github.com/google/brotli
+[submodule "BaseTools/Source/C/BrotliCompress/brotli"]
+	path = BaseTools/Source/C/BrotliCompress/brotli
+	url = https://github.com/google/brotli
+	ignore = untracked
+[submodule "RedfishPkg/Library/JsonLib/jansson"]
+	path = RedfishPkg/Library/JsonLib/jansson
+	url = https://github.com/akheron/jansson

.mailmap

@@ -1,8 +1,7 @@
 #
-# This list is used by git-shortlog to fix a few botched name translations
-# in the git archive, either because the author's full name was messed up
-# and/or not always written the same way, making contributions from the
-# same person appearing not to be so or badly displayed.
+# This list is used by git-shortlog to update a few name translations
+# in the git archive to adjust for job changes or incorrect/inconsistent
+# name usage.
 #
 # Please keep this file sorted alphabetically, and email in lowercase.
 # The format used is:
@@ -23,6 +22,8 @@ Eric Dong <eric.dong@intel.com> Eric Dong <eirc.dong@intel.com>
 Eric Dong <eric.dong@intel.com> <ydong10@6f19259b-4bc3-4df7-8a09-765794883524>
 Eric Dong <eric.dong@intel.com> <ydong10@Edk2>
 Erik Bjorge <erik.c.bjorge@intel.com> <geekboy15a@6f19259b-4bc3-4df7-8a09-765794883524>
+Eugene Cohen <eugene@nuviainc.com>
+Eugene Cohen <eugene@nuviainc.com> <eugene@hp.com>
 Hao A Wu <hao.a.wu@intel.com>
 Hao A Wu <hao.a.wu@intel.com> <hwu1225@Edk2>
 Hot Tian <hot.tian@intel.com>
@@ -37,6 +38,7 @@ Jim Dailey <Jim.Dailey@Dell.com>
 Jim Dailey <Jim.Dailey@Dell.com> <Jim_Dailey@Dell.com>
 Laszlo Ersek <lersek@redhat.com> <lersek@6f19259b-4bc3-4df7-8a09-765794883524>
 Laszlo Ersek <lersek@redhat.com> <lersek@Edk2>
+Liming Gao <gaoliming@byosoft.com.cn>
 Liming Gao <liming.gao@intel.com> <Gao, Liming liming.gao@intel.com>
 Liming Gao <liming.gao@intel.com> <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>
 Liming Gao <liming.gao@intel.com> <lgao4@Edk2>
@@ -46,6 +48,7 @@ Marc-André Lureau <marcandre.lureau@redhat.com> <marcandre.lureau@redhat.com>
 Marvin Häuser <Marvin.Haeuser@outlook.com>
 Marvin Häuser <Marvin.Haeuser@outlook.com> edk2-devel <edk2-devel-bounces@lists.01.org>
 Marvin Häuser <mhaeuser@outlook.de>
+Matt DeVillier <matt.devillier@gmail.com>
 Maurice Ma <maurice.ma@intel.com>
 Michael Kubacki <michael.a.kubacki@intel.com>
 Michael Kubacki <michael.a.kubacki@intel.com> </o=Intel/ou=External (FYDIBOHF25SPDLT)/cn=Recipients/cn=3c8b0226e75f4ab08d20c151cb7a8a72>
@@ -59,14 +62,20 @@ Ray Ni <ray.ni@intel.com> <niruiyu@Edk2>
 Ray Ni <ray.ni@intel.com> <ruiyu.ni@intel.com>
 Ray Ni <ray.ni@intel.com> <Ruiyu.ni@Intel.com>
 Ray Ni <ray.ni@intel.com> <ruyu.ni@intel.com>
+Rebecca Cran <rebecca@bluestop.org>
+Rebecca Cran <rebecca@bsdio.com>
 Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <elhaj@hpe.com>
 Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <Samer El-Haj-Mahmoud elhaj@hp.com>
 Shenglei Zhang <shenglei.zhang@intel.com>
 Star Zeng <star.zeng@intel.com>
 Star Zeng <star.zeng@intel.com> <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524>
 Star Zeng <star.zeng@intel.com> <lzeng14@Edk2>
+Tom Lendacky <thomas.lendacky@amd.com>
 Vitaly Cheptsov <vit9696@protonmail.com> Vitaly Cheptsov via Groups.Io <vit9696=protonmail.com@groups.io>
 Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Vladimir Olovyannikov via edk2-devel <edk2-devel@lists.01.org>
+Wei6 Xu <wei6.xu@intel.com>
 Yonghong Zhu <yonghong.zhu@intel.com>
 Yonghong Zhu <yonghong.zhu@intel.com> <yzhu52@Edk2>
 Yu-Chen Lin <yuchenlin@synology.com>
+Zhichao Gao <zhichao.gao@intel.com>
+Zhiguang Liu <zhiguang.liu@intel.com>

.mergify/config.yml

@@ -16,7 +16,7 @@
 # * This file must be checked into the 'default' branch of a repo.  Copies
 #   of this file on other branches of a repo are ignored by Mergify.
 #
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 # https://github.com/apps/mergify
@@ -24,74 +24,27 @@
 #
 ##
 
-pull_request_rules:
+queue_rules:
+  - name: default
+    conditions:
+      - base~=(^main|^master|^stable/)
+      - label=push
 
+pull_request_rules:
   - name: Automatically merge a PR when all required checks pass and 'push' label is present
     conditions:
-      - base=master
+      - base~=(^main|^master|^stable/)
       - label=push
-      - author=@tianocore/edk-ii-maintainers
-      - status-success=tianocore.PatchCheck
-      - status-success=Ubuntu GCC5 PR
-      - status-success=Windows VS2019 PR
     actions:
-      merge:
-        strict: true
+      queue:
         method: rebase
-
-  - name: Automatically close a PR when all required checks pass and 'push' label is not present
-    conditions:
-      - base=master
-      - -label=push
-      - -closed
-      - status-success=tianocore.PatchCheck
-      - status-success=Ubuntu GCC5 PR
-      - status-success=Windows VS2019 PR
-      - status-success=Ubuntu GCC5 PR (FINISHED)
-      - status-success=Windows VS2019 PR (FINISHED)
-    actions:
-      close:
-        message: All checks passed. Auto close personal build.
+        rebase_fallback: none
+        name: default
 
   - name: Post a comment on a PR that can not be merged due to a merge conflict
     conditions:
-      - base=master
+      - base~=(^main|^master|^stable/)
       - conflict
     actions:
       comment:
         message: PR can not be merged due to conflict.  Please rebase and resubmit
-
-  - name: Automatically close a PR that fails the EDK II Maintainers membership check and 'push' label is present
-    conditions:
-      - base=master
-      - label=push
-      - -author=@tianocore/edk-ii-maintainers
-    actions:
-      close:
-        message: PR submitter is not a member of the Tianocore EDK II Maintainers team
-
-  - name: Post a comment on a PR if PatchCheck fails
-    conditions:
-      - base=master
-      - status-failure=tianocore.PatchCheck
-    actions:
-      comment:
-        message: PR can not be merged due to a PatchCheck failure.  Please resolve and resubmit
-
-  - name: Post a comment on a PR if Ubuntu GCC5 fails
-    conditions:
-      - base=master
-      - status-failure=Ubuntu GCC5 PR
-      - status-success=Ubuntu GCC5 PR (FAILED)
-    actions:
-      comment:
-        message: PR can not be merged due to an Ubuntu GCC5 failure.  Please resolve and resubmit
-
-  - name: Post a comment on a PR if Windows VS2019 fails
-    conditions:
-      - base=master
-      - status-failure=Windows VS2019 PR
-      - status-success=Windows VS2019 PR (FAILED)
-    actions:
-      comment:
-        message: PR can not be merged due to a Windows VS2019 failure.  Please resolve and resubmit

.pytool/CISettings.py

@@ -1,6 +1,8 @@
 # @file
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 import os
@@ -20,16 +22,24 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
         self.ActualTargets = []
         self.ActualArchitectures = []
         self.ActualToolChainTag = ""
+        self.UseBuiltInBaseTools = None
+        self.ActualScopes = None
 
     # ####################################################################################### #
     #                             Extra CmdLine configuration                                 #
     # ####################################################################################### #
 
     def AddCommandLineOptions(self, parserObj):
-        pass
+        group = parserObj.add_mutually_exclusive_group()
+        group.add_argument("-force_piptools", "--fpt", dest="force_piptools", action="store_true", default=False, help="Force the system to use pip tools")
+        group.add_argument("-no_piptools", "--npt", dest="no_piptools", action="store_true", default=False, help="Force the system to not use pip tools")
 
     def RetrieveCommandLineOptions(self, args):
-        pass
+        super().RetrieveCommandLineOptions(args)
+        if args.force_piptools:
+            self.UseBuiltInBaseTools = True
+        if args.no_piptools:
+            self.UseBuiltInBaseTools = False
 
     # ####################################################################################### #
     #                        Default Support for this Ci Build                                #
@@ -39,7 +49,12 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
         ''' return iterable of edk2 packages supported by this build.
         These should be edk2 workspace relative paths '''
 
-        return ("MdePkg",
+        return ("ArmPkg",
+                "ArmPlatformPkg",
+                "ArmVirtPkg",
+                "DynamicTablesPkg",
+                "EmulatorPkg",
+                "MdePkg",
                 "MdeModulePkg",
                 "NetworkPkg",
                 "PcAtChipsetPkg",
@@ -47,17 +62,22 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
                 "UefiCpuPkg",
                 "FmpDevicePkg",
                 "ShellPkg",
+                "StandaloneMmPkg",
                 "FatPkg",
                 "CryptoPkg",
-                "UnitTestFrameworkPkg"
+                "UnitTestFrameworkPkg",
+                "OvmfPkg",
+                "RedfishPkg"
                 )
 
     def GetArchitecturesSupported(self):
         ''' return iterable of edk2 architectures supported by this build '''
-        return ("IA32",
+        return (
+                "IA32",
                 "X64",
                 "ARM",
-                "AARCH64")
+                "AARCH64",
+                "RISCV64")
 
     def GetTargetsSupported(self):
         ''' return iterable of edk2 target tags supported by this build '''
@@ -118,20 +138,38 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
 
     def GetActiveScopes(self):
         ''' return tuple containing scopes that should be active for this process '''
+        if self.ActualScopes is None:
             scopes = ("cibuild", "edk2-build", "host-based-test")
 
             self.ActualToolChainTag = shell_environment.GetBuildVars().GetValue("TOOL_CHAIN_TAG", "")
 
-        if GetHostInfo().os.upper() == "WINDOWS":
-            scopes += ('host-test-win',)
+            is_linux = GetHostInfo().os.upper() == "LINUX"
 
-        if GetHostInfo().os.upper() == "LINUX" and self.ActualToolChainTag.upper().startswith("GCC"):
+            if self.UseBuiltInBaseTools is None:
+                is_linux = GetHostInfo().os.upper() == "LINUX"
+                # try and import the pip module for basetools
+                try:
+                    import edk2basetools
+                    self.UseBuiltInBaseTools = True
+                except ImportError:
+                    self.UseBuiltInBaseTools = False
+                    pass
+
+            if self.UseBuiltInBaseTools == True:
+                scopes += ('pipbuild-unix',) if is_linux else ('pipbuild-win',)
+                logging.warning("Using Pip Tools based BaseTools")
+            else:
+                logging.warning("Falling back to using in-tree BaseTools")
+
+            if is_linux and self.ActualToolChainTag.upper().startswith("GCC"):
                 if "AARCH64" in self.ActualArchitectures:
                     scopes += ("gcc_aarch64_linux",)
                 if "ARM" in self.ActualArchitectures:
                     scopes += ("gcc_arm_linux",)
-
-        return scopes
+                if "RISCV64" in self.ActualArchitectures:
+                    scopes += ("gcc_riscv64_unknown",)
+            self.ActualScopes = scopes
+        return self.ActualScopes
 
     def GetRequiredSubmodules(self):
         ''' return iterable containing RequiredSubmodule objects.
@@ -144,6 +182,14 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
             "CryptoPkg/Library/OpensslLib/openssl", False))
         rs.append(RequiredSubmodule(
             "UnitTestFrameworkPkg/Library/CmockaLib/cmocka", False))
+        rs.append(RequiredSubmodule(
+            "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma", False))
+        rs.append(RequiredSubmodule(
+            "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli", False))
+        rs.append(RequiredSubmodule(
+            "BaseTools/Source/C/BrotliCompress/brotli", False))
+        rs.append(RequiredSubmodule(
+            "RedfishPkg/Library/JsonLib/jansson", False))
         return rs
 
     def GetName(self):

.pytool/Plugin/EccCheck/EccCheck.py

@@ -0,0 +1,311 @@
+# @file EccCheck.py
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+import os
+import shutil
+import re
+import csv
+import xml.dom.minidom
+from typing import List, Dict, Tuple
+import logging
+from io import StringIO
+from edk2toolext.environment import shell_environment
+from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
+from edk2toolext.environment.var_dict import VarDict
+from edk2toollib.utility_functions import RunCmd
+
+
+class EccCheck(ICiBuildPlugin):
+    """
+    A CiBuildPlugin that finds the Ecc issues of newly added code in pull request.
+
+    Configuration options:
+    "EccCheck": {
+        "ExceptionList": [],
+        "IgnoreFiles": []
+    },
+    """
+
+    ReModifyFile = re.compile(r'[B-Q,S-Z]+[\d]*\t(.*)')
+    FindModifyFile = re.compile(r'\+\+\+ b\/(.*)')
+    LineScopePattern = (r'@@ -\d*\,*\d* \+\d*\,*\d* @@.*')
+    LineNumRange = re.compile(r'@@ -\d*\,*\d* \+(\d*)\,*(\d*) @@.*')
+
+    def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
+        """ Provide the testcase name and classname for use in reporting
+            testclassname: a descriptive string for the testcase can include whitespace
+            classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
+
+            Args:
+              packagename: string containing name of package to build
+              environment: The VarDict for the test to run in
+            Returns:
+                a tuple containing the testcase name and the classname
+                (testcasename, classname)
+        """
+        return ("Check for efi coding style for " + packagename, packagename + ".EccCheck")
+
+    ##
+    # External function of plugin.  This function is used to perform the task of the ci_build_plugin Plugin
+    #
+    #   - package is the edk2 path to package.  This means workspace/packagepath relative.
+    #   - edk2path object configured with workspace and packages path
+    #   - PkgConfig Object (dict) for the pkg
+    #   - EnvConfig Object
+    #   - Plugin Manager Instance
+    #   - Plugin Helper Obj Instance
+    #   - Junit Logger
+    #   - output_stream the StringIO output stream from this plugin via logging
+    def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
+        workspace_path = Edk2pathObj.WorkspacePath
+        basetools_path = environment.GetValue("EDK_TOOLS_PATH")
+        python_path = os.path.join(basetools_path, "Source", "Python")
+        env = shell_environment.GetEnvironment()
+        env.set_shell_var('PYTHONPATH', python_path)
+        env.set_shell_var('WORKSPACE', workspace_path)
+        env.set_shell_var('PACKAGES_PATH', os.pathsep.join(Edk2pathObj.PackagePathList))
+        self.ECC_PASS = True
+        self.ApplyConfig(pkgconfig, workspace_path, basetools_path, packagename)
+        modify_dir_list = self.GetModifyDir(packagename)
+        patch = self.GetDiff(packagename)
+        ecc_diff_range = self.GetDiffRange(patch, packagename, workspace_path)
+        self.GenerateEccReport(modify_dir_list, ecc_diff_range, workspace_path, basetools_path)
+        ecc_log = os.path.join(workspace_path, "Ecc.log")
+        self.RevertCode()
+        if self.ECC_PASS:
+            tc.SetSuccess()
+            self.RemoveFile(ecc_log)
+            return 0
+        else:
+            with open(ecc_log, encoding='utf8') as output:
+                ecc_output = output.readlines()
+                for line in ecc_output:
+                    logging.error(line.strip())
+            self.RemoveFile(ecc_log)
+            tc.SetFailed("EccCheck failed for {0}".format(packagename), "Ecc detected issues")
+            return 1
+
+    def RevertCode(self) -> None:
+        submoudle_params = "submodule update --init"
+        RunCmd("git", submoudle_params)
+        reset_params = "reset HEAD --hard"
+        RunCmd("git", reset_params)
+
+    def GetDiff(self, pkg: str) -> List[str]:
+        return_buffer = StringIO()
+        params = "diff --unified=0 origin/master HEAD"
+        RunCmd("git", params, outstream=return_buffer)
+        p = return_buffer.getvalue().strip()
+        patch = p.split("\n")
+        return_buffer.close()
+
+        return patch
+
+    def RemoveFile(self, file: str) -> None:
+        if os.path.exists(file):
+            os.remove(file)
+        return
+
+    def GetModifyDir(self, pkg: str) -> List[str]:
+        return_buffer = StringIO()
+        params = "diff --name-status" + ' HEAD' + ' origin/master'
+        RunCmd("git", params, outstream=return_buffer)
+        p1 = return_buffer.getvalue().strip()
+        dir_list = p1.split("\n")
+        return_buffer.close()
+        modify_dir_list = []
+        for modify_dir in dir_list:
+            file_path = self.ReModifyFile.findall(modify_dir)
+            if file_path:
+                file_dir = os.path.dirname(file_path[0])
+            else:
+                continue
+            if pkg in file_dir and file_dir != pkg:
+                modify_dir_list.append('%s' % file_dir)
+            else:
+                continue
+
+        modify_dir_list = list(set(modify_dir_list))
+        return modify_dir_list
+
+    def GetDiffRange(self, patch_diff: List[str], pkg: str, workingdir: str) -> Dict[str, List[Tuple[int, int]]]:
+        IsDelete = True
+        StartCheck = False
+        range_directory: Dict[str, List[Tuple[int, int]]] = {}
+        for line in patch_diff:
+            modify_file = self.FindModifyFile.findall(line)
+            if modify_file and pkg in modify_file[0] and not StartCheck and os.path.isfile(modify_file[0]):
+                modify_file_comment_dic = self.GetCommentRange(modify_file[0], workingdir)
+                IsDelete = False
+                StartCheck = True
+                modify_file_dic = modify_file[0]
+                modify_file_dic = modify_file_dic.replace("/", os.sep)
+                range_directory[modify_file_dic] = []
+            elif line.startswith('--- '):
+                StartCheck = False
+            elif re.match(self.LineScopePattern, line, re.I) and not IsDelete and StartCheck:
+                start_line = self.LineNumRange.search(line).group(1)
+                line_range = self.LineNumRange.search(line).group(2)
+                if not line_range:
+                    line_range = '1'
+                range_directory[modify_file_dic].append((int(start_line), int(start_line) + int(line_range) - 1))
+                for i in modify_file_comment_dic:
+                    if int(i[0]) <= int(start_line) <= int(i[1]):
+                        range_directory[modify_file_dic].append(i)
+        return range_directory
+
+    def GetCommentRange(self, modify_file: str, workingdir: str) -> List[Tuple[int, int]]:
+        modify_file_path = os.path.join(workingdir, modify_file)
+        with open(modify_file_path) as f:
+            line_no = 1
+            comment_range: List[Tuple[int, int]] = []
+            Start = False
+            for line in f:
+                if line.startswith('/**'):
+                    start_no = line_no
+                    Start = True
+                if line.startswith('**/') and Start:
+                    end_no = line_no
+                    Start = False
+                    comment_range.append((int(start_no), int(end_no)))
+                line_no += 1
+
+        if comment_range and comment_range[0][0] == 1:
+            del comment_range[0]
+        return comment_range
+
+    def GenerateEccReport(self, modify_dir_list: List[str], ecc_diff_range: Dict[str, List[Tuple[int, int]]],
+                           workspace_path: str, basetools_path: str) -> None:
+        ecc_need = False
+        ecc_run = True
+        config = os.path.join(basetools_path, "Source", "Python", "Ecc", "config.ini")
+        exception = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
+        report = os.path.join(workspace_path, "Ecc.csv")
+        for modify_dir in modify_dir_list:
+            target = os.path.join(workspace_path, modify_dir)
+            logging.info('Run ECC tool for the commit in %s' % modify_dir)
+            ecc_need = True
+            ecc_params = "-c {0} -e {1} -t {2} -r {3}".format(config, exception, target, report)
+            return_code = RunCmd("Ecc", ecc_params, workingdir=workspace_path)
+            if return_code != 0:
+                ecc_run = False
+                break
+            if not ecc_run:
+                logging.error('Fail to run ECC tool')
+            self.ParseEccReport(ecc_diff_range, workspace_path)
+
+        if not ecc_need:
+            logging.info("Doesn't need run ECC check")
+
+        revert_params = "checkout -- {}".format(exception)
+        RunCmd("git", revert_params)
+        return
+
+    def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], workspace_path: str) -> None:
+        ecc_log = os.path.join(workspace_path, "Ecc.log")
+        ecc_csv = os.path.join(workspace_path, "Ecc.csv")
+        row_lines = []
+        ignore_error_code = self.GetIgnoreErrorCode()
+        if os.path.exists(ecc_csv):
+            with open(ecc_csv) as csv_file:
+                reader = csv.reader(csv_file)
+                for row in reader:
+                    for modify_file in ecc_diff_range:
+                        if modify_file in row[3]:
+                            for i in ecc_diff_range[modify_file]:
+                                line_no = int(row[4])
+                                if i[0] <= line_no <= i[1] and row[1] not in ignore_error_code:
+                                    row[0] = '\nEFI coding style error'
+                                    row[1] = 'Error code: ' + row[1]
+                                    row[3] = 'file: ' + row[3]
+                                    row[4] = 'Line number: ' + row[4]
+                                    row_line = '\n  *'.join(row)
+                                    row_lines.append(row_line)
+                                    break
+                            break
+        if row_lines:
+            self.ECC_PASS = False
+
+        with open(ecc_log, 'a') as log:
+            all_line = '\n'.join(row_lines)
+            all_line = all_line + '\n'
+            log.writelines(all_line)
+        return
+
+    def ApplyConfig(self, pkgconfig: Dict[str, List[str]], workspace_path: str, basetools_path: str, pkg: str) -> None:
+        if "IgnoreFiles" in pkgconfig:
+            for a in pkgconfig["IgnoreFiles"]:
+                a = os.path.join(workspace_path, pkg, a)
+                a = a.replace(os.sep, "/")
+
+                logging.info("Ignoring Files {0}".format(a))
+                if os.path.exists(a):
+                    if os.path.isfile(a):
+                        self.RemoveFile(a)
+                    elif os.path.isdir(a):
+                        shutil.rmtree(a)
+                else:
+                    logging.error("EccCheck.IgnoreInf -> {0} not found in filesystem.  Invalid ignore files".format(a))
+
+        if "ExceptionList" in pkgconfig:
+            exception_list = pkgconfig["ExceptionList"]
+            exception_xml = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
+            try:
+                logging.info("Appending exceptions")
+                self.AppendException(exception_list, exception_xml)
+            except Exception as e:
+                logging.error("Fail to apply exceptions")
+                raise e
+        return
+
+    def AppendException(self, exception_list: List[str], exception_xml: str) -> None:
+        error_code_list = exception_list[::2]
+        keyword_list = exception_list[1::2]
+        dom_tree = xml.dom.minidom.parse(exception_xml)
+        root_node = dom_tree.documentElement
+        for error_code, keyword in zip(error_code_list, keyword_list):
+            customer_node = dom_tree.createElement("Exception")
+            keyword_node = dom_tree.createElement("KeyWord")
+            keyword_node_text_value = dom_tree.createTextNode(keyword)
+            keyword_node.appendChild(keyword_node_text_value)
+            customer_node.appendChild(keyword_node)
+            error_code_node = dom_tree.createElement("ErrorID")
+            error_code_text_value = dom_tree.createTextNode(error_code)
+            error_code_node.appendChild(error_code_text_value)
+            customer_node.appendChild(error_code_node)
+            root_node.appendChild(customer_node)
+        with open(exception_xml, 'w') as f:
+            dom_tree.writexml(f, indent='', addindent='', newl='\n', encoding='UTF-8')
+        return
+
+    def GetIgnoreErrorCode(self) -> set:
+        """
+        Below are kinds of error code that are accurate in ecc scanning of edk2 level.
+        But EccCheck plugin is partial scanning so they are always false positive issues.
+        The mapping relationship of error code and error message is listed BaseTools/Sourc/Python/Ecc/EccToolError.py
+        """
+        ignore_error_code = {
+                             "10000",
+                             "10001",
+                             "10002",
+                             "10003",
+                             "10004",
+                             "10005",
+                             "10006",
+                             "10007",
+                             "10008",
+                             "10009",
+                             "10010",
+                             "10011",
+                             "10012",
+                             "10013",
+                             "10015",
+                             "10016",
+                             "10017",
+                             "10022",
+                            }
+        return ignore_error_code

.pytool/Plugin/EccCheck/EccCheck_plug_in.yaml

@@ -0,0 +1,11 @@
+## @file
+# CiBuildPlugin used to check Ecc issues
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+{
+  "scope": "cibuild",
+  "name": "EccCheck Test",
+  "module": "EccCheck"
+}

.pytool/Plugin/EccCheck/Readme.md

@@ -0,0 +1,15 @@
+# EFI Coding style Check Plugin
+
+This CiBuildPlugin finds the Ecc issues of newly added code in pull request.
+
+## Configuration
+
+The plugin can be configured to ignore certain files and issues.
+
+"EccCheck": {
+        "ExceptionList": [],
+        "IgnoreFiles": []
+    },
+    """
+
+OPTIONAL List of file to ignore.

.pytool/Plugin/LicenseCheck/LicenseCheck.py

@@ -0,0 +1,115 @@
+# @file LicenseCheck.py
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+import os
+import logging
+import re
+from io import StringIO
+from typing import List, Tuple
+from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
+from edk2toolext.environment.var_dict import VarDict
+from edk2toollib.utility_functions import RunCmd
+
+
+class LicenseCheck(ICiBuildPlugin):
+
+    """
+    A CiBuildPlugin to check the license for new added files.
+
+    Configuration options:
+    "LicenseCheck": {
+        "IgnoreFiles": []
+    },
+    """
+
+    license_format_preflix = 'SPDX-License-Identifier'
+
+    bsd2_patent = 'BSD-2-Clause-Patent'
+
+    Readdedfileformat = re.compile(r'\+\+\+ b\/(.*)')
+
+    file_extension_list = [".c", ".h", ".inf", ".dsc", ".dec", ".py", ".bat", ".sh", ".uni", ".yaml",
+                           ".fdf", ".inc", "yml", ".asm", ".asm16", ".asl", ".vfr", ".s", ".S", ".aslc",
+                           ".nasm", ".nasmb", ".idf", ".Vfr", ".H"]
+
+    def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
+        """ Provide the testcase name and classname for use in reporting
+            testclassname: a descriptive string for the testcase can include whitespace
+            classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
+
+            Args:
+              packagename: string containing name of package to build
+              environment: The VarDict for the test to run in
+            Returns:
+                a tuple containing the testcase name and the classname
+                (testcasename, classname)
+        """
+        return ("Check for license for " + packagename, packagename + ".LicenseCheck")
+
+    ##
+    # External function of plugin.  This function is used to perform the task of the ci_build_plugin Plugin
+    #
+    #   - package is the edk2 path to package.  This means workspace/packagepath relative.
+    #   - edk2path object configured with workspace and packages path
+    #   - PkgConfig Object (dict) for the pkg
+    #   - EnvConfig Object
+    #   - Plugin Manager Instance
+    #   - Plugin Helper Obj Instance
+    #   - Junit Logger
+    #   - output_stream the StringIO output stream from this plugin via logging
+    def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
+        return_buffer = StringIO()
+        params = "diff --unified=0 origin/master HEAD"
+        RunCmd("git", params, outstream=return_buffer)
+        p = return_buffer.getvalue().strip()
+        patch = p.split("\n")
+        return_buffer.close()
+
+        ignore_files = []
+        if "IgnoreFiles" in pkgconfig:
+            ignore_files = pkgconfig["IgnoreFiles"]
+
+        self.ok = True
+        self.startcheck = False
+        self.license = True
+        self.all_file_pass = True
+        count = len(patch)
+        line_index = 0
+        for line in patch:
+            if line.startswith('--- /dev/null'):
+                nextline = patch[line_index + 1]
+                added_file = self.Readdedfileformat.search(nextline).group(1)
+                added_file_extension = os.path.splitext(added_file)[1]
+                if added_file_extension in self.file_extension_list and packagename in added_file:
+                    if (self.IsIgnoreFile(added_file, ignore_files)):
+                        line_index = line_index + 1
+                        continue
+                    self.startcheck = True
+                    self.license = False
+            if self.startcheck and self.license_format_preflix in line:
+                if self.bsd2_patent in line:
+                    self.license = True
+            if line_index + 1 == count or patch[line_index + 1].startswith('diff --') and self.startcheck:
+                if not self.license:
+                    self.all_file_pass = False
+                    error_message = "Invalid license in: " + added_file + " Hint: Only BSD-2-Clause-Patent is accepted."
+                    logging.error(error_message)
+                self.startcheck = False
+                self.license = True
+            line_index = line_index + 1
+
+        if self.all_file_pass:
+            tc.SetSuccess()
+            return 0
+        else:
+            tc.SetFailed("License Check {0} Failed. ".format(packagename), "LICENSE_CHECK_FAILED")
+            return 1
+
+    def IsIgnoreFile(self, file: str, ignore_files: List[str]) -> bool:
+        for f in ignore_files:
+            if f in file:
+                return True
+        return False

.pytool/Plugin/LicenseCheck/LicenseCheck_plug_in.yaml

@@ -0,0 +1,11 @@
+## @file
+# CiBuildPlugin used to check license issues for new added files
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+{
+  "scope": "cibuild",
+  "name": "License Check Test",
+  "module": "LicenseCheck"
+}

.pytool/Plugin/LicenseCheck/Readme.md

@@ -0,0 +1,17 @@
+# License Check Plugin
+
+This CiBuildPlugin scans all new added files in a package to make sure code
+is contributed under BSD-2-Clause-Patent.
+
+## Configuration
+
+The plugin can be configured to ignore certain files.
+
+``` yaml
+"LicenseCheck": {
+    "IgnoreFiles": []
+}
+```
+### IgnoreFiles
+
+OPTIONAL List of file to ignore.

.pytool/Plugin/SpellCheck/SpellCheck.py

@@ -37,12 +37,12 @@ class SpellCheck(ICiBuildPlugin):
     #
     # A package can remove any of these using IgnoreStandardPaths
     #
-    STANDARD_PLUGIN_DEFINED_PATHS = ["*.c", "*.h",
+    STANDARD_PLUGIN_DEFINED_PATHS = ("*.c", "*.h",
                                      "*.nasm", "*.asm", "*.masm", "*.s",
                                      "*.asl",
                                      "*.dsc", "*.dec", "*.fdf", "*.inf",
                                      "*.md", "*.txt"
-                                     ]
+                                     )
 
     def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
         """ Provide the testcase name and classname for use in reporting
@@ -107,7 +107,8 @@ class SpellCheck(ICiBuildPlugin):
         version_aggregator.GetVersionAggregator().ReportVersion(
             "CSpell", cspell_version, version_aggregator.VersionTypes.INFO)
 
-        package_relative_paths_to_spell_check = SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS
+        # copy the default as a list
+        package_relative_paths_to_spell_check = list(SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS)
 
         #
         # Allow the ci.yaml to remove any of the above standard paths
@@ -133,7 +134,8 @@ class SpellCheck(ICiBuildPlugin):
         #
         relpath = os.path.relpath(abs_pkg_path)
         cpsell_paths = " ".join(
-            [f"{relpath}/**/{x}" for x in package_relative_paths_to_spell_check])
+            # Double quote each path to defer expansion to cspell parameters
+            [f'"{relpath}/**/{x}"' for x in package_relative_paths_to_spell_check])
 
         # Make the config file
         config_file_path = os.path.join(

.pytool/Plugin/SpellCheck/cspell.base.yaml

@@ -22,6 +22,8 @@
     ],
     "minWordLength": 5,
     "allowCompoundWords": false,
+    "maxNumberOfProblems": 200,
+    "maxDuplicateProblems": 200,
     "ignoreWords": [
         "muchange"
     ],
@@ -161,5 +163,21 @@
         "bootability",
         "Sdhci",
         "inmodule",
+        "RISCV",
+        "edksetup",
+        "iscsi",
+        "nvdata",
+        "pytools",
+        "NTDDI",
+        "Wnonportable",
+        "CLANGPDB",
+        "nologo",
+        "lldmap",
+        "ASMLINK",
+        "NODEFAULTLIB",
+        "vcruntimed",
+        "ucrtd",
+        "msvcrtd",
+        "XIPFLAGS"
     ]
 }

.pytool/Readme.md

@@ -4,13 +4,13 @@
 
 | Package              | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues |
 | :----                | :-----                   | :----                             | :---         |
-| ArmPkg              |
-| ArmPlatformPkg      |
-| ArmVirtPkg          |
+| ArmPkg               |                    | :heavy_check_mark: |
+| ArmPlatformPkg       |                    | :heavy_check_mark: |
+| ArmVirtPkg           | SEE PACKAGE README | SEE PACKAGE README |
 | CryptoPkg            | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
-| DynamicTablesPkg    |
+| DynamicTablesPkg     |                    | :heavy_check_mark: |
 | EmbeddedPkg          |
-| EmulatorPkg         |
+| EmulatorPkg          | SEE PACKAGE README | SEE PACKAGE README | Spell checking in audit mode
 | FatPkg               | :heavy_check_mark: | :heavy_check_mark: |
 | FmpDevicePkg         | :heavy_check_mark: | :heavy_check_mark: |
 | IntelFsp2Pkg         |
@@ -18,15 +18,16 @@
 | MdeModulePkg         | :heavy_check_mark: | :heavy_check_mark: | DxeIpl dependency on ArmPkg, Depends on StandaloneMmPkg, Spell checking in audit mode
 | MdePkg               | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
 | NetworkPkg           | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
-| OvmfPkg             |
+| OvmfPkg              | SEE PACKAGE README | SEE PACKAGE README | Spell checking in audit mode
 | PcAtChipsetPkg       | :heavy_check_mark: | :heavy_check_mark: |
 | SecurityPkg          | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
 | ShellPkg             | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 3 modules are not being built by DSC
 | SignedCapsulePkg     |
 | SourceLevelDebugPkg  |
-| StandaloneMmPkg     |
+| StandaloneMmPkg      | :heavy_check_mark: | :heavy_check_mark: |
 | UefiCpuPkg           | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 2 binary modules not being built by DSC
 | UefiPayloadPkg       |
+| UnitTestFrameworkPkg | :heavy_check_mark: | :heavy_check_mark: |
 
 For more detailed status look at the test results of the latest CI run on the
 repo readme.
@@ -77,7 +78,7 @@ per package configuration which comes from this file.
 ## Running CI locally
 
 The EDKII Tools environment (and by extension the ci) is designed to support
-easily and consistantly running locally and in a cloud ci environment.  To do
+easily and consistently running locally and in a cloud ci environment.  To do
 that a few steps should be followed.  Details of EDKII Tools can be found in the
 [docs folder here](https://github.com/tianocore/edk2-pytool-extensions/tree/master/docs)
 
@@ -88,7 +89,7 @@ that a few steps should be followed.  Details of EDKII Tools can be found in the
      * VS 2017 or VS 2019
      * Windows SDK (for rc)
      * Windows WDK (for capsules)
-   * Ubuntu 16.04
+   * Ubuntu 18.04 or Fedora
      * GCC5
    * Easy to add more but this is the current state
 2. Python 3.7.x or newer on path
@@ -137,11 +138,31 @@ location makes more sense for the community.
 
 ### Module Inclusion Test - DscCompleteCheck
 
-This test scans all available modules (via INF files) and compares them to the
-package-level DSC file for the package each module is contained within. The test
-considers it an error if any module does not appear in the `Components` section
-of at least one package-level DSC (indicating that it would not be built if the
-package were built).
+This scans all INF files from a package and confirms they are
+listed in the package level DSC file. The test considers it an error if any INF
+does not appear in the `Components` section of the package-level DSC (indicating
+that it would not be built if the package were built). This is critical because
+much of the CI infrastructure assumes that all modules will be listed in the DSC
+and compiled.
+
+This test will ignore INFs in the following cases:
+
+1. When `MODULE_TYPE` = `HOST_APPLICATION`
+2. When a Library instance **only** supports the `HOST_APPLICATION` environment
+
+### Host Module Inclusion Test - HostUnitTestDscCompleteCheck
+
+This test scans all INF files from a package for those related to host
+based unit tests and confirms they are listed in the unit test DSC file for the package.
+The test considers it an error if any INF meeting the requirements does not appear
+in the `Components` section of the unit test DSC. This is critical because
+much of the CI infrastructure assumes that  modules will be listed in the DSC
+and compiled.
+
+This test will only require INFs in the following cases:
+
+1. When `MODULE_TYPE` = `HOST_APPLICATION`
+2. When a Library instance explicitly supports the `HOST_APPLICATION` environment
 
 ### Code Compilation Test - CompilerPlugin
 
@@ -150,6 +171,46 @@ all package-level DSCs were built, the Code Compilation Test simply runs through
 and builds every package-level DSC on every toolchain and for every architecture
 that is supported. Any module that fails to build is considered an error.
 
+### Host Unit Test Compilation and Run Test - HostUnitTestCompilerPlugin
+
+A test that compiles the dsc for host based unit test apps.
+On Windows this will also enable a build plugin to execute that will run the unit tests and verify the results.
+
+These tools will be invoked on any CI
+pass that includes the NOOPT target. In order for these tools to do their job,
+the package and tests must be configured in a particular way...
+
+#### Including Host-Based Tests in the Package YAML
+
+For example, looking at the `MdeModulePkg.ci.yaml` config file, there are two
+config options that control HostBased test behavior:
+
+```json
+    ## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
+    "HostUnitTestCompilerPlugin": {
+        "DscPath": "Test/MdeModulePkgHostTest.dsc"
+    },
+```
+
+This option tell the test builder to run. The test builder needs to know which
+modules in this package are host-based tests, so that DSC path is provided.
+
+#### Configuring the HostBased DSC
+
+The HostBased DSC for `MdeModulePkg` is located at
+`MdeModulePkg/Test/MdeModulePkgHostTest.dsc`.
+
+To add automated host-based unit test building to a new package, create a
+similar DSC. The new DSC should make sure to have the `NOOPT` BUILD_TARGET
+and should include the line:
+
+```
+!include UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
+```
+
+All of the modules that are included in the `Components` section of this
+DSC should be of type HOST_APPLICATION.
+
 ### GUID Uniqueness Test - GuidCheck
 
 This test works on the collection of all packages rather than an individual
@@ -193,6 +254,16 @@ Install
 
   More cspell info: https://github.com/streetsidesoftware/cspell
 
+### License Checking - LicenseCheck
+
+Scans all new added files in a package to make sure code is contributed under
+BSD-2-Clause-Patent.
+
+### Ecc tool - EccCheck
+
+Run the Ecc tool on the package. The Ecc tool is available in the BaseTools
+package. It checks that the code complies to the EDKII coding standard.
+
 ## PyTool Scopes
 
 Scopes are how the PyTool ext_dep, path_env, and plugins are activated.  Meaning
@@ -207,6 +278,8 @@ few standard scopes.
 | global-nix | edk2_invocable++                                     | Running on Linux based OS    |
 | edk2-build |                                                      | This indicates that an invocable is building EDK2 based UEFI code |
 | cibuild    | set in .pytool/CISettings.py                         | Suggested target for edk2 continuous integration builds.  Tools used for CiBuilds can use this scope.  Example: asl compiler |
+| host-based-test | set in .pytool/CISettings.py                    | Turns on the host based tests and plugin |
+| host-test-win | set in .pytool/CISettings.py                      | Enables the host based test runner for Windows |
 
 ## Future investments
 
@@ -216,8 +289,6 @@ few standard scopes.
 * Visual Studio AARCH64 and ARM support
 * BaseTools C tools CI/PR and binary release process
 * BaseTools Python tools CI/PR process
-* Host based unit testing
 * Extensible private/closed source platform reporting
-* Platform builds, validation
 * UEFI SCTs
 * Other automation

ArmPkg/ArmPkg.ci.yaml

@@ -0,0 +1,240 @@
+## @file
+# CI configuration for ArmPkg
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+{
+    ## options defined .pytool/Plugin/LicenseCheck
+    "LicenseCheck": {
+        "IgnoreFiles": []
+    },
+
+    "EccCheck": {
+        ## Exception sample looks like below:
+        ## "ExceptionList": [
+        ##     "<ErrorID>", "<KeyWord>"
+        ## ]
+        "ExceptionList": [
+        ],
+        ## Both file path and directory path are accepted.
+        "IgnoreFiles": [
+            "Library/ArmSoftFloatLib/berkeley-softfloat-3"
+        ]
+    },
+
+    ## options defined .pytool/Plugin/CompilerPlugin
+    "CompilerPlugin": {
+        "DscPath": "ArmPkg.dsc"
+    },
+
+    ## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
+    "HostUnitTestCompilerPlugin": {
+        "DscPath": "" # Don't support this test
+    },
+
+    ## options defined .pytool/Plugin/CharEncodingCheck
+    "CharEncodingCheck": {
+        "IgnoreFiles": []
+    },
+
+    ## options defined .pytool/Plugin/DependencyCheck
+    "DependencyCheck": {
+        "AcceptableDependencies": [
+            "ArmPlatformPkg/ArmPlatformPkg.dec",
+            "ArmPkg/ArmPkg.dec",
+            "EmbeddedPkg/EmbeddedPkg.dec",
+            "MdeModulePkg/MdeModulePkg.dec",
+            "MdePkg/MdePkg.dec",
+            "ShellPkg/ShellPkg.dec"
+        ],
+        # For host based unit tests
+        "AcceptableDependencies-HOST_APPLICATION":[
+            "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
+        ],
+        # For UEFI shell based apps
+        "AcceptableDependencies-UEFI_APPLICATION":[],
+        "IgnoreInf": []
+    },
+
+    ## options defined .pytool/Plugin/DscCompleteCheck
+    "DscCompleteCheck": {
+        "IgnoreInf": [],
+        "DscPath": "ArmPkg.dsc"
+    },
+
+    ## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
+    "HostUnitTestDscCompleteCheck": {
+        "IgnoreInf": [""],
+        "DscPath": "" # Don't support this test
+    },
+
+    ## options defined .pytool/Plugin/GuidCheck
+    "GuidCheck": {
+        "IgnoreGuidName": [],
+        "IgnoreGuidValue": [],
+        "IgnoreFoldersAndFiles": [],
+        "IgnoreDuplicates": [],
+    },
+
+    ## options defined .pytool/Plugin/LibraryClassCheck
+    "LibraryClassCheck": {
+        "IgnoreHeaderFile": []
+    },
+
+    ## options defined .pytool/Plugin/SpellCheck
+    "SpellCheck": {
+        "AuditOnly": False,
+        "IgnoreFiles": [
+            "Library/ArmSoftFloatLib/berkeley-softfloat-3/**"
+        ],                           # use gitignore syntax to ignore errors
+                                     # in matching files
+        "ExtendWords": [
+          "api's",
+          "ackintid",
+          "actlr",
+          "aeabi",
+          "asedis",
+          "ashldi",
+          "ashrdi",
+          "baddr",
+          "ccidx",
+          "ccsidr",
+          "clidr",
+          "clrex",
+          "clzsi",
+          "cnthctl",
+          "cortexa",
+          "cpacr",
+          "cpuactlr",
+          "csselr",
+          "ctzsi",
+          "cygdrive",
+          "cygpaths",
+          "datas",
+          "dcmpeq",
+          "dcmpge",
+          "dcmpgt",
+          "dcmple",
+          "dcmplt",
+          "ddisable",
+          "divdi",
+          "divsi",
+          "dmdepkg",
+          "dpref",
+          "drsub",
+          "fcmpeq",
+          "fcmpge",
+          "fcmpgt",
+          "fcmple",
+          "fcmplt",
+          "ffreestanding",
+          "frsub",
+          "hisilicon",
+          "iccabpr",
+          "iccbpr",
+          "icciar",
+          "iccicr",
+          "icciidr",
+          "iccpir",
+          "iccpmr",
+          "iccrpr",
+          "icdabr",
+          "icdicer",
+          "icdicfr",
+          "icdicpr",
+          "icdictr",
+          "icdiidr",
+          "icdiser",
+          "icdisr",
+          "icdppisr",
+          "icdsgir",
+          "icdspr",
+          "icenabler",
+          "intid",
+          "ipriority",
+          "irouter",
+          "isenabler",
+          "istatus",
+          "itargets",
+          "lable",
+          "ldivmod",
+          "ldmdb",
+          "ldmia",
+          "ldrbt",
+          "ldrex",
+          "ldrexb",
+          "ldrexd",
+          "ldrexh",
+          "ldrhbt",
+          "ldrht",
+          "ldrsb",
+          "ldrsbt",
+          "ldrsh",
+          "lshrdi",
+          "moddi",
+          "modsi",
+          "mpcore",
+          "mpidr",
+          "muldi",
+          "mullu",
+          "nonshareable",
+          "nsacr",
+          "nsasedis",
+          "nuvia",
+          "oldit",
+          "pcten",
+          "plpis",
+          "procno",
+          "readc",
+          "revsh",
+          "rfedb",
+          "sctlr",
+          "smccc",
+          "smlabb",
+          "smlabt",
+          "smlad",
+          "smladx",
+          "smlatb",
+          "smlatt",
+          "smlawb",
+          "smlawt",
+          "smlsd",
+          "smlsdx",
+          "smmla",
+          "smmlar",
+          "smmls",
+          "smmlsr",
+          "sourcery",
+          "srsdb",
+          "ssacr",
+          "stmdb",
+          "stmia",
+          "strbt",
+          "strexb",
+          "strexd",
+          "strexh",
+          "strht",
+          "switchu",
+          "tpidrurw",
+          "ttbcr",
+          "typer",
+          "ucmpdi",
+          "udivdi",
+          "udivmoddi",
+          "udivsi",
+          "uefi's",
+          "uldiv",
+          "umoddi",
+          "umodsi",
+          "usada",
+          "vlpis",
+          "writec"
+        ],                          # words to extend to the dictionary for this package
+        "IgnoreStandardPaths": [    # Standard Plugin defined paths that
+            "*.asm", "*.s"          # should be ignore
+        ],
+        "AdditionalIncludePaths": [] # Additional paths to spell check
+                                     # (wildcards supported)
+    }
+}

ArmPkg/ArmPkg.dec

@@ -2,7 +2,7 @@
 # ARM processor package.
 #
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
 #
 #    SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -27,15 +27,68 @@
   Include                        # Root include for the package
 
 [LibraryClasses.common]
-  ArmLib|Include/Library/ArmLib.h
-  ArmMmuLib|Include/Library/ArmMmuLib.h
-  SemihostLib|Include/Library/Semihosting.h
-  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
+  ##  @libraryclass  Convert Arm instructions to a human readable format.
+  #
   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
+
+  ##  @libraryclass  Provides an interface to Arm generic counters.
+  #
+  ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
+
+  ##  @libraryclass  Provides an interface to initialize a
+  #   Generic Interrupt Controller (GIC).
+  #
   ArmGicArchLib|Include/Library/ArmGicArchLib.h
-  ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
+
+  ##  @libraryclass  Provides a Generic Interrupt Controller (GIC)
+  #   configuration interface.
+  #
+  ArmGicLib|Include/Library/ArmGicLib.h
+
+  ##  @libraryclass  Provides a HyperVisor Call (HVC) interface.
+  #
+  ArmHvcLib|Include/Library/ArmHvcLib.h
+
+  ##  @libraryclass  Provides an interface to Arm registers.
+  #
+  ArmLib|Include/Library/ArmLib.h
+
+  ##  @libraryclass  Provides a Mmu interface.
+  #
+  ArmMmuLib|Include/Library/ArmMmuLib.h
+
+  ##  @libraryclass  Provides a Mailbox Transport Layer (MTL) interface
+  #   for the System Control and Management Interface (SCMI).
+  #
+  ArmMtlLib|Include/Library/ArmMtlLib.h
+
+  ##  @libraryclass  Provides a System Monitor Call (SMC) interface.
+  #
+  ArmSmcLib|Include/Library/ArmSmcLib.h
+
+  ##  @libraryclass  Provides a SuperVisor Call (SVC) interface.
+  #
   ArmSvcLib|Include/Library/ArmSvcLib.h
+
+  ##  @libraryclass  Provides a default exception handler.
+  #
+  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
+
+  ##  @libraryclass  Provides an interface to query miscellaneous OEM
+  #   information.
+  #
+  OemMiscLib|Include/Library/OemMiscLib.h
+
+  ##  @libraryclass  Provides an OpTee interface.
+  #
   OpteeLib|Include/Library/OpteeLib.h
+
+  ##  @libraryclass  Provides a semihosting interface.
+  #
+  SemihostLib|Include/Library/SemihostLib.h
+
+  ##  @libraryclass  Provides an interface for a StandaloneMm Mmu.
+  #
   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
 
 [Guids.common]
@@ -84,6 +137,13 @@
   # hardware coherency (i.e., no virtualization or cache coherent DMA)
   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
 
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
+  ## Used to select method for requesting services from S-EL1.<BR><BR>
+  #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
+  #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
+  # @Prompt Enable FF-A support.
+  gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 
@@ -115,6 +175,20 @@
   # The Primary Core is ClusterId[0] & CoreId[0]
   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 
+  #
+  # SMBIOS PCDs
+  #
+  gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
+  gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
+  gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
+  gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
+  gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
+  gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
+  gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
+  gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
+  gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
+  gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
+
   #
   # ARM L2x0 PCDs
   #
@@ -215,6 +289,9 @@
   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 
+  gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
+  gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
+
 [PcdsFixedAtBuild.common, PcdsDynamic.common]
   #
   # ARM Architectural Timer

ArmPkg/ArmPkg.dsc

@@ -2,8 +2,9 @@
 # ARM processor package.
 #
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2018, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 # Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
 #
 #    SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -28,17 +29,25 @@
   RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
   *_*_*_CC_FLAGS  = -DDISABLE_NEW_DEPRECATED_INTERFACES
 
+[PcdsFixedAtBuild]
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+!include MdePkg/MdeLibs.dsc.inc
+
 [LibraryClasses.common]
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
   CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
   UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
   UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
   UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
@@ -46,6 +55,7 @@
   UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
   PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
   PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
 
   UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@@ -80,6 +90,8 @@
 
   ArmMtlLib|ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
 
+  OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
+
 [LibraryClasses.common.PEIM]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -133,12 +145,22 @@
   ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
   ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
   ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
   ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
+  ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
   ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
   ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 
+  ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
   ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
 
+  ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+  ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+  ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
+
 [Components.AARCH64]
+  ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
   ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
+
+[Components.AARCH64, Components.ARM]
   ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf

ArmPkg/Drivers/ArmGic/ArmGicDxe.h

@@ -6,8 +6,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 --*/
 
-#ifndef __ARM_GIC_DXE_H__
-#define __ARM_GIC_DXE_H__
+#ifndef ARM_GIC_DXE_H_
+#define ARM_GIC_DXE_H_
 
 #include <Library/ArmGicLib.h>
 #include <Library/ArmLib.h>
@@ -76,4 +76,4 @@ GicGetDistributorIcfgBaseAndBit (
   OUT UINTN                               *Config1Bit
   );
 
-#endif
+#endif // ARM_GIC_DXE_H_

ArmPkg/Drivers/ArmGic/ArmGicLib.c

@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -25,10 +25,13 @@
                                            + ARM_GICR_SGI_RESERVED_FRAME_SIZE)
 
 #define ISENABLER_ADDRESS(base,offset) ((base) + \
-          ARM_GICR_CTLR_FRAME_SIZE +  ARM_GICR_ISENABLER + (4 * offset))
+          ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
 
 #define ICENABLER_ADDRESS(base,offset) ((base) + \
-          ARM_GICR_CTLR_FRAME_SIZE +  ARM_GICR_ICENABLER + (4 * offset))
+          ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
+
+#define IPRIORITY_ADDRESS(base,offset) ((base) + \
+          ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
 
 /**
  *
@@ -117,7 +120,14 @@ ArmGicGetMaxNumInterrupts (
   IN  INTN          GicDistributorBase
   )
 {
-  return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
+  UINTN ItLines;
+
+  ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
+
+  //
+  // Interrupt ID 1020-1023 are reserved.
+  //
+  return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);
 }
 
 VOID
@@ -199,6 +209,50 @@ ArmGicEndOfInterrupt (
   }
 }
 
+VOID
+EFIAPI
+ArmGicSetInterruptPriority (
+  IN UINTN                  GicDistributorBase,
+  IN UINTN                  GicRedistributorBase,
+  IN UINTN                  Source,
+  IN UINTN                  Priority
+  )
+{
+  UINT32                RegOffset;
+  UINTN                 RegShift;
+  ARM_GIC_ARCH_REVISION Revision;
+  UINTN                 GicCpuRedistributorBase;
+
+  // Calculate register offset and bit position
+  RegOffset = Source / 4;
+  RegShift = (Source % 4) * 8;
+
+  Revision = ArmGicGetSupportedArchRevision ();
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
+      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
+      SourceIsSpi (Source)) {
+    MmioAndThenOr32 (
+      GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+      ~(0xff << RegShift),
+      Priority << RegShift
+      );
+  } else {
+    GicCpuRedistributorBase = GicGetCpuRedistributorBase (
+                                GicRedistributorBase,
+                                Revision
+                                );
+    if (GicCpuRedistributorBase == 0) {
+      return;
+    }
+
+    MmioAndThenOr32 (
+      IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),
+      ~(0xff << RegShift),
+      Priority << RegShift
+      );
+  }
+}
+
 VOID
 EFIAPI
 ArmGicEnableInterrupt (

ArmPkg/Drivers/ArmGic/ArmGicSecLib.c

@@ -1,58 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include <Base.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-/*
- * This function configures the interrupts set by the mask to be secure.
- *
- */
-VOID
-EFIAPI
-ArmGicSetSecureInterrupts (
-  IN  UINTN         GicDistributorBase,
-  IN  UINTN*        GicSecureInterruptMask,
-  IN  UINTN         GicSecureInterruptMaskSize
-  )
-{
-  UINTN  Index;
-  UINT32 InterruptStatus;
-
-  // We must not have more interrupts defined by the mask than the number of available interrupts
-  ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
-
-  // Set all the interrupts defined by the mask as Secure
-  for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
-    InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
-    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
-  }
-}
-
-VOID
-EFIAPI
-ArmGicEnableDistributor (
-  IN  INTN          GicDistributorBase
-  )
-{
-  // Turn on the GIC distributor
-  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
-}
-
-VOID
-EFIAPI
-ArmGicSetupNonSecure (
-  IN  UINTN         MpId,
-  IN  INTN          GicDistributorBase,
-  IN  INTN          GicInterruptInterfaceBase
-  )
-{
-  ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
-}

ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c

@@ -121,7 +121,7 @@ GicV2GetInterruptSourceState (
   @param This     Instance pointer for this protocol
   @param Source   Hardware source of the interrupt
 
-  @retval EFI_SUCCESS       Source interrupt EOI'ed.
+  @retval EFI_SUCCESS       Source interrupt ended successfully.
   @retval EFI_UNSUPPORTED   Source interrupt is not supported
 
 **/

ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

@@ -115,7 +115,7 @@ GicV3GetInterruptSourceState (
   @param This     Instance pointer for this protocol
   @param Source   Hardware source of the interrupt
 
-  @retval EFI_SUCCESS       Source interrupt EOI'ed.
+  @retval EFI_SUCCESS       Source interrupt ended successfully.
   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
 
 **/
@@ -374,8 +374,6 @@ GicV3DxeInitialize (
 {
   EFI_STATUS              Status;
   UINTN                   Index;
-  UINT32                  RegOffset;
-  UINTN                   RegShift;
   UINT64                  CpuTarget;
   UINT64                  MpId;
 
@@ -397,12 +395,11 @@ GicV3DxeInitialize (
     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 
     // Set Priority
-    RegOffset = Index / 4;
-    RegShift = (Index % 4) * 8;
-    MmioAndThenOr32 (
-      mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
-      ~(0xff << RegShift),
-      ARM_GIC_DEFAULT_PRIORITY << RegShift
+    ArmGicSetInterruptPriority (
+      mGicDistributorBase,
+      mGicRedistributorsBase,
+      Index,
+      ARM_GIC_DEFAULT_PRIORITY
       );
   }
 

ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf

@@ -1,6 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+#  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -18,11 +18,16 @@
   ENTRY_POINT                    = ArmScmiDxeEntryPoint
 
 [Sources.common]
-  Scmi.c
+  ArmScmiBaseProtocolPrivate.h
+  ArmScmiClockProtocolPrivate.h
+  ArmScmiPerformanceProtocolPrivate.h
   ScmiBaseProtocol.c
+  Scmi.c
   ScmiClockProtocol.c
   ScmiDxe.c
+  ScmiDxe.h
   ScmiPerformanceProtocol.c
+  ScmiPrivate.h
 
 [Packages]
   ArmPkg/ArmPkg.dec

ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -22,7 +22,7 @@
 #define NUM_REMAIN_PERF_LEVELS_SHIFT  16
 #define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
 
-/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command.
+/** Return values for ScmiMessageIdPerformanceDescribeLevels command.
   SCMI Spec section 4.5.2.5
 **/
 typedef struct {

ArmPkg/Drivers/ArmScmiDxe/Scmi.c

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -95,7 +95,7 @@ ScmiCommandExecute (
   // Fill in message header.
   MessageHeader = SCMI_MESSAGE_HEADER (
                     Command->MessageId,
-                    SCMI_MESSAGE_TYPE_COMMAND,
+                    ScmiMessageTypeCommand,
                     Command->ProtocolId
                     );
 
@@ -123,7 +123,7 @@ ScmiCommandExecute (
 
   Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
 
-  if (Response->Status != SCMI_SUCCESS) {
+  if (Response->Status != ScmiSuccess) {
     DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
       Command->ProtocolId,
       Command->MessageId,
@@ -161,8 +161,9 @@ ScmiProtocolDiscoveryCommon (
   )
 {
   SCMI_COMMAND  Command;
-  UINT32        PayloadLength = 0;
+  UINT32        PayloadLength;
 
+  PayloadLength = 0;
   Command.ProtocolId = ProtocolId;
   Command.MessageId  = MessageId;
 
@@ -194,7 +195,7 @@ ScmiGetProtocolVersion (
 
   Status = ScmiProtocolDiscoveryCommon (
              ProtocolId,
-             SCMI_MESSAGE_ID_PROTOCOL_VERSION,
+             ScmiMessageIdProtocolVersion,
              (UINT32**)&ProtocolVersion
              );
   if (EFI_ERROR (Status)) {
@@ -223,7 +224,7 @@ ScmiGetProtocolAttributes (
 {
   return ScmiProtocolDiscoveryCommon (
            ProtocolId,
-           SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES,
+           ScmiMessageIdProtocolAttributes,
            ReturnValues
            );
 }
@@ -245,7 +246,7 @@ ScmiGetProtocolMessageAttributes (
 {
   return ScmiProtocolDiscoveryCommon (
            ProtocolId,
-           SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES,
+           ScmiMessageIdProtocolMessageAttributes,
            ReturnValues
            );
 }

ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -34,7 +34,7 @@ BaseGetVersion (
   OUT UINT32              *Version
   )
 {
-  return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version);
+  return ScmiGetProtocolVersion (ScmiProtocolIdBase, Version);
 }
 
 /** Return total number of SCMI protocols supported by the SCP firmware.
@@ -57,7 +57,7 @@ BaseGetTotalProtocols (
   EFI_STATUS  Status;
   UINT32      *ReturnValues;
 
-  Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValues);
+  Status = ScmiGetProtocolAttributes (ScmiProtocolIdBase, &ReturnValues);
   if (EFI_ERROR (Status)) {
     return Status;
   }
@@ -69,9 +69,9 @@ BaseGetTotalProtocols (
 
 /** Common function which returns vendor details.
 
-  @param[in] MessageId       SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR
+  @param[in] MessageId       ScmiMessageIdBaseDiscoverVendor
                              OR
-                             SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR
+                             ScmiMessageIdBaseDiscoverSubVendor
 
   @param[out] VendorIdentifier ASCII name of the vendor/subvendor.
 
@@ -91,7 +91,7 @@ BaseDiscoverVendorDetails (
   SCMI_COMMAND  Cmd;
   UINT32        PayloadLength;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
+  Cmd.ProtocolId = ScmiProtocolIdBase;
   Cmd.MessageId  = MessageId;
 
   PayloadLength = 0;
@@ -133,7 +133,7 @@ BaseDiscoverVendor (
   )
 {
   return BaseDiscoverVendorDetails (
-           SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR,
+           ScmiMessageIdBaseDiscoverVendor,
            VendorIdentifier
            );
 }
@@ -156,7 +156,7 @@ BaseDiscoverSubVendor (
   )
 {
   return BaseDiscoverVendorDetails (
-           SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR,
+           ScmiMessageIdBaseDiscoverSubVendor,
            VendorIdentifier
            );
 }
@@ -183,8 +183,8 @@ BaseDiscoverImplVersion (
   SCMI_COMMAND  Cmd;
   UINT32        PayloadLength;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION;
+  Cmd.ProtocolId = ScmiProtocolIdBase;
+  Cmd.MessageId  = ScmiMessageIdBaseDiscoverImplementationVersion;
 
   PayloadLength = 0;
 
@@ -250,8 +250,8 @@ BaseDiscoverListProtocols (
     return EFI_BUFFER_TOO_SMALL;
   }
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS;
+  Cmd.ProtocolId = ScmiProtocolIdBase;
+  Cmd.MessageId  = ScmiMessageIdBaseDiscoverListProtocols;
 
   Skip = 0;
 

ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -52,7 +52,7 @@ ClockGetVersion (
   OUT UINT32               *Version
   )
 {
-  return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version);
+  return ScmiGetProtocolVersion (ScmiProtocolIdClock, Version);
 }
 
 /** Return total number of clock devices supported by the clock management
@@ -76,7 +76,7 @@ ClockGetTotalClocks (
   EFI_STATUS  Status;
   UINT32     *ReturnValues;
 
-  Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnValues);
+  Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
   if (EFI_ERROR (Status)) {
     return Status;
   }
@@ -122,8 +122,8 @@ ClockGetClockAttributes (
 
   *MessageParams = ClockId;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES;
+  Cmd.ProtocolId = ScmiProtocolIdClock;
+  Cmd.MessageId  = ScmiMessageIdClockAttributes;
 
   PayloadLength = sizeof (ClockId);
 
@@ -152,10 +152,10 @@ ClockGetClockAttributes (
   @param[in] This        A pointer to SCMI_CLOCK_PROTOCOL Instance.
   @param[in] ClockId     Identifier for the clock device.
 
-  @param[out] Format      SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+  @param[out] Format      ScmiClockRateFormatDiscrete: Clock device
                           supports range of clock rates which are non-linear.
 
-                          SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+                          ScmiClockRateFormatLinear: Clock device supports
                           range of linear clock rates from Min to Max in steps.
 
   @param[out] TotalRates  Total number of rates.
@@ -189,20 +189,22 @@ ClockDescribeRates (
   CLOCK_DESCRIBE_RATES   *DescribeRates;
   CLOCK_RATE_DWORD       *Rate;
 
-  UINT32                 RequiredArraySize = 0;
-  UINT32                 RateIndex = 0;
+  UINT32                 RequiredArraySize;
+  UINT32                 RateIndex;
   UINT32                 RateNo;
   UINT32                 RateOffset;
 
   *TotalRates = 0;
+  RequiredArraySize = 0;
+  RateIndex = 0;
 
   Status = ScmiCommandGetPayload (&MessageParams);
   if (EFI_ERROR (Status)) {
     return Status;
   }
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES;
+  Cmd.ProtocolId = ScmiProtocolIdClock;
+  Cmd.MessageId  = ScmiMessageIdClockDescribeRates;
 
   *MessageParams++  = ClockId;
 
@@ -234,7 +236,7 @@ ClockDescribeRates (
       *TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
                     + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
 
-      if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
+      if (*Format == ScmiClockRateFormatDiscrete) {
          RequiredArraySize = (*TotalRates) * sizeof (UINT64);
       } else {
          // We need to return triplet of 64 bit value for each rate
@@ -249,26 +251,30 @@ ClockDescribeRates (
 
     RateOffset = 0;
 
-    if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
+    if (*Format == ScmiClockRateFormatDiscrete) {
       for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
         Rate = &DescribeRates->Rates[RateOffset++];
         // Non-linear discrete rates.
-        RateArray[RateIndex++].Rate = ConvertTo64Bit (Rate->Low, Rate->High);
+        RateArray[RateIndex++].DiscreteRate.Rate =
+          ConvertTo64Bit (Rate->Low, Rate->High);
       }
     } else {
       for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
         // Linear clock rates from minimum to maximum in steps
         // Minimum clock rate.
         Rate = &DescribeRates->Rates[RateOffset++];
-        RateArray[RateIndex].Min = ConvertTo64Bit (Rate->Low, Rate->High);
+        RateArray[RateIndex].ContinuousRate.Min =
+          ConvertTo64Bit (Rate->Low, Rate->High);
 
         Rate = &DescribeRates->Rates[RateOffset++];
         // Maximum clock rate.
-        RateArray[RateIndex].Max = ConvertTo64Bit (Rate->Low, Rate->High);
+        RateArray[RateIndex].ContinuousRate.Max =
+          ConvertTo64Bit (Rate->Low, Rate->High);
 
         Rate = &DescribeRates->Rates[RateOffset++];
         // Step.
-        RateArray[RateIndex++].Step = ConvertTo64Bit (Rate->Low, Rate->High);
+        RateArray[RateIndex++].ContinuousRate.Step =
+          ConvertTo64Bit (Rate->Low, Rate->High);
       }
     }
   } while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
@@ -314,8 +320,8 @@ ClockRateGet (
   // Fill arguments for clock protocol command.
   *MessageParams  = ClockId;
 
-  Cmd.ProtocolId  = SCMI_PROTOCOL_ID_CLOCK;
-  Cmd.MessageId   = SCMI_MESSAGE_ID_CLOCK_RATE_GET;
+  Cmd.ProtocolId  = ScmiProtocolIdClock;
+  Cmd.MessageId   = ScmiMessageIdClockRateGet;
 
   PayloadLength = sizeof (ClockId);
 
@@ -368,8 +374,8 @@ ClockRateSet (
   ClockRateSetAttributes->Rate.Low   = (UINT32)Rate;
   ClockRateSetAttributes->Rate.High  = (UINT32)(Rate >> 32);
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_CLOCK_RATE_SET;
+  Cmd.ProtocolId = ScmiProtocolIdClock;
+  Cmd.MessageId  = ScmiMessageIdClockRateSet;
 
   PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
 
@@ -415,8 +421,8 @@ ClockEnable (
   ClockConfigSetAttributes->ClockId    = ClockId;
   ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET;
+  Cmd.ProtocolId = ScmiProtocolIdClock;
+  Cmd.MessageId  = ScmiMessageIdClockConfigSet;
 
   PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);
 

ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c

@@ -1,12 +1,12 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  System Control and Management Interface V1.0
-    http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
-    DEN0056A_System_Control_and_Management_Interface.pdf
+  @par Specification Reference:
+  - Arm System Control and Management Interface - Platform Design Document
+    (https://developer.arm.com/documentation/den0056/)
 **/
 
 #include <Base.h>
@@ -24,9 +24,9 @@
 #include "ScmiPrivate.h"
 
 STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
-  { SCMI_PROTOCOL_ID_BASE, ScmiBaseProtocolInit },
-  { SCMI_PROTOCOL_ID_PERFORMANCE, ScmiPerformanceProtocolInit },
-  { SCMI_PROTOCOL_ID_CLOCK, ScmiClockProtocolInit }
+  { ScmiProtocolIdBase, ScmiBaseProtocolInit },
+  { ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
+  { ScmiProtocolIdClock, ScmiClockProtocolInit }
 };
 
 /** ARM SCMI driver entry point function.
@@ -61,7 +61,7 @@ ArmScmiDxeEntryPoint (
   UINT32              SupportedListSize;
 
   // Every SCMI implementation must implement the base protocol.
-  ASSERT (Protocols[0].Id == SCMI_PROTOCOL_ID_BASE);
+  ASSERT (Protocols[0].Id == ScmiProtocolIdBase);
 
   Status = ScmiBaseProtocolInit (&ImageHandle);
   if (EFI_ERROR (Status)) {
@@ -86,7 +86,9 @@ ArmScmiDxeEntryPoint (
     return Status;
   }
 
-  if (Version != BASE_PROTOCOL_VERSION) {
+  // Accept any version between SCMI v1.0 and SCMI v2.0
+  if ((Version < BASE_PROTOCOL_VERSION_V1) ||
+    (Version > BASE_PROTOCOL_VERSION_V2)) {
     ASSERT (FALSE);
     return EFI_UNSUPPORTED;
   }

ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -35,7 +35,7 @@ PerformanceGetVersion (
   OUT UINT32                     *Version
   )
 {
-  return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version);
+  return ScmiGetProtocolVersion (ScmiProtocolIdPerformance, Version);
 }
 
 /** Return protocol attributes of the performance management protocol.
@@ -59,7 +59,7 @@ PerformanceGetAttributes (
   UINT32* ReturnValues;
 
   Status = ScmiGetProtocolAttributes (
-             SCMI_PROTOCOL_ID_PERFORMANCE,
+             ScmiProtocolIdPerformance,
              &ReturnValues
              );
   if (EFI_ERROR (Status)) {
@@ -107,8 +107,8 @@ PerformanceDomainAttributes (
 
   *MessageParams = DomainId;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceDomainAttributes;
 
   PayloadLength = sizeof (DomainId);
 
@@ -179,8 +179,8 @@ PerformanceDescribeLevels (
 
   *MessageParams++ = DomainId;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceDescribeLevels;
 
   do {
 
@@ -258,8 +258,8 @@ PerformanceLimitsSet (
   *MessageParams++ = Limits->RangeMax;
   *MessageParams   = Limits->RangeMin;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceLimitsSet;
 
   PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
 
@@ -304,8 +304,8 @@ PerformanceLimitsGet (
 
   *MessageParams = DomainId;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceLimitsGet;
 
   PayloadLength = sizeof (DomainId);
 
@@ -354,8 +354,8 @@ PerformanceLevelSet (
   *MessageParams++ = DomainId;
   *MessageParams   = Level;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceLevelSet;
 
   PayloadLength = sizeof (DomainId) + sizeof (Level);
 
@@ -399,8 +399,8 @@ PerformanceLevelGet (
 
   *MessageParams = DomainId;
 
-  Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
-  Cmd.MessageId  = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET;
+  Cmd.ProtocolId = ScmiProtocolIdPerformance;
+  Cmd.MessageId  = ScmiMessageIdPerformanceLevelGet;
 
   PayloadLength = sizeof (DomainId);
 

ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -13,41 +13,41 @@
 
 // SCMI protocol IDs.
 typedef enum {
-  SCMI_PROTOCOL_ID_BASE         = 0x10,
-  SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
-  SCMI_PROTOCOL_ID_SYSTEM_POWER = 0x12,
-  SCMI_PROTOCOL_ID_PERFORMANCE  = 0x13,
-  SCMI_PROTOCOL_ID_CLOCK        = 0x14,
-  SCMI_PROTOCOL_ID_SENSOR       = 0x15
+  ScmiProtocolIdBase        = 0x10,
+  ScmiProtocolIdPowerDomain = 0x11,
+  ScmiProtocolIdSystemPower = 0x12,
+  ScmiProtocolIdPerformance = 0x13,
+  ScmiProtocolIdClock       = 0x14,
+  ScmiProtocolIdSensor      = 0x15
 } SCMI_PROTOCOL_ID;
 
 // SCMI message types.
 typedef enum {
-  SCMI_MESSAGE_TYPE_COMMAND          = 0,
-  SCMI_MESSAGE_TYPE_DELAYED_RESPONSE = 2, // Skipping 1 is deliberate.
-  SCMI_MESSAGE_TYPE_NOTIFICATION     = 3
+  ScmiMessageTypeCommand         = 0,
+  ScmiMessageTypeDelayedResponse = 2, // Skipping 1 is deliberate.
+  ScmiMessageTypeNotification    = 3
 } SCMI_MESSAGE_TYPE;
 
 // SCMI response error codes.
 typedef enum {
-  SCMI_SUCCESS            =  0,
-  SCMI_NOT_SUPPORTED      = -1,
-  SCMI_INVALID_PARAMETERS = -2,
-  SCMI_DENIED             = -3,
-  SCMI_NOT_FOUND          = -4,
-  SCMI_OUT_OF_RANGE       = -5,
-  SCMI_BUSY               = -6,
-  SCMI_COMMS_ERROR        = -7,
-  SCMI_GENERIC_ERROR      = -8,
-  SCMI_HARDWARE_ERROR     = -9,
-  SCMI_PROTOCOL_ERROR     = -10
+  ScmiSuccess           =  0,
+  ScmiNotSupported      = -1,
+  ScmiInvalidParameters = -2,
+  ScmiDenied            = -3,
+  ScmiNotFound          = -4,
+  ScmiOutOfRange        = -5,
+  ScmiBusy              = -6,
+  ScmiCommsError        = -7,
+  ScmiGenericError      = -8,
+  ScmiHardwareError     = -9,
+  ScmiProtocolError     = -10
 } SCMI_STATUS;
 
 // SCMI message IDs common to all protocols.
 typedef enum {
-  SCMI_MESSAGE_ID_PROTOCOL_VERSION            = 0x0,
-  SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES         = 0x1,
-  SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2
+  ScmiMessageIdProtocolVersion           = 0x0,
+  ScmiMessageIdProtocolAttributes        = 0x1,
+  ScmiMessageIdProtocolMessageAttributes = 0x2
 } SCMI_MESSAGE_ID;
 
 // Not defined in SCMI specification but will help to identify a message.

ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c

@@ -2,7 +2,7 @@
 
 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+Portions copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -13,7 +13,68 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/MemoryAllocationLib.h>
 #include "CpuDxe.h"
 
-#define TT_ATTR_INDX_INVALID    ((UINT32)~0)
+#define INVALID_ENTRY   ((UINT32)~0)
+
+#define MIN_T0SZ        16
+#define BITS_PER_LEVEL  9
+
+STATIC
+VOID
+GetRootTranslationTableInfo (
+  IN  UINTN     T0SZ,
+  OUT UINTN     *RootTableLevel,
+  OUT UINTN     *RootTableEntryCount
+  )
+{
+  *RootTableLevel       = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
+  *RootTableEntryCount  = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
+}
+
+STATIC
+UINT64
+PageAttributeToGcdAttribute (
+  IN UINT64 PageAttributes
+  )
+{
+  UINT64  GcdAttributes;
+
+  switch (PageAttributes & TT_ATTR_INDX_MASK) {
+  case TT_ATTR_INDX_DEVICE_MEMORY:
+    GcdAttributes = EFI_MEMORY_UC;
+    break;
+  case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
+    GcdAttributes = EFI_MEMORY_WC;
+    break;
+  case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
+    GcdAttributes = EFI_MEMORY_WT;
+    break;
+  case TT_ATTR_INDX_MEMORY_WRITE_BACK:
+    GcdAttributes = EFI_MEMORY_WB;
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR,
+      "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
+      PageAttributes));
+    ASSERT (0);
+    // The Global Coherency Domain (GCD) value is defined as a bit set.
+    // Returning 0 means no attribute has been set.
+    GcdAttributes = 0;
+  }
+
+  // Determine protection attributes
+  if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||
+      ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
+    // Read only cases map to write-protect
+    GcdAttributes |= EFI_MEMORY_RO;
+  }
+
+  // Process eXecute Never attribute
+  if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) {
+    GcdAttributes |= EFI_MEMORY_XP;
+  }
+
+  return GcdAttributes;
+}
 
 STATIC
 UINT64
@@ -37,7 +98,7 @@ GetFirstPageAttribute (
   {
     return FirstEntry & TT_ATTR_INDX_MASK;
   } else {
-    return TT_ATTR_INDX_INVALID;
+    return INVALID_ENTRY;
   }
 }
 
@@ -78,8 +139,8 @@ GetNextEntryAttribute (
     // If Entry is a Table Descriptor type entry then go through the sub-level table
     if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||
         ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) {
-      if ((*PrevEntryAttribute == TT_ATTR_INDX_INVALID) || (EntryAttribute != *PrevEntryAttribute)) {
-        if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) {
+      if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {
+        if (*PrevEntryAttribute != INVALID_ENTRY) {
           // Update GCD with the last region
           SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
               *StartGcdRegion,
@@ -103,7 +164,7 @@ GetNextEntryAttribute (
                              (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))),
                              PrevEntryAttribute, StartGcdRegion);
     } else {
-      if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) {
+      if (*PrevEntryAttribute != INVALID_ENTRY) {
         // Update GCD with the last region
         SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
             *StartGcdRegion,
@@ -112,7 +173,7 @@ GetNextEntryAttribute (
 
         // Start of the new region
         *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
-        *PrevEntryAttribute = TT_ATTR_INDX_INVALID;
+        *PrevEntryAttribute = INVALID_ENTRY;
       }
     }
   }
@@ -128,7 +189,7 @@ SyncCacheConfig (
   )
 {
   EFI_STATUS                          Status;
-  UINT32                              PageAttribute = 0;
+  UINT32                              PageAttribute;
   UINT64                             *FirstLevelTableAddress;
   UINTN                               TableLevel;
   UINTN                               TableCount;
@@ -177,7 +238,7 @@ SyncCacheConfig (
                                                &PageAttribute, &BaseAddressGcdRegion);
 
   // Update GCD with the last region if valid
-  if (PageAttribute != TT_ATTR_INDX_INVALID) {
+  if (PageAttribute != INVALID_ENTRY) {
     SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
         BaseAddressGcdRegion,
         EndAddressGcdRegion - BaseAddressGcdRegion,
@@ -221,12 +282,12 @@ EfiAttributeToArmAttribute (
   ArmAttributes |= TT_AF;
 
   // Determine protection attributes
-  if (EfiAttributes & EFI_MEMORY_RO) {
+  if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
     ArmAttributes |= TT_AP_RO_RO;
   }
 
   // Process eXecute Never attribute
-  if (EfiAttributes & EFI_MEMORY_XP) {
+  if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
     ArmAttributes |= TT_PXN_MASK;
   }
 

ArmPkg/Drivers/CpuDxe/Arm/Mmu.c

@@ -2,7 +2,7 @@
 
 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+Portions copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -155,8 +155,8 @@ SyncCacheConfigPage (
   EFI_STATUS                          Status;
   UINT32                              i;
   volatile ARM_PAGE_TABLE_ENTRY       *SecondLevelTable;
-  UINT32                              NextPageAttributes = 0;
-  UINT32                              PageAttributes = 0;
+  UINT32                              NextPageAttributes;
+  UINT32                              PageAttributes;
   UINT32                              BaseAddress;
   UINT64                              GcdAttributes;
 
@@ -226,8 +226,8 @@ SyncCacheConfig (
   UINT32                              i;
   EFI_PHYSICAL_ADDRESS                NextRegionBase;
   UINT64                              NextRegionLength;
-  UINT32                              NextSectionAttributes = 0;
-  UINT32                              SectionAttributes = 0;
+  UINT32                              NextSectionAttributes;
+  UINT32                              SectionAttributes;
   UINT64                              GcdAttributes;
   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
   UINTN                               NumberOfDescriptors;
@@ -345,7 +345,7 @@ EfiAttributeToArmAttribute (
       break;
 
     case EFI_MEMORY_WC:
-      // Map to normal non-cachable
+      // Map to normal non-cacheable
       ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
       break;
 
@@ -366,14 +366,14 @@ EfiAttributeToArmAttribute (
   }
 
   // Determine protection attributes
-  if (EfiAttributes & EFI_MEMORY_RO) {
+  if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
     ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
   } else {
     ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
   }
 
   // Determine eXecute Never attribute
-  if (EfiAttributes & EFI_MEMORY_XP) {
+  if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
     ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
   }
 

ArmPkg/Drivers/CpuDxe/CpuDxe.h

@@ -7,8 +7,8 @@
 
 **/
 
-#ifndef __CPU_DXE_ARM_EXCEPTION_H__
-#define __CPU_DXE_ARM_EXCEPTION_H__
+#ifndef CPU_DXE_H_
+#define CPU_DXE_H_
 
 #include <Uefi.h>
 
@@ -134,13 +134,6 @@ GetMemoryRegion (
   OUT    UINTN                   *RegionAttributes
   );
 
-VOID
-GetRootTranslationTableInfo (
-  IN  UINTN    T0SZ,
-  OUT UINTN   *TableLevel,
-  OUT UINTN   *TableEntryCount
-  );
-
 EFI_STATUS
 SetGcdMemorySpaceAttributes (
   IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR    *MemorySpaceMap,
@@ -150,4 +143,4 @@ SetGcdMemorySpaceAttributes (
   IN UINT64                              Attributes
   );
 
-#endif // __CPU_DXE_ARM_EXCEPTION_H__
+#endif // CPU_DXE_H_

ArmPkg/Drivers/CpuDxe/CpuMpCore.c

@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -32,7 +32,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
 };
 
 /** Publish ARM Processor Data table in UEFI SYSTEM Table.
- * @param:  HobStart               Pointer to the beginning of the HOB List from PEI.
+ * @param  HobStart               Pointer to the beginning of the HOB List from PEI.
  *
  * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
  *               If  the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory

ArmPkg/Drivers/CpuDxe/Exception.c

@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Portions Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -14,7 +14,8 @@
 EFI_STATUS
 InitializeExceptions (
   IN EFI_CPU_ARCH_PROTOCOL    *Cpu
-  ) {
+  )
+{
   EFI_STATUS                      Status;
   EFI_VECTOR_HANDOFF_INFO         *VectorInfoList;
   EFI_VECTOR_HANDOFF_INFO         *VectorInfo;
@@ -92,7 +93,8 @@ EFI_STATUS
 RegisterInterruptHandler(
   IN EFI_EXCEPTION_TYPE             InterruptType,
   IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler
-  ) {
+  )
+{
   // pass down to CpuExceptionHandlerLib
   return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
 }

ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h

@@ -5,8 +5,8 @@
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
-#ifndef __GENERIC_WATCHDOG_H__
-#define __GENERIC_WATCHDOG_H__
+#ifndef GENERIC_WATCHDOG_H_
+#define GENERIC_WATCHDOG_H_
 
 // Refresh Frame:
 #define GENERIC_WDOG_REFRESH_REG              ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
@@ -21,4 +21,4 @@
 #define GENERIC_WDOG_ENABLED          1
 #define GENERIC_WDOG_DISABLED         0
 
-#endif  // __GENERIC_WATCHDOG_H__
+#endif  // GENERIC_WATCHDOG_H_

ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf

@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2013-2017, ARM Limited. All rights reserved.
+#  Copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -13,6 +13,7 @@
   ENTRY_POINT                    = GenericWatchdogEntry
 
 [Sources.common]
+  GenericWatchdog.h
   GenericWatchdogDxe.c
 
 [Packages]

ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h

@@ -1,13 +1,13 @@
 /** @file
 
-  Copyright (c) 2016-2018, ARM Limited. All rights reserved.
+  Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#if !defined _MM_COMMUNICATE_H_
-#define _MM_COMMUNICATE_H_
+#ifndef MM_COMMUNICATE_H_
+#define MM_COMMUNICATE_H_
 
 #define MM_MAJOR_VER_MASK        0xEFFF0000
 #define MM_MINOR_VER_MASK        0x0000FFFF
@@ -19,4 +19,4 @@
 #define MM_CALLER_MAJOR_VER      0x1UL
 #define MM_CALLER_MINOR_VER      0x0
 
-#endif /* _MM_COMMUNICATE_H_ */
+#endif /* MM_COMMUNICATE_H_ */

ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2016-2018, ARM Limited. All rights reserved.
+  Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -16,7 +16,7 @@
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
 
-#include <Protocol/MmCommunication.h>
+#include <Protocol/MmCommunication2.h>
 
 #include <IndustryStandard/ArmStdSmc.h>
 
@@ -39,38 +39,33 @@ STATIC EFI_HANDLE  mMmCommunicateHandle;
 /**
   Communicates with a registered handler.
 
-  This function provides an interface to send and receive messages to the
-  Standalone MM environment on behalf of UEFI services.  This function is part
-  of the MM Communication Protocol that may be called in physical mode prior to
-  SetVirtualAddressMap() and in virtual mode after SetVirtualAddressMap().
+  This function provides a service to send and receive messages from a registered UEFI service.
 
-  @param[in]      This                The EFI_MM_COMMUNICATION_PROTOCOL
-                                      instance.
-  @param[in, out] CommBuffer          A pointer to the buffer to convey
-                                      into MMRAM.
-  @param[in, out] CommSize            The size of the data buffer being
-                                      passed in. This is optional.
+  @param[in] This                The EFI_MM_COMMUNICATION_PROTOCOL instance.
+  @param[in] CommBufferPhysical  Physical address of the MM communication buffer
+  @param[in] CommBufferVirtual   Virtual address of the MM communication buffer
+  @param[in] CommSize            The size of the data buffer being passed in. On exit, the size of data
+                                 being returned. Zero if the handler does not wish to reply with any data.
+                                 This parameter is optional and may be NULL.
 
   @retval EFI_SUCCESS            The message was successfully posted.
-  @retval EFI_INVALID_PARAMETER       The CommBuffer was NULL.
-  @retval EFI_BAD_BUFFER_SIZE         The buffer size is incorrect for the MM
-                                      implementation. If this error is
-                                      returned, the MessageLength field in
-                                      the CommBuffer header or the integer
-                                      pointed by CommSize are updated to reflect
-                                      the maximum payload size the
-                                      implementation can accommodate.
-  @retval EFI_ACCESS_DENIED           The CommunicateBuffer parameter
-                                      or CommSize parameter, if not omitted,
-                                      are in address range that cannot be
-                                      accessed by the MM environment
+  @retval EFI_INVALID_PARAMETER  CommBufferPhysical was NULL or CommBufferVirtual was NULL.
+  @retval EFI_BAD_BUFFER_SIZE    The buffer is too large for the MM implementation.
+                                 If this error is returned, the MessageLength field
+                                 in the CommBuffer header or the integer pointed by
+                                 CommSize, are updated to reflect the maximum payload
+                                 size the implementation can accommodate.
+  @retval EFI_ACCESS_DENIED      The CommunicateBuffer parameter or CommSize parameter,
+                                 if not omitted, are in address range that cannot be
+                                 accessed by the MM environment.
+
 **/
-STATIC
 EFI_STATUS
 EFIAPI
-MmCommunicationCommunicate (
-  IN CONST EFI_MM_COMMUNICATION_PROTOCOL  *This,
-  IN OUT VOID                             *CommBuffer,
+MmCommunication2Communicate (
+  IN CONST EFI_MM_COMMUNICATION2_PROTOCOL   *This,
+  IN OUT VOID                               *CommBufferPhysical,
+  IN OUT VOID                               *CommBufferVirtual,
   IN OUT UINTN                              *CommSize OPTIONAL
   )
 {
@@ -87,11 +82,11 @@ MmCommunicationCommunicate (
   //
   // Check parameters
   //
-  if (CommBuffer == NULL) {
+  if (CommBufferVirtual == NULL) {
     return EFI_INVALID_PARAMETER;
   }
 
-  CommunicateHeader = CommBuffer;
+  CommunicateHeader = CommBufferVirtual;
   // CommBuffer is a mandatory parameter. Hence, Rely on
   // MessageLength + Header to ascertain the
   // total size of the communication payload rather than
@@ -101,7 +96,7 @@ MmCommunicationCommunicate (
                sizeof (CommunicateHeader->MessageLength);
 
   // If the length of the CommBuffer is 0 then return the expected length.
-  if (CommSize) {
+  if (CommSize != 0) {
     // This case can be used by the consumer of this driver to find out the
     // max size that can be used for allocating CommBuffer.
     if ((*CommSize == 0) ||
@@ -136,7 +131,7 @@ MmCommunicationCommunicate (
   CommunicateSmcArgs.Arg1 = 0;
 
   // Copy Communication Payload
-  CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBuffer, BufferSize);
+  CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBufferVirtual, BufferSize);
 
   // comm_buffer_address (64-bit physical address)
   CommunicateSmcArgs.Arg2 = (UINTN)mNsCommBuffMemRegion.PhysicalBase;
@@ -149,7 +144,7 @@ MmCommunicationCommunicate (
 
   switch (CommunicateSmcArgs.Arg0) {
   case ARM_SMC_MM_RET_SUCCESS:
-    ZeroMem (CommBuffer, BufferSize);
+    ZeroMem (CommBufferVirtual, BufferSize);
     // On successful return, the size of data being returned is inferred from
     // MessageLength + Header.
     CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
@@ -158,7 +153,7 @@ MmCommunicationCommunicate (
                  sizeof (CommunicateHeader->MessageLength);
 
     CopyMem (
-      CommBuffer,
+      CommBufferVirtual,
       (VOID *)mNsCommBuffMemRegion.VirtualBase,
       BufferSize
       );
@@ -191,8 +186,8 @@ MmCommunicationCommunicate (
 //
 // MM Communication Protocol instance
 //
-EFI_MM_COMMUNICATION_PROTOCOL  mMmCommunication = {
-  MmCommunicationCommunicate
+STATIC EFI_MM_COMMUNICATION2_PROTOCOL  mMmCommunication2 = {
+  MmCommunication2Communicate
 };
 
 /**
@@ -293,7 +288,7 @@ MmGuidedEventNotify (
   Header.Data[0] = 0;
 
   Size = sizeof (Header);
-  MmCommunicationCommunicate (&mMmCommunication, &Header, &Size);
+  MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);
 }
 
 /**
@@ -312,7 +307,7 @@ MmGuidedEventNotify (
 **/
 EFI_STATUS
 EFIAPI
-MmCommunicationInitialize (
+MmCommunication2Initialize (
   IN EFI_HANDLE         ImageHandle,
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
@@ -363,9 +358,9 @@ MmCommunicationInitialize (
   // Install the communication protocol
   Status = gBS->InstallProtocolInterface (
                   &mMmCommunicateHandle,
-                  &gEfiMmCommunicationProtocolGuid,
+                  &gEfiMmCommunication2ProtocolGuid,
                   EFI_NATIVE_INTERFACE,
-                  &mMmCommunication
+                  &mMmCommunication2
                   );
   if (EFI_ERROR(Status)) {
     DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: "
@@ -390,12 +385,20 @@ MmCommunicationInitialize (
                     MmGuidedEventNotify, mGuidedEventGuid[Index],
                     mGuidedEventGuid[Index], &mGuidedEvent[Index]);
     ASSERT_EFI_ERROR (Status);
+    if (EFI_ERROR (Status)) {
+      while (Index-- > 0) {
+        gBS->CloseEvent (mGuidedEvent[Index]);
       }
+      goto UninstallProtocol;
+    }
+  }
+  return EFI_SUCCESS;
 
+UninstallProtocol:
   gBS->UninstallProtocolInterface (
          mMmCommunicateHandle,
-         &gEfiMmCommunicationProtocolGuid,
-         &mMmCommunication
+         &gEfiMmCommunication2ProtocolGuid,
+         &mMmCommunication2
          );
 
 CleanAddedMemorySpace:

ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf

@@ -2,7 +2,7 @@
 #
 #  DXE MM Communicate driver
 #
-#  Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.
+#  Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -14,7 +14,7 @@
   FILE_GUID                      = 09EE81D3-F15E-43F4-85B4-CB9873DA5D6B
   MODULE_TYPE                    = DXE_RUNTIME_DRIVER
   VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = MmCommunicationInitialize
+  ENTRY_POINT                    = MmCommunication2Initialize
 
 #
 # The following is for reference only and not required by
@@ -24,6 +24,7 @@
 #
 
 [Sources.AARCH64]
+  MmCommunicate.h
   MmCommunication.c
 
 [Packages]
@@ -40,7 +41,7 @@
   UefiDriverEntryPoint
 
 [Protocols]
-  gEfiMmCommunicationProtocolGuid              ## PRODUCES
+  gEfiMmCommunication2ProtocolGuid              ## PRODUCES
 
 [Guids]
   gEfiEndOfDxeEventGroupGuid

ArmPkg/Drivers/TimerDxe/TimerDxe.c

@@ -1,7 +1,7 @@
 /** @file
   Timer Architecture Protocol driver of the ARM flavor
 
-  Copyright (c) 2011-2013 ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -307,7 +307,7 @@ TimerInterruptHandler (
   // Check if the timer interrupt is active
   if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
 
-    if (mTimerNotifyFunction) {
+    if (mTimerNotifyFunction != 0) {
       mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
     }
 
@@ -359,7 +359,7 @@ TimerInitialize (
   IN EFI_SYSTEM_TABLE   *SystemTable
   )
 {
-  EFI_HANDLE  Handle = NULL;
+  EFI_HANDLE  Handle;
   EFI_STATUS  Status;
   UINTN       TimerCtrlReg;
   UINT32      TimerHypIntrNum;
@@ -408,6 +408,7 @@ TimerInitialize (
   Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
   ASSERT_EFI_ERROR (Status);
 
+  Handle = NULL;
   // Install the Timer Architectural Protocol onto a new handle
   Status = gBS->InstallMultipleProtocolInterfaces(
                   &Handle,

ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c

@@ -2,7 +2,7 @@
   Support a Semi Host file system over a debuggers JTAG
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Portions copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -51,7 +51,7 @@ EFI_FILE gSemihostFsFile = {
 };
 
 //
-// Device path for semi-hosting. It contains our autogened Caller ID GUID.
+// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
 //
 typedef struct {
   VENDOR_DEVICE_PATH        Guid;
@@ -90,8 +90,9 @@ AllocateFCB (
   VOID
   )
 {
-  SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
+  SEMIHOST_FCB *Fcb;
 
+  Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
   if (Fcb != NULL) {
     CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));
     Fcb->Signature = SEMIHOST_FCB_SIGNATURE;
@@ -122,7 +123,7 @@ VolumeOpen (
   OUT EFI_FILE                        **Root
   )
 {
-  SEMIHOST_FCB *RootFcb = NULL;
+  SEMIHOST_FCB *RootFcb;
 
   if (Root == NULL) {
     return EFI_INVALID_PARAMETER;
@@ -196,8 +197,8 @@ FileOpen (
     return EFI_INVALID_PARAMETER;
   }
 
-  if ((OpenMode & EFI_FILE_MODE_CREATE) &&
-      (Attributes & EFI_FILE_DIRECTORY)    ) {
+  if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
+      ((Attributes & EFI_FILE_DIRECTORY) != 0)) {
     return EFI_WRITE_PROTECTED;
   }
 
@@ -234,7 +235,7 @@ FileOpen (
   Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
 
   if (RETURN_ERROR (Return)) {
-    if (OpenMode & EFI_FILE_MODE_CREATE) {
+    if ((OpenMode & EFI_FILE_MODE_CREATE) != 0) {
       //
       // In the create if does not exist case, if the opening in update
       // mode failed, create it and open it in update mode. The update
@@ -277,7 +278,8 @@ FileOpen (
 
   FileFcb->Info.FileSize     = Length;
   FileFcb->Info.PhysicalSize = Length;
-  FileFcb->Info.Attribute    = (OpenMode & EFI_FILE_MODE_CREATE) ? Attributes : 0;
+  FileFcb->Info.Attribute    = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
+                                 Attributes : 0;
 
   InsertTailList (&gFileList, &FileFcb->Link);
 
@@ -758,12 +760,13 @@ GetFileInfo (
   OUT    VOID          *Buffer
   )
 {
-  EFI_FILE_INFO   *Info = NULL;
-  UINTN           NameSize = 0;
+  EFI_FILE_INFO   *Info;
+  UINTN           NameSize;
   UINTN           ResultSize;
   UINTN           Index;
 
-  if (Fcb->IsRoot == TRUE) {
+  if (Fcb->IsRoot) {
+    NameSize = 0;
     ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
   } else {
     NameSize   = AsciiStrLen (Fcb->FileName) + 1;
@@ -783,7 +786,7 @@ GetFileInfo (
   // Fill in the structure
   Info->Size = ResultSize;
 
-  if (Fcb->IsRoot == TRUE) {
+  if (Fcb->IsRoot) {
     Info->FileName[0]  = L'\0';
   } else {
     for (Index = 0; Index < NameSize; Index++) {

ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h

@@ -7,8 +7,8 @@
 
 **/
 
-#ifndef __SEMIHOST_FS_H__
-#define __SEMIHOST_FS_H__
+#ifndef SEMIHOST_FS_H_
+#define SEMIHOST_FS_H_
 
 EFI_STATUS
 VolumeOpen (
@@ -242,5 +242,5 @@ FileFlush (
   IN EFI_FILE *File
   );
 
-#endif // __SEMIHOST_FS_H__
+#endif // SEMIHOST_FS_H_
 

ArmPkg/Include/AsmMacroIoLib.h

@@ -10,8 +10,8 @@
 **/
 
 
-#ifndef __MACRO_IO_LIB_H__
-#define __MACRO_IO_LIB_H__
+#ifndef ASM_MACRO_IO_LIB_H_
+#define ASM_MACRO_IO_LIB_H_
 
 #define _ASM_FUNC(Name, Section)    \
   .global   Name                  ; \
@@ -36,4 +36,4 @@
   movt      Reg, #:upper16:(Sym) - (. + 12) ; \
   ldr       Reg, [pc, Reg]
 
-#endif
+#endif // ASM_MACRO_IO_LIB_H_

ArmPkg/Include/AsmMacroIoLibV8.h

@@ -10,8 +10,8 @@
 **/
 
 
-#ifndef __MACRO_IO_LIBV8_H__
-#define __MACRO_IO_LIBV8_H__
+#ifndef ASM_MACRO_IO_LIBV8_H_
+#define ASM_MACRO_IO_LIBV8_H_
 
 // CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
 // This only selects between EL1 and EL2, else we die.
@@ -54,4 +54,4 @@
   movk      Reg, ((Val) >> 16) & 0xffff, lsl #16  ; \
   movk      Reg, (Val) & 0xffff
 
-#endif // __MACRO_IO_LIBV8_H__
+#endif // ASM_MACRO_IO_LIBV8_H_

ArmPkg/Include/Chipset/AArch64.h

@@ -1,14 +1,14 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef __AARCH64_H__
-#define __AARCH64_H__
+#ifndef AARCH64_H_
+#define AARCH64_H_
 
 #include <Chipset/AArch64Mmu.h>
 
@@ -39,7 +39,7 @@
 // MIDR - Main ID Register definitions
 #define ARM_CPU_TYPE_SHIFT      4
 #define ARM_CPU_TYPE_MASK       0xFFF
-#define ARM_CPU_TYPE_AEMv8      0xD0F
+#define ARM_CPU_TYPE_AEMV8      0xD0F
 #define ARM_CPU_TYPE_A53        0xD03
 #define ARM_CPU_TYPE_A57        0xD07
 #define ARM_CPU_TYPE_A72        0xD08
@@ -97,10 +97,10 @@
 #define ARM_VECTOR_CUR_SP0_FIQ  0x100
 #define ARM_VECTOR_CUR_SP0_SERR 0x180
 
-#define ARM_VECTOR_CUR_SPx_SYNC 0x200
-#define ARM_VECTOR_CUR_SPx_IRQ  0x280
-#define ARM_VECTOR_CUR_SPx_FIQ  0x300
-#define ARM_VECTOR_CUR_SPx_SERR 0x380
+#define ARM_VECTOR_CUR_SPX_SYNC 0x200
+#define ARM_VECTOR_CUR_SPX_IRQ  0x280
+#define ARM_VECTOR_CUR_SPX_FIQ  0x300
+#define ARM_VECTOR_CUR_SPX_SERR 0x380
 
 #define ARM_VECTOR_LOW_A64_SYNC 0x400
 #define ARM_VECTOR_LOW_A64_IRQ  0x480
@@ -112,6 +112,10 @@
 #define ARM_VECTOR_LOW_A32_FIQ  0x700
 #define ARM_VECTOR_LOW_A32_SERR 0x780
 
+// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
+// build for ARMv8.0, we need to define the register here.
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+
 #define VECTOR_BASE(tbl)          \
   .section .text.##tbl##,"ax";    \
   .align 11;                      \
@@ -219,11 +223,6 @@ ArmReadCurrentEL (
   VOID
   );
 
-UINT64
-PageAttributeToGcdAttribute (
-  IN UINT64 PageAttributes
-  );
-
 UINTN
 ArmWriteCptr (
   IN  UINT64 Cptr
@@ -239,4 +238,4 @@ ArmWriteCntHctl (
   IN UINT32 CntHctl
   );
 
-#endif // __AARCH64_H__
+#endif // AARCH64_H_

ArmPkg/Include/Chipset/AArch64Mmu.h

@@ -1,13 +1,13 @@
 /** @file
 *
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
 
-#ifndef __AARCH64_MMU_H_
-#define __AARCH64_MMU_H_
+#ifndef AARCH64_MMU_H_
+#define AARCH64_MMU_H_
 
 //
 // Memory Attribute Indirection register Definitions
@@ -190,9 +190,9 @@
 
 // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
 // Virtual address range for 512GB of virtual space sets T*SZ to 25
-#define INPUT_ADDRESS_SIZE_TO_TxSZ(a)        (64 - a)
+#define INPUT_ADDRESS_SIZE_TO_TXSZ(a)        (64 - a)
 
 // Uses LPAE Page Table format
 
-#endif // __AARCH64_MMU_H_
+#endif // AARCH64_MMU_H_
 

ArmPkg/Include/Chipset/ArmCortexA5x.h

@@ -1,13 +1,13 @@
 /** @file
 
-  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
+  Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef __ARM_CORTEX_A5x_H__
-#define __ARM_CORTEX_A5x_H__
+#ifndef ARM_CORTEX_A5X_H_
+#define ARM_CORTEX_A5X_H_
 
 //
 // Cortex A5x feature bit definitions
@@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
   IN  UINT64    Bits
   );
 
-#endif
+#endif // ARM_CORTEX_A5X_H_

ArmPkg/Include/Chipset/ArmCortexA9.h

@@ -6,8 +6,8 @@
 
 **/
 
-#ifndef __ARM_CORTEX_A9_H__
-#define __ARM_CORTEX_A9_H__
+#ifndef ARM_CORTEX_A9_H_
+#define ARM_CORTEX_A9_H_
 
 #include <Chipset/ArmV7.h>
 
@@ -55,5 +55,5 @@ ArmGetScuBaseAddress (
   VOID
   );
 
-#endif
+#endif // ARM_CORTEX_A9_H_
 

ArmPkg/Include/Chipset/ArmV7.h

@@ -1,14 +1,14 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef __ARM_V7_H__
-#define __ARM_V7_H__
+#ifndef ARM_V7_H_
+#define ARM_V7_H_
 
 #include <Chipset/ArmV7Mmu.h>
 
@@ -70,7 +70,7 @@
 // MIDR - Main ID Register definitions
 #define ARM_CPU_TYPE_SHIFT      4
 #define ARM_CPU_TYPE_MASK       0xFFF
-#define ARM_CPU_TYPE_AEMv8      0xD0F
+#define ARM_CPU_TYPE_AEMV8      0xD0F
 #define ARM_CPU_TYPE_A53        0xD03
 #define ARM_CPU_TYPE_A57        0xD07
 #define ARM_CPU_TYPE_A15        0xC0F
@@ -120,4 +120,4 @@ ArmWriteNsacr (
   IN  UINT32   Nsacr
   );
 
-#endif // __ARM_V7_H__
+#endif // ARM_V7_H_

ArmPkg/Include/Chipset/ArmV7Mmu.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARMV7_MMU_H_
-#define __ARMV7_MMU_H_
+#ifndef ARMV7_MMU_H_
+#define ARMV7_MMU_H_
 
 #define TTBR_NOT_OUTER_SHAREABLE             BIT5
 #define TTBR_RGN_OUTER_NON_CACHEABLE         0
@@ -235,4 +235,4 @@ ConvertSectionAttributesToPageAttributes (
   IN BOOLEAN  IsLargePage
   );
 
-#endif
+#endif // ARMV7_MMU_H_

ArmPkg/Include/Guid/ArmMpCoreInfo.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_MP_CORE_INFO_GUID_H_
-#define __ARM_MP_CORE_INFO_GUID_H_
+#ifndef ARM_MP_CORE_INFO_GUID_H_
+#define ARM_MP_CORE_INFO_GUID_H_
 
 #define MAX_CPUS_PER_MPCORE_SYSTEM    0x04
 #define SCU_CONFIG_REG_OFFSET         0x04
@@ -57,4 +57,4 @@ typedef struct {
 
 extern EFI_GUID gArmMpCoreInfoGuid;
 
-#endif /* MPCOREINFO_H_ */
+#endif /* ARM_MP_CORE_INFO_GUID_H_ */

ArmPkg/Include/IndustryStandard/ArmCache.h

@@ -0,0 +1,112 @@
+/** @file
+
+  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_CACHE_H_
+#define ARM_CACHE_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// The ARM Architecture Reference Manual for ARMv8-A defines up
+// to 7 levels of cache, L1 through L7.
+#define MAX_ARM_CACHE_LEVEL   7
+
+/// Defines the structure of the CSSELR (Cache Size Selection) register
+typedef union {
+  struct {
+    UINT32    InD       :1;  ///< Instruction not Data bit
+    UINT32    Level     :3;  ///< Cache level (zero based)
+    UINT32    TnD       :1;  ///< Allocation not Data bit
+    UINT32    Reserved  :27; ///< Reserved, RES0
+  } Bits; ///< Bitfield definition of the register
+  UINT32 Data; ///< The entire 32-bit value
+} CSSELR_DATA;
+
+/// The cache type values for the InD field of the CSSELR register
+typedef enum
+{
+  /// Select the data or unified cache
+  CsselrCacheTypeDataOrUnified = 0,
+  /// Select the instruction cache
+  CsselrCacheTypeInstruction,
+  CsselrCacheTypeMax
+} CSSELR_CACHE_TYPE;
+
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register
+typedef union {
+  struct {
+    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)
+    UINT64    Associativity      :10; ///< Associativity - 1
+    UINT64    NumSets            :15; ///< Number of sets in the cache -1
+    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN
+    UINT64    Reserved           :32; ///< Reserved, RES0
+  } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
+  struct {
+    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)
+    UINT64    Associativity      :21; ///< Associativity - 1
+    UINT64    Reserved1          :8;  ///< Reserved, RES0
+    UINT64    NumSets            :24; ///< Number of sets in the cache -1
+    UINT64    Reserved2          :8;  ///< Reserved, RES0
+  } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
+  struct {
+    UINT64    LineSize           : 3;
+    UINT64    Associativity      : 21;
+    UINT64    Reserved           : 8;
+    UINT64    Unallocated        : 32;
+  } BitsCcidxAA32;
+  UINT64 Data; ///< The entire 64-bit value
+} CCSIDR_DATA;
+
+/// Defines the structure of the AARCH32 CCSIDR2 register.
+typedef union {
+  struct {
+    UINT32 NumSets               :24; ///< Number of sets in the cache - 1
+    UINT32 Reserved              :8;  ///< Reserved, RES0
+  } Bits; ///< Bitfield definition of the register
+  UINT32 Data; ///< The entire 32-bit value
+} CCSIDR2_DATA;
+
+/** Defines the structure of the CLIDR (Cache Level ID) register.
+ *
+ * The lower 32 bits are the same for both AARCH32 and AARCH64
+ * so we can use the same structure for both.
+**/
+typedef union {
+  struct {
+    UINT32    Ctype1   : 3; ///< Level 1 cache type
+    UINT32    Ctype2   : 3; ///< Level 2 cache type
+    UINT32    Ctype3   : 3; ///< Level 3 cache type
+    UINT32    Ctype4   : 3; ///< Level 4 cache type
+    UINT32    Ctype5   : 3; ///< Level 5 cache type
+    UINT32    Ctype6   : 3; ///< Level 6 cache type
+    UINT32    Ctype7   : 3; ///< Level 7 cache type
+    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable
+    UINT32    LoC      : 3; ///< Level of Coherency
+    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor
+    UINT32    Icb      : 3; ///< Inner Cache Boundary
+  } Bits; ///< Bitfield definition of the register
+  UINT32 Data; ///< The entire 32-bit value
+} CLIDR_DATA;
+
+/// The cache types reported in the CLIDR register.
+typedef enum {
+  /// No cache is present
+  ClidrCacheTypeNone = 0,
+  /// There is only an instruction cache
+  ClidrCacheTypeInstructionOnly,
+  /// There is only a data cache
+  ClidrCacheTypeDataOnly,
+  /// There are separate data and instruction caches
+  ClidrCacheTypeSeparate,
+  /// There is a unified cache
+  ClidrCacheTypeUnified,
+  ClidrCacheTypeMax
+} CLIDR_CACHE_TYPE;
+
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+
+#endif /* ARM_CACHE_H_ */

ArmPkg/Include/IndustryStandard/ArmFfaSvc.h

@@ -0,0 +1,56 @@
+/** @file
+  Header file for FF-A ABI's that will be used for
+  communication between S-EL0 and the Secure Partition
+  Manager(SPM)
+
+  Copyright (c) 2020, ARM Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    - FF-A Version 1.0
+
+
+**/
+
+#ifndef ARM_FFA_SVC_H_
+#define ARM_FFA_SVC_H_
+
+#define ARM_SVC_ID_FFA_VERSION_AARCH32                  0x84000063
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32      0x8400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32     0x84000070
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64      0xC400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64     0xC4000070
+
+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ     ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP    ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ     ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP    ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#endif
+
+#define SPM_MAJOR_VERSION_FFA                           1
+#define SPM_MINOR_VERSION_FFA                           0
+
+#define ARM_FFA_SPM_RET_SUCCESS                          0
+#define ARM_FFA_SPM_RET_NOT_SUPPORTED                   -1
+#define ARM_FFA_SPM_RET_INVALID_PARAMETERS              -2
+#define ARM_FFA_SPM_RET_NO_MEMORY                       -3
+#define ARM_FFA_SPM_RET_BUSY                            -4
+#define ARM_FFA_SPM_RET_INTERRUPTED                     -5
+#define ARM_FFA_SPM_RET_DENIED                          -6
+#define ARM_FFA_SPM_RET_RETRY                           -7
+#define ARM_FFA_SPM_RET_ABORTED                         -8
+
+// For now, the destination id to be used in the FF-A calls
+// is being hard-coded. Subsequently, support will be added
+// to get the endpoint id's dynamically
+// This is the endpoint id used by the optee os's implementation
+// of the spmc.
+// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
+#define ARM_FFA_DESTINATION_ENDPOINT_ID                  3
+
+#endif // ARM_FFA_SVC_H_

ArmPkg/Include/IndustryStandard/ArmMmSvc.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_MM_SVC_H__
-#define __ARM_MM_SVC_H__
+#ifndef ARM_MM_SVC_H_
+#define ARM_MM_SVC_H_
 
 /*
  * SVC IDs to allow the MM secure partition to initialise itself, handle
@@ -15,10 +15,25 @@
  * privileged operations on its behalf.
  */
 #define ARM_SVC_ID_SPM_VERSION_AARCH32             0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32       0x84000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32   0x84000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32   0x84000065
 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64       0xC4000061
 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64   0xC4000064
 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64   0xC4000065
 
+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE               ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_SP_EVENT_COMPLETE               ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES       ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#endif
+
 #define SET_MEM_ATTR_DATA_PERM_MASK       0x3
 #define SET_MEM_ATTR_DATA_PERM_SHIFT        0
 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS    0
@@ -41,4 +56,7 @@
 #define ARM_SVC_SPM_RET_DENIED               -3
 #define ARM_SVC_SPM_RET_NO_MEMORY            -5
 
-#endif
+#define SPM_MAJOR_VERSION                     0
+#define SPM_MINOR_VERSION                     1
+
+#endif // ARM_MM_SVC_H_

ArmPkg/Include/IndustryStandard/ArmStdSmc.h

@@ -1,13 +1,17 @@
 /** @file
 *
+*  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
 *  Copyright (c) 2012-2017, ARM Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
+* @par Revision Reference:
+*  - SMC Calling Convention version 1.2
+*    (https://developer.arm.com/documentation/den0028/c/?lang=en)
 **/
 
-#ifndef __ARM_STD_SMC_H__
-#define __ARM_STD_SMC_H__
+#ifndef ARM_STD_SMC_H_
+#define ARM_STD_SMC_H_
 
 /*
  * SMC function IDs for Standard Service queries
@@ -45,6 +49,14 @@
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32          0x84000041
 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64          0xC4000041
 
+/* Generic ID when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SMC_ID_MM_COMMUNICATE   ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#endif
+
 /* MM return error codes */
 #define ARM_SMC_MM_RET_SUCCESS              0
 #define ARM_SMC_MM_RET_NOT_SUPPORTED       -1
@@ -52,6 +64,18 @@
 #define ARM_SMC_MM_RET_DENIED              -3
 #define ARM_SMC_MM_RET_NO_MEMORY           -4
 
+// ARM Architecture Calls
+#define SMCCC_VERSION           0x80000000
+#define SMCCC_ARCH_FEATURES     0x80000001
+#define SMCCC_ARCH_SOC_ID       0x80000002
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
+
+#define SMC_ARCH_CALL_SUCCESS            0
+#define SMC_ARCH_CALL_NOT_SUPPORTED     -1
+#define SMC_ARCH_CALL_NOT_REQUIRED      -2
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3
+
 /*
  * Power State Coordination Interface (PSCI) calls cover a subset of the
  * Standard Service Call range.
@@ -113,4 +137,4 @@
 /*                                    0xbf00ff02 is reserved */
 #define ARM_SMC_ID_TOS_REVISION       0xbf00ff03
 
-#endif
+#endif // ARM_STD_SMC_H_

ArmPkg/Include/Library/ArmDisassemblerLib.h

@@ -6,8 +6,8 @@
 
 **/
 
-#ifndef __ARM_DISASSEBLER_LIB_H__
-#define __ARM_DISASSEBLER_LIB_H__
+#ifndef ARM_DISASSEMBLER_LIB_H_
+#define ARM_DISASSEMBLER_LIB_H_
 
 /**
   Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
@@ -34,4 +34,4 @@ DisassembleInstruction (
   OUT UINTN     Size
   );
 
-#endif
+#endif // ARM_DISASSEMBLER_LIB_H_

ArmPkg/Include/Library/ArmGenericTimerCounterLib.h

@@ -7,8 +7,8 @@
 
 **/
 
-#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__
-#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__
+#ifndef ARM_GENERIC_TIMER_COUNTER_LIB_H_
+#define ARM_GENERIC_TIMER_COUNTER_LIB_H_
 
 VOID
 EFIAPI
@@ -82,4 +82,4 @@ ArmGenericTimerSetCompareVal (
   IN   UINT64   Value
   );
 
-#endif
+#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_

ArmPkg/Include/Library/ArmGicArchLib.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_GIC_ARCH_LIB_H__
-#define __ARM_GIC_ARCH_LIB_H__
+#ifndef ARM_GIC_ARCH_LIB_H_
+#define ARM_GIC_ARCH_LIB_H_
 
 //
 // GIC definitions
@@ -24,4 +24,4 @@ ArmGicGetSupportedArchRevision (
   VOID
   );
 
-#endif
+#endif // ARM_GIC_ARCH_LIB_H_

ArmPkg/Include/Library/ArmGicLib.h

@@ -1,13 +1,13 @@
 /** @file
 *
-*  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
 
-#ifndef __ARMGIC_H
-#define __ARMGIC_H
+#ifndef ARMGIC_H_
+#define ARMGIC_H_
 
 #include <Library/ArmGicArchLib.h>
 
@@ -208,6 +208,15 @@ ArmGicSetPriorityMask (
   IN  INTN          PriorityMask
   );
 
+VOID
+EFIAPI
+ArmGicSetInterruptPriority (
+  IN UINTN                  GicDistributorBase,
+  IN UINTN                  GicRedistributorBase,
+  IN UINTN                  Source,
+  IN UINTN                  Priority
+  );
+
 VOID
 EFIAPI
 ArmGicEnableInterrupt (
@@ -324,4 +333,4 @@ ArmGicV3SetPriorityMask (
   IN UINTN                  Priority
   );
 
-#endif
+#endif // ARMGIC_H_

ArmPkg/Include/Library/ArmHvcLib.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_HVC_LIB__
-#define __ARM_HVC_LIB__
+#ifndef ARM_HVC_LIB_H_
+#define ARM_HVC_LIB_H_
 
 /**
  * The size of the HVC arguments are different between AArch64 and AArch32.
@@ -37,4 +37,4 @@ ArmCallHvc (
   IN OUT ARM_HVC_ARGS *Args
   );
 
-#endif
+#endif // ARM_HVC_LIB_H_

ArmPkg/Include/Library/ArmLib.h

@@ -2,13 +2,14 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef __ARM_LIB__
-#define __ARM_LIB__
+#ifndef ARM_LIB_H_
+#define ARM_LIB_H_
 
 #include <Uefi/UefiBaseType.h>
 
@@ -108,6 +109,38 @@ typedef enum {
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 
+/** Reads the CCSIDR register for the specified cache.
+
+  @param CSSELR The CSSELR cache selection register value.
+
+  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+          Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+  IN UINT32 CSSELR
+  );
+
+/** Reads the CCSIDR2 for the specified cache.
+
+  @param CSSELR The CSSELR cache selection register value
+
+  @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+  IN UINT32 CSSELR
+  );
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+  @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
+  VOID
+  );
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
@@ -132,18 +165,6 @@ ArmIsArchTimerImplemented (
   VOID
   );
 
-UINTN
-EFIAPI
-ArmReadIdPfr0 (
-  VOID
-  );
-
-UINTN
-EFIAPI
-ArmReadIdPfr1 (
-  VOID
-  );
-
 UINTN
 EFIAPI
 ArmCacheInfo (
@@ -211,24 +232,6 @@ ArmCleanInvalidateDataCacheEntryByMVA (
   IN  UINTN   Address
   );
 
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryBySetWay (
-  IN  UINTN  SetWayFormat
-  );
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryBySetWay (
-  IN  UINTN  SetWayFormat
-  );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryBySetWay (
-  IN  UINTN   SetWayFormat
-  );
-
 VOID
 EFIAPI
 ArmEnableDataCache (
@@ -733,4 +736,49 @@ ArmGetPhysicalAddressBits (
   VOID
   );
 
-#endif // __ARM_LIB__
+
+///
+///  ID Register Helper functions
+///
+
+/**
+  Check whether the CPU supports the GIC system register interface (any version)
+
+  @return   Whether GIC System Register Interface is supported
+
+**/
+BOOLEAN
+EFIAPI
+ArmHasGicSystemRegisters (
+  VOID
+  );
+
+/** Checks if CCIDX is implemented.
+
+   @retval TRUE  CCIDX is implemented.
+   @retval FALSE CCIDX is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasCcidx (
+  VOID
+  );
+
+#ifdef MDE_CPU_ARM
+///
+/// AArch32-only ID Register Helper functions
+///
+/**
+  Check whether the CPU supports the Security extensions
+
+  @return   Whether the Security extensions are implemented
+
+**/
+BOOLEAN
+EFIAPI
+ArmHasSecurityExtensions (
+  VOID
+  );
+#endif // MDE_CPU_ARM
+
+#endif // ARM_LIB_H_

ArmPkg/Include/Library/ArmMmuLib.h

@@ -6,8 +6,8 @@
 
 **/
 
-#ifndef __ARM_MMU_LIB__
-#define __ARM_MMU_LIB__
+#ifndef ARM_MMU_LIB_H_
+#define ARM_MMU_LIB_H_
 
 #include <Uefi/UefiBaseType.h>
 
@@ -64,4 +64,4 @@ ArmSetMemoryAttributes (
   IN UINT64                    Attributes
   );
 
-#endif
+#endif // ARM_MMU_LIB_H_

ArmPkg/Include/Library/ArmSmcLib.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_SMC_LIB__
-#define __ARM_SMC_LIB__
+#ifndef ARM_SMC_LIB_H_
+#define ARM_SMC_LIB_H_
 
 /**
  * The size of the SMC arguments are different between AArch64 and AArch32.
@@ -37,4 +37,4 @@ ArmCallSmc (
   IN OUT ARM_SMC_ARGS *Args
   );
 
-#endif
+#endif // ARM_SMC_LIB_H_

ArmPkg/Include/Library/ArmSvcLib.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_SVC_LIB__
-#define __ARM_SVC_LIB__
+#ifndef ARM_SVC_LIB_H_
+#define ARM_SVC_LIB_H_
 
 /**
  * The size of the SVC arguments are different between AArch64 and AArch32.
@@ -27,14 +27,20 @@ typedef struct {
 /**
   Trigger an SVC call
 
-  SVC calls can take up to 7 arguments and return up to 4 return values.
-  Therefore, the 4 first fields in the ARM_SVC_ARGS structure are used
+  SVC calls can take up to 8 arguments and return up to 8 return values.
+  Therefore, the 8 first fields in the ARM_SVC_ARGS structure are used
   for both input and output values.
 
+  @param[in, out]    Args Arguments to be passed as part of the SVC call
+                     The return values of the SVC call are also placed
+                     in the same structure
+
+  @retval None
+
 **/
 VOID
 ArmCallSvc (
   IN OUT ARM_SVC_ARGS *Args
   );
 
-#endif
+#endif // ARM_SVC_LIB_H_

ArmPkg/Include/Library/DefaultExceptionHandlerLib.h

@@ -6,8 +6,8 @@
 
 **/
 
-#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
-#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
+#ifndef DEFAULT_EXCEPTION_HANDLER_LIB_H_
+#define DEFAULT_EXCEPTION_HANDLER_LIB_H_
 
 /**
   This is the default action to take on an unexpected exception
@@ -22,4 +22,4 @@ DefaultExceptionHandler (
   IN OUT EFI_SYSTEM_CONTEXT           SystemContext
   );
 
-#endif
+#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_

ArmPkg/Include/Library/OemMiscLib.h

@@ -0,0 +1,235 @@
+/** @file
+*
+*  Copyright (c) 2021, NUVIA Inc. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+
+#ifndef OEM_MISC_LIB_H_
+#define OEM_MISC_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+
+typedef enum
+{
+  CpuCacheL1 = 1,
+  CpuCacheL2,
+  CpuCacheL3,
+  CpuCacheL4,
+  CpuCacheL5,
+  CpuCacheL6,
+  CpuCacheL7,
+  CpuCacheLevelMax
+} OEM_MISC_CPU_CACHE_LEVEL;
+
+typedef struct
+{
+  UINT8 Voltage;        ///< Processor voltage
+  UINT16 CurrentSpeed;  ///< Current clock speed in MHz
+  UINT16 MaxSpeed;      ///< Maximum clock speed in MHz
+  UINT16 ExternalClock; ///< External clock speed in MHz
+  UINT16 CoreCount;     ///< Number of cores available
+  UINT16 CoresEnabled;  ///< Number of cores enabled
+  UINT16 ThreadCount;   ///< Number of threads per processor
+} OEM_MISC_PROCESSOR_DATA;
+
+typedef enum
+{
+    ProductNameType01,
+    SerialNumType01,
+    UuidType01,
+    SystemManufacturerType01,
+    SkuNumberType01,
+    FamilyType01,
+    AssertTagType02,
+    SerialNumberType02,
+    BoardManufacturerType02,
+    SkuNumberType02,
+    ChassisLocationType02,
+    AssetTagType03,
+    SerialNumberType03,
+    VersionType03,
+    ChassisTypeType03,
+    ManufacturerType03,
+    SkuNumberType03,
+    SmbiosHiiStringFieldMax
+} OEM_MISC_SMBIOS_HII_STRING_FIELD;
+
+/*
+ * The following are functions that the each platform needs to
+ * implement in its OemMiscLib library.
+ */
+
+/** Gets the CPU frequency of the specified processor.
+
+  @param ProcessorIndex Index of the processor to get the frequency for.
+
+  @return               CPU frequency in Hz
+**/
+UINTN
+EFIAPI
+OemGetCpuFreq (
+  IN UINT8 ProcessorIndex
+  );
+
+/** Gets information about the specified processor and stores it in
+    the structures provided.
+
+  @param ProcessorIndex  Index of the processor to get the information for.
+  @param ProcessorStatus Processor status.
+  @param ProcessorCharacteristics Processor characteritics.
+  @param MiscProcessorData        Miscellaneous processor information.
+
+  @return  TRUE on success, FALSE on failure.
+**/
+BOOLEAN
+EFIAPI
+OemGetProcessorInformation (
+  IN UINTN ProcessorIndex,
+  IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+  IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+  IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
+  );
+
+/** Gets information about the cache at the specified cache level.
+
+  @param ProcessorIndex The processor to get information for.
+  @param CacheLevel     The cache level to get information for.
+  @param DataCache  Whether the cache is a data cache.
+  @param UnifiedCache Whether the cache is a unified cache.
+  @param SmbiosCacheTable The SMBIOS Type7 cache information structure.
+
+  @return TRUE on success, FALSE on failure.
+**/
+BOOLEAN
+EFIAPI
+OemGetCacheInformation (
+  IN UINT8   ProcessorIndex,
+  IN UINT8   CacheLevel,
+  IN BOOLEAN DataCache,
+  IN BOOLEAN UnifiedCache,
+  IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
+  );
+
+/** Gets the maximum number of processors supported by the platform.
+
+  @return The maximum number of processors.
+**/
+UINT8
+EFIAPI
+OemGetMaxProcessors (
+  VOID
+  );
+
+/** Gets the type of chassis for the system.
+
+  @retval The type of the chassis.
+**/
+MISC_CHASSIS_TYPE
+EFIAPI
+OemGetChassisType (
+  VOID
+  );
+
+/** Returns whether the specified processor is present or not.
+
+  @param ProcessIndex The processor index to check.
+
+  @return TRUE is the processor is present, FALSE otherwise.
+**/
+BOOLEAN
+EFIAPI
+OemIsProcessorPresent (
+  IN UINTN ProcessorIndex
+  );
+
+/** Updates the HII string for the specified field.
+
+  @param HiiHandle     The HII handle.
+  @param TokenToUpdate The string to update.
+  @param Field         The field to get information about.
+**/
+VOID
+EFIAPI
+OemUpdateSmbiosInfo (
+  IN EFI_HII_HANDLE    HiiHandle,
+  IN EFI_STRING_ID     TokenToUpdate,
+  IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
+  );
+
+/** Fetches the Type 32 boot information status.
+
+  @return Boot status.
+**/
+MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
+EFIAPI
+OemGetBootStatus (
+  VOID
+  );
+
+/** Fetches the chassis status when it was last booted.
+
+ @return Chassis status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisBootupState (
+  VOID
+  );
+
+/** Fetches the chassis power supply/supplies status when last booted.
+
+ @return Chassis power supply/supplies status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisPowerSupplyState (
+  VOID
+  );
+
+/** Fetches the chassis thermal status when last booted.
+
+ @return Chassis thermal status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisThermalState (
+  VOID
+  );
+
+/** Fetches the chassis security status when last booted.
+
+ @return Chassis security status.
+**/
+MISC_CHASSIS_SECURITY_STATE
+EFIAPI
+OemGetChassisSecurityStatus (
+  VOID
+  );
+
+/** Fetches the chassis height in RMUs (Rack Mount Units).
+
+  @return The height of the chassis.
+**/
+UINT8
+EFIAPI
+OemGetChassisHeight (
+  VOID
+  );
+
+/** Fetches the number of power cords.
+
+  @return The number of power cords.
+**/
+UINT8
+EFIAPI
+OemGetChassisNumPowerCords (
+  VOID
+  );
+
+#endif // OEM_MISC_LIB_H_

ArmPkg/Include/Library/OpteeLib.h

@@ -2,13 +2,14 @@
   OP-TEE specific header file.
 
   Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef _OPTEE_H_
-#define _OPTEE_H_
+#ifndef OPTEE_LIB_H_
+#define OPTEE_LIB_H_
 
 /*
  * The 'Trusted OS Call UID' is supposed to return the following UUID for
@@ -45,12 +46,14 @@ typedef struct {
   UINT64    C;
 } OPTEE_MESSAGE_PARAM_VALUE;
 
-typedef struct {
-  UINT64 Attribute;
-  union {
+typedef union {
   OPTEE_MESSAGE_PARAM_MEMORY   Memory;
   OPTEE_MESSAGE_PARAM_VALUE    Value;
-  } Union;
+} OPTEE_MESSAGE_PARAM_UNION;
+
+typedef struct {
+  UINT64 Attribute;
+  OPTEE_MESSAGE_PARAM_UNION Union;
 } OPTEE_MESSAGE_PARAM;
 
 #define OPTEE_MAX_CALL_PARAMS       4
@@ -114,4 +117,4 @@ OpteeInvokeFunction (
   IN OUT OPTEE_INVOKE_FUNCTION_ARG       *InvokeFunctionArg
   );
 
-#endif
+#endif // OPTEE_LIB_H_

ArmPkg/Include/Library/SemihostLib.h

@@ -7,8 +7,8 @@
 
 **/
 
-#ifndef __SEMIHOSTING_H__
-#define __SEMIHOSTING_H__
+#ifndef SEMIHOSTING_LIB_H_
+#define SEMIHOSTING_LIB_H_
 
 /*
  *
@@ -129,4 +129,4 @@ SemihostSystem (
   IN CHAR8 *CommandLine
   );
 
-#endif // __SEMIHOSTING_H__
+#endif // SEMIHOSTING_LIB_H_

ArmPkg/Include/Library/StandaloneMmMmuLib.h

@@ -6,8 +6,8 @@
 
 **/
 
-#ifndef __STANDALONEMM_MMU_LIB__
-#define __STANDALONEMM_MMU_LIB__
+#ifndef STANDALONE_MM_MMU_LIB_
+#define STANDALONE_MM_MMU_LIB_
 
 EFI_STATUS
 ArmSetMemoryRegionNoExec (
@@ -33,4 +33,4 @@ ArmClearMemoryRegionReadOnly (
   IN  UINT64                    Length
   );
 
-#endif /* __STANDALONEMM_MMU_LIB__ */
+#endif /* STANDALONE_MM_MMU_LIB_ */

ArmPkg/Include/Ppi/ArmMpCoreInfo.h

@@ -6,8 +6,8 @@
 *
 **/
 
-#ifndef __ARM_MP_CORE_INFO_PPI_H__
-#define __ARM_MP_CORE_INFO_PPI_H__
+#ifndef ARM_MP_CORE_INFO_PPI_H_
+#define ARM_MP_CORE_INFO_PPI_H_
 
 #include <Guid/ArmMpCoreInfo.h>
 
@@ -49,4 +49,4 @@ typedef struct {
 extern EFI_GUID gArmMpCoreInfoPpiGuid;
 extern EFI_GUID gArmMpCoreInfoGuid;
 
-#endif
+#endif // ARM_MP_CORE_INFO_PPI_H_

ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h

@@ -1,12 +1,12 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  System Control and Management Interface V1.0
-    http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
-    DEN0056A_System_Control_and_Management_Interface.pdf
+  @par Specification Reference:
+  - Arm System Control and Management Interface - Platform Design Document
+    (https://developer.arm.com/documentation/den0056/)
 **/
 
 #ifndef ARM_SCMI_BASE_PROTOCOL_H_
@@ -14,7 +14,8 @@
 
 #include <Protocol/ArmScmi.h>
 
-#define BASE_PROTOCOL_VERSION  0x10000
+#define BASE_PROTOCOL_VERSION_V1  0x10000
+#define BASE_PROTOCOL_VERSION_V2  0x20000
 
 #define NUM_PROTOCOL_MASK      0xFFU
 #define NUM_AGENT_MASK         0xFFU
@@ -158,11 +159,10 @@ typedef struct _SCMI_BASE_PROTOCOL {
 
 // SCMI Message IDs for Base protocol.
 typedef enum {
-  SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR                  = 0x3,
-  SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR              = 0x4,
-  SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION  = 0x5,
-  SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS          = 0x6
+  ScmiMessageIdBaseDiscoverVendor                 = 0x3,
+  ScmiMessageIdBaseDiscoverSubVendor              = 0x4,
+  ScmiMessageIdBaseDiscoverImplementationVersion  = 0x5,
+  ScmiMessageIdBaseDiscoverListProtocols          = 0x6
 } SCMI_MESSAGE_ID_BASE;
 
 #endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
-

ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -89,10 +89,10 @@ EFI_STATUS
   @param[in] This        A pointer to SCMI_CLOCK2_PROTOCOL Instance.
   @param[in] ClockId     Identifier for the clock device.
 
-  @param[out] Format      SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+  @param[out] Format      ScmiClockRateFormatDiscrete: Clock device
                           supports range of clock rates which are non-linear.
 
-                          SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+                          ScmiClockRateFormatLinear: Clock device supports
                           range of linear clock rates from Min to Max in steps.
 
   @param[out] TotalRates  Total number of rates.

ArmPkg/Include/Protocol/ArmScmiClockProtocol.h

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -22,16 +22,16 @@ extern EFI_GUID gArmScmiClockProtocolGuid;
 
 // Message Type for clock management protocol.
 typedef enum {
-  SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES     = 0x3,
-  SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES = 0x4,
-  SCMI_MESSAGE_ID_CLOCK_RATE_SET       = 0x5,
-  SCMI_MESSAGE_ID_CLOCK_RATE_GET       = 0x6,
-  SCMI_MESSAGE_ID_CLOCK_CONFIG_SET     = 0x7
+  ScmiMessageIdClockAttributes    = 0x3,
+  ScmiMessageIdClockDescribeRates = 0x4,
+  ScmiMessageIdClockRateSet       = 0x5,
+  ScmiMessageIdClockRateGet       = 0x6,
+  ScmiMessageIdClockConfigSet     = 0x7
 } SCMI_MESSAGE_ID_CLOCK;
 
 typedef enum {
-  SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range.
-  SCMI_CLOCK_RATE_FORMAT_LINEAR    // Linear range.
+  ScmiClockRateFormatDiscrete, // Non-linear range.
+  ScmiClockRateFormatLinear    // Linear range.
 } SCMI_CLOCK_RATE_FORMAT;
 
 // Clock management protocol version.
@@ -57,12 +57,18 @@ typedef enum {
    either Rate or Min/Max/Step triplet is valid.
 */
 typedef struct {
-  union {
   UINT64 Min;
-  UINT64 Rate;
-  };
   UINT64 Max;
   UINT64 Step;
+} SCMI_CLOCK_RATE_CONTINUOUS;
+
+typedef struct {
+  UINT64 Rate;
+} SCMI_CLOCK_RATE_DISCRETE;
+
+typedef union {
+  SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
+  SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
 } SCMI_CLOCK_RATE;
 
 #pragma pack()
@@ -133,10 +139,10 @@ EFI_STATUS
   @param[in] This        A pointer to SCMI_CLOCK_PROTOCOL Instance.
   @param[in] ClockId     Identifier for the clock device.
 
-  @param[out] Format      SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+  @param[out] Format      ScmiClockRateFormatDiscrete: Clock device
                           supports range of clock rates which are non-linear.
 
-                          SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+                          ScmiClockRateFormatLinear: Clock device supports
                           range of linear clock rates from Min to Max in steps.
 
   @param[out] TotalRates  Total number of rates.

ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h

@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+  Copyright (c) 2017-2021, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -247,12 +247,12 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL {
 } SCMI_PERFORMANCE_PROTOCOL;
 
 typedef enum {
-  SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES = 0x3,
-  SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS   = 0x4,
-  SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET        = 0x5,
-  SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET        = 0x6,
-  SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET         = 0x7,
-  SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET         = 0x8,
+  ScmiMessageIdPerformanceDomainAttributes = 0x3,
+  ScmiMessageIdPerformanceDescribeLevels   = 0x4,
+  ScmiMessageIdPerformanceLimitsSet        = 0x5,
+  ScmiMessageIdPerformanceLimitsGet        = 0x6,
+  ScmiMessageIdPerformanceLevelSet         = 0x7,
+  ScmiMessageIdPerformanceLevelGet         = 0x8,
 } SCMI_MESSAGE_ID_PERFORMANCE;
 
 #endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */

ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c

@@ -1,7 +1,7 @@
 /** @file
   Generic ARM implementation of TimerLib.h
 
-  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+  Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -20,9 +20,9 @@
 
 // Select appropriate multiply function for platform architecture.
 #ifdef MDE_CPU_ARM
-#define MultU64xN MultU64x32
+#define MULT_U64_X_N MultU64x32
 #else
-#define MultU64xN MultU64x64
+#define MULT_U64_X_N MultU64x64
 #endif
 
 
@@ -56,7 +56,7 @@ TimerConstructor (
       // If the security extension is not implemented, set Timer Frequency
       // here.
       //
-      if ((ArmReadIdPfr1 () & ARM_PFR1_SEC) == 0x0) {
+      if (ArmHasSecurityExtensions ()) {
         ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
       }
 #endif
@@ -121,7 +121,7 @@ MicroSecondDelay (
   //  = MicroSeconds x TICKS_PER_MICRO_SEC
   //  = MicroSeconds x Frequency.10^-6
   TimerTicks64 = DivU64x32 (
-                   MultU64xN (
+                   MULT_U64_X_N (
                      MicroSeconds,
                      GetPlatformTimerFreq ()
                      ),
@@ -263,7 +263,7 @@ GetTimeInNanoSecond (
   // Time = --------- x 1,000,000,000
   //        Frequency
   //
-  NanoSeconds = MultU64xN (
+  NanoSeconds = MULT_U64_X_N (
                   DivU64x32Remainder (
                     Ticks,
                     TimerFreq,
@@ -276,7 +276,7 @@ GetTimeInNanoSecond (
   // will not overflow 64-bit.
   //
   NanoSeconds += DivU64x32 (
-                   MultU64xN (
+                   MULT_U64_X_N (
                      (UINT64) Remainder,
                      1000000000U),
                    TimerFreq

ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c

@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+  Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -20,11 +20,14 @@ CacheRangeOperation (
   IN  UINTN           LineLength
   )
 {
-  UINTN ArmCacheLineAlignmentMask  = LineLength - 1;
-
+  UINTN ArmCacheLineAlignmentMask;
   // Align address (rounding down)
-  UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
-  UINTN EndAddress     = (UINTN)Start + Length;
+  UINTN AlignedAddress;
+  UINTN EndAddress;
+
+  ArmCacheLineAlignmentMask = LineLength - 1;
+  AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+  EndAddress     = (UINTN)Start + Length;
 
   // Perform the line operation on an address in each cache line
   while (AlignedAddress < EndAddress) {

ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c

@@ -2,6 +2,7 @@
   Default exception handler
 
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -70,7 +71,7 @@ CHAR8 *gLdmStack[] = {
 
 
 #define SIGN(_U)  ((_U) ? "" : "-")
-#define WRITE(_W) ((_W) ? "!" : "")
+#define WRITE(_Write) ((_Write) ? "!" : "")
 #define BYTE(_B)  ((_B) ? "B":"")
 #define USER(_B)  ((_B) ? "^" : "")
 
@@ -157,22 +158,25 @@ DisassembleArmInstruction (
   IN  BOOLEAN   Extended
   )
 {
-  UINT32    OpCode = **OpCodePtr;
-  CHAR8     *Type, *Root;
-  BOOLEAN   I, P, U, B, W, L, S, H;
+  UINT32    OpCode;
+  CHAR8     *Type;
+  CHAR8     *Root;
+  BOOLEAN   Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
   UINT32    Rn, Rd, Rm;
-  UINT32    imode, offset_8, offset_12;
+  UINT32    IMod, Offset8, Offset12;
   UINT32    Index;
-  UINT32    shift_imm, shift;
+  UINT32    ShiftImm, Shift;
 
-  I = (OpCode & BIT25) == BIT25;
-  P = (OpCode & BIT24) == BIT24;
-  U = (OpCode & BIT23) == BIT23;
-  B = (OpCode & BIT22) == BIT22;  // Also called S
-  W = (OpCode & BIT21) == BIT21;
-  L = (OpCode & BIT20) == BIT20;
-  S = (OpCode & BIT6) == BIT6;
-  H = (OpCode & BIT5) == BIT5;
+  OpCode = **OpCodePtr;
+
+  Imm = (OpCode & BIT25) == BIT25; // I
+  Pre = (OpCode & BIT24) == BIT24; // P
+  Up = (OpCode & BIT23) == BIT23; // U
+  WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
+  Write = (OpCode & BIT21) == BIT21; // W
+  Load = (OpCode & BIT20) == BIT20; // L
+  Sign = (OpCode & BIT6) == BIT6; // S
+  Half = (OpCode & BIT5) == BIT5; // H
   Rn = (OpCode >> 16) & 0xf;
   Rd = (OpCode >> 12) & 0xf;
   Rm = (OpCode & 0xf);
@@ -186,7 +190,7 @@ DisassembleArmInstruction (
 
   // LDREX, STREX
   if ((OpCode  & 0x0fe000f0) == 0x01800090) {
-    if (L) {
+    if (Load) {
       // A4.1.27  LDREX{<cond>} <Rd>, [<Rn>]
       AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
     } else {
@@ -198,89 +202,89 @@ DisassembleArmInstruction (
 
   // LDM/STM
   if ((OpCode  & 0x0e000000) == 0x08000000) {
-    if (L) {
+    if (Load) {
       // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
       // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
       // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
-      AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
+      AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
     } else {
       // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
       // A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
-      AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
+      AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
     }
     return;
   }
 
   // LDR/STR Address Mode 2
   if ( ((OpCode  & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
-    offset_12 = OpCode & 0xfff;
+    Offset12 = OpCode & 0xfff;
     if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
       Index = AsciiSPrint (Buf, Size, "PLD");
     } else {
-      Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
+      Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
     }
-    if (P) {
-      if (!I) {
+    if (Pre) {
+      if (!Imm) {
         // A5.2.2 [<Rn>, #+/-<offset_12>]
         // A5.2.5 [<Rn>, #+/-<offset_12>]
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
       } else if ((OpCode & 0x03000ff0) == 0x03000000) {
         // A5.2.3 [<Rn>, +/-<Rm>]
         // A5.2.6 [<Rn>, +/-<Rm>]!
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
       } else {
         // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
         // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
-        shift_imm = (OpCode >> 7) & 0x1f;
-        shift = (OpCode >> 5) & 0x3;
-        if (shift == 0x0) {
+        ShiftImm = (OpCode >> 7) & 0x1f;
+        Shift = (OpCode >> 5) & 0x3;
+        if (Shift == 0x0) {
           Type = "LSL";
-        } else if (shift == 0x1) {
+        } else if (Shift == 0x1) {
           Type = "LSR";
-          if (shift_imm == 0) {
-            shift_imm = 32;
+          if (ShiftImm == 0) {
+            ShiftImm = 32;
           }
-        } else if (shift == 0x12) {
+        } else if (Shift == 0x2) {
           Type = "ASR";
-        } else if (shift_imm == 0) {
-          AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
+        } else if (ShiftImm == 0) {
+          AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
           return;
         } else {
           Type = "ROR";
         }
 
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
       }
-    } else {  // !P
-      if (!I) {
+    } else {  // !Pre
+      if (!Imm) {
         // A5.2.8  [<Rn>], #+/-<offset_12>
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
       } else if ((OpCode & 0x03000ff0) == 0x03000000) {
         // A5.2.9  [<Rn>], +/-<Rm>
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
       } else {
         // A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
-        shift_imm = (OpCode >> 7) & 0x1f;
-        shift = (OpCode >> 5) & 0x3;
+        ShiftImm = (OpCode >> 7) & 0x1f;
+        Shift = (OpCode >> 5) & 0x3;
 
-        if (shift == 0x0) {
+        if (Shift == 0x0) {
           Type = "LSL";
-        } else if (shift == 0x1) {
+        } else if (Shift == 0x1) {
           Type = "LSR";
-          if (shift_imm == 0) {
-            shift_imm = 32;
+          if (ShiftImm == 0) {
+            ShiftImm = 32;
           }
-        } else if (shift == 0x12) {
+        } else if (Shift == 0x2) {
           Type = "ASR";
-        } else if (shift_imm == 0) {
-          AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
+        } else if (ShiftImm == 0) {
+          AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
           // FIx me
           return;
         } else {
           Type = "ROR";
         }
 
-        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
+        AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
       }
     }
     return;
@@ -289,18 +293,18 @@ DisassembleArmInstruction (
   if ((OpCode  & 0x0e000000) == 0x00000000) {
     // LDR/STR address mode 3
     // LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
-    if (L) {
-      if (!S) {
+    if (Load) {
+      if (!Sign) {
         Root = "LDR%aH %a, ";
-      } else if (!H) {
+      } else if (!Half) {
         Root = "LDR%aSB %a, ";
       } else {
         Root = "LDR%aSH %a, ";
       }
     } else {
-      if (!S) {
+      if (!Sign) {
         Root = "STR%aH %a ";
-      } else if (!H) {
+      } else if (!Half) {
         Root = "LDR%aD %a ";
       } else {
         Root = "STR%aD %a ";
@@ -309,28 +313,28 @@ DisassembleArmInstruction (
 
     Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
 
-    S = (OpCode & BIT6) == BIT6;
-    H = (OpCode & BIT5) == BIT5;
-    offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
-    if (P & !W) {
+    Sign = (OpCode & BIT6) == BIT6;
+    Half = (OpCode & BIT5) == BIT5;
+    Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
+    if (Pre & !Write) {
       // Immediate offset/index
-      if (B) {
+      if (WriteBack) {
         // A5.3.2  [<Rn>, #+/-<offset_8>]
         // A5.3.4  [<Rn>, #+/-<offset_8>]!
-        AsciiSPrint  (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
+        AsciiSPrint  (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
       } else {
         // A5.3.3  [<Rn>, +/-<Rm>]
         // A5.3.5  [<Rn>, +/-<Rm>]!
-        AsciiSPrint  (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
+        AsciiSPrint  (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
       }
     } else {
       // Register offset/index
-      if (B) {
+      if (WriteBack) {
         // A5.3.6 [<Rn>], #+/-<offset_8>
-        AsciiSPrint  (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
+        AsciiSPrint  (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
       } else {
         // A5.3.7 [<Rn>], +/-<Rm>
-        AsciiSPrint  (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
+        AsciiSPrint  (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
       }
     }
     return;
@@ -339,19 +343,19 @@ DisassembleArmInstruction (
   if ((OpCode  & 0x0fb000f0) == 0x01000050) {
     // A4.1.108  SWP   SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
     // A4.1.109  SWPB  SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
-    AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
+    AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
     return;
   }
 
   if ((OpCode  & 0xfe5f0f00) == 0xf84d0500) {
     // A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
-    AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
+    AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
     return;
   }
 
   if ((OpCode  & 0xfe500f00) == 0xf8100500) {
     // A4.1.59 RFE<addressing_mode> <Rn>{!}
-    AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
+    AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
     return;
   }
 
@@ -366,8 +370,12 @@ DisassembleArmInstruction (
     if (((OpCode >> 6) & 0x7) == 0) {
       AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
     } else {
-      imode = (OpCode >> 18) & 0x3;
-      Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":"");
+      IMod = (OpCode >> 18) & 0x3;
+      Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
+                      (IMod == 3) ? "ID":"IE",
+                      ((OpCode & BIT8) != 0) ? "A":"",
+                      ((OpCode & BIT7) != 0) ? "I":"",
+                      ((OpCode & BIT6) != 0) ? "F":"");
       if ((OpCode & BIT17) != 0) {
         AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
       }
@@ -383,19 +391,19 @@ DisassembleArmInstruction (
 
   if ((OpCode  & 0x0fb00000) == 0x01000000) {
     // A4.1.38 MRS{<cond>} <Rd>, CPSR  MRS{<cond>} <Rd>, SPSR
-    AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
+    AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
     return;
   }
 
 
   if ((OpCode  & 0x0db00000) == 0x01200000) {
     // A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
-    if (I) {
+    if (Imm) {
       // MSR{<cond>} CPSR_<fields>, #<immediate>
-      AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode),  B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
+      AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode),  WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
     } else {
       // MSR{<cond>} CPSR_<fields>, <Rm>
-      AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
+      AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
     }
     return;
   }
@@ -409,35 +417,35 @@ DisassembleArmInstruction (
   if ((OpCode  & 0x0e000000) == 0x0c000000) {
     // A4.1.19 LDC and A4.1.96 SDC
     if ((OpCode & 0xf0000000) == 0xf0000000) {
-      Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
+      Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
     } else {
-      Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ",  L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
+      Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ",  Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
     }
 
-    if (!P) {
-      if (!W) {
+    if (!Pre) {
+      if (!Write) {
         // A5.5.5.5 [<Rn>], <option>
       AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
       } else {
         // A.5.5.4  [<Rn>], #+/-<offset_8>*4
-      AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
+      AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
       }
     } else {
       // A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
-      AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
+      AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
     }
 
   }
 
   if ((OpCode  & 0x0f000010) == 0x0e000010) {
     // A4.1.32 MRC2, MCR2
-    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
+    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
     return;
   }
 
   if ((OpCode  & 0x0ff00000) == 0x0c400000) {
     // A4.1.33 MRRC2, MCRR2
-    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
+    AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
     return;
   }
 

ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c

@@ -9,6 +9,7 @@
   try to reuse existing case entries if possible.
 
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -451,7 +452,7 @@ SignExtend32 (
 // in the instruction address and you get back the aligned answer
 //
 UINT32
-PCAlign4 (
+PcAlign4 (
   IN  UINT32  Data
   )
 {
@@ -486,12 +487,19 @@ DisassembleThumbInstruction (
   UINT32  Index;
   UINT32  Offset;
   UINT16  Rd, Rn, Rm, Rt, Rt2;
-  BOOLEAN H1, H2, imod;
+  BOOLEAN H1Bit; // H1
+  BOOLEAN H2Bit; // H2
+  BOOLEAN IMod;  // imod
   //BOOLEAN ItFlag;
-  UINT32  PC, Target, msbit, lsbit;
+  UINT32  Pc, Target, MsBit, LsBit;
   CHAR8   *Cond;
-  BOOLEAN S, J1, J2, P, U, W;
-  UINT32  coproc, opc1, opc2, CRd, CRn, CRm;
+  BOOLEAN Sign;      // S
+  BOOLEAN J1Bit;     // J1
+  BOOLEAN J2Bit;     // J2
+  BOOLEAN Pre;       // P
+  BOOLEAN UAdd;      // U
+  BOOLEAN WriteBack; // W
+  UINT32  Coproc, Opc1, Opc2, CRd, CRn, CRm;
   UINT32  Mask;
 
   OpCodePtr = *OpCodePtrPtr;
@@ -504,10 +512,10 @@ DisassembleThumbInstruction (
   Rd = OpCode & 0x7;
   Rn = (OpCode >> 3) & 0x7;
   Rm = (OpCode >> 6) & 0x7;
-  H1 = (OpCode & BIT7) != 0;
-  H2 = (OpCode & BIT6) != 0;
-  imod = (OpCode & BIT4) != 0;
-  PC = (UINT32)(UINTN)OpCodePtr;
+  H1Bit = (OpCode & BIT7) != 0;
+  H2Bit = (OpCode & BIT6) != 0;
+  IMod = (OpCode & BIT4) != 0;
+  Pc = (UINT32)(UINTN)OpCodePtr;
 
   // Increment by the minimum instruction size, Thumb2 could be bigger
   *OpCodePtrPtr += 1;
@@ -548,7 +556,7 @@ DisassembleThumbInstruction (
       case LOAD_STORE_FORMAT3:
         // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
         Target = (OpCode & 0xff) << 2;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
         return;
       case LOAD_STORE_FORMAT4:
         // Rt, [SP, #imm8]
@@ -583,16 +591,16 @@ DisassembleThumbInstruction (
         Cond = gCondition[(OpCode >> 8) & 0xf];
         Buf[Offset-5] = *Cond++;
         Buf[Offset-4] = *Cond;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x",  PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x",  Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
         return;
       case UNCONDITIONAL_BRANCH_SHORT:
         // A6.3.2 B  <target_address>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
         return;
 
       case BRANCH_EXCHANGE:
         // A6.3.3 BX|BLX <Rm>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
         return;
 
       case DATA_FORMAT1:
@@ -629,12 +637,12 @@ DisassembleThumbInstruction (
         return;
       case DATA_FORMAT8:
         // A6.4.3  <Rd>|<Rn>, <Rm>
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
         return;
 
       case CPS_FORMAT:
         // A7.1.24
-        AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a",  ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
+        AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a",  ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
         return;
 
       case ENDIAN_FORMAT:
@@ -645,13 +653,13 @@ DisassembleThumbInstruction (
       case DATA_CBZ:
         // CB{N}Z <Rn>, <Lable>
         Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
         return;
 
       case ADR_FORMAT:
         // ADR <Rd>, <Label>
         Target = (OpCode & 0xff) << 2;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
         return;
 
       case IT_BLOCK:
@@ -708,32 +716,32 @@ DisassembleThumbInstruction (
         Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0;  // J1
         Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0;  // S
         Target = SignExtend32 (Target, BIT20);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
         return;
       case B_T4:
         // S:I1:I2:imm10:imm11:0
         Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
-        S  = (OpCode32 & BIT26) == BIT26;
-        J1 = (OpCode32 & BIT13) == BIT13;
-        J2 = (OpCode32 & BIT11) == BIT11;
-        Target |= (!(J2 ^ S) ? BIT22 : 0);  // I2
-        Target |= (!(J1 ^ S) ? BIT23 : 0);  // I1
-        Target |= (S ? BIT24 : 0);  // S
+        Sign  = (OpCode32 & BIT26) == BIT26;
+        J1Bit = (OpCode32 & BIT13) == BIT13;
+        J2Bit = (OpCode32 & BIT11) == BIT11;
+        Target |= (!(J2Bit ^ Sign) ? BIT22 : 0);  // I2
+        Target |= (!(J1Bit ^ Sign) ? BIT23 : 0);  // I1
+        Target |= (Sign ? BIT24 : 0);  // S
         Target = SignExtend32 (Target, BIT24);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
         return;
 
       case BL_T2:
         // BLX  S:I1:I2:imm10:imm11:0
         Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
-        S  = (OpCode32 & BIT26) == BIT26;
-        J1 = (OpCode32 & BIT13) == BIT13;
-        J2 = (OpCode32 & BIT11) == BIT11;
-        Target |= (!(J2 ^ S) ? BIT23 : 0);  // I2
-        Target |= (!(J1 ^ S) ? BIT24 : 0);  // I1
-        Target |= (S ? BIT25 : 0);  // S
+        Sign  = (OpCode32 & BIT26) == BIT26;
+        J1Bit = (OpCode32 & BIT13) == BIT13;
+        J2Bit = (OpCode32 & BIT11) == BIT11;
+        Target |= (!(J2Bit ^ Sign) ? BIT23 : 0);  // I2
+        Target |= (!(J1Bit ^ Sign) ? BIT24 : 0);  // I1
+        Target |= (Sign ? BIT25 : 0);  // S
         Target = SignExtend32 (Target, BIT25);
-        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
         return;
 
       case POP_T2:
@@ -748,8 +756,8 @@ DisassembleThumbInstruction (
 
       case STM_FORMAT:
         // <Rn>{!}, <registers>
-        W = (OpCode32 & BIT21) == BIT21;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
+        WriteBack = (OpCode32 & BIT21) == BIT21;
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
         return;
 
       case LDM_REG_IMM12_SIGNED:
@@ -759,7 +767,7 @@ DisassembleThumbInstruction (
           // U == 0 means subtrack, U == 1 means add
           Target = -Target;
         }
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
         return;
 
       case LDM_REG_INDIRECT_LSL:
@@ -784,36 +792,36 @@ DisassembleThumbInstruction (
 
       case LDM_REG_IMM8:
         // <rt>, [<rn>, {, #<imm8>}]{!}
-        W = (OpCode32 & BIT8) == BIT8;
-        U = (OpCode32 & BIT9) == BIT9;
-        P = (OpCode32 & BIT10) == BIT10;
+        WriteBack = (OpCode32 & BIT8) == BIT8;
+        UAdd = (OpCode32 & BIT9) == BIT9;
+        Pre = (OpCode32 & BIT10) == BIT10;
         Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
-        if (P) {
+        if (Pre) {
           if ((OpCode32 & 0xff) == 0) {
-            AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
+            AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
           } else {
-            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
+            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
           }
         } else {
-          AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
+          AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
         }
         return;
 
       case LDRD_REG_IMM8_SIGNED:
         // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
-        P = (OpCode32 & BIT24) == BIT24;  // index = P
-        U = (OpCode32 & BIT23) == BIT23;
-        W = (OpCode32 & BIT21) == BIT21;
+        Pre = (OpCode32 & BIT24) == BIT24;  // index = P
+        UAdd = (OpCode32 & BIT23) == BIT23;
+        WriteBack = (OpCode32 & BIT21) == BIT21;
         Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
-        if (P) {
+        if (Pre) {
           if ((OpCode32 & 0xff) == 0) {
             AsciiSPrint (&Buf[Offset], Size - Offset, "]");
           } else {
-            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");
+            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
           }
         } else {
           if ((OpCode32 & 0xff) != 0) {
-            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);
+            AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
           }
         }
         return;
@@ -825,7 +833,7 @@ DisassembleThumbInstruction (
           // U == 0 means subtrack, U == 1 means add
           Target = -Target;
         }
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
         return;
 
       case LDREXB:
@@ -840,14 +848,14 @@ DisassembleThumbInstruction (
 
       case SRS_FORMAT:
         // SP{!}, #<mode>
-        W = (OpCode32 & BIT21) == BIT21;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);
+        WriteBack = (OpCode32 & BIT21) == BIT21;
+        AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
         return;
 
       case RFE_FORMAT:
         // <Rn>{!}
-        W = (OpCode32 & BIT21) == BIT21;
-        AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
+        WriteBack = (OpCode32 & BIT21) == BIT21;
+        AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
         return;
 
       case ADD_IMM12:
@@ -917,9 +925,9 @@ DisassembleThumbInstruction (
         // ADDR <Rd>, <label>
         Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
         if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
-          Target = PCAlign4 (PC) - Target;
+          Target = PcAlign4 (Pc) - Target;
         } else {
-          Target = PCAlign4 (PC) + Target;
+          Target = PcAlign4 (Pc) + Target;
         }
         AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
         return;
@@ -932,52 +940,52 @@ DisassembleThumbInstruction (
 
       case BFC_THUMB2:
         // BFI <Rd>, <Rn>, #<lsb>, #<width>
-        msbit = OpCode32 & 0x1f;
-        lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) &  0x1c);
+        MsBit = OpCode32 & 0x1f;
+        LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) &  0x1c);
         if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
           // BFC <Rd>, #<lsb>, #<width>
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
         } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
         } else {
-          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
+          AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
         }
         return;
 
       case CPD_THUMB2:
         // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
-        coproc = (OpCode32 >> 8)  & 0xf;
-        opc1   = (OpCode32 >> 20) & 0xf;
-        opc2   = (OpCode32 >> 5)  & 0x7;
+        Coproc = (OpCode32 >> 8)  & 0xf;
+        Opc1   = (OpCode32 >> 20) & 0xf;
+        Opc2   = (OpCode32 >> 5)  & 0x7;
         CRd    = (OpCode32 >> 12) & 0xf;
         CRn    = (OpCode32 >> 16) & 0xf;
         CRm    = OpCode32 & 0xf;
-        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
-        if (opc2 != 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
+        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
+        if (Opc2 != 0) {
+          AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
         }
         return;
 
       case MRC_THUMB2:
         // MRC  <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
-        coproc = (OpCode32 >> 8)  & 0xf;
-        opc1   = (OpCode32 >> 20) & 0xf;
-        opc2   = (OpCode32 >> 5)  & 0x7;
+        Coproc = (OpCode32 >> 8)  & 0xf;
+        Opc1   = (OpCode32 >> 20) & 0xf;
+        Opc2   = (OpCode32 >> 5)  & 0x7;
         CRn    = (OpCode32 >> 16) & 0xf;
         CRm    = OpCode32 & 0xf;
-        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
-        if (opc2 != 0) {
-          AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
+        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
+        if (Opc2 != 0) {
+          AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
         }
         return;
 
       case MRRC_THUMB2:
         // MRC  <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
-        coproc = (OpCode32 >> 8)  & 0xf;
-        opc1   = (OpCode32 >> 20) & 0xf;
+        Coproc = (OpCode32 >> 8)  & 0xf;
+        Opc1   = (OpCode32 >> 20) & 0xf;
         CRn    = (OpCode32 >> 16) & 0xf;
         CRm    = OpCode32 & 0xf;
-        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
+        Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
         return;
 
       case THUMB2_2REGS:

ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c

@@ -2,6 +2,7 @@
 *  Exception Handling support specific for AArch64
 *
 *  Copyright (c) 2016 HP Development Company, L.P.
+*  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -19,26 +20,25 @@ EFI_EXCEPTION_CALLBACK  gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] =
 PHYSICAL_ADDRESS        gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
 UINTN                   gDebuggerNoHandlerValue = 0; // todo: define for AArch64
 
-#define EL0_STACK_PAGES   2
+#define EL0_STACK_SIZE  EFI_PAGES_TO_SIZE(2)
+STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
 
 VOID
 RegisterEl0Stack (
   IN  VOID    *Stack
   );
 
-RETURN_STATUS ArchVectorConfig(
+RETURN_STATUS
+ArchVectorConfig (
   IN  UINTN       VectorBaseAddress
   )
 {
   UINTN             HcrReg;
-  UINT8             *Stack;
 
-  Stack = AllocatePages (EL0_STACK_PAGES);
-  if (Stack == NULL) {
-    return RETURN_OUT_OF_RESOURCES;
-  }
-
-  RegisterEl0Stack ((UINT8 *)Stack + EFI_PAGES_TO_SIZE (EL0_STACK_PAGES));
+  // Round down sp by 16 bytes alignment
+  RegisterEl0Stack (
+    (VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
+    );
 
   if (ArmReadCurrentEL() == AARCH64_EL2) {
     HcrReg = ArmReadHcr();

ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>
+// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
 // Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
 // Copyright (c) 2016 HP Development Company, L.P.
 //
@@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
 //
 // Current EL with SPx: 0x200 - 0x380
 //
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)
 ASM_PFX(SynchronousExceptionSPx):
   ExceptionEntry  EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
 
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)
 ASM_PFX(IrqSPx):
   ExceptionEntry  EXCEPT_AARCH64_IRQ
 
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)
 ASM_PFX(FiqSPx):
   ExceptionEntry  EXCEPT_AARCH64_FIQ
 
-VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)
 ASM_PFX(SErrorSPx):
   ExceptionEntry  EXCEPT_AARCH64_SERROR
 

ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c

@@ -2,7 +2,7 @@
 *  Exception handling support specific for ARM
 *
 * Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-* Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2021, Arm Limited. All rights reserved.<BR>
 * Copyright (c) 2016 HP Development Company, L.P.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -26,7 +26,8 @@ PHYSICAL_ADDRESS        gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNME
 // NOTE: This code assumes vectors are ARM and not Thumb code
 UINTN                   gDebuggerNoHandlerValue = 0xEAFFFFFE;
 
-RETURN_STATUS ArchVectorConfig(
+RETURN_STATUS
+ArchVectorConfig (
   IN  UINTN       VectorBaseAddress
   )
 {

ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c

@@ -2,7 +2,7 @@
 *  Main file supporting the SEC Phase for Versatile Express
 *
 *  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
 *  Copyright (c) 2016 HP Development Company, L.P.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -253,7 +253,8 @@ RETURN_STATUS
 RegisterCpuInterruptHandler(
   IN EFI_EXCEPTION_TYPE             ExceptionType,
   IN EFI_CPU_INTERRUPT_HANDLER      ExceptionHandler
-  ) {
+  )
+{
   if (ExceptionType > gMaxExceptionNumber) {
     return RETURN_UNSUPPORTED;
   }

ArmPkg/Library/ArmGicArchLib/Arm/ArmGicArchLib.c

@@ -1,60 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2014, ARM Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include <Library/ArmLib.h>
-#include <Library/ArmGicLib.h>
-
-STATIC ARM_GIC_ARCH_REVISION        mGicArchRevision;
-
-RETURN_STATUS
-EFIAPI
-ArmGicArchLibInitialize (
-  VOID
-  )
-{
-  UINT32    IccSre;
-
-  // Ideally we would like to use the GICC IIDR Architecture version here, but
-  // this does not seem to be very reliable as the implementation could easily
-  // get it wrong. It is more reliable to check if the GICv3 System Register
-  // feature is implemented on the CPU. This is also convenient as our GICv3
-  // driver requires SRE. If only Memory mapped access is available we try to
-  // drive the GIC as a v2.
-  if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
-    // Make sure System Register access is enabled (SRE). This depends on the
-    // higher privilege level giving us permission, otherwise we will either
-    // cause an exception here, or the write doesn't stick in which case we need
-    // to fall back to the GICv2 MMIO interface.
-    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
-    // at the same exception level.
-    // It is the OS responsibility to set this bit.
-    IccSre = ArmGicV3GetControlSystemRegisterEnable ();
-    if (!(IccSre & ICC_SRE_EL2_SRE)) {
-      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
-      IccSre = ArmGicV3GetControlSystemRegisterEnable ();
-    }
-    if (IccSre & ICC_SRE_EL2_SRE) {
-      mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
-      goto Done;
-    }
-  }
-
-  mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
-
-Done:
-  return RETURN_SUCCESS;
-}
-
-ARM_GIC_ARCH_REVISION
-EFIAPI
-ArmGicGetSupportedArchRevision (
-  VOID
-  )
-{
-  return mGicArchRevision;
-}

ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c

@@ -25,7 +25,7 @@ ArmGicArchLibInitialize (
   // feature is implemented on the CPU. This is also convenient as our GICv3
   // driver requires SRE. If only Memory mapped access is available we try to
   // drive the GIC as a v2.
-  if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
+  if (ArmHasGicSystemRegisters ()) {
     // Make sure System Register access is enabled (SRE). This depends on the
     // higher privilege level giving us permission, otherwise we will either
     // cause an exception here, or the write doesn't stick in which case we need

ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf

@@ -14,11 +14,8 @@
   LIBRARY_CLASS                  = ArmGicArchLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
   CONSTRUCTOR                    = ArmGicArchLibInitialize
 
-[Sources.ARM]
-  Arm/ArmGicArchLib.c
-
-[Sources.AARCH64]
-  AArch64/ArmGicArchLib.c
+[Sources]
+  ArmGicArchLib.c
 
 [Packages]
   MdePkg/MdePkg.dec

ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c

@@ -1,45 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2014, ARM Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include <Library/ArmLib.h>
-#include <Library/ArmGicLib.h>
-
-ARM_GIC_ARCH_REVISION
-EFIAPI
-ArmGicGetSupportedArchRevision (
-  VOID
-  )
-{
-  UINT32    IccSre;
-
-  // Ideally we would like to use the GICC IIDR Architecture version here, but
-  // this does not seem to be very reliable as the implementation could easily
-  // get it wrong. It is more reliable to check if the GICv3 System Register
-  // feature is implemented on the CPU. This is also convenient as our GICv3
-  // driver requires SRE. If only Memory mapped access is available we try to
-  // drive the GIC as a v2.
-  if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
-    // Make sure System Register access is enabled (SRE). This depends on the
-    // higher privilege level giving us permission, otherwise we will either
-    // cause an exception here, or the write doesn't stick in which case we need
-    // to fall back to the GICv2 MMIO interface.
-    // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
-    // at the same exception level.
-    // It is the OS responsibility to set this bit.
-    IccSre = ArmGicV3GetControlSystemRegisterEnable ();
-    if (!(IccSre & ICC_SRE_EL2_SRE)) {
-      ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
-      IccSre = ArmGicV3GetControlSystemRegisterEnable ();
-    }
-    if (IccSre & ICC_SRE_EL2_SRE) {
-      return ARM_GIC_ARCH_REVISION_3;
-    }
-  }
-
-  return ARM_GIC_ARCH_REVISION_2;
-}

ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c

@@ -23,7 +23,7 @@ ArmGicGetSupportedArchRevision (
   // feature is implemented on the CPU. This is also convenient as our GICv3
   // driver requires SRE. If only Memory mapped access is available we try to
   // drive the GIC as a v2.
-  if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
+  if (ArmHasGicSystemRegisters ()) {
     // Make sure System Register access is enabled (SRE). This depends on the
     // higher privilege level giving us permission, otherwise we will either
     // cause an exception here, or the write doesn't stick in which case we need

ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf

@@ -13,11 +13,8 @@
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = ArmGicArchLib|SEC
 
-[Sources.ARM]
-  Arm/ArmGicArchLib.c
-
-[Sources.AARCH64]
-  AArch64/ArmGicArchLib.c
+[Sources]
+  ArmGicArchLib.c
 
 [Packages]
   MdePkg/MdePkg.dec

ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c

@@ -2,16 +2,19 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include <Uefi.h>
-#include <Chipset/AArch64.h>
+#include <Base.h>
+
 #include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+
+#include <Chipset/AArch64.h>
+
 #include "AArch64Lib.h"
 #include "ArmLibPrivate.h"
 
@@ -40,6 +43,8 @@ ArmInvalidateDataCache (
   VOID
   )
 {
+  ASSERT (!ArmMmuEnabled ());
+
   ArmDataSynchronizationBarrier ();
   AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
 }
@@ -50,6 +55,8 @@ ArmCleanInvalidateDataCache (
   VOID
   )
 {
+  ASSERT (!ArmMmuEnabled ());
+
   ArmDataSynchronizationBarrier ();
   AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
 }
@@ -60,6 +67,40 @@ ArmCleanDataCache (
   VOID
   )
 {
+  ASSERT (!ArmMmuEnabled ());
+
   ArmDataSynchronizationBarrier ();
   AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
 }
+
+/**
+  Check whether the CPU supports the GIC system register interface (any version)
+
+  @return   Whether GIC System Register Interface is supported
+
+**/
+BOOLEAN
+EFIAPI
+ArmHasGicSystemRegisters (
+  VOID
+  )
+{
+  return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) != 0);
+}
+
+/** Checks if CCIDX is implemented.
+
+   @retval TRUE  CCIDX is implemented.
+   @retval FALSE CCIDX is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasCcidx (
+  VOID
+  )
+{
+  UINTN Mmfr2;
+
+  Mmfr2 = ArmReadIdAA64Mmfr2 ();
+  return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
+}

ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h

@@ -2,13 +2,14 @@
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#ifndef __AARCH64_LIB_H__
-#define __AARCH64_LIB_H__
+#ifndef AARCH64_LIB_H_
+#define AARCH64_LIB_H_
 
 typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
 
@@ -17,5 +18,39 @@ AArch64AllDataCachesOperation (
   IN  AARCH64_CACHE_OPERATION  DataCacheOperation
   );
 
-#endif // __AARCH64_LIB_H__
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+  IN  UINTN  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+  IN  UINTN  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+  IN  UINTN   SetWayFormat
+  );
+
+UINTN
+EFIAPI
+ArmReadIdAA64Pfr0 (
+  VOID
+  );
+
+/** Reads the ID_AA64MMFR2_EL1 register.
+
+   @return The contents of the ID_AA64MMFR2_EL1 register.
+**/
+UINTN
+EFIAPI
+ArmReadIdAA64Mmfr2 (
+  VOID
+  );
+
+#endif // AARCH64_LIB_H_
 

ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

@@ -3,6 +3,7 @@
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
 # Copyright (c) 2016, Linaro Limited. All rights reserved.
+# Copyright (c) 2020, NUVIA Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -395,7 +396,7 @@ ASM_FUNC(ArmReadVBar)
 ASM_FUNC(ArmEnableVFP)
   // Check whether floating-point is implemented in the processor.
   mov   x1, x30                 // Save LR
-  bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
+  bl    ArmReadIdAA64Pfr0       // Read EL1 Processor Feature Register (PFR0)
   mov   x30, x1                 // Restore LR
   ubfx  x0, x0, #16, #4         // Extract the FP bits 16:19
   cmp   x0, #0xF                // Check if FP bits are '1111b',
@@ -424,6 +425,9 @@ ASM_FUNC(ArmCallWFI)
   wfi
   ret
 
+ASM_FUNC(ArmReadIdAA64Mmfr2)
+  mrs   x0, ID_AA64MMFR2_EL1           // read EL1 MMFR2
+  ret
 
 ASM_FUNC(ArmReadMpidr)
   mrs   x0, mpidr_el1           // read EL1 MPIDR
@@ -448,19 +452,11 @@ ASM_FUNC(ArmIsArchTimerImplemented)
   ret
 
 
-ASM_FUNC(ArmReadIdPfr0)
+ASM_FUNC(ArmReadIdAA64Pfr0)
   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
   ret
 
 
-// Q: id_aa64pfr1_el1 not defined yet. What does this function want to access?
-// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
-//    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
-//    Not defined yet, but stick in here for now, should read all zeros.
-ASM_FUNC(ArmReadIdPfr1)
-  mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
-  ret
-
 // VOID ArmWriteHcr(UINTN Hcr)
 ASM_FUNC(ArmWriteHcr)
   msr   hcr_el2, x0        // Write the passed HCR value