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Author SHA1 Message Date
ba0e0e4c6a BaseTools: Fix DevicePath GNUmakefile for macOS
On macOS, /usr/bin/gcc is clang, and so doesn't have
the -Wno-error=stringop-overflow flag that was added
for gcc 12.
Update the GNUmakefile for DevicePath to skip setting
that on macOS.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2022-08-28 04:11:48 +00:00
39ff9769ca Revert "BaseTools: Fix DSC LibraryClass precedence rule"
This reverts commit 039bdb4d3e for tag202208.
This brings the behavior changes, and needs more discussion.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Bob Feng <bob.c.feng@intel.com>
2022-08-28 02:17:24 +00:00
166c49c212 Revert "ShellPkg: Adds Local APIC parser to AcpiView"
This reverts commit d5fd86f256 for tag202208.
This feature will be merged after stable tag 202208 is created.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-28 02:17:24 +00:00
722e03bc2e Revert "UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test"
This reverts commit 2812668bfc for tag202208.
This feature will be merged after stable tag 202208 is created.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-28 02:17:24 +00:00
0ede7cad73 Maintainers.txt: Update maintainers list
Update package maintainers for below package/arch,

1. RISCV64 Architecture:
   Abner is stepping out from RISC-V stuff for now and hand over edk2 RISC-V
   responsibilities to Sunil.
   Daniel Schaefer is no longer with HPE. Update his email address for
   RISCV64 arch. He will keep helping on RISC-V stuff with his personal
   email.

2. EmbeddedPkg:
   Daniel Schaefer is no longer with HPE. Update his email address for
   EmbeddedPkg.

3. EmulatorPkg and RedfishPkg:
   Nickle Wang is no longer with HPE. Update his email address for
   EmulatorPkg and RedfishPkg packages. He will use the personal email for
   the time being until he gets ready with his next journey.

Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Nickle Wang <nickle@csie.io>
Reviewed-by: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Nickle Wang <nickle@csie.io>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2022-08-25 11:35:31 +00:00
4d83ee04f4 ShellPkg: Add revision check for DSDT Header on Arm
Bugzilla: 3995 (https://bugzilla.tianocore.org/show_bug.cgi?id=3995)

ACPI 6.4 spec states that if the revision field in the DSDT header is less
than 2, then all integers are restricted in width to 32 bits, including in
SSDTs.

Arm Base boot requirements state that platforms must conform to ACPI 6.3
or later, and that legacy tables are not supported.

Adds a check for this field and raise warning if revision is less
than 2 on arm.

Signed-off-by: Edward Pickup <edward.pickup@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2022-08-24 03:14:52 +00:00
dfdba857a6 UefiPayloadPkg: Fix Coverity report defect
https://bugzilla.tianocore.org/show_bug.cgi?id=4018
Coverity report FORWARD_NULL and OVERFLOW_BEFORE_WIDEN potential defect
in UefiPayloadPkg.

Signed-off-by: Gregx Yeh <gregx.yeh@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: James Lu <james.lu@intel.com>
2022-08-23 04:03:01 +00:00
f2bf043aaa RedfishPkg: Redfish functions for REST requests are not fully spec complied
There is no function to send POST request with the
ContentType different from "application\json".
There is no function to send DELETE request with the body.

Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
2022-08-23 03:13:11 +00:00
eebef1b3b7 RedfishPkg: Redfish modules may need to use the functions which are private
Definitions of the required functions to send requests to BMC
are in the PrivateInclude folder. So they cannot be used by
the other Redfish packages.

Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
2022-08-23 03:13:11 +00:00
938430741f RedfishPkg/RedfishDiscoverDxe: USB Redfish host interface is not supported
Host Interface details are described by the SMBIOS Type 42
table. The table is published by the RedfishHostInterfaceDxe
driver. That driver supports PCI-E and USB host interface
types.The table is consumed by the edfishGetHostInterfaceProtocolData
function in the RedfishDiscoverDxe driver. The function only supports
PCI-E host interface type.

Cc: Abner Chang <abner.chang@amd.com>
Cc: Nickle Wang <nickle.wang@hpe.com>
Signed-off-by: Igor Kulchytskyy <igork@ami.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
2022-08-23 03:13:11 +00:00
c15c9fa420 UefiPayloadPkg: Add macro to control NvmExpressDxe
Add NVME_ENABLE macro to control NvmExpressDxe driver.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
2022-08-23 01:31:35 +00:00
2bb0020675 UefiPayloadPkg: Return PciRootBridges instead of NULL
Return PciRootBridges instead of NULL and set
PcdPciDisableBusEnumeration to FALSE when
root bridge count is zero.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
2022-08-23 01:04:17 +00:00
d5fd86f256 ShellPkg: Adds Local APIC parser to AcpiView
Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2022-08-22 09:33:56 +00:00
e2ac68a23b BaseTools/Source/C/GenSec: Fix EFI_SECTION_FREEFORM_SUBTYPE_GUID header
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4021

When the size of a EFI_SECTION_FREEFORM_SUBTYPE_GUID section required
the use of EFI_FREEFORM_SUBTYPE_GUID_SECTION2 header, set the section
type to EFI_SECTION_FREEFORM_SUBTYPE_GUID.

Cc: Leif Lindholm <llindhol@qti.qualcomm.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Konstantin Aladyshev <aladyshev22@gmail.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Leif Lindholm <llindhol@qti.qualcomm.com>
2022-08-19 05:12:26 +00:00
68bf712d4f MdePkg: Added support for SMBIOS spec v3.6.0 to Smbios.h
Updated SmBios.h with new fields added as part of SMBIOS 3.6.0 spec update.

Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Cc: Vasudevan Sambandan <vasudevans@ami.com>
Cc: Sundaresan S <sundaresans@ami.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-08-18 08:41:22 +00:00
35d167ef3c ShellPkg: Improved Smbios Type 9 table changes in PrintInfo.c
Since PeerGroups has a variable number of entries, new fields added
after PeerGroups are defined in a extended structure.
Done changes in PrintInfo.c to access those fields using
SMBIOS_TABLE_TYPE9_EXTENDED structure from SmBios.h.

Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>

Cc: Vasudevan Sambandan <vasudevans@ami.com>
Cc: Sundaresan S <sundaresans@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-08-18 08:41:22 +00:00
9102518d29 MdePkg: Improved Smbios Type9 table and Smbios spec v3.5.0 Changes
In Type9 structure since PeerGroups has a variable
number of entries, must not define new fields in the structure.So added an
extended structure and defined new fields added after PeerGroups. Also done
some improvements to Smbios 3.5.0 spec changes.

Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-08-18 08:41:22 +00:00
64a20bea97 MdeModulePkg/DumpDynPcd: Remove unsupported format specifiers
Some print statements use format specifiers like %N/%H/%E/%B that are
only supported in the shell print functions. In the ordinary 'Print'
function they are just displayed as letters N/H/E/B.
Remove these unsupported format specifiers from the 'Print' statements
to fix the issue.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-08-17 07:45:58 +00:00
3f282f4510 OvmfPkg/VirtioFsDxe: Check GetDriverName arguments
The current implementation does not check if Language or DriverName
are NULL. This causes the SCT test suite to crash.

Add a check to return EFI_INVALID_PARAMETER if any of these pointers
are NULL.

Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2022-08-16 20:52:19 +00:00
b94836b224 OvmfPkg/VirtioGpuDxe: Check QueryMode arguments
The current implementation does not check if Info or SizeInfo
pointers are NULL. This causes the SCT test suite to crash.

Add a check to return EFI_INVALID_PARAMETER if any of these
pointers are NULL.

Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2022-08-16 20:52:19 +00:00
30d62f5e31 OvmfPkg/PlatformDxe: Check ExtractConfig and RouteConfig arguments
The current implementation does not check if Progress or Results
pointers in ExtractConfig are NULL, or if Progress pointer in
RouteConfig is NULL. This causes the SCT test suite to crash.

Add a check to return EFI_INVALID_PARAMETER if any of these pointers
are NULL.

Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2022-08-16 20:52:19 +00:00
2812668bfc UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test
Add host based unit tests for the CpuPageTableLib services.

Unit test focuses on PageTableMap function, containing two kinds of test
cases: manual test case and random test case.
Manual test case creates some corner case to test function PageTableMap.
Random test case generates multiple random memory entries (with random
attribute) as the input of function PageTableMap to get the output
pagetable. Output pagetable will be validated and be parsed to get output
memory entries, and then the input and output memory entries will be
compared to verify the functionality.

The unit test is not perfect yet. There are options for random test, and
some of them control the test coverage, and some option are not ready.
Will enhance in the future.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-08-16 02:44:08 +00:00
809b5a3d2a MdeModulePkg: Update the SMBIOS version by UPL
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4013

For the SMBIOS version can be update by UPL,we create
the gUniversalPayloadSmbios3TableGuid HOB to store
the value then updated version.

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
2022-08-15 08:43:38 +00:00
a2b61de2f6 IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019

FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and
should be fixed for both IA32 and X64 builds.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2022-08-15 08:03:06 +00:00
803ed060ee UefiPayloadPkg: Remove clearing CR0.WP when protecting pagetable
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by UefiPayloadEntry.
This page table address is written to Cr3 after these protection
steps. Till this, the memory used for page table is always RW.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-08-15 05:15:43 +00:00
62391b4ce9 MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable
Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by DxeIpl. This page
table address is written to Cr3 after these protection steps. Till
this, the memory used for page table is always RW.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-08-15 05:15:43 +00:00
7b4754904e UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm
This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-08-15 05:15:43 +00:00
83d5871184 UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag
This patch is code refactoring and doesn't change any functionality.
Add a new mIsShadowStack flag to identify whether current memory is
shadow stack. Previous smm code logic regards a RO range as shadow
stack and set the dirty bit in corresponding page table entry if
mInternalCr3 is not 0, which may be confusing.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-08-15 05:15:43 +00:00
74f44d920a ShellPkg/SmbiosView: Display extended memory info in smbiosview -t 17
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4014

If Configured Memory Speed is 65,535 MT/s or greater,
and the actual speed is stored in the Extended Configured Memory Speed
field. but current Smbiosview have no this logic.

Signed-off-by: Shengfengx Xue <shengfengx.xue@intel.com>
2022-08-15 03:44:57 +00:00
bd06717863 MdeModulePkg: Enhance bus scan for all root bridge instances
Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000

Change flow to bus scan all root bridge instances even when any
one root bridge meet bus resource OUT_OF_RESOURCE case.
thus platform handler  of "EfiPciHostBridgeEndBusAllocation" has
an chance to do relative pci bus rebalance to handle this case.

Signed-off-by: Foster Nong <foster.nong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-08-12 06:50:02 +00:00
e76496530c MdePkg/Library/UefiDevicePathLib: Add back StandaloneMm INF file
REF: https://github.com/tianocore/edk2/pull/3130

The above PR removed UefiDevicePathLibStandaloneMm.inf, which is
a non-backwards compatible change and does not provide time for
downstream platforms to use the UefiDevicePathLibBase.inf.

Add UefiDevicePathLibStandaloneMm.inf back, but add comments that
it is deprecated and that UefiDevicePathLibBase.inf should be used
instead.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Mateusz Albecki <mateusz.albecki@intel.com>
Cc: Yanbo Huang <yanbo.huang@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-08-10 21:43:49 +00:00
e9e2ecab2d CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally
The change doesn't change functionality behavior.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
927113c83b CpuPageTableLib: Fix bug that wrongly requires extra size for mapping
With following paging structure to map
  [2M-4K, 2M] as P = 1, RW = 0,
  [2M, 4M]    as P = 1, RW = 1:

PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
                    -> PDE[1](RW = 1)

When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.

But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.

The change fixes the bug.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
9f53fd4ba7 CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
              \-> PDPTE[1] --> PDE[0-255]

If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as read-only, today's logic unnecessarily changes
the paging structure in 2 aspects:
1. When setting PageTableBaseAddress in the entry, the code clears
    all attributes.
2. Even the ReadWrite bit in parent entry is not set, the code clears
    the ReadWrite bit in the leaf entry.

First change is wrong. It should not change other attributes when
setting the PA.
Second change is unnecessary. Because the parent entry already
declares the whole region as read-only, there is no need to clear
ReadWrite bit in the leaf entry again.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
f4c845e46b CpuPageTableLib: Fix parent attributes are not inherited properly
With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
              \-> PDPTE[1] --> PDE[0-255]

If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.

The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.

E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
c16f02f776 CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.

The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
9cb8974f06 CpuPageTableLib: Split the page entry when LA is aligned but PA is not
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
13a0471bfd CpuPageTableLib: Refactor the logic
The patch replaces
  LinearAddress + Offset == RegionStart
with
  ((LinearAddress + Offset) & RegionMask) == 0

The replace should not cause any behavior change.

Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
  because the lower "BitStart" bits of RegionStart are all-zero,
  all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
  Because all lower "BitStart" bits of RegionMask is all-one and
  bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.

2. In following loops of the while, even RegionStart is increased
  by RegionLength, the lower "BitStart" bits are still all-zero.
  So the two expressions still semantically equal to each other.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
bf334513b3 CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask
To reproduce the issue:
  UINTN               PageTable;
  VOID                *Buffer;
  UINTN               PageTableBufferSize;
  IA32_MAP_ATTRIBUTE  Attribute;
  IA32_MAP_ATTRIBUTE  Mask;
  RETURN_STATUS       Status;

  Attribute.Uint64       = 0;
  Mask.Uint64            = 0;
  PageTableBufferSize    = 0;
  PageTable              = 0;
  Buffer                 = NULL;
  Attribute.Bits.Present = 1;
  Attribute.Bits.Nx      = 1;
  Mask.Bits.Present      = 1;
  Mask.Uint64            = MAX_UINT64;

  //
  // Create page table to cover [0, 10M)
  //
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_BUFFER_TOO_SMALL);
  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS);

  //
  // Change the mapping for [0, 4KB)
  // No change actually. Just clear Nx bit in Mask.
  //
  Mask.Bits.Nx        = 0;
  PageTableBufferSize = 0;

  Status = PageTableMap (
             &PageTable, PagingMode, NULL, &PageTableBufferSize,
             0, (UINT64)SIZE_4KB, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS); // FAIL!!

The root cause is when comparing the existing mapping attributes
against the requested one, Mask is not used but it should be used.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
f336e30ba1 UefiCpuPkg/CpuPageTableLib: Return error on invalid parameters
When LinearAddress or Length is not aligned on 4KB, PageTableMap()
should return Invalid Parameter.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
75e3c2435c UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs
The lib includes two APIs:
* PageTableMap
  It creates/updates mapping from LA to PA.
  The implementation only supports paging structures used in 64bit
  mode now. PAE paging structure support will be added in future.

* PageTableParse
   It parses the page table and returns the mapping relations in an
  array of IA32_MAP_ENTRY.

It passed some stress tests. These test code will be upstreamed in
other patches following edk2 Unit Test framework.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
f1688ec9da UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA
CPU_EXCEPTION_INIT_DATA is now an internal implementation of
CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the
same definition. Also, two fields (Revision and InitDefaultHandlers)are
useless, can be removed.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-08-09 04:12:28 +00:00
9a24c3546e MdeModulePkg: Move CPU_EXCEPTION_INIT_DATA to UefiCpuPkg
Since the API InitializeSeparateExceptionStacks is simplified and does't
use the struct CPU_EXCEPTION_INIT_DATA, CPU_EXCEPTION_INIT_DATA become
a inner implementation of CpuExcetionHandlerLib.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-08-09 04:12:28 +00:00
0f7bccf584 UefiCpuPkg: Simplify InitializeSeparateExceptionStacks
Hide the Exception implementation details in CpuExcetionHandlerLib and
caller only need to provide buffer

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-08-09 04:12:28 +00:00
1da2012d93 PrmPkg: Add details on AArch64 build to the Readme.
Specify how to build the PrmPkg for the AArch64 architecture.
Make the 2 following notes:
 - the PrmPkg has only been tested on AArch64 using the GCC5
toolchain.
 - All symbols to be listed in the PRMT as well as the
PrmModuleExportDescriptor must be explicitly preserved by resorting to
the --require-defined linker flag.

Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-08 22:43:51 +00:00
57faeb782a PrmPkg: Support AArch64 builds using GCC
Add support to build PrmPkg for AArch64 using the GCC compiler.

Add AARCH64 architecture to the list of supported architectures.
Add BaseStackCheck library to allow for Prm module builds on AARCH64.

Also update the CI to add dependency on ArmPkg.

Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-08 22:43:51 +00:00
21200d9fe6 PrmPkg: Build Prm Samples with GCC for AARCH64
- Add the --prm flag to the GENFW_FLAGS
- Add the --no-gc-section to the linker flags so that apparently
unreferenced symbols are not prematurely removed from the .dll which
is used to generate the Prm module .efi.
- Force the linker to maintain the PrmModuleExportDescriptor symbol.
- Force the linker to maintain the PRM handler funtion's symbol.

Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-08 22:43:51 +00:00
9f197e44b1 PrmPkg: Enable external visibility on PRM symbols
Enable GCC compilations to keep external symbols when generating a PRM
module.

Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-08 22:43:51 +00:00
1ee1622817 Basetools/GenFw: Allow AARCH64 builds to use the --prm flag
The GenFw invocation with the --prm flag was previously reserved for
X64.
AArch64 platforms, built with GCC5, can also deploy PRM modules, hence
the --prm flag is also applicable in builds targeting the AARCH64
architecture.

This commit enables the --prm flag to be used for EDK2 builds targeting
AARCH64.

Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-08 22:43:51 +00:00
cf02322c98 BaseTools/GenSec: Support EFI_SECTION_FREEFORM_SUBTYPE_GUID sections
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-06 15:12:28 +00:00
d241a09afb BaseTools/VolInfo: Parse EFI_SECTION_FREEFORM_SUBTYPE_GUID header
Print 'SubtypeGuid' field from the EFI_FREEFORM_SUBTYPE_GUID_SECTION
structure.
This value describes the raw data inside the section.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng<bob.c.feng@intel.com>
2022-08-06 15:12:28 +00:00
f5f8c08db9 BaseTools/VolInfo: Show FV section boundaries
Currently there is no labels for start and end of the
EFI_SECTION_FIRMWARE_VOLUME_IMAGE type section. Therefore it is not
possible to see where the FV section ends and another section starts.
Add labels for start and end of the FV sections to fix the issue.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-06 15:12:28 +00:00
a0a03b5154 BaseTools/GenSec: Fix typo
Fix typo in the help message.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-08-06 13:30:18 +00:00
3e599bbc10 DynamicTablesPkg: Fix using RmrNodeCount unitlitialised
Fix using RmrNodeCount uninitliased by initliasing it to zero. Also, add
an additional check for ACPI version. This fixes a crash running on
kvmtool.

Signed-off-by: Edward Pickup <edward.pickup@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-08-06 06:56:50 +00:00
a8f59e2eb4 MdeModulePkg/AhciPei: Use PCI_DEVICE_PPI to manage AHCI device
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907

This change modifies AhciPei library to allow usage both EDKII_PCI_DEVICE_PPI
and EDKII_PEI_ATA_AHCI_HOST_CONTROLLER_PPI to manage ATA HDD working under
AHCI mode.

Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2022-08-05 02:20:00 +00:00
86757f0b47 MdeModulePkg: Add EDKII_PCI_DEVICE_PPI definition
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907

This commit introduces EDKII_PCI_DEVICE_PPI. The purpose of this PPI is
to provide a way of accessing PCI devices to drvice drivers such as
NvmExpressPei or AhciPei.

Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Maciej Czajkowski <maciej.czajkowski@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2022-08-05 02:20:00 +00:00
444260d45e UefiPayloadPkg: Load Boot Logo into ACPI table
If the boot logo is enabled, this will allow edk2 to pass the logo
to the OS via ACPI.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
2022-08-03 22:15:00 +00:00
79aab22fca UefiPayloadPkg: Add a Macro to enable Boot Logo
Add a macro called BOOTSPLASH_IMAGE, which when enabled, will
display a logo at boot time.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
2022-08-03 22:15:00 +00:00
d219119721 UefiPayloadPkg/PlatformBootManagerLib: Correct spacing in boot prompt
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
2022-08-03 21:47:22 +00:00
0dc9b78a46 Maintainers.txt: Add missing Github IDs for OvmfPkg TPM/TGC modules
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ard Biesheuvel <ardb+tianocore@kernel.org>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-08-03 00:30:38 +00:00
a551de0d93 ArmVirtPkg: Fix KVM Guest Firmware
Fix build of KVM Guest Firmware, broken by commit

  4c55f6394f ("MdePkg: IORT header update for IORT Rev E.d spec")

Signed-off-by: Edward Pickup <edward.pickup@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-08-02 17:07:08 +00:00
19cbfaa431 OvmfPkg/QemuVideoDxe: Zero out PixelInformation in QueryMode
Ensure that the PixelInformation field of the
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure is zeroed out in
EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode() and
EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode() when PixelFormat is
PixelBlueGreenRedReserved8BitPerColor.

According to UEFI 2.9 Section 12.9, PixelInformation field of the
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure is valid only if
PixelFormat is PixelBitMask. This means that firmware is not required
to fill out the PixelInformation field for other PixelFormat types,
which implies that the QemuVideoDxe implementation is technically
correct.

However, not zeroing out those fields will leak the contents of the
memory returned by the memory allocator, so it is better to explicitly
set them to zero.

In addition, the SCT test suite relies on PixelInformation always
having a consistent value, which causes failures.

Signed-off-by: Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2022-08-01 20:34:21 +00:00
6f4e10d6db SecurityPkg: Add retry mechanism for tpm command
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3980

As per TCG PC Client Device Driver Design Principle document,
if tpm commands fails due to timeout condition, then it should
have retry mechanism (3 retry attempts).
Existing implementation of PtpCrbTpmCommand does not have retry
mechanism if it fails with EFI_TIMEOUT.

See TCG PC Client Device Driver Design Principles for TPM 2.0
https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_Device_Driver_Design_Principles_TPM2p0_v1p1_r4_211104_final.pdf
Vision 1.1, Revision 0.04
Section 7.2.1

Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Swapnil Patil <S.Keshavrao.Patil@dell.com>
2022-07-31 16:34:01 +00:00
e9150618ec DynamicTablesPkg: IORT generator updates for Rev E.d spec
Bugzilla: 3458 - Add support IORT Rev E.d specification updates
          (https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.d,
Feb 2022 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
 - increments the IORT table revision to 5.
 - updates the node definition to add an 'Identifier' field.
 - adds definition of node type 6 - Reserved Memory Range node.
 - adds definition for Memory Range Descriptors.
 - adds flag to indicate PRI support for root complexes.
 - adds flag to indicate if the root complex supports forwarding
   of PASID information on translated transactions to the SMMU.
 - adds flag to indicate if the root complex supports PASID.
 - adds flags to define access privilege and attributes for the
   memory ranges.

Therefore, update the IORT generator to:
  - increment IORT table revision count to 5.
  - populate Identifier filed if revision is greater than 4.
  - add support to populate Reserved Memory Range nodes and
    the Memory range descriptors.
  - add validation to check that the Identifier field is
    unique.
  - Populate the PASID capabilities and Flags field of the
    Root complex node.
 - Added checks to not generate IORT Rev E, Rev E.<a,b,c>.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
de200b7e2c DynamicTablesPkg: Update ArmNameSpaceObjects for IORT Rev E.d
Bugzilla: 3458 - Add support IORT Rev E.d specification updates
          (https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.d,
    Feb 2022 (https://developer.arm.com/documentation/den0049/)
    introduces the following updates, collectively including the
    updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
     - increments the IORT table revision to 5.
     - updates the node definition to add an 'Identifier' field.
     - adds definition of node type 6 - Reserved Memory Range node.
     - adds definition for Memory Range Descriptors.
     - adds flag to indicate PRI support for root complexes.
     - adds flag to indicate if the root complex supports forwarding
       of PASID information on translated transactions to the SMMU.
     - adds flag to indicate if the root complex supports PASID.
     - adds flags to define access privilege and attributes for the
       memory ranges.

Therefore, update the Arm namespace objects to:
  - add Identifier field to IORT nodes.
  - introduce enums to represent RMR nodes and Memory Range
    descriptors.
  - add definition of node type 6 - Reserved Memory Range node.
  - add definition for Memory Range Descriptors.
  - add PASID capabilities and flags field to Root Complex node.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
cd67efa1b2 ShellPkg: Acpiview: IORT parser update for IORT Rev E.d spec
Bugzilla: 3458 - Add support IORT Rev E.d specification updates
          (https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.d,
Feb 2022 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
 - increments the IORT table revision to 5.
 - updates the node definition to add an 'Identifier' field.
 - adds definition of node type 6 - Reserved Memory Range node.
 - adds definition for Memory Range Descriptors.
 - adds flag to indicate PRI support for root complexes.
 - adds flag to indicate if the root complex supports forwarding
   of PASID information on translated transactions to the SMMU.
 - adds flag to indicate if the root complex supports PASID.
 - adds flags to define access privilege and attributes for the
   memory ranges.

Therefore, update the IORT parser to:
  - parse the Identifier field.
  - parse Reserved Memory Range node.
  - parse Memory Range Descriptors.
  - add validations to check that the physical range base
    and size of the Memory Range Descriptor is 64KB aligned.
  - add validation to check that the IORT Table Revision is
    not 4 as IORT Rev E.c is deprecated.
  - add validation to check that the IORT RMR node revision
    is not 2 as it breaks backward compatibility and was
    deprecated as part of IORT Rev E.c.
  - skip parsing of IORT Rev E, Rev E.a, Rev E.b, Rev E.c as
    some fields were deprecated in these revisions.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
4c55f6394f MdePkg: IORT header update for IORT Rev E.d spec
Bugzilla: 3458 - Add support IORT Rev E.d specification updates
          (https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.d,
Feb 2022 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E, Rev E.a, Rev E.b, Rev E.c:
  - increments the IORT table revision to 5.
  - updates the node definition to add an 'Identifier' field.
  - adds definition of node type 6 - Reserved Memory Range node.
  - adds definition for Memory Range Descriptors.
  - adds flag to indicate PRI support for root complexes.
  - adds flag to indicate if the root complex supports forwarding
    of PASID information on translated transactions to the SMMU.
  - adds flag to indicate if the root complex supports PASID.
  - adds flags to define access privilege and attributes for the
    memory ranges.

Therefore, update the IORT header file to reflect these changes,
and also rename the EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Also update the IORT generator in DynamicTablesPkg to fix the
compilation errors so that Git Bisect can work.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2022-07-29 19:22:15 +00:00
238f903e8d DynamicTablesPkg: IORT set reference to interrupt array if present
The IORT generator is populating the reference field for Context and
PMU interrupts even if their count is zero.

Update the IORT generator to set the references only if the interrupt
count is not 0. Also add checks to ensure a valid reference token has
been provided.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
f5cea604a6 DynamicTablesPkg: IORT set reference to Id array only if present
The IORT table generator is setting up a reference to ID array for
nodes even when the ID Mapping count is zero. This is not an issue as an
OS would only access the ID Reference if the ID mapping count is not zero.

However, it would be good to set the reference to ID array to zero when
the ID Mapping count is zero rather than populating it with an incorrect
value.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
65c4f3f2be DynamicTablesPkg: Handle error when IdMappingToken is NULL
Add error handling when the IdMappingCount is not zero and the
IdMappingToken is NULL.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
8a210b9ac0 ShellPkg: Acpiview: Abbreviate field names to preserve alignment
Some field names in the IORT table parser were longer than the
OUTPUT_FIELD_COLUMN_WIDTH plus indentation, resulting in loss of
the output print alignment. Therefore, abbreviate the field names.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
2022-07-29 19:22:15 +00:00
0d0bfcb457 IntelFsp2Pkg: Fix GenCfgOpt bug for FSPI_UPD support.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993
Fixed a logic bug in GenCfgOpt.py to skip FSPI_UPD when platforms
do not support.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2022-07-29 03:07:28 +00:00
3eca64f157 IntelFsp2Pkg: FSPI_UPD is not mandatory.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993
FSPI_UPD is required only When platforms implemented FSP_I component.
Updated the scripts to allow FSPI_UPD not present scenario.
Also fixed FSP_GLOBAL_DATA structure alignment issue and unnecessary
non-backward compatibility change in previous FSP_I patch.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2022-07-28 16:41:41 +00:00
0e7add1d75 OvmfPkg/XenHypercallLib: Fix naming of AArch64
Fix path to follow naming convention of "AArch64", and allow the path
in "Maintainers.txt" to work as expected.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3982
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-07-28 01:22:13 +00:00
1774a44ad9 Maintainers.txt: Remove MptScsi and PvScsi reviewers
The email addresses for the reviewers of the MptScsi and
PvScsi in the OvmfPkg are no longer valid.  Remove the
reviewers for the MptScsi and PvScsi drivers until new
maintainers/reviewers can be identified.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-07-28 00:31:19 +00:00
57783adfb5 OvmfPkg: Change default to disable MptScsi and PvScsi
The email addresses for the reviewers of the MptScsi and
PvScsi are no longer valid.  Disable the MptScsi and PvScsi
drivers in all DSC files until new maintainers/reviewers can
be identified.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Sebastien Boeuf <sebastien.boeuf@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2022-07-28 00:31:19 +00:00
f26b70cb9f UefiPayloadPkg: Add support for logging to CBMEM console
Writes TianoCore debug logs into the CBMEM console ringbuffer, from
where the user can retrieve them with the `cbmem` userspace utility.

The intention is to aid in debugging non-fatal issues even in release
builds, or simply make TianoCore's logs available to those interested.
Consequently, MDEPKG_NDEBUG must be masked. As an in-memory debug
logging library, ASSERTs must be non-fatal to be seen, so they neither
dead-loop nor create a breakpoint. It is assumed that ASSERT() neither
enforces fatal conditions nor security integrity, as release builds do
not call DebugAssert() from the ASSERT macro.

More detailed debug logs are produced with the DEBUG_CODE macro, but
this guards other debug-related code throughout the codebase. To avoid
changing behaviour on release builds, this is only set for debug builds.

Tested on QEMU, dumping the appropriate memory region in the UEFI shell
shows the TianoCore log. An improved revision of the debug library used
in several coreboot-related EDK2 forks, including MrChromebox's.
Previous revisions also tested on an Acer Aspire VN7-572G laptop.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
2022-07-27 20:54:35 +00:00
2677286307 UefiPayloadPkg: Fix RelaAddress type always mismatch in if condition
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3984

Under function RolocateElfDynamic() in Elf32Lib.c
if (RelaAddress == MAX_UINT64) is always FALSE while RelaAddress is UINT32
Fix is to  modify if condition check to "if (RelaAddress == MAX_UINT32)"

Cc: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Gua Guo <gua.guo@intel.com>
Signed-off-by: James Lu <james.lu@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
2022-07-27 17:00:40 +00:00
e3d468acb9 BaseTools/VolInfo: Show encapsulation sections
Currently there is no labels for start and end of the encapsulation
sections. Therefore it is not possible to see where the encapsulation
section ends and another section starts.
Add labels for start and end of encapsulation sections to fix the
issue.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-27 07:48:28 +00:00
b68d566439 BaseTools/Capsule: Support signtool input subject name to sign capsule file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3928

Windows-based system using signtool.exe to sign the capsule.
Add the support to using "--subject-name" argument to assign
the subject name used to sign the capsule file.
This argument would pass to signtool.exe as a part of input
argument with "/n" flag.

NOTE: If using signtool.exe to sign capsule at least need to
      choose one of "--pfx-file" and "--subject-name"
      argument to input the value.

Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Dakota Chiang <dakota.chiang@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-27 05:00:06 +00:00
7f1c89f167 Maintainers.txt: Remove reviewer Harry Han
Cc: Harry Han <harry.han@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Harry Han <harry.han@intel.com>
Reviewed-by: Andrew Fish <afish@apple.com>
2022-07-25 23:22:14 +00:00
a8c4fe23c4 Maintainers.txt: Add missing github ids
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gary Lin <gary.lin@hpe.com>
Cc: Julien Grall <julien@xen.org>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Debkumar De <debkumar.de@intel.com>
Acked-by: Gary Lin <gary.lin@hpe.com>
Reviewed-by: Andrew Fish <afish@apple.com>
2022-07-25 23:22:14 +00:00
69f76d0f72 Maintainers.txt: Remove OvmfPkg/XenTimerDxe reference
XenTimerDxe has been removed from the OvmfPkg.  Remove
file pattern for XenTimerDxe reviews from Maintainers.txt.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien@xen.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Andrew Fish <afish@apple.com>
2022-07-25 23:22:14 +00:00
a47241f133 UefiPayloadPkg: Add macro to support selection of CryptoDxe driver
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4006

Add CRYPTO_PROTOCOL_SUPPORT to decide CryptoDxe built into UPL.efi
If CRYPTO_PROTOCOL_SUPPORT is true, BIOS will use crypto protocol
instead of building OpensslLib into drivers.

Reviewed-by: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: PaytonX Hsieh <paytonx.hsieh@intel.com>
2022-07-25 16:32:42 +00:00
8a5782d704 UefiCpuPkg: Fix nasm warning "signed byte value exceeds"
Currently, "push byte %[Vector]" causes nasm warning when Vector is larger
than 0x7F. This is because push accepts a signed value, and byte means
signed int8. Maximum signed int8 is 0x7F.
When Vector is larger the 0x7F, for example, when Vector is 255, byte 255
turns to -1, and causes the warning "signed byte value exceeds".
To avoid such warning, use dword instead of byte, this will increase 3 bytes
for each IdtVector.
For IA32, the size of IdtVector will increase from 10 bytes to 13 bytes.
For X64, the size of IdtVector will increase from 15 bytes to 18 bytes.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-07-25 02:18:26 +00:00
fca5de51e1 BaseTools/VolInfo: Correct EFI_SECTION_VERSION display
- Correct typo in print statement,
- "BuildNumber" field is UINT16, therefore it needs "0x%04X" format
modifier,
- "VersionString" field is CHAR16, therefore the input data should be
processed to be displayed with "%s" printf modifier.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-24 15:21:20 +00:00
c0b7679aac BaseTools/VolInfo: Increase define for highest section value
Currently sections with unknown types are displayed as
`EFI_SECTION_SMM_DEPEX` which is wrong.
Increase the highest value for the section type to 0x1C
for correct parsing.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Yuwei Chen<yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-24 14:03:47 +00:00
8ee26529d1 BaseTools/VolInfo: Correct alignment attributes display
Alignment attribute is not a bitmask, therefore we need to compare
field value with all alignment defines.
Remove duplicate print statements. Unify indent with other attribute
print statements.

Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-24 07:51:10 +00:00
d32a84b5ad BaseTools: INF should use latest Pcd value instead of default value
This patch is a bug fix about FeatureFlagExpression in INF file:
 INF [Source] section now unconditionally use Pcd default value in DEC
 when handling FeatureFlagExpression, it is wrong.
 If a Pcd value has been set in the DSC file, we should use latest
 value in DSC instead of default value.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Yi Li <yi1.li@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-24 06:46:33 +00:00
6964b5c48c MdeModulePkg/Include: Long debug string is truncated to 104 char
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3986

The EFI_STATUS_CODE_DATA_MAX_SIZE is defined as 200 in MdeModulePkg.
After reducing 96byte buffer for variable parameters it is limited to
only 104 char debug string. This is a non-necessary limitation.
This change sets EFI_STATUS_CODE_DATA_MAX_SIZE to 0x200, and moves
MAX_EXTENDED_DATA_SIZE definition to the same header file with value
of EFI_STATUS_CODE_DATA_MAX_SIZE + sizeof (EFI_STATUS_CODE_DATA)
which is used in ReportStatusCodeLib to support longer debug string.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Dandan Bi <dandan.bi@intel.com>

Signed-off-by: Cosmo Lai <cosmo.lai@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
2022-07-23 03:12:49 +00:00
bf1ff540d9 MdePkg/UefiDevicePathLib: Add support for PEIMs
DevicePathLib utilities are useful in PEI to locate the devices which need
an opal unlock on S3 resume. This commit reuses the implementation done
for standalone MM support and makes the StandaloneMm library Base.

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-23 02:11:31 +00:00
5a3641bfcd IntelFsp2Pkg: Add FSPI_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993

Adding the missing FSPI_ARCH_UPD, FSP_GLOBAL_DATA_VERSION bumpping up,
and some comments for clarification.
Also fixed a bug in SplitFspBin.py for FSP-I support.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-22 18:13:19 +00:00
c8af26627a ArmPkg/CpuDxe: drop ARM_PROCESSOR_TABLE pseudo-ACPI table
The ARM_PROCESSOR_TABLE pseudo-ACPI table (which carries a ACPI-table
like header but is published as a EFI config table) is not described in
any relevant spec, and is not known to be relied upon by any OS. Let's
just get rid of it.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Tested-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-22 17:10:09 +00:00
343f37b5c0 MdeModulePkg/SetupBrowserDxe:Follow spec'd way to reconnect driver
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3952

In UEFI spec, it defines reconnect timing that will be activated upon
exiting of the formset or the browser. However, we did't use this kind
of way to check reconnect conditioncode. Code only blocks reconnect if
page is updated dynamically. That's not matched spec'd way. We should
check current formset whether is exiting, then reconnect driver.

Signed-off-by: Walon Li <walon.li@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-22 06:19:53 +00:00
494f333aba MdeModulePkg/CoreDxe: Allow DXE Drivers to use untested memory
REF: https://https://bugzilla.tianocore.org/show_bug.cgi?id=3795
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Updated CoreInternalAllocatePages() to call PromoteMemoryResource() and
re-attempt the allocation if unable to convert the specified memory range

Signed-off-by: Stacy Howell <stacy.howell@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-22 05:36:57 +00:00
7ef91af84c EmulatorPkg/PosixFileSystem: Add NULL check on memory allocation
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4001

This commit adds NULL check on memory allocation of the size
for FileName in ASCII string format at PosixFileSetInfo().

Signed-off-by: Miki Shindo <miki.shindo@intel.com>
Cc: Andrew Fish <afish@apple.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-07-21 06:18:23 +00:00
3b8cee1781 Maintainers.txt: update Gary's email address
I've left SUSE last month, so the original email address is not
functional anymore. Update my email address to the new one.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Gary Lin <gary.lin@hpe.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2022-07-20 19:02:28 +00:00
4824924377 IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993
Add FSP-I API entry point for SMM support.
Also update 64bit API entry code to assign ApiIdx to RAX
to avoid confusion.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-20 02:15:55 +00:00
24eac4caf3 IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-19 22:24:31 +00:00
140446cd59 IntelFsp2Pkg: Support 64bit FspResetType for X64 build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-19 22:24:31 +00:00
671b0cea51 NetworkPkg/HttpBootDxe: Add Support for HTTP Boot Basic Authentication
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2504

Add support for TLS Client Authentication using Basic Authentication
for HTTP Boot

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
2022-07-19 17:43:07 +00:00
19a8768365 DynamicTablesPkg: AcpiSsdtPcieLibArm: Create support library
Add support library to allow for customization of _OSC and slot info.
The functions in the library are unchanged,
with the exception of adding PciInfo pointer to the APIs.

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-19 16:15:35 +00:00
9ac155bf0b DynamicTablesPkg: AcpiSsdtPcieLibArm: Support UID > 0xF
Add support for PCIe devices with UID > 0xF.
This is done by using the next value in the name so
PCI5, PC26, etc

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-19 16:15:35 +00:00
6cda306da1 DynamicTablesPkg: AcpiSsdtPcieLibArm: Correct translation value
The translation value in ACPI should be the difference between the CPU and PCIe address.

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-19 16:15:35 +00:00
f0064ac3af Maintainers.txt: Update email address
Update Abner's email address from hpe.com to amd.com for
the packages those are maintained by Abner, except RISC-V stuff.

Cc: Andrew Fish <afish@apple.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Signed-off-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2022-07-19 02:21:28 +00:00
e21b203911 UefiPayloadPkg: Add macro to support selective driver in UPL
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3967

Add macros to decide modules built into UPL.elf.

Macro list:
 - GENERIC_MEMORY_TEST_ENABLE: GenericMemoryTestDxe
 - MEMORY_TEST: NullMemoryTestDxe or GenericMemoryDxe
 - ATA_ENABLE: SataControllerDxe, AtaBusDxe
 - SD_ENABLE: SdMmcPciDxe, EmmcDxe, SdDxe
 - PS2_MOUSE_ENABLE: Ps2MouseDxe

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Gua Guo <gua.guo@intel.com>
Signed-off-by: James Lu <james.lu@intel.com>
Reviewed-by: Ray Ni <Ray.ni@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
2022-07-18 22:18:16 +00:00
e18a5f813c Maintainers.txt: Update Maintainers/reviewers for UefiPayloadPkg
Promote Sean Rhodes as UefiPayloadPkg maintainer.
Remove Maurice and Benjamin since their role was changed.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
2022-07-18 21:45:08 +00:00
586b4a104b Maintainers.txt: Add IntelFsp2*Pkg Maintainer
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-18 21:09:37 +00:00
c966204049 IntelFsp2Pkg: Add Definition of EDKII_PEI_VARIABLE_PPI
Adds definition of EDKII_PEI_VARIABLE_PPI.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2022-07-18 20:42:55 +00:00
792ebb6374 DynamicTablesPkg: Fix generated _HID value for SBSA
SSDT tables describing an SBSA compatible serial port receive an '_HID'
value of 'ARMH0011'. This value represents a PL011 serial port.

This patch:
 - Generates an 'ARMHB000' instead
 - References the 'ACPI for Arm Components 1.0 - 2020' document
   specifying the '_HID' values to use.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-18 16:55:37 +00:00
fc4a132c0e DynamicTables: Fix DT PCI interrupt flags parsing
Device Tree PCI interrupt flags use the convention described at
linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml

The 3rd cell is the flags, encoded as follows:
  bits[3:0] trigger type and level flags.
  1 = low-to-high edge triggered
  2 = high-to-low edge triggered (invalid for SPIs)
  4 = active high level-sensitive
  8 = active low level-sensitive (invalid for SPIs).

Fix the incorrect code.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-18 12:44:09 +00:00
039bdb4d3e BaseTools: Fix DSC LibraryClass precedence rule
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3965

Currently DSC LibraryClass precedence rule is not align with DSC Spec.

The expectation rule should be:
[LibraryClasses.$(ARCH)] < [LibraryClasses.Common.$(MODULE_TYPE)]

The actual behavior is:
[LibraryClasses.$(ARCH)] > [LibraryClasses.Common.$(MODULE_TYPE)]

This patch fixes the issue.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Long1 Huang <long1.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-17 03:33:41 +00:00
176016387f BaseTools: add '-p' for Linux 'cp' command.
Currently BaseTools use 'cp' command for PcdValueInit and GenMake
process, as the command can not keep the time info of the source
file, which will cause incremental build issue in Linux system,
thus the '-p' need be added to keep the source file's attributes
in copy process.

This patch fixes this issue.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-07-17 02:20:51 +00:00
07c8e5e59b UefiPayloadPkg/PlatformBootManagerLib: Evenly space boot prompt
Add 4 spaces before the boot prompt "F2 or Down..." so that the
spacing is equadistant from the top, which is spaced with a `\n`,
and the left.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guo Dong <guo.dong@intel.com>
2022-07-16 02:57:38 +00:00
0d23c447d6 DynamicTablesPkg: Add support to specify FADT minor revision
The CM_STD_OBJ_ACPI_TABLE_INFO.AcpiTableRevision can be used to specify
the major revision number of the ACPI table that the generator must use.
Although most ACPI tables only have a major revision number, the FADT
table additionally has a minor revision number.

The FADT generator currently defaults to setting the latest supported
ACPI revision for the FADT table i.e. ACPI 6.4. This means that the minor
revision for the FADT table is always set to 4 and there is no provision
for a user to specify the minor revision to be selected.

Therefore, update CM_STD_OBJ_ACPI_TABLE_INFO to introduce a new field
MinorRevision which can be used to specify the minor revision for an
ACPI table. Also update the FADT generator to validate the supported
FADT revisions ans use the specified minor revision for the FADT table
if supported. If an unsupported minor revision is specified the FADT
generator defaults to the latest supported minor revision.

Since the CM_STD_OBJ_ACPI_TABLE_INFO.MinorRevision field is added to
the end of the structure, it should not break existing platform code.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: <pierre.gondois@arm.com>
Tested-by: Jagadeesh Ujja <Jagadeesh.Ujja@arm.com>
2022-07-15 18:07:49 +00:00
470206ba7f IntelFsp2Pkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2022-07-14 18:13:44 +00:00
9ab389c01b UefiCpuPkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64. dff

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2022-07-14 18:13:44 +00:00
12dd064a18 MdePkg/include: Update DMAR definitions to Intel VT-d spec ver4.0
Updated DMAR definitions accordingly to changes in Intel(R) Virtualization
Technology for Directed I/O (VT-D) Architecture Specification ver4.0.

Added new definition of remapping structure - SIDP. The SoC Integrated
Device Property (SIDP) reporting structure identifies devices that have
special properties and that may put restrictions on how system software
must configure remapping structures that govern such devices in a platform
where remapping hardware is enabled.

Updated DRHD definition - field 'reserved' is replaced with 'Size'.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3978

Signed-off-by: Robert Kowalewski <robert.kowalewski@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Sheng Wei <w.sheng@intel.com>
Reviewed-by: Sheng Wei <w.sheng@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-11 07:46:10 +00:00
f6f3cc7ead UefiPayloadPkg: Add CryptoDxe driver to UefiPayload
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3979

Add CryptoDxe into UPL.
Drviers can locate protocol instead of building openssl lib into drivers.
This can reduce the binary size that UPL required.

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: PaytonX Hsieh <paytonx.hsieh@intel.com>
2022-07-11 04:16:37 +00:00
c8e30482fd .gitignore: Ignore build tools build logs
The python BaseTools/Edk2ToolsBuild.py creates files in
BaseTools/BaseToolsBuild and should be ignored.

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-09 14:57:49 +00:00
86a0f84470 ArmVirtPkg: Pipeline: Resolving newly introduced dependency
The new changes in SecureBootVariableLib brought in a new dependency
of PlatformPKProtectionLib.

This change added the new library instance from SecurityPkg to resolve
ArmVirtPkg builds.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
2022-07-09 06:57:55 +00:00
e93bc6309b UefiCpuPkg/SecCore: Add debug messages to illuminate data flow
Add debug messages to make it easier to verify PlatformSecLib
is passing the data properly.

Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
2022-07-08 04:04:22 +00:00
5496c763aa StandaloneMmPkg: Fix check buffer address failed issue from TF-A
There are two scene communicate with StandaloneMm(MM):
1 edk2 -> TF-A -> MM, communicate MM use non-secure buffer which
  specify by EFI_SECURE_PARTITION_BOOT_INFO.SpNsCommBufBase;
2 RAS scene: fiq -> TF-A -> MM, use secure buffer which
  specify by EFI_SECURE_PARTITION_BOOT_INFO.SpShareBufBase;

For now, the second scene will failed because check buffer address.
This patch add CheckBufferAddr() to support check address for secure
buffer.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-07 10:20:06 +00:00
31d3eeb103 StandaloneMmPkg: Replace DEBUG_INFO with DEBUG_ERROR
DEBUG_ERROR should be used in error branch.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-07 10:20:06 +00:00
9ab18fec82 StandaloneMmPkg: Fix issue about SpPcpuSharedBufSize field
TF-A: TrustedFirmware-A
SPM: Secure Partition Manager(MM)

In TF-A, the name of this field is sp_shared_buf_size. This field is
the size of range for transmit data from TF-A to standaloneMM when
SPM enable.

SpPcpuSharedBufSize is pass from TF-A while StandaloneMM initialize.
So, SpPcpuSharedBufSize should be rename to SpSharedBufSize and this field
should no multiply by PayloadBootInfo->NumCpus;

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-07-07 10:20:06 +00:00
f193b945ea EmulatorPkg: Pipeline: Resolve SecureBootVariableLib dependency
The new changes in SecureBootVariableLib brought in a new dependency of
PlatformPKProtectionLib.

This change added the new library instance from SecurityPkg to resolve
pipeline builds.

Cc: Andrew Fish <afish@apple.com>
Cc: Ray Ni <ray.ni@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
152e37cc5a OvmfPkg: Pipeline: Resolve SecureBootVariableLib dependency
The new changes in SecureBootVariableLib brought in a new dependency of
PlatformPKProtectionLib.

This change added the new library instance from SecurityPkg to resolve
pipeline builds.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Cc: Peter Grehan <grehan@freebsd.org>
Cc: Sebastien Boeuf <sebastien.boeuf@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
dbc4e3675f SecurityPkg: SecureBootVariableLib: Added unit tests
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3911

This change added unit test and enabled it from pipeline for the updated
SecureBootVariableLib.

The unit test covers all implemented interfaces and certain corner cases.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
5678ebb42b SecurityPkg: SecureBootConfigDxe: Updated invocation pattern
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3909

This change is in pair with the previous SecureBootVariableLib change,
which updated the interface of `CreateTimeBasedPayload`.

This change added a helper function to query the current time through
Real Time Clock protocol. This function is used when needing to format
an authenticated variable payload.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
d2a0f379d5 SecurityPkg: Secure Boot Drivers: Added common header files
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3910

This change added common header files to consumer drivers to unblock
pipeline builds.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
fe73e9cd89 SecurityPkg: SecureBootVariableProvisionLib: Updated implementation
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3910

This change is in pair with the previous SecureBootVariableLib, which
removes the explicit invocation of `CreateTimeBasedPayload` and used new
interface `EnrollFromInput` instead.

The original `SecureBootFetchData` is also moved to this library and
incorporated with the newly defined `SecureBootCreateDataFromInput` to
keep the original code flow.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
6eb4079475 SecurityPkg: SecureBootVariableLib: Added newly supported interfaces
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3911

This change updated the interfaces provided by SecureBootVariableLib.

The new additions provided interfaces to enroll single authenticated
variable from input, a helper function to query secure boot status,
enroll all secure boot variables from UefiSecureBoot.h defined data
structures, a as well as a routine that deletes all secure boot related
variables.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
6de7c084db SecurityPkg: SecureBootVariableLib: Updated signature list creator
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3910

This change removes the interface of SecureBootFetchData, and replaced
it with `SecureBootCreateDataFromInput`, which will require caller to
prepare available certificates in defined structures.

This improvement will eliminate the dependency of reading from FV,
extending the availability of this library instance.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
56c717aafa SecurityPkg: SecureBootVariableLib: Updated time based payload creator
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3909

This change updated the interface of 'CreateTimeBasedPayload' by
requiring the caller to provide a timestamp, instead of relying on time
protocol to be ready during runtime. It intends to extend the library
availability during boot environment.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
d6bee54c45 SecurityPkg: PlatformPKProtectionLib: Added PK protection interface
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3911

This patch provides an abstracted interface for platform to implement PK
variable related protection interface, which is designed to be used when
PK variable is about to be changed by UEFI firmware.

This change also provided a variable policy based library implementation
to accomodate platforms that supports variable policy for variable
protections.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
134fbd552c SecurityPkg: UefiSecureBoot: Definitions of cert and payload structures
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3910

This change added certificate and payload structures that can be consumed
by SecureBootVariableLib and other Secure Boot related operations.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min Xu <min.m.xu@intel.com>

Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-07-07 01:07:00 +00:00
e1eef3a8b0 NetworkPkg: Add Wi-Fi Wpa3 support in WifiConnectManager
https://bugzilla.tianocore.org/show_bug.cgi?id=3961

Add below Wpa3 support:
    WPA3-Personal:
      Ieee80211AkmSuiteSAE                = 8
    WPA3-Enterprise:
      Ieee80211AkmSuite8021XSuiteB        = 11
      Ieee80211AkmSuite8021XSuiteB192     = 12
    Wi-Fi CERTIFIED Enhanced Open:
      Ieee80211AkmSuiteOWE                = 18

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
2022-07-01 16:02:32 +00:00
7861b24dc9 ArmPkg/Drivers: ArmGicIsInterruptEnabled returns incorrect value
The issue appears to have been introduced by:

41fb5d46 : ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3

The changes to ArmGicIsInterruptEnabled() introduced the error where the Boolean
result is assigned to Interrupts, but then the bit position check is performed
again (against the computed Boolean result instead of the interrupt mask) during
the return statement.

Fix removes erroneous test and relies on boolean test made at return.

Signed-off-by: Robbie King <robbiek@xsightlabs.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-07-01 15:28:08 +00:00
70586d4e3a MdePkg/Acpi62: Add bit definitions to NFIT Platform Capabilities Structure
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3915

This commit adds each capability bit definition
for NFIT Platform Capabilities Structure.
The type has been added since ACPI Specification Version 6.2A.

Signed-off-by: Miki Shindo <miki.shindo@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-07-01 15:00:06 +00:00
f966093f5b OvmfPkg/PlatformCI: add IntelTdxBuild.py
Add build test for OvmfPkg/IntelTdx

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2022-07-01 06:48:12 +00:00
8d0564deaf pip-requirements.txt: Update basetools version to 0.1.24
Upgrade the edk2-basetools version from 0.1.17 to 0.1.24

features and bug fixes:
1. Add FMMT Python Tool
2. Remove RVCT support
3. Fix dependency issue in PcdValueInit
4. Output the intermediate library instance when error occurs
5. Ecc: Fix grammar in Ecc error message
6. Fix the GenMake bug for .cpp source file

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-06-30 04:18:27 +00:00
21e6ef7522 UefiPayloadPkg: Align Attribute value with UPL spec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3963

Based on UPL spec 2.12.2. Universal Payload Information Section,
it defines item "Attribute" on UPLD_INFO_HEADER for Debug build
should be "1", and Release build should be "0".

Currently, The value of item "Attribute" is always "0"

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
2022-06-30 03:45:38 +00:00
c13377153f MdePkg/Acpi62: Add type 7 NFIT Platform Capabilities Structure support
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3915

This commit adds a definition type 7 Platform Capabilities Structure
and the struct definition for NFIT Table Structure Types.
The type has been added since ACPI Specification Version 6.2A.

Signed-off-by: Miki Shindo <miki.shindo@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-06-29 02:53:49 +00:00
5914128871 BaseTools: Fix the GenMake bug for .cpp source file
Build-rules.txt lists .cc and .cpp as supported file extensions.
BaseTools commit 05217d210e introduce a regression issue that
ignore the .cc and .cpp file type.

This patch is to fix this bug.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Yuwei Chen<yuwei.chen@intel.com>
2022-06-28 09:14:55 +00:00
7f4eca4cc2 MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities Pointer
Add support process Port Speed field value of PORTSC according to
Supported Protocol Capability (define in xHCI spec 1.1)

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914

The value of Port Speed field in PORTSC bit[10:13]
(xHCI spec 1.1 section 5.4.8) should be change to use this value to
query thru Protocol Speed ID (PSI) (xHCI spec 1.1 section 7.2.1)
in xHCI Supported Protocol Capability and return the value according
the Protocol Speed ID (PSIV) Dword.

With this mechanism may able to detect more kind of Protocol Speed
in USB3 and also compatiable with three kind of speed of USB2.

Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Ian Chiu <Ian.chiu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2022-06-27 02:48:11 +00:00
b600f253b3 BaseTools/Ecc: Fix grammar in Ecc error message
Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-06-27 01:06:48 +00:00
15b25045e6 Ovmf: Include HardwareInfoLib library classes for IntelTdx
Include HardwareInfoLib classes in the IntelTdxX64.dsc for this
platform to use it during build given that PciHostBridgeUtilityLib
depends on it.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-24 18:06:25 +00:00
8f0722434b ArmVirtPkg: Include DxeHardwareInfoLib library class in dsc
Include DxeHardwareInfoLib class in the common ArmVirt.dsc.inc so that
ArmVirt* platforms use it during build given that PciHostBridgeUtilityLib
depends on it.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-24 18:06:25 +00:00
2aee08c0b6 UefiPayloadPkg: Backward support with python 3.6
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3960

Currently, UniversalPayloadBuild.py don't have support
python3.6, we use python3.6 will encounter f"" failure
use the change to fix it to support python3.6/3.7/3.8.

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: James Lu <james.lu@intel.com>
Reviewed-by: Gua Guo <gua.guo@intel.com>
Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
2022-06-24 12:59:41 +00:00
4bfd668e5e UefiCpuPkg: CpuDxe: Set RW and P Attributes on Split Pages
A memory range can be submitted for attribute changes which is large
enough to not require a page split during the attribute update. Consider
the following scenario:

1. An attribute update removed the RW attribute on a range large enough
to not require a page split.
2. Later, an attributes update is called to re-add the RW attribute for
a subsection of that larger page which requires a split
3. The attribute update logic performs a page split, so now the parent
and child pages have matching attributes
4. Then, the attribute update logic changes the child page to have the
RW attribute.
5. The child page would then correctly have the RW attribute added but
the parent page would still have the RW attribute removed which will
cause an improper access violation.

The page being split should have loose attributes to accommodate the
above case. The split page should always have the attributes set so
the lowest level page frame determines the access rights as detailed
in 4.10.2.2 of the Intel 64 and IA-32 Architectures Software
Developer Manual. Setting the User/Supervisor attribute shouldn't
be necessary.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Taylor Beebe <t@taylorbeebe.com>
2022-06-23 06:36:56 +00:00
f304308e1c ArmPlatformPkg: Add PCD for serial debug port interrupt
For Arm platforms that support more that one serial port, one of the
serial port can be used for connecting debuggers such as WinDbg. There
are PCDs that allow the base address and clock rate to be specified for
this debug serial port but not its interrupt number. So add a PCD to
specify the interrupt number assigned to the serial debug port
controller.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-06-22 17:31:49 +00:00
3f5b1b9132 OvmfPkg/PciHostBridgeUtilityLib: Initialize RootBridges apertures with spec
Consume the host-provided specification of PCI host bridges if
available. Using the DxeHardwareInfoLib, populate a list of
hardware descriptors based on the content of the "hardware-info"
fw-cfg file, if provided. In the affirmative case, use the
resources and attributes specified by the hypervisor for each
Host Bridge to create the RootBridge elements.

In Ovmf platforms, the host can provide the specification of
non-discoverable hardware resources like PCI host bridges. If the
proper fw-cfg file is found, parse the contents provided by the
host into a linked list by using the Hardware Info library. Then,
using the list of PCI host bridges' descriptions, populate the
PCI_ROOT_BRIDGES array with the resources and attributes specified
by the host. If the file is not provided or no Host Bridge is found
in it, fold back to the legacy method based on pre-defined
apertures and rules.

In some use cases, the host requires additional control over the
hardware resources' configurations in the guest for performance and
discoverability reasons. For instance, to disclose information about
the PCI hierarchy to the guest so that this can profit from
optimized accesses. In this case, the host can decide to describe
multiple PCI Host Bridges and provide a specific set of resources
(e.g. MMIO apertures) so that the guest uses the values provided.
Using the provided values may entitle the guest to added performance,
for example by using specific MMIO mappings that can enable peer-to-peer
communication across the PCI hierarchy or by allocating memory closer
to a device for faster DMA transactions.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-22 15:34:16 +00:00
3497fd5c26 Ovmf/PlatformPei: Use host-provided GPA end if available
Read the "hardware-info" item from fw-cfg to extract specifications
of PCI host bridges and analyze the 64-bit apertures of them to
find out the highest 64-bit MMIO address required which determines
the address space required by the guest, and, consequently, the
FirstNonAddress used to calculate size of physical addresses.

Using the static PeiHardwareInfoLib, read the fw-cfg file of
hardware information to extract, one by one, all the host
bridges. Find the last 64-bit MMIO address of each host bridge,
using the HardwareInfoPciHostBridgeLib API, and compare it to an
accumulate value to discover the highest address used, which
corresponds to the highest value that must be included in the
guest's physical address space.

Given that platforms with multiple host bridges may provide the PCI
apertures' addresses, the memory detection logic must take into
account that, if the host provided the MMIO windows that can and must
be used, the guest needs to take those values. Therefore, if the
MMIO windows are found in the host-provided fw-cfg file, skip all the
logic calculating the physical address size and just use the value
provided. Since each PCI host bridge corresponds to an element in
the information provided by the host, each of these must be analyzed
looking for the highest address used.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-22 15:34:16 +00:00
a1bd79c514 Ovmf/HardwareInfoLib: Add Dxe lib to dynamically parse heterogenous data
Following the Hardware Info library, create the DxeHardwareInfoLib
which implements the whole API capable of parsing heterogeneous hardware
information. The list-like API grants callers a flexible and common
pattern to retrieve the data. Moreover, the initial source is a BLOB
which generalizes the host-to-guest transmission mechanism.

The Hardware Info library main objective is to provide a way to
describe non-discoverable hardware so that the host can share the
available resources with the guest in Ovmf platforms. This change
features and embraces the main idea behind the library by providing
an API that parses a BLOB into a linked list to retrieve hardware
data from any source. Additionally, list-like APIs are provided so
that the hardware info list can be traversed conveniently.
Similarly, the capability is provided to filter results by specific
hardware types. However, heterogeneous elements can be added to the
list, increasing the flexibility. This way, a single source, for
example a fw-cfg file, can be used to describe several instances of
multiple types of hardware.

This part of the Hardware Info library makes use of dynamic memory
and is intended for stages in which memory services are available.
A motivation example is the PciHostBridgeLib. This library, part
of the PCI driver populates the list of PCI root bridges during DXE
stage for future steps to discover the resources under them. The
hardware info library can be used to obtain the detailed description
of available host bridges, for instance in the form of a fw-cfg file,
and parse that information into a dynmaic list that allows, first to
verify consistency of the data, and second discover the resources
availabe for each root bridge.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-22 15:34:16 +00:00
2b1a5b8c61 Ovmf/HardwareInfoLib: Create Pei lib to parse directly from fw-cfg
Define the HardwareInfoLib API and create the PeiHardwareInfoLib
which implements it, specifically for Pei usage, supporting
only static accesses to parse data directly from a fw-cfg file.
All list-like APIs are implemented as unsupported and only a
fw-cfg wrapper to read hardware info elements is provided.

The Hardware Info library is intended to describe non-discoverable
hardware information and share that from the host to the guest in Ovmf
platforms. The QEMU fw-cfg extension for this library provides a first
variation to parse hardware info by reading it directly from a fw-cfg
file. This library offers a wrapper function to the plain
QmeuFwCfgReadBytes which, specifically, parses header-data pairs out
of the binary values in the file. For this purpose, the approach is
incremental, reading the file block by block and outputting the values
only for a specific known hardware type (e.g. PCI host bridges). One
element is returned in each call until the end of the file is reached.

Considering fw-cfg as the first means to transport hardware info from
the host to the guest, this wrapping library offers the possibility
to statically, and in steps, read a specific type of hardware info
elements out of the file. This method reads one hardware element of a
specific type at a time, without the need to pre-allocate memory and
read the whole file or dynamically allocate memory for each new
element found.

As a usage example, the static approach followed by this library
enables early UEFI stages to use and read hardware information
supplied by the host. For instance, in early times of the PEI stage,
hardware information can be parsed out from a fw-cfg file prescinding
from memory services, that may not yet be available, and avoiding
dynamic memory allocations.

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-22 15:34:16 +00:00
6c9f218bc0 OvmfPkg/Library: Create base HardwareInfoLib for PCI Host Bridges
Create the Hardware Info library base together with the specifics to
describe PCI Host Bridges.

The Hardware Info library is intended to be used for disclosing
non-discoverable hardware information from the host to the guest in
Ovmf platforms. Core functionality will provide the possibility to
parse information from a generic BLOB into runtime structures. The
library is conceived in a generic way so that further hardware
elements can also be described using it. For such purpose the length
of the BLOB is not restricted but instead regarded as a sequence of
header-info elements that allow the parsing during runtime. The first
type of hardware defined will be PCI host bridges, providing the
possibility to define multiple and specify the resources each of them
can use. This enables the guest firmware to configure PCI resources
properly. Having the size of each individual element favors the reuse
of a single interface to convey descriptions of an arbitrary number
of heterogenous hardware elements. Furthermore, flexible access
mechanisms coupled with the size will grant the possibility of
interpreting them in a single run.

Define the base types of the generic Hardware Info library to parse
heterogeneous data. Also provide the specific changes to support
PCI host bridges as the first hardware type supported by the
library.
Additionally, define the HOST_BRIDGE_INFO structure to describe PCI
host bridges along with the functionality to parse such information
into proper structures used by the PCI driver in a centralized manner
and taking care of versioning.

As an example and motivation, the library will be used to define
multiple PCI host bridges for complex platforms that require it.
The first means of transportation that will be used is going to be
fw-cfg, over which a stream of bytes will be transferred and later
parsed by the hardware info library. Accordingly, the PCI driver
will make use of these host bridges definitions to populate the
list of Root Bridges and proceed with the configuration and discovery
of underlying hardware components.

As mentioned before, the binary data to be parsed by the Hardware
Info library should be organized as a sequence of Header-element
pairs in which the header describes the type and size of the associated
element that comes right after it. As an illustration, to provide
inforation of 3 host bridges the data, conceptually, would look
like this:

Header PCI Host Bridge (type and size) # 1
PCI Host Bridge info # 1
Header PCI Host Bridge (type and size) # 2
PCI Host Bridge info # 2
Header PCI Host Bridge (type and size) # 3
PCI Host Bridge info # 3

Cc: Alexander Graf <graf@amazon.de>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
2022-06-22 15:34:16 +00:00
aa1bce0e5e OvmfPkg: reduce the number of dsc include files for tpm libs
We can have multiple [LibraryClasses] sections, so we can place
all TPM-related library configuration to a single include file.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2022-06-22 15:34:16 +00:00
3930d1791a ArmPlatformPkg: Remove overly verbose DEBUG lines in LcdGraphicsBlt
The DEBUG output in LcdGraphicsBlt is overly verbose, and makes using
the console difficult, for example when using the UiApp.

Since the extra output should no longer be needed, delete the DEBUG
lines.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-06-22 14:57:31 +00:00
b97243dea3 MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE register
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954

Report error if reserved bits are not 0 for PageSize

Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2022-06-22 01:15:39 +00:00
cfe165140a UefiPayloadPkg: UniversalPayloadBuild.py to support --pcd feature
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3955

Currently, UPL freezed all PCD and only known UPL hob can hook DXE
Drivers behavior, add optional feature on UniversalPayloadBuild.py to
have another way to hook PCD value.

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: : Ray Ni <ray.ni@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
2022-06-21 04:11:13 +00:00
e8034b534a UefiPayloadPkg: Always split page table entry to 4K if it covers stack.
We observed page fault in the following situation:
1.PayloadEntry uses 2M entry in page table to cover DXE stack range.
2.In DXE phase, image protection code needs to mark some sub-range in
this 2M entry as readonly. So the the 2M page table entry is split to
512 4K entries, and some of the entries are marked as readonly.
(the entries covering stack still remain R/W)
3.Page fault exception happens when trying to access stack.

Always split the page table entry to 4K if it covers stack to avoid this
issue.
More discussion about this issue can be seen at below link
https://edk2.groups.io/g/devel/topic/91446026

Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
2022-06-20 04:53:17 +00:00
cc2db6ebfb UefiPayloadPkg: Increase the PcdMaximumUnicodeStringLength
The maximum Unicode string could be as large as 1800000 in certain
platforms when HII code builds the configuration strings.
This causes assertion in PrintLib.
The patch increases the PcdMaximumUnicodeStringLength to 1800000 to
avoid the assertion.

Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
2022-06-17 09:15:31 +00:00
92ab049719 BaseTools: output the intermediate library instance when error occurs
When a module "Module" depends on a library instance "Lib1" which
depends on "Lib2" which depends on "Lib3" ... depends on "LibN",
but "LibN" doesn't support the type (e.g.: SEC) of the "Module", the
following error messages are printed by build tool:

<DSC path>(...): error 1001: Module by library instance [<LibN path>]
        consumed by [<Module path>]

But it's unclear to user how LibN is consumed by the Module.

With the patch, following errors are printed:

<DSC path>(...): error 1001: Module by library instance [<LibN path>]
        consumed by library instance [<Lib N-1 path>] which is
        consumed by module[<Module path>]

It doesn't print all the intermediate library instances between the
Module and LibN but at least the path of Lib N-1 can help users
to help how to fix the build errors.

I hope this patch can be a trigger point that a better solution could
be developed by tool experts to print all the library instances
between the Module and LibN.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Bob Feng <bob.c.fen@intel.com>
2022-06-16 12:18:07 +00:00
05e57cc9ce SecurityPkg/HashLibTdx: Return EFI_UNSUPPORTED if it is not Tdx guest
HashLibTdx is designed for the Tdx guest. So if is not a Tdx guest,
return EFI_UNSUPPORTED in RegisterHashInterfaceLib.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-16 08:08:19 +00:00
16d97fa601 OvmfPkg: Use PcdOvmfWorkAreaBase instead of PcdSevEsWorkAreaBase
It is an typo error that HobList pointer should be stored at
PcdOvmfWorkAreaBase, not PcdSevEsWorkAreaBase.

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-16 08:08:19 +00:00
6676162f64 DxeMain: Fix the bug that StackGuard is not enabled
Commit e7abb94d1 removed InitializeCpuExceptionHandlersEx
and updated DxeMain to call InitializeCpuExceptionHandlers
for exception setup. But the old behavior that calls *Ex() sets
up the stack guard as well. To match the old behavior,
the patch calls InitializeSeparateExceptionStacks.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
2022-06-14 02:59:22 +00:00
e2ae0bed29 ArmPkg/ArmExceptionLib: Follow new CpuExceptionHandlerLib APIs
CpuExceptionHandlerLib has been refactored with following changes:
1. Removed InitializeCpuInterruptHandlers in 2a09527ebc
2. Removed InitializeCpuExceptionHandlersEx and
   added InitializeSeparateExceptionStacks in e7abb94d1f

The patch updates ARM version of CpuExceptionHandlerLib to follow
the API changes.

The functionality to ARM platforms should be none.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2022-06-14 02:59:22 +00:00
92288f4334 MdePkg/BaseLib: Add CRC16-ANSI and CRC32c implementations
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3871

Add the CRC16-ANSI and CRC32C implementations previously found at
Features/Ext4Pkg/Ext4Dxe/Crc{16,32c}.c to BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-06-13 02:41:35 +00:00
b09ada6edc MdePkg: Remove "assert" from SmmCpuRendevousLibNull.c
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3931

Some drivers will break down when they use
SmmWaitForAllProcessor() which from SmmCpuRendezvousLibNull.c.
Removing the code "ASSERT(False)" will make consumer
work normally if they keep default setting for sync mode.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Zhihao Li <zhihao.li@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2022-06-13 01:37:16 +00:00
f0b97e165e Revert "OvmfPkg/Sec: fix stack switch"
This reverts commit ff36b2550f.

Has no effect because GCC_IA32_CC_FLAGS and GCC_X64_CC_FLAGS are unused.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-10 17:19:59 +00:00
ccc269756f MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitialize
The AP vector consists of 2 parts:
1. the initial 16-bit code that should be under 1MB and page aligned.
2. the 32-bit/64-bit code that can be anywhere in the memory with any
   alignment.

The need of part #2 is because the memory under 1MB is temporary
"stolen" for use and will "give" back after all AP wake up. The range
of memory is not marked as code page in page table. CPU may trigger
exception as soon as NX is enabled.

The part #2 memory allocation can be done in the MpInitLibInitialize.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-06-10 12:15:49 +00:00
283ab9437a MpInitLib: Only allocate below 1MB memory for 16bit code
Today's implementation allocates below 1MB memory for the 16bit, 32bit
and 64bit code.

But it's not necessary since now the 32bit and 64bit code run at high
memory no matter in PEI and DXE phase.

The patch simplifies the logic to remove the code that handles the
case when WakeupBufferHigh is 0.
It also reduce the memory foot print under 1MB by allocating
memory for 16bit code only.

MP_CPU_EXCHANGE_INFO is still under 1MB which is immediate
after the 16bit code.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-06-10 12:15:49 +00:00
b4d7b9d2b5 MpInitLib: Put SEV logic in separate file
The patch does several simplifications:
1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
   So the common logic in MpLib.c doesn't need to be aware of
   SwitchToRealProc.
   As a result, SwitchToRealSize/Offset are removed from
   MP_ASSEMBLY_ADDRESS_MAP.

2. Move SwitchToRealProc to AmdSev.nasm.
   All other assembly code in AmdSev.nasm is called through
   OneTimeCall.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
2022-06-10 12:15:49 +00:00
76323c3145 MpInitLib: remove unneeded global ASM_PFX
global in NASM file is used for symbols that are
referenced in C files.
Remove unneeded global keyword in NASM file.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-06-10 12:15:49 +00:00
54aeed7e00 MpInitLib: Allocate code buffer for PEI phase
Today's implementation assumes PEI phase runs at 32bit so
the execution-disable feature is not applicable.
It's not always TRUE.
The patch allocates 32bit&64bit code buffer for PEI phase as well.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-06-10 12:15:49 +00:00
e7abb94d1f CpuException: Add InitializeSeparateExceptionStacks
Today InitializeCpuExceptionHandlersEx is called from three modules:
1. DxeCore (links to DxeCpuExceptionHandlerLib)
    DxeCore expects it initializes the IDT entries as well as
    assigning separate stacks for #DF and #PF.
2. CpuMpPei (links to PeiCpuExceptionHandlerLib)
   and CpuDxe (links to DxeCpuExceptionHandlerLib)
    It's called for each thread for only assigning separate stacks for
    #DF and #PF. The IDT entries initialization is skipped because
    caller sets InitData->X64.InitDefaultHandlers to FALSE.

Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib
also implement such API and the behavior of the API is simply to initialize
IDT entries only.

Because it mixes the IDT entries initialization and separate stacks
assignment for certain exception handlers together, in order to know
whether the function call only initializes IDT entries, or assigns stacks,
we need to check:
1. value of InitData->X64.InitDefaultHandlers
2. library instance

This patch cleans up the code to separate the stack assignment to a new API:
InitializeSeparateExceptionStacks().

Only when caller calls the new API, the separate stacks are assigned.
With this change, the SecPei and Smm instance can return unsupported which
gives caller a very clear status.

The old API InitializeCpuExceptionHandlersEx() is removed in this patch.
Because no platform module is consuming the old API, the impact is none.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
2022-06-10 07:54:48 +00:00
2a09527ebc CpuException: Remove InitializeCpuInterruptHandlers
InitializeCpuExceptionHandlers() expects caller allocates IDT while
InitializeCpuInterruptHandlers() allocates 256 IDT entries itself.

InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated
by caller. If caller allocates 10 entries, the API just fills 10 IDT
entries.

The inconsistency between the two APIs makes code hard to
unerstand and hard to share.

Because there is only one caller (CpuDxe) for
InitializeCpuInterruptHandler(), this patch updates CpuDxe driver
to allocates 256 IDT entries then call
InitializeCpuExceptionHandlers().

This is also a backward compatible change.

With this change, InitializeCpuInterruptHandlers() is removed
completely.

And InitializeCpuExceptionHandlers() fills max 32 entries for PEI
and SMM instance, max 256 entries for DXE instance.
Such behavior matches to the original one.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
2022-06-10 07:54:48 +00:00
2fbc5ff0a5 CpuException: Avoid allocating page but using global variables
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
2022-06-10 07:54:48 +00:00
34d505123e CpuException: Init global variables in-place
Additionally removed two useless global variables:
"SPIN_LOCK  mDisplayMessageSpinLock" from SMM instance.
"UINTN mEnabledInterruptNum" from DXE instance.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
2022-06-10 07:54:48 +00:00
21a9b605b8 CpuException: Avoid allocating code pages for DXE instance
Today the DXE instance allocates code page and then copies the IDT
vectors to the allocated code page. Then it fixes up the vector number
in the IDT vector.

But if we update the NASM file to generate 256 IDT vectors, there is
no need to do the copy and fix-up.

A side effect is 4096 bytes (HOOKAFTER_STUB_SIZE * 256) is used for
256 IDT vectors while 32 IDT vectors only require 512 bytes without
this change, in following library instances:
1. 32bit SecPeiCpuExceptionHandlerLib and PeiCpuExceptionHandlerLib
2. 64bit PeiCpuExceptionHandlerLib

But considering the code logic simplification, 3.5K extra space is
not a big deal.
If 3.5K is too much, we can enhance the code further to generate 32
vectors for above mentioned library instances.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Eric Dong <eric.dong@intel.com>
2022-06-10 07:54:48 +00:00
ff36b2550f OvmfPkg/Sec: fix stack switch
The ebp/rbp register can either be used for the frame pointer or
as general purpose register.  With gcc (and clang) this depends
on the -f(no-)omit-frame-pointer switch.

This patch updates tools_def.template to explicitly set the compiler
option and also add a define to allow conditionally compile code.

The new define is used to fix stack switching in TemporaryRamMigration.
The ebp/rbp must not be touched when the compiler can use it as general
purpose register.  With version 12 gcc starts actually using the
register, so changing it leads to firmware crashes in some
configurations.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3934
Reported-by: Jiri Slaby <jirislaby@kernel.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-08 11:48:07 +00:00
a81a650da1 OvmfPkg: Delete SecMeasurementLibTdx
The feature of SecMeasurementLibTdx is replaced by SecTpmMeasurementLibTdx
(which is in SecurityPkg). So SecMeasurementLibTdx is deleted.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-07 11:05:53 +00:00
ff0ffe5999 OvmfPkg: Implement MeasureHobList/MeasureFvImage
MeasureHobList and MeasureFvImage once were implemented in
SecMeasurementTdxLib. The intention of this patch-set is to refactor
SecMeasurementTdxLib to be an instance of TpmMeasurementLib. So these
2 functions (MeasureHobList/MeasureFvImage) are moved to
PeilessStartupLib. This is because:
1. RTMR based trusted boot is implemented in Config-B (See below link)
2. PeilessStartupLib is designed for PEI-less boot and it is the right
   place to do the measurement for Hoblist and Config-FV.

Config-B: https://edk2.groups.io/g/devel/message/76367

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-07 11:05:53 +00:00
2818fda9bc Security: Add SecTpmMeasurementLibTdx
SecTpmMeasurementLitTdx is an instance of TpmMeasurementLib. It is
designed to used in a Td guest. This lib measures and logs data, and
extendx the measurement result into a specific RTMR.

SecTpmMeasurementLibTdx is a refactored lib of
OvmfPkg/Library/SecMeasurementLibTdx and it just copies
GetMappedRtmrIndex/TdxMeasureAndLogData from that lib. At the end of
this patch-set SecMeasurementLibTdx will be deleted.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-07 11:05:53 +00:00
4f89e4b3e8 .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package path
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942

`IgnoreFiles` tag is specified in the CI YAML files in each individual
packages. The current logic for UncrustifyCheck script bases specified
file paths from workspace, which requires the package name to be included
in each entry.

This change updates the ignore checking logic to be based on current
package path in order to reduce redundancy. It also keeps the consistency
of `IgnoreFiles` field other pytools such as SpellCheck and EccCheck.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael Kubacki <mikuback@linux.microsoft.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
2022-06-07 01:53:24 +00:00
0b36dea3f8 BaseTools: Fix dependency issue in PcdValueInit
The generated Makefile was missing a dependency.  This resulted in a
build-time race condition if the recursive make is multi-threaded and
shares job control.

Signed-off-by: Jake Garver <jake@nvidia.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2022-06-06 00:02:30 +00:00
0a4019ec9d OvmfPkg/IntelTdx: Enable RTMR based measurement and measure boot
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

Enable RTMR based measurement and measure boot for Td guest.

Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Ken Lu <ken.lu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
57a6ee3461 OvmfPkg/IntelTdx: Add TdTcg2Dxe
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TdTcg2Dxe mimics the Security/Tcg/Tcg2Dxe. It does below tasks:
 - Set up and install CC_EVENTLOG ACPI table
 - Parse the GUIDed HOB (gCcEventEntryHobGuid) and create CC event log
 - Measure handoff tables, Boot##### variables etc
 - Measure Exit Boot Service failed
 - Install CcMeasurement Protocol

Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Ken Lu <ken.lu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
f8264e1303 MdePkg: Define CC Measure EventLog ACPI Table
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the
event-log information. The event log created by the TD owner contains
the hashes to reconstruct the MRTD and RTMR registers.

Please refer to Sec 4.3.3 in blow link:
https://www.intel.com/content/dam/develop/external/us/en/documents/
intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf

Please be noted, the definition of EFI_CC_EVENTLOG_ACPI_TABLE is a
little different from the above document. This difference is based on
below discussion:
- https://edk2.groups.io/g/devel/message/87396
- https://edk2.groups.io/g/devel/message/87402

This change will be reflected in the next version of the above document.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ken Lu <ken.lu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
ac03c339de OvmfPkg: Add PCDs for LAML/LASA field in CC EVENTLOG ACPI table
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

Add PCDs to records LAML/LASA field in CC EVENTLOG ACPI table.

Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Ken Lu <ken.lu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
4b0a622635 OvmfPkg/IntelTdx: Measure Td HobList and Configuration FV
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TdHobList and Configuration FV are external data provided by Host VMM.
These are not trusted in Td guest. So they should be validated , measured
and extended to Td RTMR registers. In the meantime 2 EFI_CC_EVENT_HOB are
created. These 2 GUIDed HOBs carry the hash value of TdHobList and
Configuration FV. In DXE phase EFI_CC_EVENT can be created based on these
2 GUIDed HOBs.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
a708536dce OvmfPkg: Introduce SecMeasurementLib
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

SecMeasurementLib is designed to do the measurement in SEC phase. In
current stage there are 2 functions introduced:
 - MeasureHobList: Measure the Hoblist passed from the VMM.
 - MeasureFvImage: Measure the FV image.

SecMeasurementLibTdx is the TDX version of the library.

Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Ken Lu <ken.lu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
dc443e4437 SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUID
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass
TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will
be introduced in the following commit in this patch-sets ). In that
DXE driver this GUIDed HOB will be parsed and the TDX_DIGEST_VALUE
then will be extracted. After that a EFI_CC_EVENT will be created
based on it.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
b1567b2e15 CryptoPkg: Add SecCryptLib
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

This is the Cryptographic library instance for SEC. The motivation of
this library is to support SHA384 in SEC phase for Td guest. So only
Hash/CryptSha512.c is included which supports SHA384 and SHA512. Other
cryptographics are added with the null version, such as CryptMd5Null.c.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
72c5afd0b4 Security: Add HashLibTdx
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

This library provides hash service by registered hash handler in Td
guest. Currently only SHA384 is supported. After that the hash value is
extended to Td RTMR registers which is similar to TPM PCRs.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
2022-06-03 11:41:36 +00:00
bf25f27e00 OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
Since Cloud Hypervisor doesn't emulate an A20 gate register on I/O port
0x92, it's better to avoid accessing it when the platform is identified
as Cloud Hypervisor.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-03 10:51:26 +00:00
3129ed374c OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
Since Cloud Hypervisor doesn't support the fw_cfg mechanism, it's more
appropriate to rely on QemuFwCfgLibNull implementation of QemuFwCfgLib
since it provides a null implementation that will not issue any PIO
accesses to ports 0x510 and 0x511.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-03 10:51:26 +00:00
43f3cfce19 OvmfPkg: Check for QemuFwCfg availability before accessing it
There are few places in the codebase assuming QemuFwCfg will be present
and supported, which can cause some issues when trying to rely on the
QemuFwCfgLibNull implementation of QemuFwCfgLib.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
2022-06-03 10:51:26 +00:00
5c9f151e0c OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
The FW_BASE_ADDRESS value provided by OvmfPkgDefines.fdf.inc is
incorrect for the CloudHv target. We know the generated firmware
contains a PVH ELF header, meaning it will be loaded according to the
address provided through this header. And since we know this address
isn't going to change as it's part of CloudHvElfHeader.fdf.inc, we can
hardcode it through a new include file CloudHvDefines.fdf.inc, which
replaces the generic one OvmfPkgDefines.fdf.inc.

With this change, we prevent the firmware from accessing MMIO addresses
from the address range 0xffc00000-0xffffffff since we know the firmware
hasn't been loaded on this address range.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
2022-06-03 10:51:26 +00:00
632574ced1 OvmfPkg/Microvm/pcie: add pcie support
Link in pcie and host bridge bits.  Enables support for PCIe in microvm
(qemu-system-x86_64 -M microvm,pcie=on).

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3777
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-03 09:06:44 +00:00
bd10d4e201 OvmfPkg/Microvm/pcie: mPhysMemAddressWidth tweak
microvm places the 64bit mmio space at the end of the physical address
space.  So mPhysMemAddressWidth must be correct, otherwise the pci host
bridge setup throws an error because it thinks the 64bit mmio window is
not addressable.

On microvm we can simply use standard cpuid to figure the address width
because the host-phys-bits option (-cpu ${name},host-phys-bits=on) is
forced to be enabled.  Side note: For 'pc' and 'q35' this is not the
case for backward compatibility reasons.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-03 09:06:44 +00:00
ad3bafa7d5 OvmfPkg/Microvm/pcie: no vbeshim please
Those old windows versions which need the vbeshim hack
will not run on microvm anyway.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-03 09:06:44 +00:00
47f44097eb OvmfPkg/Platform: unfix PcdPciExpressBaseAddress
Will be set by FdtPciHostBridgeLib, so it can't be an fixed when we
want use that library.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-03 09:06:44 +00:00
b57911c84c OvmfPkg/FdtPciHostBridgeLib: io range is not mandatory
io range is not mandatory according to pcie spec,
so allow host bridges without io address space.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-03 09:06:44 +00:00
0223898f3e OvmfPkg/Microvm: drop CODE and VARS files
microvm doesn't support pflash and loads the firmware via -bios,
so we can't use the separate CODE and VARS files.  Remove them.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2022-06-03 08:14:27 +00:00
81ab97b7b9 OvmfPkg/AmdSev: remove unused SMM bits from .dsc and .fdf files
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Dov Murik <dovmurik@linux.ibm.com>
Reviewed-by: Dov Murik <dovmurik@linux.ibm.com>
2022-06-03 08:14:27 +00:00
64706ef761 OvmfPkg: Search EFI_RESOURCE_MEMORY_UNACCEPTED for Fw hoblist
In current TDVF implementation all unaccepted memory passed in Hoblist
are tagged as EFI_RESOURCE_MEMORY_UNACCEPTED. They're all accepted before
they can be accessed. After accepting memory region, the Hob ResourceType
is unchanged (still be EFI_RESOURCE_MEMORY_UNACCEPTED).

TDVF Config-B skip PEI phase and it tries to find a memory region which
is the largest one below 4GB. Then this memory region will be used as the
firmware hoblist.

So we should walk thru the input hoblist and search for the memory region
with the type of EFI_RESOURCE_MEMORY_UNACCEPTED.

Because EFI_RESOURCE_MEMORY_UNACCEPTED has not been officially in PI spec.
So it cannot be defined in MdePkg/Include/Pi/PiHob.h. As a temporary
solution it is defined in Hob.c.

There is a patch-set for lazy-accept very soon. In that patch-set
EFI_RESOURCE_MEMORY_UNACCEPTED will be defined in MdeModulePkg.

Config-B: https://edk2.groups.io/g/devel/message/76367

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-02 09:10:00 +00:00
54cd0d9b2f OvmfPkg: Fix TDVMCALL error in ApRunLoop.nasm
According to GHCI Spec Table 2-1, in TDVMCALL R10 should be cleared
to 0 in input operands, and be checked for the return result.
https://cdrdv2.intel.com/v1/dl/getContent/726790

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-02 09:10:00 +00:00
62044aa99b OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check
The SEV-ES bit of Fn800-001F[EAX] - Bit 3 is used for a host to
determine support for running SEV-ES guests. It should not be checked by
a guest to determine if it is running under SEV-ES. The guest should use
the SEV_STATUS MSR Bit 1 to determine if SEV-ES is enabled. This check
was not part of the original SEV-ES support and was added in
a91b700e38. Removing the check makes this code consistent with the
Linux kernel

Fixes: a91b700e38 ("Ovmf/ResetVector: Simplify and consolidate the SEV features checks")
Signed-off-by: Peter Gonda <pgonda@google.com>
Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
2022-06-01 12:52:34 +00:00
df1c7e91b4 IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call for X64 Calling Convention
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Ted Kuo <ted.kuo@intel.com>
2022-05-31 11:14:20 +00:00
11d8abcba2 IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2022-05-31 11:14:20 +00:00
fa2b212d61 IntelFsp2Pkg: Add FSP 2.3 header support
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921

This patch adds a couple of fields supported in FSP 2.3 header from
both header generation and tool support perspective.

Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2022-05-31 02:04:13 +00:00
3ca7326b37 OvmfPkg/VirtioGpuDxe: replace struct copy with CopyMem call
Buildfix for `-t CLANG38 -b NOOPT -p OvmfPkg/OvmfPkgX64.dsc`.

Fixes: 5f6ecaa398 ("OvmfPkg/VirtioGpuDxe: use GopQueryMode in GopSetMode")
Reported-by: Rebecca Cran <quic_rcran@quicinc.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-05-30 10:44:45 +00:00
dac2fc8146 UefiPayloadPkg: Align SpecRevision value with UPL spec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3933
URL: https://universalpayload.github.io/documentation/

1. Currently, SpecRevision on USF spec is 0.7. Change to align it.
2. SpecRevision is not be patched into UniversalPayloadInfo.bin due to
different structure item name. Change item name from "HeaderRevision"
 to "SpecRevision" to check the correct value can be patched.

Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
2022-05-27 16:15:26 +00:00
b4be5f05dd UefiPayloadPkg: Align Identifier value with UPL spec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3933

URL: https://universalpayload.github.io/documentation/
Currently, Identifier value is "UPLD", it needs to have correct value
"PLDH" based on Universal Payload Specification spec section 2.12.2

Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
2022-05-27 16:15:26 +00:00
7f0890776e MdeModulePkg/UniversalPayload: Align Identifier value with UPL spec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3933

URL: https://universalpayload.github.io/documentation/
Currently, Identifier value is "UPLD", it needs to have correct value
"PLDH" based on Universal Payload Specification spec section 2.12.2

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
2022-05-27 16:15:26 +00:00
303 changed files with 18279 additions and 3103 deletions

View File

@ -290,7 +290,7 @@ class UncrustifyCheck(ICiBuildPlugin):
# This information is only used for reporting (not used here) and # This information is only used for reporting (not used here) and
# the ignore lines are being passed directly as they are given to # the ignore lines are being passed directly as they are given to
# this plugin. # this plugin.
return parse_gitignore_lines(ignored_files, "Package configuration file", self._abs_workspace_path) return parse_gitignore_lines(ignored_files, "Package configuration file", self._abs_package_path)
def _get_git_ignored_paths(self) -> List[str]: def _get_git_ignored_paths(self) -> List[str]:
"""" """"

View File

@ -366,10 +366,9 @@ ArmGicIsInterruptEnabled (
FeaturePcdGet (PcdArmGicV3WithV2Legacy) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
SourceIsSpi (Source)) SourceIsSpi (Source))
{ {
Interrupts = ((MmioRead32 ( Interrupts = MmioRead32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset) GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
) );
& (1 << RegShift)) != 0);
} else { } else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase ( GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase, GicRedistributorBase,

View File

@ -256,12 +256,6 @@ CpuDxeInitialize (
SyncCacheConfig (&mCpu); SyncCacheConfig (&mCpu);
mIsFlushingGCD = FALSE; mIsFlushingGCD = FALSE;
// If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
if (ArmIsMpCore ()) {
PublishArmProcessorTable ();
}
// //
// Setup a callback for idle events // Setup a callback for idle events
// //

View File

@ -104,21 +104,6 @@ SyncCacheConfig (
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
); );
/**
* Publish ARM Processor Data table in UEFI SYSTEM Table.
* @param HobStart Pointer to the beginning of the HOB List from PEI.
*
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
* and a pointer is assigned to it in ARM processor table. Then the ARM processor table is
* installed in EFI configuration table.
**/
VOID
EFIAPI
PublishArmProcessorTable (
VOID
);
// The ARM Attributes might be defined on 64-bit (case of the long format description table) // The ARM Attributes might be defined on 64-bit (case of the long format description table)
UINT64 UINT64
EfiAttributeToArmAttribute ( EfiAttributeToArmAttribute (

View File

@ -21,7 +21,6 @@
[Sources.Common] [Sources.Common]
CpuDxe.c CpuDxe.c
CpuDxe.h CpuDxe.h
CpuMpCore.c
CpuMmuCommon.c CpuMmuCommon.c
Exception.c Exception.c

View File

@ -1,98 +0,0 @@
/** @file
*
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Guid/ArmMpCoreInfo.h>
ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
{
EFI_ARM_PROCESSOR_TABLE_SIGNATURE,
0,
EFI_ARM_PROCESSOR_TABLE_REVISION,
EFI_ARM_PROCESSOR_TABLE_OEM_ID,
EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID,
EFI_ARM_PROCESSOR_TABLE_OEM_REVISION,
EFI_ARM_PROCESSOR_TABLE_CREATOR_ID,
EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,
{ 0 },
0
}, // ARM Processor table header
0, // Number of entries in ARM processor Table
NULL // ARM Processor Table
};
/** Publish ARM Processor Data table in UEFI SYSTEM Table.
* @param HobStart Pointer to the beginning of the HOB List from PEI.
*
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
* and a pointer is assigned to it in ARM processor table. Then the ARM processor table is
* installed in EFI configuration table.
**/
VOID
EFIAPI
PublishArmProcessorTable (
VOID
)
{
EFI_PEI_HOB_POINTERS Hob;
Hob.Raw = GetHobList ();
// Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
for ( ; !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {
// Check for Correct HOB type
if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
// Check for correct GUID type
if (CompareGuid (&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
ARM_PROCESSOR_TABLE *ArmProcessorTable;
EFI_STATUS Status;
// Allocate Runtime memory for ARM processor table
ArmProcessorTable = (ARM_PROCESSOR_TABLE *)AllocateRuntimePool (sizeof (ARM_PROCESSOR_TABLE));
// Check if the memory allocation is successful or not
ASSERT (NULL != ArmProcessorTable);
// Set ARM processor table to default values
CopyMem (ArmProcessorTable, &mArmProcessorTableTemplate, sizeof (ARM_PROCESSOR_TABLE));
// Fill in Length fields of ARM processor table
ArmProcessorTable->Header.Length = sizeof (ARM_PROCESSOR_TABLE);
ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE (Hob);
// Fill in Identifier(ARM processor table GUID)
ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;
// Set Number of ARM core entries in the Table
ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE (Hob)/sizeof (ARM_CORE_INFO);
// Allocate runtime memory for ARM processor Table entries
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO *)AllocateRuntimePool (
ArmProcessorTable->NumberOfEntries * sizeof (ARM_CORE_INFO)
);
// Check if the memory allocation is successful or not
ASSERT (NULL != ArmProcessorTable->ArmCpus);
// Copy ARM Processor Table data from HOB list to newly allocated memory
CopyMem (ArmProcessorTable->ArmCpus, GET_GUID_HOB_DATA (Hob), ArmProcessorTable->Header.DataLen);
// Install the ARM Processor table into EFI system configuration table
Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);
ASSERT_EFI_ERROR (Status);
}
}
}
}

View File

@ -23,36 +23,9 @@ typedef struct {
UINT64 MailboxClearValue; UINT64 MailboxClearValue;
} ARM_CORE_INFO; } ARM_CORE_INFO;
typedef struct {
UINT64 Signature;
UINT32 Length;
UINT32 Revision;
UINT64 OemId;
UINT64 OemTableId;
UINTN OemRevision;
UINTN CreatorId;
UINTN CreatorRevision;
EFI_GUID Identifier;
UINTN DataLen;
} ARM_PROCESSOR_TABLE_HEADER;
typedef struct {
ARM_PROCESSOR_TABLE_HEADER Header;
UINTN NumberOfEntries;
ARM_CORE_INFO *ArmCpus;
} ARM_PROCESSOR_TABLE;
#define ARM_MP_CORE_INFO_GUID \ #define ARM_MP_CORE_INFO_GUID \
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0
#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
extern EFI_GUID gArmMpCoreInfoGuid; extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* ARM_MP_CORE_INFO_GUID_H_ */ #endif /* ARM_MP_CORE_INFO_GUID_H_ */

View File

@ -4,6 +4,7 @@
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> * Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR> * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
* Copyright (c) 2016 HP Development Company, L.P. * Copyright (c) 2016 HP Development Company, L.P.
* Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
* *
* SPDX-License-Identifier: BSD-2-Clause-Patent * SPDX-License-Identifier: BSD-2-Clause-Patent
* *
@ -194,32 +195,6 @@ CopyExceptionHandlers (
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
@param[in] VectorInfo Pointer to reserved vector list.
@retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
with default interrupt/exception handlers.
@retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
@retval EFI_UNSUPPORTED This function is not supported.
**/
EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
// not needed, this is what the CPU driver is for
return EFI_UNSUPPORTED;
}
/** /**
Registers a function to be called from the processor exception handler. (On ARM/AArch64 this only Registers a function to be called from the processor exception handler. (On ARM/AArch64 this only
provides exception handlers, not interrupt handling which is provided through the Hardware Interrupt provides exception handlers, not interrupt handling which is provided through the Hardware Interrupt
@ -229,8 +204,8 @@ This function registers and enables the handler specified by ExceptionHandler fo
interrupt or exception type specified by ExceptionType. If ExceptionHandler is NULL, then the interrupt or exception type specified by ExceptionType. If ExceptionHandler is NULL, then the
handler for the processor interrupt or exception type specified by ExceptionType is uninstalled. handler for the processor interrupt or exception type specified by ExceptionType is uninstalled.
The installed handler is called once for each processor interrupt or exception. The installed handler is called once for each processor interrupt or exception.
NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or NOTE: This function should be invoked after InitializeCpuExceptionHandlers() is invoked,
InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned. otherwise EFI_UNSUPPORTED returned.
@param[in] ExceptionType Defines which interrupt or exception to hook. @param[in] ExceptionType Defines which interrupt or exception to hook.
@param[in] ExceptionHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called @param[in] ExceptionHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
@ -312,33 +287,25 @@ CommonCExceptionHandler (
} }
/** /**
Initializes all CPU exceptions entries with optional extra initializations. Setup separate stacks for certain exception handlers.
If the input Buffer and BufferSize are both NULL, use global variable if possible.
By default, this method should include all functionalities implemented by @param[in] Buffer Point to buffer used to separate exception stack.
InitializeCpuExceptionHandlers(), plus extra initialization works, if any. @param[in, out] BufferSize On input, it indicates the byte size of Buffer.
This could be done by calling InitializeCpuExceptionHandlers() directly If the size is not enough, the return status will
in this method besides the extra works. be EFI_BUFFER_TOO_SMALL, and output BufferSize
will be the size it needs.
InitData is optional and its use and content are processor arch dependent.
The typical usage of it is to convey resources which have to be reserved
elsewhere and are necessary for the extra initializations of exception.
@param[in] VectorInfo Pointer to reserved vector list.
@param[in] InitData Pointer to data optional for extra initializations
of exception.
@retval EFI_SUCCESS The exceptions have been successfully
initialized.
@retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid
content.
@retval EFI_SUCCESS The stacks are assigned successfully.
@retval EFI_UNSUPPORTED This function is not supported.
@retval EFI_BUFFER_TOO_SMALL This BufferSize is too small.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeSeparateExceptionStacks (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN VOID *Buffer,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN OUT UINTN *BufferSize
) )
{ {
return InitializeCpuExceptionHandlers (VectorInfo); return EFI_SUCCESS;
} }

View File

@ -94,6 +94,7 @@
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032
gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|0x00000000|UINT32|0x00000041
## PL061 GPIO ## PL061 GPIO
gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025

View File

@ -815,18 +815,6 @@ LcdGraphicsBlt (
HorizontalResolution = This->Mode->Info->HorizontalResolution; HorizontalResolution = This->Mode->Info->HorizontalResolution;
VerticalResolution = This->Mode->Info->VerticalResolution; VerticalResolution = This->Mode->Info->VerticalResolution;
DEBUG ((
DEBUG_INFO,
"LcdGraphicsBlt (BltOperation:%d,DestX:%d,DestY:%d,Width:%d,Height:%d) res(%d,%d)\n",
BltOperation,
DestinationX,
DestinationY,
Width,
Height,
HorizontalResolution,
VerticalResolution
));
// Check we have reasonable parameters // Check we have reasonable parameters
if ((Width == 0) || (Height == 0)) { if ((Width == 0) || (Height == 0)) {
DEBUG ((DEBUG_ERROR, "LcdGraphicsBlt: ERROR - Invalid dimension: Zero size area.\n")); DEBUG ((DEBUG_ERROR, "LcdGraphicsBlt: ERROR - Invalid dimension: Zero size area.\n"));

View File

@ -144,6 +144,7 @@
PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf
PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf
PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf
DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf
# USB Libraries # USB Libraries
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
@ -169,6 +170,7 @@
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf
PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf
# re-use the UserPhysicalPresent() dummy implementation from the ovmf tree # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf

View File

@ -81,6 +81,7 @@
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf
PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf
!if $(TPM2_ENABLE) == TRUE !if $(TPM2_ENABLE) == TRUE
Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf

View File

@ -128,7 +128,7 @@ EDKII_PLATFORM_REPOSITORY_INFO mKvmtoolPlatRepositoryInfo = {
// //
{ {
EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE, EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
EFI_ACPI_IO_REMAPPING_TABLE_REVISION, EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
NULL NULL
}, },

View File

@ -17,4 +17,5 @@ Source/C/VfrCompile/VfrTokens.h
Source/C/bin/ Source/C/bin/
Source/C/libs/ Source/C/libs/
Bin/Win32 Bin/Win32
Lib Lib
BaseToolsBuild/

View File

@ -16,10 +16,12 @@ include $(MAKEROOT)/Makefiles/app.makefile
GCCVERSION = $(shell gcc -dumpversion | awk -F'.' '{print $$1}') GCCVERSION = $(shell gcc -dumpversion | awk -F'.' '{print $$1}')
ifneq ("$(GCCVERSION)", "5") ifneq ("$(GCCVERSION)", "5")
ifneq ($(CXX), llvm) ifneq ($(CXX), llvm)
ifneq ($(DARWIN),Darwin)
# gcc 12 trips over device path handling # gcc 12 trips over device path handling
BUILD_CFLAGS += -Wno-error=stringop-overflow BUILD_CFLAGS += -Wno-error=stringop-overflow
endif endif
endif endif
endif
LIBS = -lCommon LIBS = -lCommon
ifeq ($(CYGWIN), CYGWIN) ifeq ($(CYGWIN), CYGWIN)

View File

@ -2,7 +2,7 @@
Elf64 convert solution Elf64 convert solution
Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR> Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -186,8 +186,8 @@ InitializeElf64 (
} }
if (mExportFlag) { if (mExportFlag) {
if (mEhdr->e_machine != EM_X86_64) { if ((mEhdr->e_machine != EM_X86_64) && (mEhdr->e_machine != EM_AARCH64)) {
Error (NULL, 0, 3000, "Unsupported", "--prm option currently only supports X64 arch."); Error (NULL, 0, 3000, "Unsupported", "--prm option currently only supports X64 and AArch64 archs.");
return FALSE; return FALSE;
} }
} }

View File

@ -191,7 +191,7 @@ Returns:
as 0, tool get alignment value from SectionFile. It is\n\ as 0, tool get alignment value from SectionFile. It is\n\
specified in same order that the section file is input.\n"); specified in same order that the section file is input.\n");
fprintf (stdout, " --dummy dummyfile\n\ fprintf (stdout, " --dummy dummyfile\n\
compare dummpyfile with input_file to decide whether\n\ compare dummyfile with input_file to decide whether\n\
need to set PROCESSING_REQUIRED attribute.\n"); need to set PROCESSING_REQUIRED attribute.\n");
fprintf (stdout, " -v, --verbose Turn on verbose output with informational messages.\n"); fprintf (stdout, " -v, --verbose Turn on verbose output with informational messages.\n");
fprintf (stdout, " -q, --quiet Disable all messages except key message and fatal error\n"); fprintf (stdout, " -q, --quiet Disable all messages except key message and fatal error\n");
@ -988,6 +988,155 @@ Returns:
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_STATUS
GenSectionSubtypeGuidSection (
CHAR8 **InputFileName,
UINT32 *InputFileAlign,
UINT32 InputFileNum,
EFI_GUID *SubTypeGuid,
UINT8 **OutFileBuffer
)
/*++
Routine Description:
Generate a section of type EFI_SECTION_FREEFORM_SUBTYPE_GUID
The function won't validate the input file contents.
The utility will add section header to the file.
Arguments:
InputFileName - Name of the input file.
InputFileAlign - Alignment required by the input file data.
InputFileNum - Number of input files. Should be 1 for this section.
SubTypeGuid - Specify vendor guid value.
OutFileBuffer - Buffer pointer to Output file contents
Returns:
EFI_SUCCESS on successful return
EFI_INVALID_PARAMETER if InputFileNum is less than 1
EFI_ABORTED if unable to open input file.
EFI_OUT_OF_RESOURCES No resource to complete the operation.
--*/
{
UINT32 TotalLength;
UINT32 InputLength;
UINT32 Offset;
UINT8 *FileBuffer;
EFI_STATUS Status;
EFI_FREEFORM_SUBTYPE_GUID_SECTION *SubtypeGuidSect;
EFI_FREEFORM_SUBTYPE_GUID_SECTION2 *SubtypeGuidSect2;
InputLength = 0;
Offset = 0;
FileBuffer = NULL;
TotalLength = 0;
if (InputFileNum > 1) {
Error (NULL, 0, 2000, "Invalid parameter", "more than one input file specified");
return STATUS_ERROR;
} else if (InputFileNum < 1) {
Error (NULL, 0, 2000, "Invalid parameter", "no input file specified");
return STATUS_ERROR;
}
//
// read all input file contents into a buffer
// first get the size of all file contents
//
Status = GetSectionContents (
InputFileName,
InputFileAlign,
InputFileNum,
FileBuffer,
&InputLength
);
if (Status == EFI_BUFFER_TOO_SMALL) {
Offset = sizeof (EFI_FREEFORM_SUBTYPE_GUID_SECTION);
if (InputLength + Offset >= MAX_SECTION_SIZE) {
Offset = sizeof (EFI_FREEFORM_SUBTYPE_GUID_SECTION2);
}
TotalLength = InputLength + Offset;
FileBuffer = (UINT8 *) malloc (InputLength + Offset);
if (FileBuffer == NULL) {
Error (NULL, 0, 4001, "Resource", "memory cannot be allocated");
return EFI_OUT_OF_RESOURCES;
}
//
// read all input file contents into a buffer
//
Status = GetSectionContents (
InputFileName,
InputFileAlign,
InputFileNum,
FileBuffer + Offset,
&InputLength
);
}
if (EFI_ERROR (Status)) {
if (FileBuffer != NULL) {
free (FileBuffer);
}
Error (NULL, 0, 0001, "Error opening file for reading", InputFileName[0]);
return Status;
}
if (InputLength == 0) {
if (FileBuffer != NULL) {
free (FileBuffer);
}
Error (NULL, 0, 2000, "Invalid parameter", "the size of input file %s can't be zero", InputFileName);
return EFI_NOT_FOUND;
}
//
// InputLength != 0, but FileBuffer == NULL means out of resources.
//
if (FileBuffer == NULL) {
Error (NULL, 0, 4001, "Resource", "memory cannot be allocated");
return EFI_OUT_OF_RESOURCES;
}
//
// Now data is in FileBuffer + Offset
//
if (TotalLength >= MAX_SECTION_SIZE) {
SubtypeGuidSect2 = (EFI_FREEFORM_SUBTYPE_GUID_SECTION2 *) FileBuffer;
SubtypeGuidSect2->CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID;
SubtypeGuidSect2->CommonHeader.Size[0] = (UINT8) 0xff;
SubtypeGuidSect2->CommonHeader.Size[1] = (UINT8) 0xff;
SubtypeGuidSect2->CommonHeader.Size[2] = (UINT8) 0xff;
SubtypeGuidSect2->CommonHeader.ExtendedSize = InputLength + sizeof (EFI_FREEFORM_SUBTYPE_GUID_SECTION2);
memcpy (&(SubtypeGuidSect2->SubTypeGuid), SubTypeGuid, sizeof (EFI_GUID));
} else {
SubtypeGuidSect = (EFI_FREEFORM_SUBTYPE_GUID_SECTION *) FileBuffer;
SubtypeGuidSect->CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID;
SubtypeGuidSect->CommonHeader.Size[0] = (UINT8) (TotalLength & 0xff);
SubtypeGuidSect->CommonHeader.Size[1] = (UINT8) ((TotalLength & 0xff00) >> 8);
SubtypeGuidSect->CommonHeader.Size[2] = (UINT8) ((TotalLength & 0xff0000) >> 16);
memcpy (&(SubtypeGuidSect->SubTypeGuid), SubTypeGuid, sizeof (EFI_GUID));
}
VerboseMsg ("the size of the created section file is %u bytes", (unsigned) TotalLength);
//
// Set OutFileBuffer
//
*OutFileBuffer = FileBuffer;
return EFI_SUCCESS;
}
EFI_STATUS EFI_STATUS
FfsRebaseImageRead ( FfsRebaseImageRead (
IN VOID *FileHandle, IN VOID *FileHandle,
@ -1591,14 +1740,22 @@ Returns:
} }
// //
// GuidValue is only required by Guided section. // GuidValue is only required by Guided section and SubtypeGuid section.
// //
if ((SectType != EFI_SECTION_GUID_DEFINED) && if ((SectType != EFI_SECTION_GUID_DEFINED) && (SectType != EFI_SECTION_FREEFORM_SUBTYPE_GUID) &&
(SectionName != NULL) && (SectionName != NULL) &&
(CompareGuid (&VendorGuid, &mZeroGuid) != 0)) { (CompareGuid (&VendorGuid, &mZeroGuid) != 0)) {
fprintf (stdout, "Warning: the input guid value is not required for this section type %s\n", SectionName); fprintf (stdout, "Warning: the input guid value is not required for this section type %s\n", SectionName);
} }
//
// Check whether there is GUID for the SubtypeGuid section
//
if ((SectType == EFI_SECTION_FREEFORM_SUBTYPE_GUID) && (CompareGuid (&VendorGuid, &mZeroGuid) == 0)) {
Error (NULL, 0, 1001, "Missing options", "GUID");
goto Finish;
}
// //
// Check whether there is input file // Check whether there is input file
// //
@ -1667,6 +1824,16 @@ Returns:
); );
break; break;
case EFI_SECTION_FREEFORM_SUBTYPE_GUID:
Status = GenSectionSubtypeGuidSection (
InputFileName,
InputFileAlign,
InputFileNum,
&VendorGuid,
&OutFileBuffer
);
break;
case EFI_SECTION_VERSION: case EFI_SECTION_VERSION:
Index = sizeof (EFI_COMMON_SECTION_HEADER); Index = sizeof (EFI_COMMON_SECTION_HEADER);
// //

View File

@ -911,140 +911,134 @@ Returns:
printf (" EFI_FVB2_WRITE_LOCK_STATUS\n"); printf (" EFI_FVB2_WRITE_LOCK_STATUS\n");
} }
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_1) { switch (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT) {
case EFI_FVB2_ALIGNMENT_1:
printf (" EFI_FVB2_ALIGNMENT_1\n"); printf (" EFI_FVB2_ALIGNMENT_1\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_2) { case EFI_FVB2_ALIGNMENT_2:
printf (" EFI_FVB2_ALIGNMENT_2\n"); printf (" EFI_FVB2_ALIGNMENT_2\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_4) { case EFI_FVB2_ALIGNMENT_4:
printf (" EFI_FVB2_ALIGNMENT_4\n"); printf (" EFI_FVB2_ALIGNMENT_4\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_8) { case EFI_FVB2_ALIGNMENT_8:
printf (" EFI_FVB2_ALIGNMENT_8\n"); printf (" EFI_FVB2_ALIGNMENT_8\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_16) { case EFI_FVB2_ALIGNMENT_16:
printf (" EFI_FVB2_ALIGNMENT_16\n"); printf (" EFI_FVB2_ALIGNMENT_16\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_32) { case EFI_FVB2_ALIGNMENT_32:
printf (" EFI_FVB2_ALIGNMENT_32\n"); printf (" EFI_FVB2_ALIGNMENT_32\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_64) { case EFI_FVB2_ALIGNMENT_64:
printf (" EFI_FVB2_ALIGNMENT_64\n"); printf (" EFI_FVB2_ALIGNMENT_64\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_128) { case EFI_FVB2_ALIGNMENT_128:
printf (" EFI_FVB2_ALIGNMENT_128\n"); printf (" EFI_FVB2_ALIGNMENT_128\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_256) { case EFI_FVB2_ALIGNMENT_256:
printf (" EFI_FVB2_ALIGNMENT_256\n"); printf (" EFI_FVB2_ALIGNMENT_256\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_512) { case EFI_FVB2_ALIGNMENT_512:
printf (" EFI_FVB2_ALIGNMENT_512\n"); printf (" EFI_FVB2_ALIGNMENT_512\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_1K) { case EFI_FVB2_ALIGNMENT_1K:
printf (" EFI_FVB2_ALIGNMENT_1K\n"); printf (" EFI_FVB2_ALIGNMENT_1K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_2K) { case EFI_FVB2_ALIGNMENT_2K:
printf (" EFI_FVB2_ALIGNMENT_2K\n"); printf (" EFI_FVB2_ALIGNMENT_2K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_4K) { case EFI_FVB2_ALIGNMENT_4K:
printf (" EFI_FVB2_ALIGNMENT_4K\n"); printf (" EFI_FVB2_ALIGNMENT_4K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_8K) { case EFI_FVB2_ALIGNMENT_8K:
printf (" EFI_FVB2_ALIGNMENT_8K\n"); printf (" EFI_FVB2_ALIGNMENT_8K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_16K) { case EFI_FVB2_ALIGNMENT_16K:
printf (" EFI_FVB2_ALIGNMENT_16K\n"); printf (" EFI_FVB2_ALIGNMENT_16K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_32K) { case EFI_FVB2_ALIGNMENT_32K:
printf (" EFI_FVB2_ALIGNMENT_32K\n"); printf (" EFI_FVB2_ALIGNMENT_32K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_64K) { case EFI_FVB2_ALIGNMENT_64K:
printf (" EFI_FVB2_ALIGNMENT_64K\n"); printf (" EFI_FVB2_ALIGNMENT_64K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_128K) { case EFI_FVB2_ALIGNMENT_128K:
printf (" EFI_FVB2_ALIGNMENT_128K\n"); printf (" EFI_FVB2_ALIGNMENT_128K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_256K) { case EFI_FVB2_ALIGNMENT_256K:
printf (" EFI_FVB2_ALIGNMENT_256K\n"); printf (" EFI_FVB2_ALIGNMENT_256K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_512K) { case EFI_FVB2_ALIGNMENT_512K:
printf (" EFI_FVB2_ALIGNMENT_512K\n"); printf (" EFI_FVB2_ALIGNMENT_512K\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_1M) { case EFI_FVB2_ALIGNMENT_1M:
printf (" EFI_FVB2_ALIGNMENT_1M\n"); printf (" EFI_FVB2_ALIGNMENT_1M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_2M) { case EFI_FVB2_ALIGNMENT_2M:
printf (" EFI_FVB2_ALIGNMENT_2M\n"); printf (" EFI_FVB2_ALIGNMENT_2M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_4M) { case EFI_FVB2_ALIGNMENT_4M:
printf (" EFI_FVB2_ALIGNMENT_4M\n"); printf (" EFI_FVB2_ALIGNMENT_4M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_8M) { case EFI_FVB2_ALIGNMENT_8M:
printf (" EFI_FVB2_ALIGNMENT_8M\n"); printf (" EFI_FVB2_ALIGNMENT_8M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_16M) { case EFI_FVB2_ALIGNMENT_16M:
printf (" EFI_FVB2_ALIGNMENT_16M\n"); printf (" EFI_FVB2_ALIGNMENT_16M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_32M) { case EFI_FVB2_ALIGNMENT_32M:
printf (" EFI_FVB2_ALIGNMENT_32M\n"); printf (" EFI_FVB2_ALIGNMENT_32M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_64M) { case EFI_FVB2_ALIGNMENT_64M:
printf (" EFI_FVB2_ALIGNMENT_64M\n"); printf (" EFI_FVB2_ALIGNMENT_64M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_128M) { case EFI_FVB2_ALIGNMENT_128M:
printf (" EFI_FVB2_ALIGNMENT_128M\n"); printf (" EFI_FVB2_ALIGNMENT_128M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_64M) { case EFI_FVB2_ALIGNMENT_256M:
printf (" EFI_FVB2_ALIGNMENT_64M\n"); printf (" EFI_FVB2_ALIGNMENT_256M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_128M) { case EFI_FVB2_ALIGNMENT_512M:
printf (" EFI_FVB2_ALIGNMENT_128M\n"); printf (" EFI_FVB2_ALIGNMENT_512M\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_256M) { case EFI_FVB2_ALIGNMENT_1G:
printf (" EFI_FVB2_ALIGNMENT_256M\n"); printf (" EFI_FVB2_ALIGNMENT_1G\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_512M) { case EFI_FVB2_ALIGNMENT_2G:
printf (" EFI_FVB2_ALIGNMENT_512M\n"); printf (" EFI_FVB2_ALIGNMENT_2G\n");
} break;
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_1G) {
printf (" EFI_FVB2_ALIGNMENT_1G\n");
}
if (VolumeHeader.Attributes & EFI_FVB2_ALIGNMENT_2G) {
printf (" EFI_FVB2_ALIGNMENT_2G\n");
} }
#endif #endif
@ -1682,6 +1676,7 @@ Returns:
CHAR8 *ToolInputFileName; CHAR8 *ToolInputFileName;
CHAR8 *ToolOutputFileName; CHAR8 *ToolOutputFileName;
CHAR8 *UIFileName; CHAR8 *UIFileName;
CHAR8 *VersionString;
ParsedLength = 0; ParsedLength = 0;
ToolInputFileName = NULL; ToolInputFileName = NULL;
@ -1801,20 +1796,30 @@ Returns:
break; break;
case EFI_SECTION_FIRMWARE_VOLUME_IMAGE: case EFI_SECTION_FIRMWARE_VOLUME_IMAGE:
printf ("/------------ Firmware Volume section start ---------------\\\n");
Status = PrintFvInfo (Ptr + SectionHeaderLen, TRUE); Status = PrintFvInfo (Ptr + SectionHeaderLen, TRUE);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Error (NULL, 0, 0003, "printing of FV section contents failed", NULL); Error (NULL, 0, 0003, "printing of FV section contents failed", NULL);
return EFI_SECTION_ERROR; return EFI_SECTION_ERROR;
} }
printf ("\\------------ Firmware Volume section end -----------------/\n");
break; break;
case EFI_SECTION_COMPATIBILITY16: case EFI_SECTION_COMPATIBILITY16:
case EFI_SECTION_FREEFORM_SUBTYPE_GUID:
// //
// Section does not contain any further header information. // Section does not contain any further header information.
// //
break; break;
case EFI_SECTION_FREEFORM_SUBTYPE_GUID:
printf (" Guid: ");
if (SectionHeaderLen == sizeof (EFI_COMMON_SECTION_HEADER))
PrintGuid (&((EFI_FREEFORM_SUBTYPE_GUID_SECTION *)Ptr)->SubTypeGuid);
else
PrintGuid (&((EFI_FREEFORM_SUBTYPE_GUID_SECTION2 *)Ptr)->SubTypeGuid);
printf ("\n");
break;
case EFI_SECTION_PEI_DEPEX: case EFI_SECTION_PEI_DEPEX:
case EFI_SECTION_DXE_DEPEX: case EFI_SECTION_DXE_DEPEX:
case EFI_SECTION_SMM_DEPEX: case EFI_SECTION_SMM_DEPEX:
@ -1822,8 +1827,14 @@ Returns:
break; break;
case EFI_SECTION_VERSION: case EFI_SECTION_VERSION:
printf (" Build Number: 0x%02X\n", *(UINT16 *)(Ptr + SectionHeaderLen)); printf (" Build Number: 0x%04X\n", *(UINT16 *)(Ptr + SectionHeaderLen));
printf (" Version Strg: %s\n", (char*) (Ptr + SectionHeaderLen + sizeof (UINT16))); VersionString = (CHAR8 *) malloc (UnicodeStrLen (((EFI_VERSION_SECTION *) Ptr)->VersionString) + 1);
if (VersionString == NULL) {
Error (NULL, 0, 4001, "Resource", "memory cannot be allocated!");
return EFI_OUT_OF_RESOURCES;
}
Unicode2AsciiString (((EFI_VERSION_SECTION *) Ptr)->VersionString, VersionString);
printf (" Version String: %s\n", VersionString);
break; break;
case EFI_SECTION_COMPRESSION: case EFI_SECTION_COMPRESSION:
@ -1902,7 +1913,9 @@ Returns:
return EFI_SECTION_ERROR; return EFI_SECTION_ERROR;
} }
printf ("/------------ Encapsulation section start -----------------\\\n");
Status = ParseSection (UncompressedBuffer, UncompressedLength); Status = ParseSection (UncompressedBuffer, UncompressedLength);
printf ("\\------------ Encapsulation section end -------------------/\n");
if (CompressionType == EFI_STANDARD_COMPRESSION) { if (CompressionType == EFI_STANDARD_COMPRESSION) {
// //
@ -2021,6 +2034,7 @@ Returns:
return EFI_SECTION_ERROR; return EFI_SECTION_ERROR;
} }
printf ("/------------ Encapsulation section start -----------------\\\n");
Status = ParseSection ( Status = ParseSection (
ToolOutputBuffer, ToolOutputBuffer,
ToolOutputLength ToolOutputLength
@ -2029,6 +2043,7 @@ Returns:
Error (NULL, 0, 0003, "parse of decoded GUIDED section failed", NULL); Error (NULL, 0, 0003, "parse of decoded GUIDED section failed", NULL);
return EFI_SECTION_ERROR; return EFI_SECTION_ERROR;
} }
printf ("\\------------ Encapsulation section end -------------------/\n");
// //
// Check for CRC32 sections which we can handle internally if needed. // Check for CRC32 sections which we can handle internally if needed.
@ -2041,6 +2056,7 @@ Returns:
// //
// CRC32 guided section // CRC32 guided section
// //
printf ("/------------ Encapsulation section start -----------------\\\n");
Status = ParseSection ( Status = ParseSection (
SectionBuffer + DataOffset, SectionBuffer + DataOffset,
BufferLength - DataOffset BufferLength - DataOffset
@ -2049,6 +2065,7 @@ Returns:
Error (NULL, 0, 0003, "parse of CRC32 GUIDED section failed", NULL); Error (NULL, 0, 0003, "parse of CRC32 GUIDED section failed", NULL);
return EFI_SECTION_ERROR; return EFI_SECTION_ERROR;
} }
printf ("\\------------ Encapsulation section end -------------------/\n");
} else { } else {
// //
// We don't know how to parse it now. // We don't know how to parse it now.

View File

@ -22,8 +22,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EFI_DEP_END 0x08 #define EFI_DEP_END 0x08
#define EFI_DEP_SOR 0x09 #define EFI_DEP_SOR 0x09
#define EFI_SECTION_LAST_LEAF_SECTION_TYPE 0x1B #define EFI_SECTION_LAST_LEAF_SECTION_TYPE 0x1C
#define EFI_SECTION_LAST_SECTION_TYPE 0x1B #define EFI_SECTION_LAST_SECTION_TYPE 0x1C
#define OPENSSL_COMMAND_FORMAT_STRING "%s sha1 -out %s %s" #define OPENSSL_COMMAND_FORMAT_STRING "%s sha1 -out %s %s"
#define EXTRACT_COMMAND_FORMAT_STRING "%s -d -o %s %s" #define EXTRACT_COMMAND_FORMAT_STRING "%s -d -o %s %s"

View File

@ -120,7 +120,7 @@ class BuildFile(object):
}, },
POSIX_PLATFORM : { POSIX_PLATFORM : {
"CP" : "cp -f", "CP" : "cp -p -f",
"MV" : "mv -f", "MV" : "mv -f",
"RM" : "rm -f", "RM" : "rm -f",
"MD" : "mkdir -p", "MD" : "mkdir -p",
@ -1110,7 +1110,8 @@ cleanlib:
CmdTargetDict[CmdSign].append(SingleCommandList[-1]) CmdTargetDict[CmdSign].append(SingleCommandList[-1])
Index = CommandList.index(Item) Index = CommandList.index(Item)
CommandList.pop(Index) CommandList.pop(Index)
if SingleCommandList[-1].endswith("%s%s.c" % (TAB_SLASH, CmdSumDict[CmdSign[3:].rsplit(TAB_SLASH, 1)[0]])): BaseName = SingleCommandList[-1].rsplit('.',1)[0]
if BaseName.endswith("%s%s" % (TAB_SLASH, CmdSumDict[CmdSign[3:].rsplit(TAB_SLASH, 1)[0]])):
Cpplist = CmdCppDict[T.Target.SubDir] Cpplist = CmdCppDict[T.Target.SubDir]
Cpplist.insert(0, '$(OBJLIST_%d): ' % list(self.ObjTargetDict.keys()).index(T.Target.SubDir)) Cpplist.insert(0, '$(OBJLIST_%d): ' % list(self.ObjTargetDict.keys()).index(T.Target.SubDir))
source_files = CmdTargetDict[CmdSign][1:] source_files = CmdTargetDict[CmdSign][1:]

View File

@ -10,7 +10,7 @@
# keep the tool as simple as possible, it has the following limitations: # keep the tool as simple as possible, it has the following limitations:
# * Do not support vendor code bytes in a capsule. # * Do not support vendor code bytes in a capsule.
# #
# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2018 - 2022, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@ -38,11 +38,11 @@ from Common.Edk2.Capsule.FmpPayloadHeader import FmpPayloadHeaderClass
# Globals for help information # Globals for help information
# #
__prog__ = 'GenerateCapsule' __prog__ = 'GenerateCapsule'
__version__ = '0.9' __version__ = '0.10'
__copyright__ = 'Copyright (c) 2018, Intel Corporation. All rights reserved.' __copyright__ = 'Copyright (c) 2022, Intel Corporation. All rights reserved.'
__description__ = 'Generate a capsule.\n' __description__ = 'Generate a capsule.\n'
def SignPayloadSignTool (Payload, ToolPath, PfxFile, Verbose = False): def SignPayloadSignTool (Payload, ToolPath, PfxFile, SubjectName, Verbose = False):
# #
# Create a temporary directory # Create a temporary directory
# #
@ -72,7 +72,10 @@ def SignPayloadSignTool (Payload, ToolPath, PfxFile, Verbose = False):
Command = Command + '"{Path}" '.format (Path = os.path.join (ToolPath, 'signtool.exe')) Command = Command + '"{Path}" '.format (Path = os.path.join (ToolPath, 'signtool.exe'))
Command = Command + 'sign /fd sha256 /p7ce DetachedSignedData /p7co 1.2.840.113549.1.7.2 ' Command = Command + 'sign /fd sha256 /p7ce DetachedSignedData /p7co 1.2.840.113549.1.7.2 '
Command = Command + '/p7 {TempDir} '.format (TempDir = TempDirectoryName) Command = Command + '/p7 {TempDir} '.format (TempDir = TempDirectoryName)
Command = Command + '/f {PfxFile} '.format (PfxFile = PfxFile) if PfxFile is not None:
Command = Command + '/f {PfxFile} '.format (PfxFile = PfxFile)
if SubjectName is not None:
Command = Command + '/n {SubjectName} '.format (SubjectName = SubjectName)
Command = Command + TempFileName Command = Command + TempFileName
if Verbose: if Verbose:
print (Command) print (Command)
@ -105,7 +108,7 @@ def SignPayloadSignTool (Payload, ToolPath, PfxFile, Verbose = False):
shutil.rmtree (TempDirectoryName) shutil.rmtree (TempDirectoryName)
return Signature return Signature
def VerifyPayloadSignTool (Payload, CertData, ToolPath, PfxFile, Verbose = False): def VerifyPayloadSignTool (Payload, CertData, ToolPath, PfxFile, SubjectName, Verbose = False):
print ('signtool verify is not supported.') print ('signtool verify is not supported.')
raise ValueError ('GenerateCapsule: error: signtool verify is not supported.') raise ValueError ('GenerateCapsule: error: signtool verify is not supported.')
@ -249,6 +252,7 @@ if __name__ == '__main__':
HardwareInstance = ConvertJsonValue (Config, 'HardwareInstance', ValidateUnsignedInteger, Required = False, Default = 0) HardwareInstance = ConvertJsonValue (Config, 'HardwareInstance', ValidateUnsignedInteger, Required = False, Default = 0)
MonotonicCount = ConvertJsonValue (Config, 'MonotonicCount', ValidateUnsignedInteger, Required = False, Default = 0) MonotonicCount = ConvertJsonValue (Config, 'MonotonicCount', ValidateUnsignedInteger, Required = False, Default = 0)
SignToolPfxFile = ConvertJsonValue (Config, 'SignToolPfxFile', os.path.expandvars, Required = False, Default = None, Open = True) SignToolPfxFile = ConvertJsonValue (Config, 'SignToolPfxFile', os.path.expandvars, Required = False, Default = None, Open = True)
SignToolSubjectName = ConvertJsonValue (Config, 'SignToolSubjectName', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslSignerPrivateCertFile = ConvertJsonValue (Config, 'OpenSslSignerPrivateCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslSignerPrivateCertFile = ConvertJsonValue (Config, 'OpenSslSignerPrivateCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslOtherPublicCertFile = ConvertJsonValue (Config, 'OpenSslOtherPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslOtherPublicCertFile = ConvertJsonValue (Config, 'OpenSslOtherPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslTrustedPublicCertFile = ConvertJsonValue (Config, 'OpenSslTrustedPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslTrustedPublicCertFile = ConvertJsonValue (Config, 'OpenSslTrustedPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
@ -264,6 +268,7 @@ if __name__ == '__main__':
HardwareInstance, HardwareInstance,
UpdateImageIndex, UpdateImageIndex,
SignToolPfxFile, SignToolPfxFile,
SignToolSubjectName,
OpenSslSignerPrivateCertFile, OpenSslSignerPrivateCertFile,
OpenSslOtherPublicCertFile, OpenSslOtherPublicCertFile,
OpenSslTrustedPublicCertFile, OpenSslTrustedPublicCertFile,
@ -303,6 +308,7 @@ if __name__ == '__main__':
UpdateImageIndex = ConvertJsonValue (Config, 'UpdateImageIndex', ValidateUnsignedInteger, Required = False, Default = 1) UpdateImageIndex = ConvertJsonValue (Config, 'UpdateImageIndex', ValidateUnsignedInteger, Required = False, Default = 1)
MonotonicCount = ConvertJsonValue (Config, 'MonotonicCount', ValidateUnsignedInteger, Required = False, Default = 0) MonotonicCount = ConvertJsonValue (Config, 'MonotonicCount', ValidateUnsignedInteger, Required = False, Default = 0)
SignToolPfxFile = ConvertJsonValue (Config, 'SignToolPfxFile', os.path.expandvars, Required = False, Default = None, Open = True) SignToolPfxFile = ConvertJsonValue (Config, 'SignToolPfxFile', os.path.expandvars, Required = False, Default = None, Open = True)
SignToolSubjectName = ConvertJsonValue (Config, 'SignToolSubjectName', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslSignerPrivateCertFile = ConvertJsonValue (Config, 'OpenSslSignerPrivateCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslSignerPrivateCertFile = ConvertJsonValue (Config, 'OpenSslSignerPrivateCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslOtherPublicCertFile = ConvertJsonValue (Config, 'OpenSslOtherPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslOtherPublicCertFile = ConvertJsonValue (Config, 'OpenSslOtherPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
OpenSslTrustedPublicCertFile = ConvertJsonValue (Config, 'OpenSslTrustedPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True) OpenSslTrustedPublicCertFile = ConvertJsonValue (Config, 'OpenSslTrustedPublicCertFile', os.path.expandvars, Required = False, Default = None, Open = True)
@ -329,6 +335,7 @@ if __name__ == '__main__':
HardwareInstance, HardwareInstance,
UpdateImageIndex, UpdateImageIndex,
SignToolPfxFile, SignToolPfxFile,
SignToolSubjectName,
OpenSslSignerPrivateCertFile, OpenSslSignerPrivateCertFile,
OpenSslOtherPublicCertFile, OpenSslOtherPublicCertFile,
OpenSslTrustedPublicCertFile, OpenSslTrustedPublicCertFile,
@ -348,6 +355,7 @@ if __name__ == '__main__':
"HardwareInstance": str(PayloadDescriptor.HardwareInstance), "HardwareInstance": str(PayloadDescriptor.HardwareInstance),
"UpdateImageIndex": str(PayloadDescriptor.UpdateImageIndex), "UpdateImageIndex": str(PayloadDescriptor.UpdateImageIndex),
"SignToolPfxFile": str(PayloadDescriptor.SignToolPfxFile), "SignToolPfxFile": str(PayloadDescriptor.SignToolPfxFile),
"SignToolSubjectName": str(PayloadDescriptor.SignToolSubjectName),
"OpenSslSignerPrivateCertFile": str(PayloadDescriptor.OpenSslSignerPrivateCertFile), "OpenSslSignerPrivateCertFile": str(PayloadDescriptor.OpenSslSignerPrivateCertFile),
"OpenSslOtherPublicCertFile": str(PayloadDescriptor.OpenSslOtherPublicCertFile), "OpenSslOtherPublicCertFile": str(PayloadDescriptor.OpenSslOtherPublicCertFile),
"OpenSslTrustedPublicCertFile": str(PayloadDescriptor.OpenSslTrustedPublicCertFile), "OpenSslTrustedPublicCertFile": str(PayloadDescriptor.OpenSslTrustedPublicCertFile),
@ -363,6 +371,8 @@ if __name__ == '__main__':
for PayloadField in PayloadSection: for PayloadField in PayloadSection:
if PayloadJsonDescriptorList[Index].SignToolPfxFile is None: if PayloadJsonDescriptorList[Index].SignToolPfxFile is None:
del PayloadField ['SignToolPfxFile'] del PayloadField ['SignToolPfxFile']
if PayloadJsonDescriptorList[Index].SignToolSubjectName is None:
del PayloadField ['SignToolSubjectName']
if PayloadJsonDescriptorList[Index].OpenSslSignerPrivateCertFile is None: if PayloadJsonDescriptorList[Index].OpenSslSignerPrivateCertFile is None:
del PayloadField ['OpenSslSignerPrivateCertFile'] del PayloadField ['OpenSslSignerPrivateCertFile']
if PayloadJsonDescriptorList[Index].OpenSslOtherPublicCertFile is None: if PayloadJsonDescriptorList[Index].OpenSslOtherPublicCertFile is None:
@ -402,6 +412,9 @@ if __name__ == '__main__':
if args.SignToolPfxFile: if args.SignToolPfxFile:
print ('GenerateCapsule: error: Argument --pfx-file conflicts with Argument -j') print ('GenerateCapsule: error: Argument --pfx-file conflicts with Argument -j')
sys.exit (1) sys.exit (1)
if args.SignToolSubjectName:
print ('GenerateCapsule: error: Argument --SubjectName conflicts with Argument -j')
sys.exit (1)
if args.OpenSslSignerPrivateCertFile: if args.OpenSslSignerPrivateCertFile:
print ('GenerateCapsule: error: Argument --signer-private-cert conflicts with Argument -j') print ('GenerateCapsule: error: Argument --signer-private-cert conflicts with Argument -j')
sys.exit (1) sys.exit (1)
@ -425,6 +438,7 @@ if __name__ == '__main__':
HardwareInstance = 0, HardwareInstance = 0,
UpdateImageIndex = 1, UpdateImageIndex = 1,
SignToolPfxFile = None, SignToolPfxFile = None,
SignToolSubjectName = None,
OpenSslSignerPrivateCertFile = None, OpenSslSignerPrivateCertFile = None,
OpenSslOtherPublicCertFile = None, OpenSslOtherPublicCertFile = None,
OpenSslTrustedPublicCertFile = None, OpenSslTrustedPublicCertFile = None,
@ -439,13 +453,15 @@ if __name__ == '__main__':
self.HardwareInstance = HardwareInstance self.HardwareInstance = HardwareInstance
self.UpdateImageIndex = UpdateImageIndex self.UpdateImageIndex = UpdateImageIndex
self.SignToolPfxFile = SignToolPfxFile self.SignToolPfxFile = SignToolPfxFile
self.SignToolSubjectName = SignToolSubjectName
self.OpenSslSignerPrivateCertFile = OpenSslSignerPrivateCertFile self.OpenSslSignerPrivateCertFile = OpenSslSignerPrivateCertFile
self.OpenSslOtherPublicCertFile = OpenSslOtherPublicCertFile self.OpenSslOtherPublicCertFile = OpenSslOtherPublicCertFile
self.OpenSslTrustedPublicCertFile = OpenSslTrustedPublicCertFile self.OpenSslTrustedPublicCertFile = OpenSslTrustedPublicCertFile
self.SigningToolPath = SigningToolPath self.SigningToolPath = SigningToolPath
self.DepexExp = DepexExp self.DepexExp = DepexExp
self.UseSignTool = self.SignToolPfxFile is not None self.UseSignTool = (self.SignToolPfxFile is not None or
self.SignToolSubjectName is not None)
self.UseOpenSsl = (self.OpenSslSignerPrivateCertFile is not None and self.UseOpenSsl = (self.OpenSslSignerPrivateCertFile is not None and
self.OpenSslOtherPublicCertFile is not None and self.OpenSslOtherPublicCertFile is not None and
self.OpenSslTrustedPublicCertFile is not None) self.OpenSslTrustedPublicCertFile is not None)
@ -504,8 +520,9 @@ if __name__ == '__main__':
raise argparse.ArgumentTypeError ('--update-image-index must be an integer in range 0x0..0xff') raise argparse.ArgumentTypeError ('--update-image-index must be an integer in range 0x0..0xff')
if self.UseSignTool: if self.UseSignTool:
self.SignToolPfxFile.close() if self.SignToolPfxFile is not None:
self.SignToolPfxFile = self.SignToolPfxFile.name self.SignToolPfxFile.close()
self.SignToolPfxFile = self.SignToolPfxFile.name
if self.UseOpenSsl: if self.UseOpenSsl:
self.OpenSslSignerPrivateCertFile.close() self.OpenSslSignerPrivateCertFile.close()
self.OpenSslOtherPublicCertFile.close() self.OpenSslOtherPublicCertFile.close()
@ -548,6 +565,7 @@ if __name__ == '__main__':
args.HardwareInstance, args.HardwareInstance,
args.UpdateImageIndex, args.UpdateImageIndex,
args.SignToolPfxFile, args.SignToolPfxFile,
args.SignToolSubjectName,
args.OpenSslSignerPrivateCertFile, args.OpenSslSignerPrivateCertFile,
args.OpenSslOtherPublicCertFile, args.OpenSslOtherPublicCertFile,
args.OpenSslTrustedPublicCertFile, args.OpenSslTrustedPublicCertFile,
@ -590,6 +608,7 @@ if __name__ == '__main__':
Result + struct.pack ('<Q', SinglePayloadDescriptor.MonotonicCount), Result + struct.pack ('<Q', SinglePayloadDescriptor.MonotonicCount),
SinglePayloadDescriptor.SigningToolPath, SinglePayloadDescriptor.SigningToolPath,
SinglePayloadDescriptor.SignToolPfxFile, SinglePayloadDescriptor.SignToolPfxFile,
SinglePayloadDescriptor.SignToolSubjectName,
Verbose = args.Verbose Verbose = args.Verbose
) )
else: else:
@ -671,6 +690,7 @@ if __name__ == '__main__':
args.HardwareInstance, args.HardwareInstance,
args.UpdateImageIndex, args.UpdateImageIndex,
args.SignToolPfxFile, args.SignToolPfxFile,
args.SignSubjectName,
args.OpenSslSignerPrivateCertFile, args.OpenSslSignerPrivateCertFile,
args.OpenSslOtherPublicCertFile, args.OpenSslOtherPublicCertFile,
args.OpenSslTrustedPublicCertFile, args.OpenSslTrustedPublicCertFile,
@ -715,6 +735,7 @@ if __name__ == '__main__':
HardwareInstance, HardwareInstance,
UpdateImageIndex, UpdateImageIndex,
PayloadDescriptorList[Index].SignToolPfxFile, PayloadDescriptorList[Index].SignToolPfxFile,
PayloadDescriptorList[Index].SignToolSubjectName,
PayloadDescriptorList[Index].OpenSslSignerPrivateCertFile, PayloadDescriptorList[Index].OpenSslSignerPrivateCertFile,
PayloadDescriptorList[Index].OpenSslOtherPublicCertFile, PayloadDescriptorList[Index].OpenSslOtherPublicCertFile,
PayloadDescriptorList[Index].OpenSslTrustedPublicCertFile, PayloadDescriptorList[Index].OpenSslTrustedPublicCertFile,
@ -753,6 +774,7 @@ if __name__ == '__main__':
HardwareInstance, HardwareInstance,
UpdateImageIndex, UpdateImageIndex,
PayloadDescriptorList[Index].SignToolPfxFile, PayloadDescriptorList[Index].SignToolPfxFile,
PayloadDescriptorList[Index].SignToolSubjectName,
PayloadDescriptorList[Index].OpenSslSignerPrivateCertFile, PayloadDescriptorList[Index].OpenSslSignerPrivateCertFile,
PayloadDescriptorList[Index].OpenSslOtherPublicCertFile, PayloadDescriptorList[Index].OpenSslOtherPublicCertFile,
PayloadDescriptorList[Index].OpenSslTrustedPublicCertFile, PayloadDescriptorList[Index].OpenSslTrustedPublicCertFile,
@ -785,6 +807,7 @@ if __name__ == '__main__':
FmpAuthHeader.CertData, FmpAuthHeader.CertData,
SinglePayloadDescriptor.SigningToolPath, SinglePayloadDescriptor.SigningToolPath,
SinglePayloadDescriptor.SignToolPfxFile, SinglePayloadDescriptor.SignToolPfxFile,
SinglePayloadDescriptor.SignToolSubjectName,
Verbose = args.Verbose Verbose = args.Verbose
) )
else: else:
@ -968,6 +991,8 @@ if __name__ == '__main__':
parser.add_argument ("--pfx-file", dest='SignToolPfxFile', type=argparse.FileType('rb'), parser.add_argument ("--pfx-file", dest='SignToolPfxFile', type=argparse.FileType('rb'),
help="signtool PFX certificate filename.") help="signtool PFX certificate filename.")
parser.add_argument ("--subject-name", dest='SignToolSubjectName',
help="signtool certificate subject name.")
parser.add_argument ("--signer-private-cert", dest='OpenSslSignerPrivateCertFile', type=argparse.FileType('rb'), parser.add_argument ("--signer-private-cert", dest='OpenSslSignerPrivateCertFile', type=argparse.FileType('rb'),
help="OpenSSL signer private certificate filename.") help="OpenSSL signer private certificate filename.")

View File

@ -2612,8 +2612,8 @@ def CheckFunctionHeaderConsistentWithDoxygenComment(FuncModifier, FuncHeader, Fu
if Tag.find(ParamName) == -1 and ParamName != 'VOID' and ParamName != 'void': if Tag.find(ParamName) == -1 and ParamName != 'VOID' and ParamName != 'void':
ErrorMsgList.append('Line %d : in Comment, <%s> does NOT consistent with parameter name %s ' % (CommentStartLine, (TagPartList[0] + ' ' + TagPartList[1]).replace('\n', '').replace('\r', ''), ParamName)) ErrorMsgList.append('Line %d : in Comment, <%s> is NOT consistent with parameter name %s ' % (CommentStartLine, (TagPartList[0] + ' ' + TagPartList[1]).replace('\n', '').replace('\r', ''), ParamName))
PrintErrorMsg(ERROR_DOXYGEN_CHECK_FUNCTION_HEADER, 'in Comment, <%s> does NOT consistent with parameter name %s ' % ((TagPartList[0] + ' ' + TagPartList[1]).replace('\n', '').replace('\r', ''), ParamName), TableName, CommentId) PrintErrorMsg(ERROR_DOXYGEN_CHECK_FUNCTION_HEADER, 'in Comment, <%s> is NOT consistent with parameter name %s ' % ((TagPartList[0] + ' ' + TagPartList[1]).replace('\n', '').replace('\r', ''), ParamName), TableName, CommentId)
Index += 1 Index += 1
if Index < ParamNumber: if Index < ParamNumber:

View File

@ -97,7 +97,8 @@ PcdMakefileEnd = '''
AppTarget = ''' AppTarget = '''
all: $(APPFILE) all: $(APPFILE)
$(APPFILE): $(OBJECTS) $(APPLICATION): $(OBJECTS)
$(APPFILE): $(APPLICATION)
%s %s
''' '''
@ -2931,7 +2932,7 @@ class DscBuildData(PlatformBuildClassObject):
MakeApp = MakeApp + PcdMakefileEnd MakeApp = MakeApp + PcdMakefileEnd
MakeApp = MakeApp + AppTarget % ("""\tcopy $(APPLICATION) $(APPFILE) /y """) MakeApp = MakeApp + AppTarget % ("""\tcopy $(APPLICATION) $(APPFILE) /y """)
else: else:
MakeApp = MakeApp + AppTarget % ("""\tcp $(APPLICATION) $(APPFILE) """) MakeApp = MakeApp + AppTarget % ("""\tcp -p $(APPLICATION) $(APPFILE) """)
MakeApp = MakeApp + '\n' MakeApp = MakeApp + '\n'
IncludeFileFullPaths = [] IncludeFileFullPaths = []
for includefile in IncludeFiles: for includefile in IncludeFiles:
@ -2954,7 +2955,7 @@ class DscBuildData(PlatformBuildClassObject):
else: else:
PcdValueCommonPath = os.path.normpath(mws.join(GlobalData.gGlobalDefines["EDK_TOOLS_PATH"], "Source/C/Common/PcdValueCommon.c")) PcdValueCommonPath = os.path.normpath(mws.join(GlobalData.gGlobalDefines["EDK_TOOLS_PATH"], "Source/C/Common/PcdValueCommon.c"))
MakeApp = MakeApp + '%s/PcdValueCommon.c : %s\n' % (self.OutputPath, PcdValueCommonPath) MakeApp = MakeApp + '%s/PcdValueCommon.c : %s\n' % (self.OutputPath, PcdValueCommonPath)
MakeApp = MakeApp + '\tcp -f %s %s/PcdValueCommon.c\n' % (PcdValueCommonPath, self.OutputPath) MakeApp = MakeApp + '\tcp -p -f %s %s/PcdValueCommon.c\n' % (PcdValueCommonPath, self.OutputPath)
MakeFileName = os.path.join(self.OutputPath, 'Makefile') MakeFileName = os.path.join(self.OutputPath, 'Makefile')
MakeApp += "$(OBJECTS) : %s\n" % MakeFileName MakeApp += "$(OBJECTS) : %s\n" % MakeFileName
SaveFileOnChange(MakeFileName, MakeApp, False) SaveFileOnChange(MakeFileName, MakeApp, False)

View File

@ -1084,7 +1084,9 @@ class InfBuildData(ModuleBuildClassObject):
else: else:
for Name, Guid in self.Pcds: for Name, Guid in self.Pcds:
if self.Pcds[(Name, Guid)].Type == 'FeatureFlag' or self.Pcds[(Name, Guid)].Type == 'FixedAtBuild': if self.Pcds[(Name, Guid)].Type == 'FeatureFlag' or self.Pcds[(Name, Guid)].Type == 'FixedAtBuild':
Pcds['%s.%s' % (Guid, Name)] = self.Pcds[(Name, Guid)].DefaultValue PcdFullName = '%s.%s' % (Guid, Name);
if not PcdFullName in Pcds:
Pcds[PcdFullName] = self.Pcds[(Name, Guid)].DefaultValue
try: try:
Value = ValueExpression(Instance, Pcds)() Value = ValueExpression(Instance, Pcds)()
if Value == True: if Value == True:

View File

@ -150,7 +150,9 @@ def GetModuleLibInstances(Module, Platform, BuildDatabase, Arch, Target, Toolcha
EdkLogger.error("build", OPTION_MISSING, EdkLogger.error("build", OPTION_MISSING,
"Module type [%s] is not supported by library instance [%s]" \ "Module type [%s] is not supported by library instance [%s]" \
% (ModuleType, LibraryPath), File=FileName, % (ModuleType, LibraryPath), File=FileName,
ExtraData="consumed by [%s]" % str(Module)) ExtraData="consumed by library instance [%s] which is consumed by module [%s]" \
% (str(M), str(Module))
)
else: else:
return [] return []

View File

@ -109,6 +109,9 @@
[LibraryClasses.ARM] [LibraryClasses.ARM]
ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
[LibraryClasses.common.SEC]
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
[LibraryClasses.common.PEIM] [LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
@ -236,6 +239,7 @@
!if $(CRYPTO_SERVICES) == PACKAGE !if $(CRYPTO_SERVICES) == PACKAGE
[Components] [Components]
CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf

View File

@ -0,0 +1,163 @@
/** @file
MD5 Digest Wrapper Null Implementation.
Copyright (c) Microsoft Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
Retrieves the size, in bytes, of the context buffer required for MD5 hash operations.
@return The size, in bytes, of the context buffer required for MD5 hash operations.
**/
UINTN
EFIAPI
Md5GetContextSize (
VOID
)
{
ASSERT (FALSE);
return 0;
}
/**
Initializes user-supplied memory pointed by Md5Context as MD5 hash context for
subsequent use.
If Md5Context is NULL, then return FALSE.
@param[out] Md5Context Pointer to MD5 context being initialized.
@retval TRUE MD5 context initialization succeeded.
@retval FALSE MD5 context initialization failed.
**/
BOOLEAN
EFIAPI
Md5Init (
OUT VOID *Md5Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Makes a copy of an existing MD5 context.
If Md5Context is NULL, then return FALSE.
If NewMd5Context is NULL, then return FALSE.
@param[in] Md5Context Pointer to MD5 context being copied.
@param[out] NewMd5Context Pointer to new MD5 context.
@retval TRUE MD5 context copy succeeded.
@retval FALSE MD5 context copy failed.
**/
BOOLEAN
EFIAPI
Md5Duplicate (
IN CONST VOID *Md5Context,
OUT VOID *NewMd5Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Digests the input data and updates MD5 context.
This function performs MD5 digest on a data buffer of the specified size.
It can be called multiple times to compute the digest of long or discontinuous data streams.
MD5 context should be already correctly intialized by Md5Init(), and should not be finalized
by Md5Final(). Behavior with invalid context is undefined.
If Md5Context is NULL, then return FALSE.
@param[in, out] Md5Context Pointer to the MD5 context.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@retval TRUE MD5 data digest succeeded.
@retval FALSE MD5 data digest failed.
**/
BOOLEAN
EFIAPI
Md5Update (
IN OUT VOID *Md5Context,
IN CONST VOID *Data,
IN UINTN DataSize
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Completes computation of the MD5 digest value.
This function completes MD5 hash computation and retrieves the digest value into
the specified memory. After this function has been called, the MD5 context cannot
be used again.
MD5 context should be already correctly intialized by Md5Init(), and should not be
finalized by Md5Final(). Behavior with invalid MD5 context is undefined.
If Md5Context is NULL, then return FALSE.
If HashValue is NULL, then return FALSE.
@param[in, out] Md5Context Pointer to the MD5 context.
@param[out] HashValue Pointer to a buffer that receives the MD5 digest
value (16 bytes).
@retval TRUE MD5 digest computation succeeded.
@retval FALSE MD5 digest computation failed.
**/
BOOLEAN
EFIAPI
Md5Final (
IN OUT VOID *Md5Context,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Computes the MD5 message digest of a input data buffer.
This function performs the MD5 message digest of a given data buffer, and places
the digest value into the specified memory.
If this interface is not supported, then return FALSE.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@param[out] HashValue Pointer to a buffer that receives the MD5 digest
value (16 bytes).
@retval TRUE MD5 digest computation succeeded.
@retval FALSE MD5 digest computation failed.
@retval FALSE This interface is not supported.
**/
BOOLEAN
EFIAPI
Md5HashAll (
IN CONST VOID *Data,
IN UINTN DataSize,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}

View File

@ -0,0 +1,166 @@
/** @file
SHA-1 Digest Wrapper Null Implementation.
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
Retrieves the size, in bytes, of the context buffer required for SHA-1 hash operations.
@return The size, in bytes, of the context buffer required for SHA-1 hash operations.
**/
UINTN
EFIAPI
Sha1GetContextSize (
VOID
)
{
//
// Retrieves SHA Context Size
//
ASSERT (FALSE);
return 0;
}
/**
Initializes user-supplied memory pointed by Sha1Context as SHA-1 hash context for
subsequent use.
If Sha1Context is NULL, then return FALSE.
@param[out] Sha1Context Pointer to SHA-1 context being initialized.
@retval TRUE SHA-1 context initialization succeeded.
@retval FALSE SHA-1 context initialization failed.
**/
BOOLEAN
EFIAPI
Sha1Init (
OUT VOID *Sha1Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Makes a copy of an existing SHA-1 context.
If Sha1Context is NULL, then return FALSE.
If NewSha1Context is NULL, then return FALSE.
@param[in] Sha1Context Pointer to SHA-1 context being copied.
@param[out] NewSha1Context Pointer to new SHA-1 context.
@retval TRUE SHA-1 context copy succeeded.
@retval FALSE SHA-1 context copy failed.
**/
BOOLEAN
EFIAPI
Sha1Duplicate (
IN CONST VOID *Sha1Context,
OUT VOID *NewSha1Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Digests the input data and updates SHA-1 context.
This function performs SHA-1 digest on a data buffer of the specified size.
It can be called multiple times to compute the digest of long or discontinuous data streams.
SHA-1 context should be already correctly initialized by Sha1Init(), and should not be finalized
by Sha1Final(). Behavior with invalid context is undefined.
If Sha1Context is NULL, then return FALSE.
@param[in, out] Sha1Context Pointer to the SHA-1 context.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@retval TRUE SHA-1 data digest succeeded.
@retval FALSE SHA-1 data digest failed.
**/
BOOLEAN
EFIAPI
Sha1Update (
IN OUT VOID *Sha1Context,
IN CONST VOID *Data,
IN UINTN DataSize
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Completes computation of the SHA-1 digest value.
This function completes SHA-1 hash computation and retrieves the digest value into
the specified memory. After this function has been called, the SHA-1 context cannot
be used again.
SHA-1 context should be already correctly initialized by Sha1Init(), and should not be
finalized by Sha1Final(). Behavior with invalid SHA-1 context is undefined.
If Sha1Context is NULL, then return FALSE.
If HashValue is NULL, then return FALSE.
@param[in, out] Sha1Context Pointer to the SHA-1 context.
@param[out] HashValue Pointer to a buffer that receives the SHA-1 digest
value (20 bytes).
@retval TRUE SHA-1 digest computation succeeded.
@retval FALSE SHA-1 digest computation failed.
**/
BOOLEAN
EFIAPI
Sha1Final (
IN OUT VOID *Sha1Context,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Computes the SHA-1 message digest of a input data buffer.
This function performs the SHA-1 message digest of a given data buffer, and places
the digest value into the specified memory.
If this interface is not supported, then return FALSE.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@param[out] HashValue Pointer to a buffer that receives the SHA-1 digest
value (20 bytes).
@retval TRUE SHA-1 digest computation succeeded.
@retval FALSE SHA-1 digest computation failed.
@retval FALSE This interface is not supported.
**/
BOOLEAN
EFIAPI
Sha1HashAll (
IN CONST VOID *Data,
IN UINTN DataSize,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}

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@ -0,0 +1,162 @@
/** @file
SHA-256 Digest Wrapper Null Implementation.
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
Retrieves the size, in bytes, of the context buffer required for SHA-256 hash operations.
@return The size, in bytes, of the context buffer required for SHA-256 hash operations.
**/
UINTN
EFIAPI
Sha256GetContextSize (
VOID
)
{
ASSERT (FALSE);
return 0;
}
/**
Initializes user-supplied memory pointed by Sha256Context as SHA-256 hash context for
subsequent use.
If Sha256Context is NULL, then return FALSE.
@param[out] Sha256Context Pointer to SHA-256 context being initialized.
@retval TRUE SHA-256 context initialization succeeded.
@retval FALSE SHA-256 context initialization failed.
**/
BOOLEAN
EFIAPI
Sha256Init (
OUT VOID *Sha256Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Makes a copy of an existing SHA-256 context.
If Sha256Context is NULL, then return FALSE.
If NewSha256Context is NULL, then return FALSE.
@param[in] Sha256Context Pointer to SHA-256 context being copied.
@param[out] NewSha256Context Pointer to new SHA-256 context.
@retval TRUE SHA-256 context copy succeeded.
@retval FALSE SHA-256 context copy failed.
**/
BOOLEAN
EFIAPI
Sha256Duplicate (
IN CONST VOID *Sha256Context,
OUT VOID *NewSha256Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Digests the input data and updates SHA-256 context.
This function performs SHA-256 digest on a data buffer of the specified size.
It can be called multiple times to compute the digest of long or discontinuous data streams.
SHA-256 context should be already correctly initialized by Sha256Init(), and should not be finalized
by Sha256Final(). Behavior with invalid context is undefined.
If Sha256Context is NULL, then return FALSE.
@param[in, out] Sha256Context Pointer to the SHA-256 context.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@retval TRUE SHA-256 data digest succeeded.
@retval FALSE SHA-256 data digest failed.
**/
BOOLEAN
EFIAPI
Sha256Update (
IN OUT VOID *Sha256Context,
IN CONST VOID *Data,
IN UINTN DataSize
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Completes computation of the SHA-256 digest value.
This function completes SHA-256 hash computation and retrieves the digest value into
the specified memory. After this function has been called, the SHA-256 context cannot
be used again.
SHA-256 context should be already correctly initialized by Sha256Init(), and should not be
finalized by Sha256Final(). Behavior with invalid SHA-256 context is undefined.
If Sha256Context is NULL, then return FALSE.
If HashValue is NULL, then return FALSE.
@param[in, out] Sha256Context Pointer to the SHA-256 context.
@param[out] HashValue Pointer to a buffer that receives the SHA-256 digest
value (32 bytes).
@retval TRUE SHA-256 digest computation succeeded.
@retval FALSE SHA-256 digest computation failed.
**/
BOOLEAN
EFIAPI
Sha256Final (
IN OUT VOID *Sha256Context,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Computes the SHA-256 message digest of a input data buffer.
This function performs the SHA-256 message digest of a given data buffer, and places
the digest value into the specified memory.
If this interface is not supported, then return FALSE.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@param[out] HashValue Pointer to a buffer that receives the SHA-256 digest
value (32 bytes).
@retval TRUE SHA-256 digest computation succeeded.
@retval FALSE SHA-256 digest computation failed.
@retval FALSE This interface is not supported.
**/
BOOLEAN
EFIAPI
Sha256HashAll (
IN CONST VOID *Data,
IN UINTN DataSize,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}

View File

@ -0,0 +1,164 @@
/** @file
SM3 Digest Wrapper Null Implementation.
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
Retrieves the size, in bytes, of the context buffer required for SM3 hash operations.
@return The size, in bytes, of the context buffer required for SM3 hash operations.
**/
UINTN
EFIAPI
Sm3GetContextSize (
VOID
)
{
ASSERT (FALSE);
return 0;
}
/**
Initializes user-supplied memory pointed by Sm3Context as SM3 hash context for
subsequent use.
If Sm3Context is NULL, then return FALSE.
@param[out] Sm3Context Pointer to SM3 context being initialized.
@retval TRUE SM3 context initialization succeeded.
@retval FALSE SM3 context initialization failed.
**/
BOOLEAN
EFIAPI
Sm3Init (
OUT VOID *Sm3Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Makes a copy of an existing SM3 context.
If Sm3Context is NULL, then return FALSE.
If NewSm3Context is NULL, then return FALSE.
If this interface is not supported, then return FALSE.
@param[in] Sm3Context Pointer to SM3 context being copied.
@param[out] NewSm3Context Pointer to new SM3 context.
@retval TRUE SM3 context copy succeeded.
@retval FALSE SM3 context copy failed.
@retval FALSE This interface is not supported.
**/
BOOLEAN
EFIAPI
Sm3Duplicate (
IN CONST VOID *Sm3Context,
OUT VOID *NewSm3Context
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Digests the input data and updates SM3 context.
This function performs SM3 digest on a data buffer of the specified size.
It can be called multiple times to compute the digest of long or discontinuous data streams.
SM3 context should be already correctly initialized by Sm3Init(), and should not be finalized
by Sm3Final(). Behavior with invalid context is undefined.
If Sm3Context is NULL, then return FALSE.
@param[in, out] Sm3Context Pointer to the SM3 context.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@retval TRUE SM3 data digest succeeded.
@retval FALSE SM3 data digest failed.
**/
BOOLEAN
EFIAPI
Sm3Update (
IN OUT VOID *Sm3Context,
IN CONST VOID *Data,
IN UINTN DataSize
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Completes computation of the SM3 digest value.
This function completes SM3 hash computation and retrieves the digest value into
the specified memory. After this function has been called, the SM3 context cannot
be used again.
SM3 context should be already correctly initialized by Sm3Init(), and should not be
finalized by Sm3Final(). Behavior with invalid SM3 context is undefined.
If Sm3Context is NULL, then return FALSE.
If HashValue is NULL, then return FALSE.
@param[in, out] Sm3Context Pointer to the SM3 context.
@param[out] HashValue Pointer to a buffer that receives the SM3 digest
value (32 bytes).
@retval TRUE SM3 digest computation succeeded.
@retval FALSE SM3 digest computation failed.
**/
BOOLEAN
EFIAPI
Sm3Final (
IN OUT VOID *Sm3Context,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Computes the SM3 message digest of a input data buffer.
This function performs the SM3 message digest of a given data buffer, and places
the digest value into the specified memory.
If this interface is not supported, then return FALSE.
@param[in] Data Pointer to the buffer containing the data to be hashed.
@param[in] DataSize Size of Data buffer in bytes.
@param[out] HashValue Pointer to a buffer that receives the SM3 digest
value (32 bytes).
@retval TRUE SM3 digest computation succeeded.
@retval FALSE SM3 digest computation failed.
@retval FALSE This interface is not supported.
**/
BOOLEAN
EFIAPI
Sm3HashAll (
IN CONST VOID *Data,
IN UINTN DataSize,
OUT UINT8 *HashValue
)
{
ASSERT (FALSE);
return FALSE;
}

View File

@ -0,0 +1,152 @@
/** @file
PKCS7 Verify Null implementation.
Copyright (C) Microsoft Corporation. All Rights Reserved.
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
This function will return the leaf signer certificate in a chain. This is
required because certificate chains are not guaranteed to have the
certificates in the order that they were issued.
A typical certificate chain looks like this:
----------------------------
| Root |
----------------------------
^
|
----------------------------
| Policy CA | <-- Typical Trust Anchor.
----------------------------
^
|
----------------------------
| Issuing CA |
----------------------------
^
|
-----------------------------
/ End-Entity (leaf) signer / <-- Bottom certificate.
----------------------------- EKU: "1.3.6.1.4.1.311.76.9.21.1"
(Firmware Signing)
@param[in] CertChain Certificate chain.
@param[out] SignerCert Last certificate in the chain. For PKCS7 signatures,
this will be the end-entity (leaf) signer cert.
@retval EFI_SUCCESS The required EKUs were found in the signature.
@retval EFI_INVALID_PARAMETER A parameter was invalid.
@retval EFI_NOT_FOUND The number of signers found was not 1.
**/
EFI_STATUS
GetSignerCertificate (
IN CONST VOID *CertChain,
OUT VOID **SignerCert
)
{
ASSERT (FALSE);
return EFI_NOT_READY;
}
/**
Determines if the specified EKU represented in ASN1 form is present
in a given certificate.
@param[in] Cert The certificate to check.
@param[in] Asn1ToFind The EKU to look for.
@retval EFI_SUCCESS We successfully identified the signing type.
@retval EFI_INVALID_PARAMETER A parameter was invalid.
@retval EFI_NOT_FOUND One or more EKU's were not found in the signature.
**/
EFI_STATUS
IsEkuInCertificate (
IN CONST VOID *Cert,
IN VOID *Asn1ToFind
)
{
ASSERT (FALSE);
return EFI_NOT_READY;
}
/**
Determines if the specified EKUs are present in a signing certificate.
@param[in] SignerCert The certificate to check.
@param[in] RequiredEKUs The EKUs to look for.
@param[in] RequiredEKUsSize The number of EKUs
@param[in] RequireAllPresent If TRUE, then all the specified EKUs
must be present in the certificate.
@retval EFI_SUCCESS We successfully identified the signing type.
@retval EFI_INVALID_PARAMETER A parameter was invalid.
@retval EFI_NOT_FOUND One or more EKU's were not found in the signature.
**/
EFI_STATUS
CheckEKUs (
IN CONST VOID *SignerCert,
IN CONST CHAR8 *RequiredEKUs[],
IN CONST UINT32 RequiredEKUsSize,
IN BOOLEAN RequireAllPresent
)
{
ASSERT (FALSE);
return EFI_NOT_READY;
}
/**
This function receives a PKCS#7 formatted signature blob,
looks for the EKU SEQUENCE blob, and if found then looks
for all the required EKUs. This function was created so that
the Surface team can cut down on the number of Certificate
Authorities (CA's) by checking EKU's on leaf signers for
a specific product. This prevents one product's certificate
from signing another product's firmware or unlock blobs.
Note that this function does not validate the certificate chain.
That needs to be done before using this function.
@param[in] Pkcs7Signature The PKCS#7 signed information content block. An array
containing the content block with both the signature,
the signer's certificate, and any necessary intermediate
certificates.
@param[in] Pkcs7SignatureSize Number of bytes in Pkcs7Signature.
@param[in] RequiredEKUs Array of null-terminated strings listing OIDs of
required EKUs that must be present in the signature.
@param[in] RequiredEKUsSize Number of elements in the RequiredEKUs string array.
@param[in] RequireAllPresent If this is TRUE, then all of the specified EKU's
must be present in the leaf signer. If it is
FALSE, then we will succeed if we find any
of the specified EKU's.
@retval EFI_SUCCESS The required EKUs were found in the signature.
@retval EFI_INVALID_PARAMETER A parameter was invalid.
@retval EFI_NOT_FOUND One or more EKU's were not found in the signature.
**/
EFI_STATUS
EFIAPI
VerifyEKUsInPkcs7Signature (
IN CONST UINT8 *Pkcs7Signature,
IN CONST UINT32 SignatureSize,
IN CONST CHAR8 *RequiredEKUs[],
IN CONST UINT32 RequiredEKUsSize,
IN BOOLEAN RequireAllPresent
)
{
ASSERT (FALSE);
return EFI_NOT_READY;
}

View File

@ -0,0 +1,121 @@
/** @file
RSA Asymmetric Cipher Wrapper Null Implementation.
This file implements following APIs which provide basic capabilities for RSA:
1) RsaNew
2) RsaFree
3) RsaSetKey
4) RsaPkcs1Verify
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "InternalCryptLib.h"
/**
Allocates and initializes one RSA context for subsequent use.
@return Pointer to the RSA context that has been initialized.
If the allocations fails, RsaNew() returns NULL.
**/
VOID *
EFIAPI
RsaNew (
VOID
)
{
//
// Allocates & Initializes RSA Context
//
ASSERT (FALSE);
return NULL;
}
/**
Release the specified RSA context.
@param[in] RsaContext Pointer to the RSA context to be released.
**/
VOID
EFIAPI
RsaFree (
IN VOID *RsaContext
)
{
//
// Free RSA Context
//
ASSERT (FALSE);
}
/**
Sets the tag-designated key component into the established RSA context.
This function sets the tag-designated RSA key component into the established
RSA context from the user-specified non-negative integer (octet string format
represented in RSA PKCS#1).
If BigNumber is NULL, then the specified key component in RSA context is cleared.
If RsaContext is NULL, then return FALSE.
@param[in, out] RsaContext Pointer to RSA context being set.
@param[in] KeyTag Tag of RSA key component being set.
@param[in] BigNumber Pointer to octet integer buffer.
If NULL, then the specified key component in RSA
context is cleared.
@param[in] BnSize Size of big number buffer in bytes.
If BigNumber is NULL, then it is ignored.
@retval TRUE RSA key component was set successfully.
@retval FALSE Invalid RSA key component tag.
**/
BOOLEAN
EFIAPI
RsaSetKey (
IN OUT VOID *RsaContext,
IN RSA_KEY_TAG KeyTag,
IN CONST UINT8 *BigNumber,
IN UINTN BnSize
)
{
ASSERT (FALSE);
return FALSE;
}
/**
Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in
RSA PKCS#1.
If RsaContext is NULL, then return FALSE.
If MessageHash is NULL, then return FALSE.
If Signature is NULL, then return FALSE.
If HashSize is not equal to the size of MD5, SHA-1 or SHA-256 digest, then return FALSE.
@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] MessageHash Pointer to octet message hash to be checked.
@param[in] HashSize Size of the message hash in bytes.
@param[in] Signature Pointer to RSA PKCS1-v1_5 signature to be verified.
@param[in] SigSize Size of signature in bytes.
@retval TRUE Valid signature encoded in PKCS1-v1_5.
@retval FALSE Invalid signature or invalid RSA context.
**/
BOOLEAN
EFIAPI
RsaPkcs1Verify (
IN VOID *RsaContext,
IN CONST UINT8 *MessageHash,
IN UINTN HashSize,
IN CONST UINT8 *Signature,
IN UINTN SigSize
)
{
ASSERT (FALSE);
return FALSE;
}

View File

@ -0,0 +1,91 @@
## @file
# Cryptographic Library Instance for SEC.
#
# Caution: This module requires additional review when modified.
# This library will have external input - signature.
# This external input must be validated carefully to avoid security issues such as
# buffer overflow or integer overflow.
#
# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SecCryptLib
FILE_GUID = 3689D343-0D32-4284-8053-BF10537990E8
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BaseCryptLib|SEC
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
InternalCryptLib.h
Hash/CryptSha512.c
Hash/CryptMd5Null.c
Hash/CryptSha1Null.c
Hash/CryptSha256Null.c
Hash/CryptSm3Null.c
Hash/CryptParallelHashNull.c
Hmac/CryptHmacSha256Null.c
Kdf/CryptHkdfNull.c
Cipher/CryptAesNull.c
Pk/CryptRsaBasicNull.c
Pk/CryptRsaExtNull.c
Pk/CryptPkcs1OaepNull.c
Pk/CryptPkcs5Pbkdf2Null.c
Pk/CryptPkcs7SignNull.c
Pk/CryptPkcs7VerifyNull.c
Pk/CryptPkcs7VerifyEkuNull.c
Pk/CryptDhNull.c
Pk/CryptX509Null.c
Pk/CryptAuthenticodeNull.c
Pk/CryptTsNull.c
Pem/CryptPemNull.c
Rand/CryptRandNull.c
Pk/CryptRsaPssNull.c
Pk/CryptRsaPssSignNull.c
SysCall/CrtWrapper.c
SysCall/ConstantTimeClock.c
SysCall/BaseMemAllocation.c
[Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
MemoryAllocationLib
DebugLib
OpensslLib
IntrinsicLib
#
# Remove these [BuildOptions] after this library is cleaned up
#
[BuildOptions]
#
# suppress the following warnings so we do not break the build with warnings-as-errors:
# C4090: 'function' : different 'const' qualifiers
# C4718: 'function call' : recursive call has no side effects, deleting
#
MSFT:*_*_*_CC_FLAGS = /wd4090 /wd4718
# -JCryptoPkg/Include : To disable the use of the system includes provided by RVCT
# --diag_remark=1 : Reduce severity of "#1-D: last line of file ends without a newline"
RVCT:*_*_ARM_CC_FLAGS = -JCryptoPkg/Include --diag_remark=1
GCC:*_CLANG35_*_CC_FLAGS = -std=c99
GCC:*_CLANG38_*_CC_FLAGS = -std=c99
GCC:*_CLANGPDB_*_CC_FLAGS = -std=c99 -Wno-error=incompatible-pointer-types
XCODE:*_*_*_CC_FLAGS = -std=c99

View File

@ -15,6 +15,7 @@
[LibraryClasses.common] [LibraryClasses.common]
AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf
AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf
SsdtPcieSupportLib|DynamicTablesPkg/Library/Common/SsdtPcieSupportLib/SsdtPcieSupportLib.inf
SsdtSerialPortFixupLib|DynamicTablesPkg/Library/Common/SsdtSerialPortFixupLib/SsdtSerialPortFixupLib.inf SsdtSerialPortFixupLib|DynamicTablesPkg/Library/Common/SsdtSerialPortFixupLib/SsdtSerialPortFixupLib.inf
TableHelperLib|DynamicTablesPkg/Library/Common/TableHelperLib/TableHelperLib.inf TableHelperLib|DynamicTablesPkg/Library/Common/TableHelperLib/TableHelperLib.inf

View File

@ -108,6 +108,7 @@
"lgreater", "lgreater",
"lless", "lless",
"MPIDR", "MPIDR",
"PASID",
"PERIPHBASE", "PERIPHBASE",
"phandle", "phandle",
"pytool", "pytool",

View File

@ -30,6 +30,9 @@
## @libraryclass Defines a set of APIs to a hardware information parser. ## @libraryclass Defines a set of APIs to a hardware information parser.
HwInfoParserLib|Include/Library/HwInfoParserLib.h HwInfoParserLib|Include/Library/HwInfoParserLib.h
## @libraryclass Defines functions for customizing the generation of _OSC and slot info.
SsdtPcieSupportLib|Include/Library/SsdtPcieSupportLib.h
## @libraryclass Defines a set of methods for fixing up a SSDT Serial Port. ## @libraryclass Defines a set of methods for fixing up a SSDT Serial Port.
SsdtSerialPortFixupLib|Include/Library/SsdtSerialPortFixupLib.h SsdtSerialPortFixupLib|Include/Library/SsdtSerialPortFixupLib.h

View File

@ -41,6 +41,7 @@
[Components.common] [Components.common]
DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf
DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf
DynamicTablesPkg/Library/Common/SsdtPcieSupportLib/SsdtPcieSupportLib.inf
DynamicTablesPkg/Library/Common/SsdtSerialPortFixupLib/SsdtSerialPortFixupLib.inf DynamicTablesPkg/Library/Common/SsdtSerialPortFixupLib/SsdtSerialPortFixupLib.inf
DynamicTablesPkg/Library/Common/TableHelperLib/TableHelperLib.inf DynamicTablesPkg/Library/Common/TableHelperLib/TableHelperLib.inf
DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParserLib.inf DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParserLib.inf

View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR> Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -61,6 +61,8 @@ typedef enum ArmObjectID {
EArmObjLpiInfo, ///< 37 - Lpi Info EArmObjLpiInfo, ///< 37 - Lpi Info
EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info
EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info
EArmObjRmr, ///< 40 - Reserved Memory Range Node
EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor
EArmObjMax EArmObjMax
} EARM_OBJECT_ID; } EARM_OBJECT_ID;
@ -477,6 +479,9 @@ typedef struct CmArmItsGroupNode {
UINT32 ItsIdCount; UINT32 ItsIdCount;
/// Reference token for the ITS identifier array /// Reference token for the ITS identifier array
CM_OBJECT_TOKEN ItsIdToken; CM_OBJECT_TOKEN ItsIdToken;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_ITS_GROUP_NODE; } CM_ARM_ITS_GROUP_NODE;
/** A structure that describes the /** A structure that describes the
@ -509,6 +514,9 @@ typedef struct CmArmNamedComponentNode {
the entry in the namespace for this object. the entry in the namespace for this object.
*/ */
CHAR8 *ObjectName; CHAR8 *ObjectName;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_NAMED_COMPONENT_NODE; } CM_ARM_NAMED_COMPONENT_NODE;
/** A structure that describes the /** A structure that describes the
@ -537,6 +545,13 @@ typedef struct CmArmRootComplexNode {
UINT32 PciSegmentNumber; UINT32 PciSegmentNumber;
/// Memory address size limit /// Memory address size limit
UINT8 MemoryAddressSize; UINT8 MemoryAddressSize;
/// PASID capabilities
UINT16 PasidCapabilities;
/// Flags
UINT32 Flags;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_ROOT_COMPLEX_NODE; } CM_ARM_ROOT_COMPLEX_NODE;
/** A structure that describes the /** A structure that describes the
@ -579,6 +594,9 @@ typedef struct CmArmSmmuV1SmmuV2Node {
UINT32 SMMU_NSgCfgIrpt; UINT32 SMMU_NSgCfgIrpt;
/// SMMU_NSgCfgIrpt interrupt flags /// SMMU_NSgCfgIrpt interrupt flags
UINT32 SMMU_NSgCfgIrptFlags; UINT32 SMMU_NSgCfgIrptFlags;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_SMMUV1_SMMUV2_NODE; } CM_ARM_SMMUV1_SMMUV2_NODE;
/** A structure that describes the /** A structure that describes the
@ -615,6 +633,9 @@ typedef struct CmArmSmmuV3Node {
UINT32 ProximityDomain; UINT32 ProximityDomain;
/// Index into the array of ID mapping /// Index into the array of ID mapping
UINT32 DeviceIdMappingIndex; UINT32 DeviceIdMappingIndex;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_SMMUV3_NODE; } CM_ARM_SMMUV3_NODE;
/** A structure that describes the /** A structure that describes the
@ -639,6 +660,9 @@ typedef struct CmArmPmcgNode {
/// Reference token for the IORT node associated with this node /// Reference token for the IORT node associated with this node
CM_OBJECT_TOKEN ReferenceToken; CM_OBJECT_TOKEN ReferenceToken;
/// Unique identifier for this node.
UINT32 Identifier;
} CM_ARM_PMCG_NODE; } CM_ARM_PMCG_NODE;
/** A structure that describes the /** A structure that describes the
@ -1006,6 +1030,46 @@ typedef struct CmArmPciInterruptMapInfo {
CM_ARM_GENERIC_INTERRUPT IntcInterrupt; CM_ARM_GENERIC_INTERRUPT IntcInterrupt;
} CM_ARM_PCI_INTERRUPT_MAP_INFO; } CM_ARM_PCI_INTERRUPT_MAP_INFO;
/** A structure that describes the
RMR node for the Platform.
ID: EArmObjRmr
*/
typedef struct CmArmRmrNode {
/// An unique token used to identify this object
CM_OBJECT_TOKEN Token;
/// Number of ID mappings
UINT32 IdMappingCount;
/// Reference token for the ID mapping array
CM_OBJECT_TOKEN IdMappingToken;
/// Unique identifier for this node.
UINT32 Identifier;
/// Reserved Memory Range flags.
UINT32 Flags;
/// Memory range descriptor count.
UINT32 MemRangeDescCount;
/// Reference token for the Memory Range descriptor array
CM_OBJECT_TOKEN MemRangeDescToken;
} CM_ARM_RMR_NODE;
/** A structure that describes the
Memory Range descriptor.
ID: EArmObjMemoryRangeDescriptor
*/
typedef struct CmArmRmrDescriptor {
/// Base address of Reserved Memory Range,
/// aligned to a page size of 64K.
UINT64 BaseAddress;
/// Length of the Reserved Memory range.
/// Must be a multiple of the page size of 64K.
UINT64 Length;
} CM_ARM_MEMORY_RANGE_DESCRIPTOR;
#pragma pack() #pragma pack()
#endif // ARM_NAMESPACE_OBJECTS_H_ #endif // ARM_NAMESPACE_OBJECTS_H_

View File

@ -0,0 +1,73 @@
/** @file
Ssdt PCIe Support Library
Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef SSDT_PCIE_SUPPORT_LIB_H_
#define SSDT_PCIE_SUPPORT_LIB_H_
#pragma pack(1)
/** Structure used to map integer to an index.
*/
typedef struct MappingTable {
/// Mapping table.
/// Contains the Index <-> integer mapping
UINT32 *Table;
/// Last used index of the Table.
/// Bound by MaxIndex.
UINT32 LastIndex;
/// Number of entries in the Table.
UINT32 MaxIndex;
} MAPPING_TABLE;
#pragma pack()
/** Add an _OSC template method to the PciNode.
The _OSC method is provided as an AML blob. The blob is
parsed and attached at the end of the PciNode list of variable elements.
@param [in] PciInfo Pci device information.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Could not allocate memory.
**/
EFI_STATUS
EFIAPI
AddOscMethod (
IN CONST CM_ARM_PCI_CONFIG_SPACE_INFO *PciInfo,
IN OUT AML_OBJECT_NODE_HANDLE PciNode
);
/** Generate Pci slots devices.
PCI Firmware Specification - Revision 3.3,
s4.8 "Generic ACPI PCI Slot Description" requests to describe the PCI slot
used. It should be possible to enumerate them, but this is additional
information.
@param [in] PciInfo Pci device information.
@param [in] MappingTable The mapping table structure.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS Success.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
**/
EFI_STATUS
EFIAPI
GeneratePciSlots (
IN CONST CM_ARM_PCI_CONFIG_SPACE_INFO *PciInfo,
IN CONST MAPPING_TABLE *MappingTable,
IN OUT AML_OBJECT_NODE_HANDLE PciNode
);
#endif // SSDT_PCIE_SUPPORT_LIB_H_

View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017 - 2019, ARM Limited. All rights reserved. Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -105,6 +105,14 @@ typedef struct CmAStdObjAcpiTableInfo {
/// Generators shall populate this information using the revision of the /// Generators shall populate this information using the revision of the
/// Configuration Manager (CM_STD_OBJ_CONFIGURATION_MANAGER_INFO.Revision). /// Configuration Manager (CM_STD_OBJ_CONFIGURATION_MANAGER_INFO.Revision).
UINT32 OemRevision; UINT32 OemRevision;
/// The minor revision of an ACPI table if required by the table.
/// Note: If this field is not populated (has value of Zero), then the
/// Generators shall populate this information based on the latest minor
/// revision of the table that is supported by the generator.
/// e.g. This field can be used to specify the minor revision to be set
/// for the FADT table.
UINT8 MinorRevision;
} CM_STD_OBJ_ACPI_TABLE_INFO; } CM_STD_OBJ_ACPI_TABLE_INFO;
/** A structure used to describe the SMBIOS table generators to be invoked. /** A structure used to describe the SMBIOS table generators to be invoked.

View File

@ -1,7 +1,7 @@
/** @file /** @file
FADT Table Generator FADT Table Generator
Copyright (c) 2017 - 2021, ARM Limited. All rights reserved. Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s): @par Reference(s):
@ -167,7 +167,7 @@ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
// UINT16 ArmBootArch // UINT16 ArmBootArch
EFI_ACPI_6_4_ARM_PSCI_COMPLIANT, // {Template}: ARM Boot Architecture Flags EFI_ACPI_6_4_ARM_PSCI_COMPLIANT, // {Template}: ARM Boot Architecture Flags
// UINT8 MinorRevision // UINT8 MinorRevision
EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // {Template}
// UINT64 XFirmwareCtrl // UINT64 XFirmwareCtrl
0, 0,
// UINT64 XDsdt // UINT64 XDsdt
@ -546,6 +546,31 @@ BuildFadtTable (
goto error_handler; goto error_handler;
} }
// Update the MinorRevision for the FADT table if it has been specified
// otherwise default to the latest FADT minor revision supported.
// Note:
// Bits 0-3 - The low order bits correspond to the minor version of the
// specification version.
// Bits 4-7 - The high order bits correspond to the version of the ACPI
// specification errata.
if (AcpiTableInfo->MinorRevision != 0) {
if (((AcpiTableInfo->MinorRevision & 0xF) >=
EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION) &&
((AcpiTableInfo->MinorRevision & 0xF) <=
EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION))
{
AcpiFadt.MinorVersion = AcpiTableInfo->MinorRevision;
} else {
DEBUG ((
DEBUG_WARN,
"WARNING: FADT: Unsupported FADT Minor Revision 0x%x specified, " \
"defaulting to FADT Minor Revision 0x%x\n",
AcpiTableInfo->MinorRevision,
EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION
));
}
}
// Update PmProfile Info // Update PmProfile Info
Status = FadtAddPmProfileInfo (CfgMgrProtocol); Status = FadtAddPmProfileInfo (CfgMgrProtocol);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2018, ARM Limited. All rights reserved. Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -25,6 +25,9 @@ typedef struct IortNodeIndexer {
VOID *Object; VOID *Object;
/// Node offset from the start of the IORT table /// Node offset from the start of the IORT table
UINT32 Offset; UINT32 Offset;
/// Unique identifier for the Node
UINT32 Identifier;
} IORT_NODE_INDEXER; } IORT_NODE_INDEXER;
typedef struct AcpiIortGenerator { typedef struct AcpiIortGenerator {

View File

@ -29,6 +29,7 @@
#include <Library/AcpiHelperLib.h> #include <Library/AcpiHelperLib.h>
#include <Library/TableHelperLib.h> #include <Library/TableHelperLib.h>
#include <Library/AmlLib/AmlLib.h> #include <Library/AmlLib/AmlLib.h>
#include <Library/SsdtPcieSupportLib.h>
#include <Protocol/ConfigurationManagerProtocol.h> #include <Protocol/ConfigurationManagerProtocol.h>
#include "SsdtPcieGenerator.h" #include "SsdtPcieGenerator.h"
@ -280,86 +281,6 @@ GeneratePciDeviceInfo (
return Status; return Status;
} }
/** Generate Pci slots devices.
PCI Firmware Specification - Revision 3.3,
s4.8 "Generic ACPI PCI Slot Description" requests to describe the PCI slot
used. It should be possible to enumerate them, but this is additional
information.
@param [in] MappingTable The mapping table structure.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS Success.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
**/
STATIC
EFI_STATUS
EFIAPI
GeneratePciSlots (
IN CONST MAPPING_TABLE *MappingTable,
IN OUT AML_OBJECT_NODE_HANDLE PciNode
)
{
EFI_STATUS Status;
UINT32 Index;
UINT32 LastIndex;
UINT32 DeviceId;
CHAR8 AslName[AML_NAME_SEG_SIZE + 1];
AML_OBJECT_NODE_HANDLE DeviceNode;
ASSERT (MappingTable != NULL);
ASSERT (PciNode != NULL);
// Generic device name is "Dxx".
CopyMem (AslName, "Dxx_", AML_NAME_SEG_SIZE + 1);
LastIndex = MappingTable->LastIndex;
// There are at most 32 devices on a Pci bus.
if (LastIndex >= 32) {
ASSERT (0);
return EFI_INVALID_PARAMETER;
}
for (Index = 0; Index < LastIndex; Index++) {
DeviceId = MappingTable->Table[Index];
AslName[AML_NAME_SEG_SIZE - 3] = AsciiFromHex (DeviceId & 0xF);
AslName[AML_NAME_SEG_SIZE - 2] = AsciiFromHex ((DeviceId >> 4) & 0xF);
// ASL:
// Device (Dxx) {
// Name (_ADR, <address value>)
// }
Status = AmlCodeGenDevice (AslName, PciNode, &DeviceNode);
if (EFI_ERROR (Status)) {
ASSERT (0);
return Status;
}
/* ACPI 6.4 specification, Table 6.2: "ADR Object Address Encodings"
High word-Device #, Low word-Function #. (for example, device 3,
function 2 is 0x00030002). To refer to all the functions on a device #,
use a function number of FFFF).
*/
Status = AmlCodeGenNameInteger (
"_ADR",
(DeviceId << 16) | 0xFFFF,
DeviceNode,
NULL
);
if (EFI_ERROR (Status)) {
ASSERT (0);
return Status;
}
// _SUN object is not generated as we don't know which slot will be used.
}
return Status;
}
/** Generate a _PRT object (Pci Routing Table) for the Pci device. /** Generate a _PRT object (Pci Routing Table) for the Pci device.
Cf. ACPI 6.4 specification, s6.2.13 "_PRT (PCI Routing Table)" Cf. ACPI 6.4 specification, s6.2.13 "_PRT (PCI Routing Table)"
@ -449,7 +370,7 @@ GeneratePrt (
if ((Index > 0) && if ((Index > 0) &&
(IrqMapInfo->IntcInterrupt.Interrupt >= 32) && (IrqMapInfo->IntcInterrupt.Interrupt >= 32) &&
(IrqMapInfo->IntcInterrupt.Interrupt < 1020) && (IrqMapInfo->IntcInterrupt.Interrupt < 1020) &&
((IrqMapInfo->IntcInterrupt.Flags & 0x3) != BIT0)) ((IrqMapInfo->IntcInterrupt.Flags & 0xB) != 0))
{ {
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@ -495,7 +416,7 @@ GeneratePrt (
PrtNode = NULL; PrtNode = NULL;
// Generate the Pci slots once all the device have been added. // Generate the Pci slots once all the device have been added.
Status = GeneratePciSlots (&Generator->DeviceTable, PciNode); Status = GeneratePciSlots (PciInfo, &Generator->DeviceTable, PciNode);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
ASSERT (0); ASSERT (0);
goto exit_handler; goto exit_handler;
@ -540,6 +461,7 @@ GeneratePciCrs (
UINT32 RefCount; UINT32 RefCount;
CM_ARM_PCI_ADDRESS_MAP_INFO *AddrMapInfo; CM_ARM_PCI_ADDRESS_MAP_INFO *AddrMapInfo;
AML_OBJECT_NODE_HANDLE CrsNode; AML_OBJECT_NODE_HANDLE CrsNode;
BOOLEAN IsPosDecode;
ASSERT (Generator != NULL); ASSERT (Generator != NULL);
ASSERT (CfgMgrProtocol != NULL); ASSERT (CfgMgrProtocol != NULL);
@ -609,6 +531,11 @@ GeneratePciCrs (
} }
Translation = (AddrMapInfo->CpuAddress != AddrMapInfo->PciAddress); Translation = (AddrMapInfo->CpuAddress != AddrMapInfo->PciAddress);
if (AddrMapInfo->CpuAddress >= AddrMapInfo->PciAddress) {
IsPosDecode = TRUE;
} else {
IsPosDecode = FALSE;
}
switch (AddrMapInfo->SpaceCode) { switch (AddrMapInfo->SpaceCode) {
case PCI_SS_IO: case PCI_SS_IO:
@ -616,12 +543,12 @@ GeneratePciCrs (
FALSE, FALSE,
TRUE, TRUE,
TRUE, TRUE,
TRUE, IsPosDecode,
3, 3,
0, 0,
AddrMapInfo->PciAddress, AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1, AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
Translation ? AddrMapInfo->CpuAddress : 0, Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize, AddrMapInfo->AddressSize,
0, 0,
NULL, NULL,
@ -635,7 +562,7 @@ GeneratePciCrs (
case PCI_SS_M32: case PCI_SS_M32:
Status = AmlCodeGenRdDWordMemory ( Status = AmlCodeGenRdDWordMemory (
FALSE, FALSE,
TRUE, IsPosDecode,
TRUE, TRUE,
TRUE, TRUE,
TRUE, TRUE,
@ -643,7 +570,7 @@ GeneratePciCrs (
0, 0,
AddrMapInfo->PciAddress, AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1, AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
Translation ? AddrMapInfo->CpuAddress : 0, Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize, AddrMapInfo->AddressSize,
0, 0,
NULL, NULL,
@ -657,7 +584,7 @@ GeneratePciCrs (
case PCI_SS_M64: case PCI_SS_M64:
Status = AmlCodeGenRdQWordMemory ( Status = AmlCodeGenRdQWordMemory (
FALSE, FALSE,
TRUE, IsPosDecode,
TRUE, TRUE,
TRUE, TRUE,
TRUE, TRUE,
@ -665,7 +592,7 @@ GeneratePciCrs (
0, 0,
AddrMapInfo->PciAddress, AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1, AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
Translation ? AddrMapInfo->CpuAddress : 0, Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize, AddrMapInfo->AddressSize,
0, 0,
NULL, NULL,
@ -689,89 +616,6 @@ GeneratePciCrs (
return Status; return Status;
} }
/** Add an _OSC template method to the PciNode.
The _OSC method is provided as an AML blob. The blob is
parsed and attached at the end of the PciNode list of variable elements.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Could not allocate memory.
**/
STATIC
EFI_STATUS
EFIAPI
AddOscMethod (
IN OUT AML_OBJECT_NODE_HANDLE PciNode
)
{
EFI_STATUS Status;
EFI_STATUS Status1;
EFI_ACPI_DESCRIPTION_HEADER *SsdtPcieOscTemplate;
AML_ROOT_NODE_HANDLE OscTemplateRoot;
AML_OBJECT_NODE_HANDLE OscNode;
ASSERT (PciNode != NULL);
// Parse the Ssdt Pci Osc Template.
SsdtPcieOscTemplate = (EFI_ACPI_DESCRIPTION_HEADER *)
ssdtpcieosctemplate_aml_code;
OscNode = NULL;
OscTemplateRoot = NULL;
Status = AmlParseDefinitionBlock (
SsdtPcieOscTemplate,
&OscTemplateRoot
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"ERROR: SSDT-PCI-OSC: Failed to parse SSDT PCI OSC Template."
" Status = %r\n",
Status
));
return Status;
}
Status = AmlFindNode (OscTemplateRoot, "\\_OSC", &OscNode);
if (EFI_ERROR (Status)) {
goto error_handler;
}
Status = AmlDetachNode (OscNode);
if (EFI_ERROR (Status)) {
goto error_handler;
}
Status = AmlAttachNode (PciNode, OscNode);
if (EFI_ERROR (Status)) {
// Free the detached node.
AmlDeleteTree (OscNode);
goto error_handler;
}
error_handler:
// Cleanup
Status1 = AmlDeleteTree (OscTemplateRoot);
if (EFI_ERROR (Status1)) {
DEBUG ((
DEBUG_ERROR,
"ERROR: SSDT-PCI-OSC: Failed to cleanup AML tree."
" Status = %r\n",
Status1
));
// If Status was success but we failed to delete the AML Tree
// return Status1 else return the original error code, i.e. Status.
if (!EFI_ERROR (Status)) {
return Status1;
}
}
return Status;
}
/** Generate a Pci device. /** Generate a Pci device.
@param [in] Generator The SSDT Pci generator. @param [in] Generator The SSDT Pci generator.
@ -818,7 +662,10 @@ GeneratePciDevice (
// Write the name of the PCI device. // Write the name of the PCI device.
CopyMem (AslName, "PCIx", AML_NAME_SEG_SIZE + 1); CopyMem (AslName, "PCIx", AML_NAME_SEG_SIZE + 1);
AslName[AML_NAME_SEG_SIZE - 1] = AsciiFromHex (Uid); AslName[AML_NAME_SEG_SIZE - 1] = AsciiFromHex (Uid & 0xF);
if (Uid > 0xF) {
AslName[AML_NAME_SEG_SIZE - 2] = AsciiFromHex ((Uid >> 4) & 0xF);
}
// ASL: Device (PCIx) {} // ASL: Device (PCIx) {}
Status = AmlCodeGenDevice (AslName, ScopeNode, &PciNode); Status = AmlCodeGenDevice (AslName, ScopeNode, &PciNode);
@ -856,7 +703,7 @@ GeneratePciDevice (
} }
// Add the template _OSC method. // Add the template _OSC method.
Status = AddOscMethod (PciNode); Status = AddOscMethod (PciInfo, PciNode);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return Status; return Status;
} }

View File

@ -31,34 +31,13 @@
Corresponding changes would be needed to support the Name and Corresponding changes would be needed to support the Name and
UID fields describing the Pci root complexes. UID fields describing the Pci root complexes.
*/ */
#define MAX_PCI_ROOT_COMPLEXES_SUPPORTED 16 #define MAX_PCI_ROOT_COMPLEXES_SUPPORTED 256
// _SB scope of the AML namespace. // _SB scope of the AML namespace.
#define SB_SCOPE "\\_SB_" #define SB_SCOPE "\\_SB_"
/** C array containing the compiled AML template.
This symbol is defined in the auto generated C file
containing the AML bytecode array.
*/
extern CHAR8 ssdtpcieosctemplate_aml_code[];
#pragma pack(1) #pragma pack(1)
/** Structure used to map integer to an index.
*/
typedef struct MappingTable {
/// Mapping table.
/// Contains the Index <-> integer mapping
UINT32 *Table;
/// Last used index of the Table.
/// Bound by MaxIndex.
UINT32 LastIndex;
/// Number of entries in the Table.
UINT32 MaxIndex;
} MAPPING_TABLE;
/** A structure holding the Pcie generator and additional private data. /** A structure holding the Pcie generator and additional private data.
*/ */
typedef struct AcpiPcieGenerator { typedef struct AcpiPcieGenerator {

View File

@ -19,7 +19,6 @@
[Sources] [Sources]
SsdtPcieGenerator.c SsdtPcieGenerator.c
SsdtPcieGenerator.h SsdtPcieGenerator.h
SsdtPcieOscTemplate.asl
[Packages] [Packages]
DynamicTablesPkg/DynamicTablesPkg.dec DynamicTablesPkg/DynamicTablesPkg.dec
@ -30,3 +29,4 @@
AcpiHelperLib AcpiHelperLib
AmlLib AmlLib
BaseLib BaseLib
SsdtPcieSupportLib

View File

@ -0,0 +1,200 @@
/** @file
SSDT PCIe Support Library.
Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
- PCI Firmware Specification - Revision 3.0
- ACPI 6.4 specification:
- s6.2.13 "_PRT (PCI Routing Table)"
- s6.1.1 "_ADR (Address)"
- linux kernel code
- Arm Base Boot Requirements v1.0
- Arm Base System Architecture v1.0
**/
#include <Library/AcpiLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Protocol/AcpiTable.h>
// Module specific include files.
#include <AcpiTableGenerator.h>
#include <ConfigurationManagerObject.h>
#include <ConfigurationManagerHelper.h>
#include <Library/AcpiHelperLib.h>
#include <Library/TableHelperLib.h>
#include <Library/AmlLib/AmlLib.h>
#include <Library/SsdtPcieSupportLib.h>
#include <Protocol/ConfigurationManagerProtocol.h>
#include "SsdtPcieSupportLibPrivate.h"
/** Generate Pci slots devices.
PCI Firmware Specification - Revision 3.3,
s4.8 "Generic ACPI PCI Slot Description" requests to describe the PCI slot
used. It should be possible to enumerate them, but this is additional
information.
@param [in] PciInfo Pci device information.
@param [in] MappingTable The mapping table structure.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS Success.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
**/
EFI_STATUS
EFIAPI
GeneratePciSlots (
IN CONST CM_ARM_PCI_CONFIG_SPACE_INFO *PciInfo,
IN CONST MAPPING_TABLE *MappingTable,
IN OUT AML_OBJECT_NODE_HANDLE PciNode
)
{
EFI_STATUS Status;
UINT32 Index;
UINT32 LastIndex;
UINT32 DeviceId;
CHAR8 AslName[AML_NAME_SEG_SIZE + 1];
AML_OBJECT_NODE_HANDLE DeviceNode;
ASSERT (MappingTable != NULL);
ASSERT (PciNode != NULL);
// Generic device name is "Dxx".
CopyMem (AslName, "Dxx_", AML_NAME_SEG_SIZE + 1);
LastIndex = MappingTable->LastIndex;
// There are at most 32 devices on a Pci bus.
if (LastIndex >= 32) {
ASSERT (0);
return EFI_INVALID_PARAMETER;
}
for (Index = 0; Index < LastIndex; Index++) {
DeviceId = MappingTable->Table[Index];
AslName[AML_NAME_SEG_SIZE - 3] = AsciiFromHex (DeviceId & 0xF);
AslName[AML_NAME_SEG_SIZE - 2] = AsciiFromHex ((DeviceId >> 4) & 0xF);
// ASL:
// Device (Dxx) {
// Name (_ADR, <address value>)
// }
Status = AmlCodeGenDevice (AslName, PciNode, &DeviceNode);
if (EFI_ERROR (Status)) {
ASSERT (0);
return Status;
}
/* ACPI 6.4 specification, Table 6.2: "ADR Object Address Encodings"
High word-Device #, Low word-Function #. (for example, device 3,
function 2 is 0x00030002). To refer to all the functions on a device #,
use a function number of FFFF).
*/
Status = AmlCodeGenNameInteger (
"_ADR",
(DeviceId << 16) | 0xFFFF,
DeviceNode,
NULL
);
if (EFI_ERROR (Status)) {
ASSERT (0);
return Status;
}
// _SUN object is not generated as we don't know which slot will be used.
}
return Status;
}
/** Add an _OSC template method to the PciNode.
The _OSC method is provided as an AML blob. The blob is
parsed and attached at the end of the PciNode list of variable elements.
@param [in] PciInfo Pci device information.
@param [in, out] PciNode Pci node to amend.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_INVALID_PARAMETER Invalid parameter.
@retval EFI_OUT_OF_RESOURCES Could not allocate memory.
**/
EFI_STATUS
EFIAPI
AddOscMethod (
IN CONST CM_ARM_PCI_CONFIG_SPACE_INFO *PciInfo,
IN OUT AML_OBJECT_NODE_HANDLE PciNode
)
{
EFI_STATUS Status;
EFI_STATUS Status1;
EFI_ACPI_DESCRIPTION_HEADER *SsdtPcieOscTemplate;
AML_ROOT_NODE_HANDLE OscTemplateRoot;
AML_OBJECT_NODE_HANDLE OscNode;
ASSERT (PciNode != NULL);
// Parse the Ssdt Pci Osc Template.
SsdtPcieOscTemplate = (EFI_ACPI_DESCRIPTION_HEADER *)
ssdtpcieosctemplate_aml_code;
OscNode = NULL;
OscTemplateRoot = NULL;
Status = AmlParseDefinitionBlock (
SsdtPcieOscTemplate,
&OscTemplateRoot
);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"ERROR: SSDT-PCI-OSC: Failed to parse SSDT PCI OSC Template."
" Status = %r\n",
Status
));
return Status;
}
Status = AmlFindNode (OscTemplateRoot, "\\_OSC", &OscNode);
if (EFI_ERROR (Status)) {
goto error_handler;
}
Status = AmlDetachNode (OscNode);
if (EFI_ERROR (Status)) {
goto error_handler;
}
Status = AmlAttachNode (PciNode, OscNode);
if (EFI_ERROR (Status)) {
// Free the detached node.
AmlDeleteTree (OscNode);
goto error_handler;
}
error_handler:
// Cleanup
Status1 = AmlDeleteTree (OscTemplateRoot);
if (EFI_ERROR (Status1)) {
DEBUG ((
DEBUG_ERROR,
"ERROR: SSDT-PCI-OSC: Failed to cleanup AML tree."
" Status = %r\n",
Status1
));
// If Status was success but we failed to delete the AML Tree
// return Status1 else return the original error code, i.e. Status.
if (!EFI_ERROR (Status)) {
return Status1;
}
}
return Status;
}

View File

@ -0,0 +1,30 @@
## @file
# Ssdt PCIe Support Library.
#
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
[Defines]
INF_VERSION = 0x0001001B
BASE_NAME = SsdtPcieSupportLib
FILE_GUID = 510451a0-60b2-446c-b6bf-59cbe4a41782
VERSION_STRING = 1.0
MODULE_TYPE = DXE_DRIVER
LIBRARY_CLASS = SsdtPcieSupportLib
[Sources]
SsdtPcieSupportLib.c
SsdtPcieSupportLibPrivate.h
SsdtPcieOscTemplate.asl
[Packages]
DynamicTablesPkg/DynamicTablesPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
AcpiHelperLib
AmlLib
BaseLib

View File

@ -0,0 +1,25 @@
/** @file
SSDT PCIe Support Library private data.
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
- PCI Firmware Specification - Revision 3.0
- ACPI 6.4 specification:
- s6.2.13 "_PRT (PCI Routing Table)"
- s6.1.1 "_ADR (Address)"
- linux kernel code
- Arm Base Boot Requirements v1.0
**/
#ifndef SSDT_PCIE_SUPPORT_LIB_PRIVATE_H_
#define SSDT_PCIE_SUPPORT_LIB_PRIVATE_H_
/** C array containing the compiled AML template.
This symbol is defined in the auto generated C file
containing the AML bytecode array.
*/
extern CHAR8 ssdtpcieosctemplate_aml_code[];
#endif // SSDT_PCIE_SUPPORT_LIB_PRIVATE_H_

View File

@ -8,6 +8,7 @@
@par Reference(s): @par Reference(s):
- Arm Server Base Boot Requirements (SBBR), s4.2.1.8 "SPCR". - Arm Server Base Boot Requirements (SBBR), s4.2.1.8 "SPCR".
- Microsoft Debug Port Table 2 (DBG2) Specification - December 10, 2015. - Microsoft Debug Port Table 2 (DBG2) Specification - December 10, 2015.
- ACPI for Arm Components 1.0 - 2020
**/ **/
#include <IndustryStandard/DebugPort2Table.h> #include <IndustryStandard/DebugPort2Table.h>
@ -176,7 +177,7 @@ FixupIds (
case EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART: case EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART:
case EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X: case EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X:
{ {
HidString = "ARMH0011"; HidString = "ARMHB000";
CidString = ""; CidString = "";
break; break;
} }

View File

@ -60,7 +60,7 @@
#define SPI_OFFSET (32U) #define SPI_OFFSET (32U)
#define DT_PPI_IRQ (1U) #define DT_PPI_IRQ (1U)
#define DT_SPI_IRQ (0U) #define DT_SPI_IRQ (0U)
#define DT_IRQ_IS_EDGE_TRIGGERED(x) ((((x) & (BIT0 | BIT2)) != 0)) #define DT_IRQ_IS_EDGE_TRIGGERED(x) ((((x) & (BIT0 | BIT1)) != 0))
#define DT_IRQ_IS_ACTIVE_LOW(x) ((((x) & (BIT1 | BIT3)) != 0)) #define DT_IRQ_IS_ACTIVE_LOW(x) ((((x) & (BIT1 | BIT3)) != 0))
#define IRQ_TYPE_OFFSET (0U) #define IRQ_TYPE_OFFSET (0U)
#define IRQ_NUMBER_OFFSET (1U) #define IRQ_NUMBER_OFFSET (1U)

View File

@ -134,6 +134,7 @@
PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf
SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf
!else !else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf

View File

@ -1187,7 +1187,7 @@ PosixFileSetInfo (
} }
OldFileName = malloc (AsciiStrSize (PrivateFile->FileName)); OldFileName = malloc (AsciiStrSize (PrivateFile->FileName));
if (OldFileInfo == NULL) { if (OldFileName == NULL) {
goto Done; goto Done;
} }

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@ -0,0 +1,54 @@
## @file
# Sec Core for FSP
#
# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspSecCoreI
FILE_GUID = 558782b5-782d-415e-ab9e-0ceb79dc3425
MODULE_TYPE = SEC
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
SecFspApiChk.c
SecFsp.h
[Sources.X64]
X64/FspApiEntryI.nasm
X64/FspApiEntryCommon.nasm
X64/FspHelper.nasm
[Sources.IA32]
Ia32/FspApiEntryI.nasm
Ia32/FspApiEntryCommon.nasm
Ia32/FspHelper.nasm
[Binaries.Ia32]
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
[Packages]
MdePkg/MdePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
BaseLib
PciCf8Lib
SerialPortLib
FspSwitchStackLib
FspCommonLib
FspSecPlatformLib

View File

@ -0,0 +1,44 @@
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
SECTION .text
;
; Following functions will be provided in C
;
extern ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; FspApiCommonContinue API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
global ASM_PFX(FspApiCommonContinue)
ASM_PFX(FspApiCommonContinue):
jmp $
;----------------------------------------------------------------------------
; FspSmmInit API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
global ASM_PFX(FspSmmInitApi)
ASM_PFX(FspSmmInitApi):
mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; Module Entrypoint API
;----------------------------------------------------------------------------
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
jmp $
; Add reference to APIs so that it will not be optimized by compiler
jmp ASM_PFX(FspSmmInitApi)

View File

@ -40,12 +40,13 @@ struc FSPM_UPD_COMMON_FSP24
.Revision: resb 1 .Revision: resb 1
.Reserved: resb 3 .Reserved: resb 3
.Length resd 1 .Length resd 1
.NvsBufferPtr resq 1
.StackBase: resq 1 .StackBase: resq 1
.StackSize: resq 1 .StackSize: resq 1
.BootLoaderTolumSize: resd 1 .BootLoaderTolumSize: resd 1
.BootMode: resd 1 .BootMode: resd 1
.FspEventHandler resq 1 .FspEventHandler resq 1
.Reserved1: resb 24 .Reserved1: resb 16
; } ; }
.size: .size:
endstruc endstruc

View File

@ -16,19 +16,20 @@
@return FSP specific IDT gate descriptor. @return FSP specific IDT gate descriptor.
**/ **/
UINT64 IA32_IDT_GATE_DESCRIPTOR
FspGetExceptionHandler ( FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate IN UINT64 IdtEntryTemplate
) )
{ {
UINT32 Entry; UINT32 Entry;
UINT64 ExceptionHandler; IA32_IDT_GATE_DESCRIPTOR ExceptionHandler;
IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;
FSP_INFO_HEADER *FspInfoHeader; FSP_INFO_HEADER *FspInfoHeader;
ZeroMem ((VOID *)&ExceptionHandler, sizeof (IA32_IDT_GATE_DESCRIPTOR));
FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader (); FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader ();
ExceptionHandler = IdtEntryTemplate; *(UINT64 *) &ExceptionHandler = IdtEntryTemplate;
IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler; IdtGateDescriptor = &ExceptionHandler;
Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;
Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1); Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);
IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16); IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);
@ -200,11 +201,11 @@ FspGlobalDataInit (
(PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \ (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \
(PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \ (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \
(PeiFspData->FspInfoHeader->HeaderRevision >= 6) ? \ (PeiFspData->FspInfoHeader->HeaderRevision >= 6) ? \
(((PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF) | (PeiFspData->FspInfoHeader->ExtendedImageRevision & 0xFF00)) :\ (((PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF) | (PeiFspData->FspInfoHeader->ExtendedImageRevision & 0xFF00)) : \
((PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF), \ ((PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF), \
(PeiFspData->FspInfoHeader->HeaderRevision >= 6) ? \ (PeiFspData->FspInfoHeader->HeaderRevision >= 6) ? \
((PeiFspData->FspInfoHeader->ImageRevision & 0xFF) | ((PeiFspData->FspInfoHeader->ExtendedImageRevision & 0xFF) << 8)): \ ((PeiFspData->FspInfoHeader->ImageRevision & 0xFF) | ((PeiFspData->FspInfoHeader->ExtendedImageRevision & 0xFF) << 8)) : \
(PeiFspData->FspInfoHeader->ImageRevision & 0xFF) (PeiFspData->FspInfoHeader->ImageRevision & 0xFF)
)); ));
} }

View File

@ -30,7 +30,7 @@
@return FSP specific IDT gate descriptor. @return FSP specific IDT gate descriptor.
**/ **/
UINT64 IA32_IDT_GATE_DESCRIPTOR
FspGetExceptionHandler ( FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate IN UINT64 IdtEntryTemplate
); );

View File

@ -71,6 +71,19 @@ FspApiCallingCheck (
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
} }
} }
} else if (ApiIdx == FspSmmInitApiIndex) {
//
// FspSmmInitApiIndex check
//
if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) || ((UINTN)FspData == MAX_UINT32)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
} else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {
Status = EFI_INVALID_PARAMETER;
}
}
} else { } else {
Status = EFI_UNSUPPORTED; Status = EFI_UNSUPPORTED;
} }

View File

@ -58,13 +58,13 @@ SecStartup (
IN UINT32 ApiIdx IN UINT32 ApiIdx
) )
{ {
EFI_SEC_PEI_HAND_OFF SecCoreData; EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack; SEC_IDT_TABLE IdtTableInStack;
UINT32 Index; UINT32 Index;
FSP_GLOBAL_DATA PeiFspData; FSP_GLOBAL_DATA PeiFspData;
UINT64 ExceptionHandler; IA32_IDT_GATE_DESCRIPTOR ExceptionHandler;
UINTN IdtSize; UINTN IdtSize;
// //
// Process all libraries constructor function linked to SecCore. // Process all libraries constructor function linked to SecCore.
@ -119,7 +119,7 @@ SecStartup (
if (IdtDescriptor.Base == 0) { if (IdtDescriptor.Base == 0) {
ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate); ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);
for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) { for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) {
CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (UINT64)); CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (IA32_IDT_GATE_DESCRIPTOR));
} }
IdtSize = sizeof (IdtTableInStack.IdtTable); IdtSize = sizeof (IdtTableInStack.IdtTable);

View File

@ -26,7 +26,7 @@
typedef typedef
VOID VOID
(EFIAPI *PEI_CORE_ENTRY) ( (EFIAPI *PEI_CORE_ENTRY)(
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
); );
@ -38,8 +38,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
// EFI_PEI_SERVICES** // EFI_PEI_SERVICES**
// //
UINT64 PeiService; UINT64 PeiService;
UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)]; IA32_IDT_GATE_DESCRIPTOR IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
} SEC_IDT_TABLE; } SEC_IDT_TABLE;
/** /**

View File

@ -24,7 +24,7 @@ STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose register *
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(NotifyPhaseApi) global ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi): ASM_PFX(NotifyPhaseApi):
mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
@ -36,7 +36,7 @@ ASM_PFX(NotifyPhaseApi):
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(FspSiliconInitApi) global ASM_PFX(FspSiliconInitApi)
ASM_PFX(FspSiliconInitApi): ASM_PFX(FspSiliconInitApi):
mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
@ -54,7 +54,7 @@ ASM_PFX(FspSiliconInitApi):
global ASM_PFX(FspMultiPhaseSiInitApi) global ASM_PFX(FspMultiPhaseSiInitApi)
ASM_PFX(FspMultiPhaseSiInitApi): ASM_PFX(FspMultiPhaseSiInitApi):
mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
@ -68,7 +68,7 @@ ASM_PFX(FspApiCommonContinue):
; ;
; Handle FspMultiPhaseSiInitApiIndex API ; Handle FspMultiPhaseSiInitApiIndex API
; ;
cmp eax, 6 cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex
jnz NotMultiPhaseSiInitApi jnz NotMultiPhaseSiInitApi
PUSHA_64 PUSHA_64

View File

@ -0,0 +1,44 @@
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
SECTION .text
;
; Following functions will be provided in C
;
extern ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; FspApiCommonContinue API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
global ASM_PFX(FspApiCommonContinue)
ASM_PFX(FspApiCommonContinue):
jmp $
;----------------------------------------------------------------------------
; FspSmmInit API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
global ASM_PFX(FspSmmInitApi)
ASM_PFX(FspSmmInitApi):
mov rax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex
jmp ASM_PFX(FspApiCommon)
;----------------------------------------------------------------------------
; Module Entrypoint API
;----------------------------------------------------------------------------
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
jmp $
; Add reference to APIs so that it will not be optimized by compiler
jmp ASM_PFX(FspSmmInitApi)

View File

@ -22,12 +22,13 @@ struc FSPM_UPD_COMMON_FSP24
.Revision: resb 1 .Revision: resb 1
.Reserved: resb 3 .Reserved: resb 3
.Length resd 1 .Length resd 1
.NvsBufferPtr resq 1
.StackBase: resq 1 .StackBase: resq 1
.StackSize: resq 1 .StackSize: resq 1
.BootLoaderTolumSize: resd 1 .BootLoaderTolumSize: resd 1
.BootMode: resd 1 .BootMode: resd 1
.FspEventHandler resq 1 .FspEventHandler resq 1
.Reserved1: resb 24 .Reserved1: resb 16
; } ; }
.size: .size:
endstruc endstruc
@ -55,7 +56,7 @@ FSP_HEADER_CFGREG_OFFSET EQU 24h
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(FspMemoryInitApi) global ASM_PFX(FspMemoryInitApi)
ASM_PFX(FspMemoryInitApi): ASM_PFX(FspMemoryInitApi):
mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
@ -66,7 +67,7 @@ ASM_PFX(FspMemoryInitApi):
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(TempRamExitApi) global ASM_PFX(TempRamExitApi)
ASM_PFX(TempRamExitApi): ASM_PFX(TempRamExitApi):
mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------

View File

@ -21,7 +21,7 @@ extern ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(NotifyPhaseApi) global ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi): ASM_PFX(NotifyPhaseApi):
mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
@ -33,7 +33,7 @@ ASM_PFX(NotifyPhaseApi):
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------
global ASM_PFX(FspSiliconInitApi) global ASM_PFX(FspSiliconInitApi)
ASM_PFX(FspSiliconInitApi): ASM_PFX(FspSiliconInitApi):
mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex
jmp ASM_PFX(FspApiCommon) jmp ASM_PFX(FspApiCommon)
;---------------------------------------------------------------------------- ;----------------------------------------------------------------------------

View File

@ -114,7 +114,7 @@ endstruc
global ASM_PFX(LoadMicrocodeDefault) global ASM_PFX(LoadMicrocodeDefault)
ASM_PFX(LoadMicrocodeDefault): ASM_PFX(LoadMicrocodeDefault):
; Inputs: ; Inputs:
; rsp -> LoadMicrocodeParams pointer ; rcx -> LoadMicrocodeParams pointer
; Register Usage: ; Register Usage:
; rsp Preserved ; rsp Preserved
; All others destroyed ; All others destroyed
@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
cmp rsp, 0 cmp rsp, 0
jz ParamError jz ParamError
mov eax, dword [rsp + 8] ; Parameter pointer cmp rcx, 0
cmp eax, 0
jz ParamError jz ParamError
mov esp, eax mov rsp, rcx
; skip loading Microcode if the MicrocodeCodeSize is zero ; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k ; and report error if size is less than 2k
@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
jne ParamError jne ParamError
; UPD structure is compliant with FSP spec 2.4 ; UPD structure is compliant with FSP spec 2.4
mov eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
cmp eax, 0 cmp rax, 0
jz Exit2 jz Exit2
cmp eax, 0800h cmp rax, 0800h
jl ParamError jl ParamError
mov esi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] mov rsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
cmp esi, 0 cmp rsi, 0
jnz CheckMainHeader jnz CheckMainHeader
ParamError: ParamError:
@ -256,7 +255,8 @@ CheckAddress:
; UPD structure is compliant with FSP spec 2.4 ; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ? ; Is automatic size detection ?
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
cmp rax, 0ffffffffffffffffh mov rcx, 0ffffffffffffffffh
cmp rax, rcx
jz LoadMicrocodeDefault4 jz LoadMicrocodeDefault4
; Address >= microcode region address + microcode region size? ; Address >= microcode region address + microcode region size?
@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
; ;
; Save parameter pointer in rdx ; Save parameter pointer in rdx
; ;
mov rdx, qword [rsp + 8] mov rdx, rcx
; ;
; Enable FSP STACK ; Enable FSP STACK
; ;
@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
; ;
ENABLE_SSE ENABLE_SSE
ENABLE_AVX ENABLE_AVX
;
; Save Input Parameter in YMM10
;
SAVE_RCX
; ;
; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6 ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
; ;
@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
; ;
; Check Parameter ; Check Parameter
; ;
mov rax, qword [rsp + 8] cmp rcx, 0
cmp rax, 0 mov rcx, 08000000000000002h
mov rax, 08000000000000002h
jz TempRamInitExit jz TempRamInitExit
; ;
@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
jnz TempRamInitExit jnz TempRamInitExit
; Load microcode ; Load microcode
LOAD_RSP LOAD_RCX
CALL_YMM ASM_PFX(LoadMicrocodeDefault) CALL_YMM ASM_PFX(LoadMicrocodeDefault)
SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits). SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 in YMM9 (upper 128bits).
; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot. ; @note If return value rax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init ; Call Sec CAR Init
LOAD_RSP LOAD_RCX
CALL_YMM ASM_PFX(SecCarInit) CALL_YMM ASM_PFX(SecCarInit)
cmp rax, 0 cmp rax, 0
jnz TempRamInitExit jnz TempRamInitExit
LOAD_RSP LOAD_RCX
CALL_YMM ASM_PFX(EstablishStackFsp) CALL_YMM ASM_PFX(EstablishStackFsp)
cmp rax, 0 cmp rax, 0
jnz TempRamInitExit jnz TempRamInitExit

View File

@ -1,6 +1,6 @@
/** @file /** @file
Intel FSP API definition from Intel Firmware Support Package External Intel FSP API definition from Intel Firmware Support Package External
Architecture Specification v2.0 - v2.2 Architecture Specification v2.0 and above.
Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR> Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -11,19 +11,24 @@
#define _FSP_API_H_ #define _FSP_API_H_
#include <Pi/PiStatusCode.h> #include <Pi/PiStatusCode.h>
#include <Base.h>
/// ///
/// FSP Reset Status code /// FSP Reset Status code
/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code /// These are defined in FSP EAS v2.4 section 13.2.2 - OEM Status Code
/// @{ /// @{
#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001
#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002 #define ENCODE_RESET_REQUEST(ResetType) \
#define FSP_STATUS_RESET_REQUIRED_3 0x40000003 ((EFI_STATUS)((MAX_BIT >> 1) | (ResetType)))
#define FSP_STATUS_RESET_REQUIRED_4 0x40000004 #define FSP_STATUS_RESET_REQUIRED_COLD ENCODE_RESET_REQUEST(1)
#define FSP_STATUS_RESET_REQUIRED_5 0x40000005 #define FSP_STATUS_RESET_REQUIRED_WARM ENCODE_RESET_REQUEST(2)
#define FSP_STATUS_RESET_REQUIRED_6 0x40000006 #define FSP_STATUS_RESET_REQUIRED_3 ENCODE_RESET_REQUEST(3)
#define FSP_STATUS_RESET_REQUIRED_7 0x40000007 #define FSP_STATUS_RESET_REQUIRED_4 ENCODE_RESET_REQUEST(4)
#define FSP_STATUS_RESET_REQUIRED_8 0x40000008 #define FSP_STATUS_RESET_REQUIRED_5 ENCODE_RESET_REQUEST(5)
#define FSP_STATUS_RESET_REQUIRED_6 ENCODE_RESET_REQUEST(6)
#define FSP_STATUS_RESET_REQUIRED_7 ENCODE_RESET_REQUEST(7)
#define FSP_STATUS_RESET_REQUIRED_8 ENCODE_RESET_REQUEST(8)
#define FSP_STATUS_VARIABLE_REQUEST ENCODE_RESET_REQUEST(10)
/// @} /// @}
/// ///
@ -95,13 +100,14 @@ typedef struct {
/// "XXXXXX_T" for FSP-T /// "XXXXXX_T" for FSP-T
/// "XXXXXX_M" for FSP-M /// "XXXXXX_M" for FSP-M
/// "XXXXXX_S" for FSP-S /// "XXXXXX_S" for FSP-S
/// "XXXXXX_I" for FSP-I
/// Where XXXXXX is an unique signature /// Where XXXXXX is an unique signature
/// ///
UINT64 Signature; UINT64 Signature;
/// ///
/// Revision of the Data structure. /// Revision of the Data structure.
/// For FSP spec 2.0/2.1 value is 1. /// For FSP spec 2.0/2.1, this value is 1 and only FSPM_UPD having ARCH_UPD.
/// For FSP spec 2.2 value is 2. /// For FSP spec 2.2 and above, this value is 2 and ARCH_UPD present in all UPD structures.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[23]; UINT8 Reserved[23];
@ -129,24 +135,24 @@ typedef struct {
} FSPT_ARCH_UPD; } FSPT_ARCH_UPD;
/// ///
/// FSPT_ARCH2_UPD Configuration. /// FSPT_ARCH2_UPD Configuration for FSP 2.4 and above.
/// ///
typedef struct { typedef struct {
/// ///
/// Revision of the structure is 2 for this version of the specification. /// Revision of the structure is 2 for this version of the specification.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Length of the structure in bytes. The current value for this field is 32. /// Length of the structure in bytes. The current value for this field is 32.
/// ///
UINT32 Length; UINT32 Length;
/// ///
/// FspDebugHandler Optional debug handler for the bootloader to receive debug messages /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
/// occurring during FSP execution. /// occurring during FSP execution.
/// ///
EFI_PHYSICAL_ADDRESS FspDebugHandler; EFI_PHYSICAL_ADDRESS FspDebugHandler;
UINT8 Reserved1[16]; UINT8 Reserved1[16];
} FSPT_ARCH2_UPD; } FSPT_ARCH2_UPD;
/// ///
@ -191,43 +197,50 @@ typedef struct {
} FSPM_ARCH_UPD; } FSPM_ARCH_UPD;
/// ///
/// FSPM_ARCH2_UPD Configuration. /// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above.
/// ///
typedef struct { typedef struct {
/// ///
/// Revision of the structure is 3 for this version of the specification. /// Revision of the structure is 3 for this version of the specification.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Length of the structure in bytes. The current value for this field is 64. /// Length of the structure in bytes. The current value for this field is 64.
/// ///
UINT32 Length; UINT32 Length;
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
/// This value is deprecated starting with v2.4 of the FSP specification,
/// and will be removed in an upcoming version of the FSP specification.
///
EFI_PHYSICAL_ADDRESS NvsBufferPtr;
/// ///
/// Pointer to the temporary stack base address to be /// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API. /// consumed inside FspMemoryInit() API.
/// ///
EFI_PHYSICAL_ADDRESS StackBase; EFI_PHYSICAL_ADDRESS StackBase;
/// ///
/// Temporary stack size to be consumed inside /// Temporary stack size to be consumed inside
/// FspMemoryInit() API. /// FspMemoryInit() API.
/// ///
UINT64 StackSize; UINT64 StackSize;
/// ///
/// Size of memory to be reserved by FSP below "top /// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage. /// of low usable memory" for bootloader usage.
/// ///
UINT32 BootLoaderTolumSize; UINT32 BootLoaderTolumSize;
/// ///
/// Current boot mode. /// Current boot mode.
/// ///
UINT32 BootMode; UINT32 BootMode;
/// ///
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution. /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
/// This value is only valid if Revision is >= 2. /// This value is only valid if Revision is >= 2.
/// ///
EFI_PHYSICAL_ADDRESS FspEventHandler; EFI_PHYSICAL_ADDRESS FspEventHandler;
UINT8 Reserved1[24]; UINT8 Reserved1[16];
} FSPM_ARCH2_UPD; } FSPM_ARCH2_UPD;
/// ///
@ -260,26 +273,60 @@ typedef struct {
} FSPS_ARCH_UPD; } FSPS_ARCH_UPD;
/// ///
/// FSPS_ARCH2_UPD Configuration. /// FSPS_ARCH2_UPD Configuration for FSP 2.4 and above.
/// ///
typedef struct { typedef struct {
/// ///
/// Revision of the structure is 2 for this version of the specification. /// Revision of the structure is 2 for this version of the specification.
/// ///
UINT8 Revision; UINT8 Revision;
UINT8 Reserved[3]; UINT8 Reserved[3];
/// ///
/// Length of the structure in bytes. The current value for this field is 32. /// Length of the structure in bytes. The current value for this field is 32.
/// ///
UINT32 Length; UINT32 Length;
/// ///
/// FspEventHandler Optional event handler for the bootloader to be informed of events /// FspEventHandler Optional event handler for the bootloader to be informed of events
/// occurring during FSP execution. /// occurring during FSP execution.
/// ///
EFI_PHYSICAL_ADDRESS FspEventHandler; EFI_PHYSICAL_ADDRESS FspEventHandler;
UINT8 Reserved1[16]; UINT8 Reserved1[16];
} FSPS_ARCH2_UPD; } FSPS_ARCH2_UPD;
///
/// FSPI_ARCH_UPD Configuration.
///
typedef struct {
///
/// Revision of the structure is 1 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Length of the structure in bytes. The current value for this field is 64.
///
UINT32 Length;
///
/// The physical memory-mapped base address of the bootloader SMM firmware volume (FV).
///
EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress;
///
/// The length in bytes of the bootloader SMM firmware volume (FV).
///
UINT64 BootloaderSmmFvLength;
///
/// The physical memory-mapped base address of the bootloader SMM FV context data.
/// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
///
EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData;
///
/// The length in bytes of the bootloader SMM FV context data.
/// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
///
UINT16 BootloaderSmmFvContextDataLength;
UINT8 Reserved1[30];
} FSPI_ARCH_UPD;
/// ///
/// FSPT_UPD_COMMON Configuration. /// FSPT_UPD_COMMON Configuration.
/// ///
@ -388,6 +435,21 @@ typedef struct {
FSPS_ARCH2_UPD FspsArchUpd; FSPS_ARCH2_UPD FspsArchUpd;
} FSPS_UPD_COMMON_FSP24; } FSPS_UPD_COMMON_FSP24;
///
/// FSPI_UPD_COMMON Configuration.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPI_ARCH_UPD Configuration.
///
FSPI_ARCH_UPD FspiArchUpd;
} FSPI_UPD_COMMON;
/// ///
/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.
/// ///
@ -609,4 +671,23 @@ EFI_STATUS
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
); );
/**
This FSP API initializes SMM and provide any OS runtime silicon services,
including Reliability, Availability, and Serviceability (RAS) features implemented by the CPU.
@param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.
If NULL, FSP will use the default parameters.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
@retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_SMM_INIT)(
IN VOID *FspiUpdDataPtr
);
#endif #endif

View File

@ -10,9 +10,9 @@
#include <FspEas.h> #include <FspEas.h>
#define FSP_IN_API_MODE 0 #define FSP_IN_API_MODE 0
#define FSP_IN_DISPATCH_MODE 1 #define FSP_IN_DISPATCH_MODE 1
#define FSP_GLOBAL_DATA_VERSION 1 #define FSP_GLOBAL_DATA_VERSION 0x2
#pragma pack(1) #pragma pack(1)
@ -24,16 +24,17 @@ typedef enum {
TempRamExitApiIndex, TempRamExitApiIndex,
FspSiliconInitApiIndex, FspSiliconInitApiIndex,
FspMultiPhaseSiInitApiIndex, FspMultiPhaseSiInitApiIndex,
FspSmmInitApiIndex,
FspApiIndexMax FspApiIndexMax
} FSP_API_INDEX; } FSP_API_INDEX;
typedef struct { typedef struct {
VOID *DataPtr; VOID *DataPtr;
UINTN MicrocodeRegionBase; UINTN MicrocodeRegionBase;
UINTN MicrocodeRegionSize; UINTN MicrocodeRegionSize;
UINTN CodeRegionBase; UINTN CodeRegionBase;
UINTN CodeRegionSize; UINTN CodeRegionSize;
UINTN Reserved; UINTN Reserved;
} FSP_PLAT_DATA; } FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
@ -48,7 +49,7 @@ typedef struct {
/// Offset 0x08 /// Offset 0x08
/// ///
UINTN CoreStack; UINTN CoreStack;
UINTN Reserved2; VOID *SmmInitUpdPtr;
/// ///
/// IA32: Offset 0x10; X64: Offset 0x18 /// IA32: Offset 0x10; X64: Offset 0x18
/// ///
@ -59,17 +60,15 @@ typedef struct {
/// ///
UINT8 FspMode; UINT8 FspMode;
UINT8 OnSeparateStack; UINT8 OnSeparateStack;
UINT8 Reserved3; UINT8 Reserved2;
UINT32 NumberOfPhases; UINT32 NumberOfPhases;
UINT32 PhasesExecuted; UINT32 PhasesExecuted;
UINT32 Reserved4[8]; UINT32 Reserved3[8];
/// ///
/// IA32: Offset 0x40; X64: Offset 0x48 /// IA32: Offset 0x40; X64: Offset 0x48
/// Start of UINTN and pointer section /// Start of UINTN and pointer section
/// All UINTN and pointer members must be put in this section /// All UINTN and pointer members are put in this section
/// except CoreStack and Reserved2. In addition, the number of /// for maintaining natural alignment for both IA32 and X64 builds.
/// UINTN and pointer members must be even for natural alignment
/// in both IA32 and X64.
/// ///
FSP_PLAT_DATA PlatformData; FSP_PLAT_DATA PlatformData;
VOID *TempRamInitUpdPtr; VOID *TempRamInitUpdPtr;
@ -85,12 +84,15 @@ typedef struct {
VOID *UpdDataPtr; VOID *UpdDataPtr;
/// ///
/// End of UINTN and pointer section /// End of UINTN and pointer section
/// At this point, next field offset must be either *0h or *8h to
/// meet natural alignment requirement.
/// ///
UINT8 Reserved5[16]; UINT8 Reserved4[16];
UINT32 PerfSig; UINT32 PerfSig;
UINT16 PerfLen; UINT16 PerfLen;
UINT16 Reserved6; UINT16 Reserved5;
UINT32 PerfIdx; UINT32 PerfIdx;
UINT32 Reserved6;
UINT64 PerfData[32]; UINT64 PerfData[32];
} FSP_GLOBAL_DATA; } FSP_GLOBAL_DATA;

View File

@ -26,13 +26,13 @@
#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0 #define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1 #define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2 #define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
#define FSP_IA32 0 #define FSP_IA32 0
#define FSP_X64 1 #define FSP_X64 1
#pragma pack(1) #pragma pack(1)
/// ///
/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1. /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
@ -52,7 +52,7 @@ typedef struct {
UINT8 Reserved1[2]; UINT8 Reserved1[2];
/// ///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format. /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23. /// For revision v2.4 the value will be 0x24.
/// ///
UINT8 SpecVersion; UINT8 SpecVersion;
/// ///
@ -93,11 +93,28 @@ typedef struct {
/// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display. /// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.
/// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4. /// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.
/// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7. /// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.
/// Bits 15:3 - Reserved /// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.
/// Bits 15:4 - Reserved
/// ///
UINT16 ImageAttribute; UINT16 ImageAttribute;
/// ///
/// Byte 0x22: Attributes of the FSP Component. /// Byte 0x22: Attributes of the FSP Component.
/// Bit 0 - Build Type
/// 0 - Debug Build
/// 1 - Release Build
/// Bit 1 - Release Type
/// 0 - Test Release
/// 1 - Official Release
/// Bit 11:2 - Reserved
/// Bits 15:12 - Component Type
/// 0000 - Reserved
/// 0001 - FSP-T
/// 0010 - FSP-M
/// 0011 - FSP-S
/// 0100 - FSP-I (FSP SMM)
/// 0101 to 0111 - Reserved
/// 1000 - FSP-O
/// 1001 to 1111 - Reserved
/// ///
UINT16 ComponentAttribute; UINT16 ComponentAttribute;
/// ///
@ -159,6 +176,14 @@ typedef struct {
/// Byte 0x4E: Reserved4. /// Byte 0x4E: Reserved4.
/// ///
UINT16 Reserved4; UINT16 Reserved4;
///
/// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
///
UINT32 FspMultiPhaseMemInitEntryOffset;
///
/// Byte 0x54: Offset for the API to initialize SMM.
///
UINT32 FspSmmInitEntryOffset;
} FSP_INFO_HEADER; } FSP_INFO_HEADER;
/// ///
@ -240,7 +265,7 @@ typedef struct {
// UINT32 PatchData[]; // UINT32 PatchData[];
} FSP_PATCH_TABLE; } FSP_PATCH_TABLE;
#pragma pack() #pragma pack()
extern EFI_GUID gFspHeaderFileGuid; extern EFI_GUID gFspHeaderFileGuid;

View File

@ -302,7 +302,7 @@ SetPhaseStatusCode (
VOID VOID
EFIAPI EFIAPI
FspApiReturnStatusReset ( FspApiReturnStatusReset (
IN UINT32 FspResetType IN EFI_STATUS FspResetType
); );
#endif #endif

View File

@ -30,7 +30,7 @@
**/ **/
UINT32 EFI_STATUS
EFIAPI EFIAPI
Pei2LoaderSwitchStack ( Pei2LoaderSwitchStack (
VOID VOID
@ -46,7 +46,7 @@ Pei2LoaderSwitchStack (
**/ **/
UINT32 EFI_STATUS
EFIAPI EFIAPI
Loader2PeiSwitchStack ( Loader2PeiSwitchStack (
VOID VOID

View File

@ -0,0 +1,195 @@
/** @file
EDKII PEI Variable PPI provides an implementation of variables
intended for use as a means to store data in the PEI environment.
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef EDKII_PEI_VARIABLE_PPI_H_
#define EDKII_PEI_VARIABLE_PPI_H_
#define EDKII_PEI_VARIABLE_PPI_GUID \
{ \
0xe7b2cd04, 0x4b14, 0x44c2, { 0xb7, 0x48, 0xce, 0xaf, 0x2b, 0x66, 0x4a, 0xb0 } \
}
typedef struct _EDKII_PEI_VARIABLE_PPI EDKII_PEI_VARIABLE_PPI;
/**
This service retrieves a variable's value using its name and GUID.
Read the specified variable from the UEFI variable store. If the Data
buffer is too small to hold the contents of the variable,
the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
required buffer size to obtain the data.
@param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
@param[in] VariableName A pointer to a null-terminated string that is the variable's name.
@param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
VariableGuid and VariableName must be unique.
@param[out] Attributes If non-NULL, on return, points to the variable's attributes.
@param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
On return, points to the size of the data returned in Data.
@param[out] Data Points to the buffer which will hold the returned variable value.
May be NULL with a zero DataSize in order to determine the size of the
buffer needed.
@retval EFI_SUCCESS The variable was read successfully.
@retval EFI_NOT_FOUND The variable was not found.
@retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
DataSize is updated with the size required for
the specified variable.
@retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
@retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
**/
typedef
EFI_STATUS
(EFIAPI *EDKII_PEI_GET_VARIABLE)(
IN CONST EDKII_PEI_VARIABLE_PPI *This,
IN CONST CHAR16 *VariableName,
IN CONST EFI_GUID *VariableGuid,
OUT UINT32 *Attributes OPTIONAL,
IN OUT UINTN *DataSize,
OUT VOID *Data OPTIONAL
);
/**
Return the next variable name and GUID.
This function is called multiple times to retrieve the VariableName
and VariableGuid of all variables currently available in the system.
On each call, the previous results are passed into the interface,
and, on return, the interface returns the data for the next
variable. To get started, VariableName should initially contain L"\0"
and VariableNameSize should be sizeof(CHAR16). When the entire
variable list has been returned, EFI_NOT_FOUND is returned.
@param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
@param[in, out] VariableNameSize On entry, points to the size of the buffer pointed to by VariableName.
On return, the size of the variable name buffer.
@param[in, out] VariableName On entry, a pointer to a null-terminated string that is the variable's name.
On return, points to the next variable's null-terminated name string.
@param[in, out] VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID.
On return, a pointer to the next variable's GUID.
@retval EFI_SUCCESS The next variable name was read successfully.
@retval EFI_NOT_FOUND All variables have been enumerated.
@retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting
data. VariableNameSize is updated with the size
required for the specified variable.
@retval EFI_INVALID_PARAMETER VariableName, VariableGuid or
VariableNameSize is NULL.
@retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
**/
typedef
EFI_STATUS
(EFIAPI *EDKII_PEI_GET_NEXT_VARIABLE_NAME)(
IN CONST EDKII_PEI_VARIABLE_PPI *This,
IN OUT UINTN *VariableNameSize,
IN OUT CHAR16 *VariableName,
IN OUT EFI_GUID *VariableGuid
);
/**
Sets the value of a variable.
@param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
@param[in] VariableName A Null-terminated string that is the name of the vendor's variable.
Each VariableName is unique for each VendorGuid. VariableName must
contain 1 or more characters. If VariableName is an empty string,
then EFI_INVALID_PARAMETER is returned.
@param[in] VendorGuid A unique identifier for the vendor.
@param[in] Attributes Attributes bitmask to set for the variable.
@param[in] DataSize The size in bytes of the Data buffer. Unless the EFI_VARIABLE_APPEND_WRITE
attribute is set, a size of zero causes the variable to be deleted. When the
EFI_VARIABLE_APPEND_WRITE attribute is set, then a SetVariable() call with a
DataSize of zero will not cause any change to the variable value.
@param[in] Data The contents for the variable.
@retval EFI_SUCCESS The firmware has successfully stored the variable and its data as
defined by the Attributes.
@retval EFI_INVALID_PARAMETER An invalid combination of attribute bits, name, and GUID was supplied, or the
DataSize exceeds the maximum allowed.
@retval EFI_INVALID_PARAMETER VariableName is an empty string.
@retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data.
@retval EFI_DEVICE_ERROR The variable could not be stored due to a hardware error.
@retval EFI_WRITE_PROTECTED The variable in question is read-only.
@retval EFI_WRITE_PROTECTED The variable in question cannot be deleted.
@retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS,
or EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS, or
EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS being set. Writing to authenticated
variables is not supported in the PEI environment. Updates to authenticated
variables can be requested during PEI via the EFI_AUTHENTICATED_VARIABLE_HOB, but
these updates won't be written to non-volatile storage until later in DXE.
The EFI_AUTHENTICATED_VARIABLE_HOB is a HOB with the GUID
gEfiAuthenticatedVariableGuid. This HOB contains a VARIABLE_STORE_HEADER followed
by one or more UEFI variables, which are stored as DWORD aligned tuples of
(VARIABLE_HEADER + CHAR16 VariableName + VariableData).
See MdeModulePkg/Include/Guid/VariableFormat.h for these data structure
definitions and MdeModulePkg/Universal/Variable/RuntimeDxe/VariableParsing.c for
an example of how to parse these data structures.
@retval EFI_NOT_FOUND The variable trying to be updated or deleted was not found.
**/
typedef
EFI_STATUS
(EFIAPI *EDKII_PEI_SET_VARIABLE)(
IN CONST EDKII_PEI_VARIABLE_PPI *This,
IN CHAR16 *VariableName,
IN EFI_GUID *VendorGuid,
IN UINT32 Attributes,
IN UINTN DataSize,
IN VOID *Data
);
/**
Returns information about the UEFI variables.
@param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
@param[in] Attributes Attributes bitmask to specify the type of variables on
which to return information.
@param[out] MaximumVariableStorageSize On output the maximum size of the storage space
available for the EFI variables associated with the
attributes specified.
@param[out] RemainingVariableStorageSize Returns the remaining size of the storage space
available for the EFI variables associated with the
attributes specified.
@param[out] MaximumVariableSize Returns the maximum size of the individual EFI
variables associated with the attributes specified.
@retval EFI_SUCCESS Valid answer returned.
@retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied
@retval EFI_UNSUPPORTED The attribute is not supported on this platform, and the
MaximumVariableStorageSize,
RemainingVariableStorageSize, MaximumVariableSize
are undefined.
**/
typedef
EFI_STATUS
(EFIAPI *EDKII_PEI_QUERY_VARIABLE_INFO)(
IN CONST EDKII_PEI_VARIABLE_PPI *This,
IN UINT32 Attributes,
OUT UINT64 *MaximumVariableStorageSize,
OUT UINT64 *RemainingVariableStorageSize,
OUT UINT64 *MaximumVariableSize
);
///
/// PEI Variable PPI is intended for use as a means
/// to store data in the PEI environment.
///
struct _EDKII_PEI_VARIABLE_PPI {
EDKII_PEI_GET_VARIABLE GetVariable;
EDKII_PEI_GET_NEXT_VARIABLE_NAME GetNextVariableName;
EDKII_PEI_SET_VARIABLE SetVariable;
EDKII_PEI_QUERY_VARIABLE_INFO QueryVariableInfo;
};
extern EFI_GUID gEdkiiPeiVariablePpiGuid;
#endif

View File

@ -177,6 +177,30 @@
LXMMN xmm5, %1, 1 LXMMN xmm5, %1, 1
%endmacro %endmacro
;
; Upper half of YMM10 to save/restore RCX
;
;
; Save RCX to YMM10[128:191]
; Modified: XMM5 and YMM10
;
%macro SAVE_RCX 0
LYMMN ymm10, xmm5, 1
SXMMN xmm5, 0, rcx
SYMMN ymm10, 1, xmm5
%endmacro
;
; Restore RCX from YMM10[128:191]
; Modified: XMM5 and RCX
;
%macro LOAD_RCX 0
LYMMN ymm10, xmm5, 1
movq rcx, xmm5
%endmacro
; ;
; YMM7[128:191] for calling stack ; YMM7[128:191] for calling stack
; arg 1:Entry ; arg 1:Entry
@ -231,6 +255,7 @@ NextAddress:
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction. ; whether the processor supports SSE instruction.
; ;
mov r10, rcx
mov rax, 1 mov rax, 1
cpuid cpuid
bt rdx, 25 bt rdx, 25
@ -241,6 +266,7 @@ NextAddress:
; ;
bt ecx, 19 bt ecx, 19
jnc SseError jnc SseError
mov rcx, r10
; ;
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@ -258,6 +284,7 @@ NextAddress:
%endmacro %endmacro
%macro ENABLE_AVX 0 %macro ENABLE_AVX 0
mov r10, rcx
mov eax, 1 mov eax, 1
cpuid cpuid
and ecx, 10000000h and ecx, 10000000h
@ -280,5 +307,6 @@ EnableAvx:
xgetbv ; result in edx:eax xgetbv ; result in edx:eax
or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state
xsetbv xsetbv
mov rcx, r10
%endmacro %endmacro

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@ -1,7 +1,7 @@
## @file ## @file
# Provides driver and definitions to build fsp in EDKII bios. # Provides driver and definitions to build fsp in EDKII bios.
# #
# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
## ##
@ -59,6 +59,12 @@
# #
gFspTempRamExitPpiGuid = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}} gFspTempRamExitPpiGuid = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
#
# PPI for Variable Services
#
gEdkiiPeiVariablePpiGuid = { 0xe7b2cd04, 0x4b14, 0x44c2, {0xb7, 0x48, 0xce, 0xaf, 0x2b, 0x66, 0x4a, 0xb0}}
[Guids] [Guids]
# #
# GUID defined in package # GUID defined in package

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@ -68,6 +68,7 @@
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf

View File

@ -200,13 +200,13 @@ SetFspCoreStackPointer (
UINT32 StackContextLen; UINT32 StackContextLen;
FspData = GetFspGlobalDataPointer (); FspData = GetFspGlobalDataPointer ();
StackContextLen = sizeof(CONTEXT_STACK) / sizeof(UINTN); StackContextLen = sizeof (CONTEXT_STACK) / sizeof (UINTN);
// //
// Reserve space for the ContinuationFunc two parameters // Reserve space for the ContinuationFunc two parameters
// //
OldStack = (UINTN *)FspData->CoreStack; OldStack = (UINTN *)FspData->CoreStack;
NewStack = (UINTN *)NewStackTop - StackContextLen - 2; NewStack = (UINTN *)NewStackTop - StackContextLen - 2;
FspData->CoreStack = (UINTN)NewStack; FspData->CoreStack = (UINTN)NewStack;
while (StackContextLen-- != 0) { while (StackContextLen-- != 0) {
*NewStack++ = *OldStack++; *NewStack++ = *OldStack++;
@ -533,7 +533,7 @@ SetPhaseStatusCode (
VOID VOID
EFIAPI EFIAPI
FspApiReturnStatusReset ( FspApiReturnStatusReset (
IN UINT32 FspResetType IN EFI_STATUS FspResetType
) )
{ {
volatile BOOLEAN LoopUntilReset; volatile BOOLEAN LoopUntilReset;
@ -546,7 +546,7 @@ FspApiReturnStatusReset (
/// calls the FSP API without honoring the reset request by FSP /// calls the FSP API without honoring the reset request by FSP
/// ///
do { do {
SetFspApiReturnStatus ((EFI_STATUS)FspResetType); SetFspApiReturnStatus (FspResetType);
Pei2LoaderSwitchStack (); Pei2LoaderSwitchStack ();
DEBUG ((DEBUG_ERROR, "!!!ERROR: FSP has requested BootLoader for reset. But BootLoader has not honored the reset\n")); DEBUG ((DEBUG_ERROR, "!!!ERROR: FSP has requested BootLoader for reset. But BootLoader has not honored the reset\n"));
DEBUG ((DEBUG_ERROR, "!!!ERROR: Please add support in BootLoader to honor the reset request from FSP\n")); DEBUG ((DEBUG_ERROR, "!!!ERROR: Please add support in BootLoader to honor the reset request from FSP\n"));

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@ -13,6 +13,7 @@ import tkinter.ttk as ttk
import tkinter.messagebox as messagebox import tkinter.messagebox as messagebox
import tkinter.filedialog as filedialog import tkinter.filedialog as filedialog
from pickle import FALSE, TRUE
from pathlib import Path from pathlib import Path
from GenYamlCfg import CGenYamlCfg, bytes_to_value, \ from GenYamlCfg import CGenYamlCfg, bytes_to_value, \
bytes_to_bracket_str, value_to_bytes, array_str_to_value bytes_to_bracket_str, value_to_bytes, array_str_to_value
@ -458,7 +459,10 @@ class FSP_INFORMATION_HEADER(Structure):
('NotifyPhaseEntryOffset', c_uint32), ('NotifyPhaseEntryOffset', c_uint32),
('FspMemoryInitEntryOffset', c_uint32), ('FspMemoryInitEntryOffset', c_uint32),
('TempRamExitEntryOffset', c_uint32), ('TempRamExitEntryOffset', c_uint32),
('FspSiliconInitEntryOffset', c_uint32) ('FspSiliconInitEntryOffset', c_uint32),
('FspMultiPhaseSiInitEntryOffset', c_uint32),
('ExtendedImageRevision', c_uint16),
('Reserved4', c_uint16)
] ]
@ -700,6 +704,34 @@ class FirmwareDevice:
raise Exception("ERROR: Incorrect FV size in image !") raise Exception("ERROR: Incorrect FV size in image !")
self.CheckFsp() self.CheckFsp()
def IsIntegerType(self, val):
if sys.version_info[0] < 3:
if type(val) in (int, long):
return True
else:
if type(val) is int:
return True
return False
def ConvertRevisionString(self, obj):
for field in obj._fields_:
key = field[0]
val = getattr(obj, key)
rep = ''
if self.IsIntegerType(val):
if (key == 'ImageRevision'):
FspImageRevisionMajor = ((val >> 24) & 0xFF)
FspImageRevisionMinor = ((val >> 16) & 0xFF)
FspImageRevisionRevision = ((val >> 8) & 0xFF)
FspImageRevisionBuildNumber = (val & 0xFF)
rep = '0x%08X' % val
elif (key == 'ExtendedImageRevision'):
FspImageRevisionRevision |= (val & 0xFF00)
FspImageRevisionBuildNumber |= ((val << 8) & 0xFF00)
rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val, FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision, FspImageRevisionBuildNumber)
return rep
def OutputFsp(self): def OutputFsp(self):
def copy_text_to_clipboard(): def copy_text_to_clipboard():
window.clipboard_clear() window.clipboard_clear()
@ -721,7 +753,8 @@ class FirmwareDevice:
self.OutputText = self.OutputText + "Fsp Header Details \n\n" self.OutputText = self.OutputText + "Fsp Header Details \n\n"
while i < len(self.FihList): while i < len(self.FihList):
try: try:
self.OutputText += str(self.BuildList[i].decode()) + "\n" # self.OutputText += str(self.BuildList[i].decode()) + "\n"
self.OutputText += str(self.BuildList[i]) + "\n"
except Exception: except Exception:
self.OutputText += "No description found\n" self.OutputText += "No description found\n"
self.OutputText += "FSP Header :\n " self.OutputText += "FSP Header :\n "
@ -729,6 +762,8 @@ class FirmwareDevice:
str(self.FihList[i].Signature.decode('utf-8')) + "\n " str(self.FihList[i].Signature.decode('utf-8')) + "\n "
self.OutputText += "Header Length : " + \ self.OutputText += "Header Length : " + \
str(hex(self.FihList[i].HeaderLength)) + "\n " str(hex(self.FihList[i].HeaderLength)) + "\n "
self.OutputText += "Reserved1 : " + \
str(hex(self.FihList[i].Reserved1)) + "\n "
self.OutputText += "Header Revision : " + \ self.OutputText += "Header Revision : " + \
str(hex(self.FihList[i].HeaderRevision)) + "\n " str(hex(self.FihList[i].HeaderRevision)) + "\n "
self.OutputText += "Spec Version : " + \ self.OutputText += "Spec Version : " + \
@ -743,15 +778,17 @@ class FirmwareDevice:
str(hex(self.FihList[i].ImageBase)) + "\n " str(hex(self.FihList[i].ImageBase)) + "\n "
self.OutputText += "Image Attribute : " + \ self.OutputText += "Image Attribute : " + \
str(hex(self.FihList[i].ImageAttribute)) + "\n " str(hex(self.FihList[i].ImageAttribute)) + "\n "
self.OutputText += "Component Attribute : " + \
str(hex(self.FihList[i].ComponentAttribute)) + "\n "
self.OutputText += "Cfg Region Offset : " + \ self.OutputText += "Cfg Region Offset : " + \
str(hex(self.FihList[i].CfgRegionOffset)) + "\n " str(hex(self.FihList[i].CfgRegionOffset)) + "\n "
self.OutputText += "Cfg Region Size : " + \ self.OutputText += "Cfg Region Size : " + \
str(hex(self.FihList[i].CfgRegionSize)) + "\n " str(hex(self.FihList[i].CfgRegionSize)) + "\n "
self.OutputText += "API Entry Num : " + \ self.OutputText += "Reserved2 : " + \
str(hex(self.FihList[i].Reserved2)) + "\n " str(hex(self.FihList[i].Reserved2)) + "\n "
self.OutputText += "Temp Ram Init Entry : " + \ self.OutputText += "Temp Ram Init Entry : " + \
str(hex(self.FihList[i].TempRamInitEntryOffset)) + "\n " str(hex(self.FihList[i].TempRamInitEntryOffset)) + "\n "
self.OutputText += "FSP Init Entry : " + \ self.OutputText += "Reserved3 : " + \
str(hex(self.FihList[i].Reserved3)) + "\n " str(hex(self.FihList[i].Reserved3)) + "\n "
self.OutputText += "Notify Phase Entry : " + \ self.OutputText += "Notify Phase Entry : " + \
str(hex(self.FihList[i].NotifyPhaseEntryOffset)) + "\n " str(hex(self.FihList[i].NotifyPhaseEntryOffset)) + "\n "
@ -760,7 +797,23 @@ class FirmwareDevice:
self.OutputText += "Temp Ram Exit Entry : " + \ self.OutputText += "Temp Ram Exit Entry : " + \
str(hex(self.FihList[i].TempRamExitEntryOffset)) + "\n " str(hex(self.FihList[i].TempRamExitEntryOffset)) + "\n "
self.OutputText += "Fsp Silicon Init Entry : " + \ self.OutputText += "Fsp Silicon Init Entry : " + \
str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n\n" str(hex(self.FihList[i].FspSiliconInitEntryOffset)) + "\n "
self.OutputText += "Fsp Multi Phase Si Init Entry : " + \
str(hex(self.FihList[i].FspMultiPhaseSiInitEntryOffset)) + "\n "
# display ExtendedImageRevision & Reserved4 if HeaderRevision >= 6
for fsp in self.FihList:
if fsp.HeaderRevision >= 6:
Display_ExtndImgRev = TRUE
else:
Display_ExtndImgRev = FALSE
self.OutputText += "\n"
if Display_ExtndImgRev == TRUE:
self.OutputText += "ExtendedImageRevision : " + \
str(self.ConvertRevisionString(self.FihList[i])) + "\n "
self.OutputText += "Reserved4 : " + \
str(hex(self.FihList[i].Reserved4)) + "\n\n"
self.OutputText += "FSP Extended Header:\n " self.OutputText += "FSP Extended Header:\n "
self.OutputText += "Signature : " + \ self.OutputText += "Signature : " + \
str(self.FspExtList[i].Signature.decode('utf-8')) + "\n " str(self.FspExtList[i].Signature.decode('utf-8')) + "\n "

View File

@ -929,17 +929,25 @@ into %d bytes !" % (value_str, length))
]]: ]]:
tmp_list.append((op_val, op_str)) tmp_list.append((op_val, op_str))
else: else:
opt_list = item['option'].split(',') if item['option'].find(';') != -1:
opt_list = item['option'].split(';')
else:
opt_list = re.split(', ', item['option'])
for option in opt_list: for option in opt_list:
option = option.strip() option = option.strip()
try: try:
(op_val, op_str) = option.split(':') if option.find(':') != -1:
(op_val, op_str) = option.split(':')
else:
op_val = option
op_str = option
except Exception: except Exception:
raise SystemExit("Exception: Invalide \ raise SystemExit("Exception: Invalid \
option format '%s' !" % option) option format '%s' !" % option)
tmp_list.append((op_val, op_str)) tmp_list.append((op_val, op_str))
return tmp_list return tmp_list
def get_page_title(self, page_id, top=None): def get_page_title(self, page_id, top=None):
if top is None: if top is None:
top = self.get_cfg_page()['root'] top = self.get_cfg_page()['root']

View File

@ -953,14 +953,19 @@ EndList
return NoFileChange return NoFileChange
def CreateSplitUpdTxt (self, UpdTxtFile): def CreateSplitUpdTxt (self, UpdTxtFile):
GuidList = ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID'] GuidList = ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID','FSP_I_UPD_TOOL_GUID']
SignatureList = ['0x545F', '0x4D5F','0x535F'] # _T, _M, and _S signature for FSPT, FSPM, FSPS SignatureList = ['0x545F', '0x4D5F','0x535F','0x495F'] # _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI
for Index in range(len(GuidList)): for Index in range(len(GuidList)):
UpdTxtFile = '' UpdTxtFile = ''
FvDir = self._FvDir FvDir = self._FvDir
if GuidList[Index] not in self._MacroDict: if GuidList[Index] not in self._MacroDict:
self.Error = "%s definition is missing in DSC file" % (GuidList[Index]) NoFSPI = False
return 1 if GuidList[Index] == 'FSP_I_UPD_TOOL_GUID':
NoFSPI = True
continue
else:
self.Error = "%s definition is missing in DSC file" % (GuidList[Index])
return 1
if UpdTxtFile == '': if UpdTxtFile == '':
UpdTxtFile = os.path.join(FvDir, self._MacroDict[GuidList[Index]] + '.txt') UpdTxtFile = os.path.join(FvDir, self._MacroDict[GuidList[Index]] + '.txt')
@ -1288,19 +1293,22 @@ EndList
Chars.append(chr(Value & 0xFF)) Chars.append(chr(Value & 0xFF))
Value = Value >> 8 Value = Value >> 8
SignatureStr = ''.join(Chars) SignatureStr = ''.join(Chars)
# Signature will be _T / _M / _S for FSPT / FSPM / FSPS accordingly # Signature will be _T / _M / _S / _I for FSPT / FSPM / FSPS /FSPI accordingly
if '_T' in SignatureStr[6:6+2]: if '_T' in SignatureStr[6:6+2]:
TxtBody.append("#define FSPT_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) TxtBody.append("#define FSPT_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))
elif '_M' in SignatureStr[6:6+2]: elif '_M' in SignatureStr[6:6+2]:
TxtBody.append("#define FSPM_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) TxtBody.append("#define FSPM_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))
elif '_S' in SignatureStr[6:6+2]: elif '_S' in SignatureStr[6:6+2]:
TxtBody.append("#define FSPS_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) TxtBody.append("#define FSPS_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))
elif '_I' in SignatureStr[6:6+2]:
if NoFSPI == False:
TxtBody.append("#define FSPI_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))
TxtBody.append("\n") TxtBody.append("\n")
for Region in ['UPD']: for Region in ['UPD']:
UpdOffsetTable = [] UpdOffsetTable = []
UpdSignature = ['0x545F', '0x4D5F', '0x535F'] #['_T', '_M', '_S'] signature for FSPT, FSPM, FSPS UpdSignature = ['0x545F', '0x4D5F', '0x535F', '0x495F'] #['_T', '_M', '_S', '_I'] signature for FSPT, FSPM, FSPS, FSPI
UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD'] UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD', 'FSPI_UPD']
for Item in self._CfgItemList: for Item in self._CfgItemList:
if Item["cname"] == 'Signature' and Item["value"][0:6] in UpdSignature: if Item["cname"] == 'Signature' and Item["value"][0:6] in UpdSignature:
Item["offset"] = 0 # re-initialize offset to 0 when new UPD structure starting Item["offset"] = 0 # re-initialize offset to 0 when new UPD structure starting
@ -1393,11 +1401,12 @@ EndList
HeaderTFileName = 'FsptUpd.h' HeaderTFileName = 'FsptUpd.h'
HeaderMFileName = 'FspmUpd.h' HeaderMFileName = 'FspmUpd.h'
HeaderSFileName = 'FspsUpd.h' HeaderSFileName = 'FspsUpd.h'
HeaderIFileName = 'FspiUpd.h'
UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS', 'FSPI'] # FSPX_UPD_REGION
UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S', 'FSP_I'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG
UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE'] UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE', 'FSPI_UPD_SIGNATURE']
ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD'] ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD', 'FSPI_ARCH_UPD']
ExcludedSpecificUpd1 = ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSPS_ARCH2_UPD'] ExcludedSpecificUpd1 = ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSPS_ARCH2_UPD']
IncLines = [] IncLines = []
@ -1420,6 +1429,9 @@ EndList
elif UpdRegionCheck[item] == 'FSPS': elif UpdRegionCheck[item] == 'FSPS':
HeaderFd = open(os.path.join(FvDir, HeaderSFileName), "w") HeaderFd = open(os.path.join(FvDir, HeaderSFileName), "w")
FileBase = os.path.basename(os.path.join(FvDir, HeaderSFileName)) FileBase = os.path.basename(os.path.join(FvDir, HeaderSFileName))
elif UpdRegionCheck[item] == 'FSPI':
HeaderFd = open(os.path.join(FvDir, HeaderIFileName), "w")
FileBase = os.path.basename(os.path.join(FvDir, HeaderIFileName))
FileName = FileBase.replace(".", "_").upper() FileName = FileBase.replace(".", "_").upper()
HeaderFd.write("%s\n" % (__copyright_h__ % date.today().year)) HeaderFd.write("%s\n" % (__copyright_h__ % date.today().year))
HeaderFd.write("#ifndef __%s__\n" % FileName) HeaderFd.write("#ifndef __%s__\n" % FileName)
@ -1696,7 +1708,7 @@ EndList
def Usage(): def Usage():
print ("GenCfgOpt Version 0.57") print ("GenCfgOpt Version 0.59")
print ("Usage:") print ("Usage:")
print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]") print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]")
print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]") print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]")

View File

@ -1,6 +1,6 @@
## @ SplitFspBin.py ## @ SplitFspBin.py
# #
# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
## ##
@ -492,7 +492,7 @@ class FspImage:
self.FihOffset = fihoff self.FihOffset = fihoff
self.Offset = offset self.Offset = offset
self.FvIdxList = [] self.FvIdxList = []
self.Type = "XTMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F] self.Type = "XTMSIXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]
self.PatchList = patch self.PatchList = patch
self.PatchList.append(fihoff + 0x1C) self.PatchList.append(fihoff + 0x1C)
@ -869,7 +869,7 @@ def main ():
parser_rebase = subparsers.add_parser('rebase', help='rebase a FSP into a new base address') parser_rebase = subparsers.add_parser('rebase', help='rebase a FSP into a new base address')
parser_rebase.set_defaults(which='rebase') parser_rebase.set_defaults(which='rebase')
parser_rebase.add_argument('-f', '--fspbin' , dest='FspBinary', type=str, help='FSP binary file path', required = True) parser_rebase.add_argument('-f', '--fspbin' , dest='FspBinary', type=str, help='FSP binary file path', required = True)
parser_rebase.add_argument('-c', '--fspcomp', choices=['t','m','s','o'], nargs='+', dest='FspComponent', type=str, help='FSP component to rebase', default = "['t']", required = True) parser_rebase.add_argument('-c', '--fspcomp', choices=['t','m','s','o','i'], nargs='+', dest='FspComponent', type=str, help='FSP component to rebase', default = "['t']", required = True)
parser_rebase.add_argument('-b', '--newbase', dest='FspBase', nargs='+', type=str, help='Rebased FSP binary file name', default = '', required = True) parser_rebase.add_argument('-b', '--newbase', dest='FspBase', nargs='+', type=str, help='Rebased FSP binary file name', default = '', required = True)
parser_rebase.add_argument('-o', '--outdir' , dest='OutputDir', type=str, help='Output directory path', default = '.') parser_rebase.add_argument('-o', '--outdir' , dest='OutputDir', type=str, help='Output directory path', default = '.')
parser_rebase.add_argument('-n', '--outfile', dest='OutputFile', type=str, help='Rebased FSP binary file name', default = '') parser_rebase.add_argument('-n', '--outfile', dest='OutputFile', type=str, help='Rebased FSP binary file name', default = '')

View File

@ -97,7 +97,7 @@ OnPciEnumerationComplete (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {
@ -140,7 +140,7 @@ OnReadyToBoot (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {
@ -184,7 +184,7 @@ OnEndOfFirmware (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {

View File

@ -43,16 +43,15 @@ extern EFI_GUID gFspHobGuid;
@return FSP-M UPD Data Address @return FSP-M UPD Data Address
**/ **/
UINTN UINTN
GetFspmUpdDataAddress ( GetFspmUpdDataAddress (
VOID VOID
) )
{ {
if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) { if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64); return (UINTN)PcdGet64 (PcdFspmUpdDataAddress64);
} else { } else {
return (UINTN) PcdGet32 (PcdFspmUpdDataAddress); return (UINTN)PcdGet32 (PcdFspmUpdDataAddress);
} }
} }
@ -97,7 +96,7 @@ PeiFspMemoryInit (
// //
// External UPD is ready, get the buffer from PCD pointer. // External UPD is ready, get the buffer from PCD pointer.
// //
FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress(); FspmUpdDataPtr = (VOID *)GetFspmUpdDataAddress ();
ASSERT (FspmUpdDataPtr != NULL); ASSERT (FspmUpdDataPtr != NULL);
} }
@ -115,6 +114,7 @@ PeiFspMemoryInit (
DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize)); DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootMode)); DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
} }
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr)); DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr));
TimeStampCounterStart = AsmReadTsc (); TimeStampCounterStart = AsmReadTsc ();
@ -129,7 +129,7 @@ PeiFspMemoryInit (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

View File

@ -96,7 +96,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot; NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
@ -108,7 +108,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware; NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;
@ -120,7 +120,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@ -186,16 +186,15 @@ FspSiliconInitDoneGetFspHobList (
@return FSP-S UPD Data Address @return FSP-S UPD Data Address
**/ **/
UINTN UINTN
GetFspsUpdDataAddress ( GetFspsUpdDataAddress (
VOID VOID
) )
{ {
if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) { if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64); return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64);
} else { } else {
return (UINTN) PcdGet32 (PcdFspsUpdDataAddress); return (UINTN)PcdGet32 (PcdFspsUpdDataAddress);
} }
} }
@ -310,7 +309,7 @@ PeiMemoryDiscoveredNotify (
SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset); SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize); CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else { } else {
FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress(); FspsUpdDataPtr = (FSPS_UPD_COMMON *)GetFspsUpdDataAddress ();
ASSERT (FspsUpdDataPtr != NULL); ASSERT (FspsUpdDataPtr != NULL);
} }
@ -327,7 +326,7 @@ PeiMemoryDiscoveredNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

View File

@ -74,7 +74,7 @@ GetS3MemoryInfo (
VOID VOID
EFIAPI EFIAPI
CallFspWrapperResetSystem ( CallFspWrapperResetSystem (
IN UINT32 FspStatusResetType IN EFI_STATUS FspStatusResetType
); );
#endif #endif

View File

@ -121,6 +121,10 @@ Execute32BitCode (
// //
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
Status = AsmExecute32BitCode (Function, Param1, Param2, &mGdt); Status = AsmExecute32BitCode (Function, Param1, Param2, &mGdt);
//
// Convert FSP Status code from 32bit to 64bit to match caller expectation.
//
Status = (Status & ~(BIT31 + BIT30)) | LShiftU64 (Status & (BIT31 + BIT30), 32);
AsmWriteIdtr (&Idtr); AsmWriteIdtr (&Idtr);
return Status; return Status;
@ -150,4 +154,3 @@ Execute64BitCode (
return Status; return Status;
} }

View File

@ -86,7 +86,7 @@ GetS3MemoryInfo (
VOID VOID
EFIAPI EFIAPI
CallFspWrapperResetSystem ( CallFspWrapperResetSystem (
IN UINT32 FspStatusResetType IN EFI_STATUS FspStatusResetType
) )
{ {
// //

View File

@ -130,6 +130,9 @@ FspHeaderFound:
mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
; Pass Fsp T Upd pointer as Input parameter
mov rcx, ASM_PFX(FsptUpdDataPtr)
; Setup the hardcode stack ; Setup the hardcode stack
mov rsp, TempRamInitStack mov rsp, TempRamInitStack
@ -167,5 +170,4 @@ FspApiFailed:
align 10h align 10h
TempRamInitStack: TempRamInitStack:
DQ TempRamInitDone DQ TempRamInitDone
DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams

View File

@ -99,8 +99,8 @@ M: Ard Biesheuvel <ardb+tianocore@kernel.org> [ardbiesheuvel]
RISCV64 RISCV64
F: */RiscV64/ F: */RiscV64/
M: Abner Chang <abner.chang@hpe.com> [changab] M: Sunil V L <sunilvl@ventanamicro.com> [vlsunil]
R: Daniel Schaefer <daniel.schaefer@hpe.com> R: Daniel Schaefer <git@danielschaefer.me> [JohnAZoidberg]
EDK II Continuous Integration: EDK II Continuous Integration:
------------------------------ ------------------------------
@ -156,7 +156,7 @@ F: ArmVirtPkg/PrePi/
F: ArmVirtPkg/XenAcpiPlatformDxe/ F: ArmVirtPkg/XenAcpiPlatformDxe/
F: ArmVirtPkg/XenPlatformHasAcpiDtDxe/ F: ArmVirtPkg/XenPlatformHasAcpiDtDxe/
F: ArmVirtPkg/XenioFdtDxe/ F: ArmVirtPkg/XenioFdtDxe/
R: Julien Grall <julien@xen.org> R: Julien Grall <julien@xen.org> [jgrall]
BaseTools BaseTools
F: BaseTools/ F: BaseTools/
@ -184,8 +184,8 @@ F: EmbeddedPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/EmbeddedPkg W: https://github.com/tianocore/tianocore.github.io/wiki/EmbeddedPkg
M: Leif Lindholm <quic_llindhol@quicinc.com> [leiflindholm] M: Leif Lindholm <quic_llindhol@quicinc.com> [leiflindholm]
M: Ard Biesheuvel <ardb+tianocore@kernel.org> [ardbiesheuvel] M: Ard Biesheuvel <ardb+tianocore@kernel.org> [ardbiesheuvel]
M: Abner Chang <abner.chang@hpe.com> [changab] M: Abner Chang <abner.chang@amd.com> [changab]
R: Daniel Schaefer <daniel.schaefer@hpe.com> [JohnAZoidberg] R: Daniel Schaefer <git@danielschaefer.me> [JohnAZoidberg]
EmulatorPkg EmulatorPkg
F: EmulatorPkg/ F: EmulatorPkg/
@ -196,8 +196,8 @@ S: Maintained
EmulatorPkg: Redfish-related modules EmulatorPkg: Redfish-related modules
F: EmulatorPkg/*Redfish* F: EmulatorPkg/*Redfish*
M: Abner Chang <abner.chang@hpe.com> [changab] M: Abner Chang <abner.chang@amd.com> [changab]
R: Nickle Wang <nickle.wang@hpe.com> [nicklela] R: Nickle Wang <nickle@csie.io> [nicklela]
FatPkg FatPkg
F: FatPkg/ F: FatPkg/
@ -218,14 +218,14 @@ IntelFsp2Pkg
F: IntelFsp2Pkg/ F: IntelFsp2Pkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
M: Chasel Chiu <chasel.chiu@intel.com> [ChaselChiu] M: Chasel Chiu <chasel.chiu@intel.com> [ChaselChiu]
R: Nate DeSimone <nathaniel.l.desimone@intel.com> [nate-desimone] M: Nate DeSimone <nathaniel.l.desimone@intel.com> [nate-desimone]
R: Star Zeng <star.zeng@intel.com> [lzeng14] R: Star Zeng <star.zeng@intel.com> [lzeng14]
IntelFsp2WrapperPkg IntelFsp2WrapperPkg
F: IntelFsp2WrapperPkg/ F: IntelFsp2WrapperPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
M: Chasel Chiu <chasel.chiu@intel.com> [ChaselChiu] M: Chasel Chiu <chasel.chiu@intel.com> [ChaselChiu]
R: Nate DeSimone <nathaniel.l.desimone@intel.com> [nate-desimone] M: Nate DeSimone <nathaniel.l.desimone@intel.com> [nate-desimone]
R: Star Zeng <star.zeng@intel.com> [lzeng14] R: Star Zeng <star.zeng@intel.com> [lzeng14]
MdeModulePkg MdeModulePkg
@ -371,8 +371,7 @@ MdeModulePkg: Pei Core
F: MdeModulePkg/Core/Pei/ F: MdeModulePkg/Core/Pei/
R: Dandan Bi <dandan.bi@intel.com> [dandanbi] R: Dandan Bi <dandan.bi@intel.com> [dandanbi]
R: Liming Gao <gaoliming@byosoft.com.cn> [lgao4] R: Liming Gao <gaoliming@byosoft.com.cn> [lgao4]
R: Debkumar De <debkumar.de@intel.com> R: Debkumar De <debkumar.de@intel.com> [dde01]
R: Harry Han <harry.han@intel.com>
R: Catharine West <catharine.west@intel.com> [catharine-intl] R: Catharine West <catharine.west@intel.com> [catharine-intl]
MdeModulePkg: Reset modules MdeModulePkg: Reset modules
@ -474,7 +473,7 @@ F: OvmfPkg/PlatformPei/AmdSev.c
F: OvmfPkg/ResetVector/ F: OvmfPkg/ResetVector/
F: OvmfPkg/Sec/ F: OvmfPkg/Sec/
R: Brijesh Singh <brijesh.singh@amd.com> [codomania] R: Brijesh Singh <brijesh.singh@amd.com> [codomania]
R: Erdem Aktas <erdemaktas@google.com> R: Erdem Aktas <erdemaktas@google.com> [ruleof2]
R: James Bottomley <jejb@linux.ibm.com> [jejb] R: James Bottomley <jejb@linux.ibm.com> [jejb]
R: Jiewen Yao <jiewen.yao@intel.com> [jyao1] R: Jiewen Yao <jiewen.yao@intel.com> [jyao1]
R: Min Xu <min.m.xu@intel.com> [mxu9] R: Min Xu <min.m.xu@intel.com> [mxu9]
@ -484,17 +483,11 @@ OvmfPkg: FDT related modules
F: OvmfPkg/Fdt F: OvmfPkg/Fdt
R: Leif Lindholm <quic_llindhol@quicinc.com> [leiflindholm] R: Leif Lindholm <quic_llindhol@quicinc.com> [leiflindholm]
R: Gerd Hoffmann <kraxel@redhat.com> [kraxel] R: Gerd Hoffmann <kraxel@redhat.com> [kraxel]
R: Abner Chang <abner.chang@hpe.com> [changab] R: Abner Chang <abner.chang@amd.com> [changab]
OvmfPkg: LsiScsi driver OvmfPkg: LsiScsi driver
F: OvmfPkg/LsiScsiDxe/ F: OvmfPkg/LsiScsiDxe/
R: Gary Lin <glin@suse.com> R: Gary Lin <gary.lin@hpe.com> [lcp]
OvmfPkg: MptScsi and PVSCSI driver
F: OvmfPkg/MptScsiDxe/
F: OvmfPkg/PvScsiDxe/
R: Liran Alon <liran.alon@oracle.com>
R: Nikita Leshenko <nikita.leshchenko@oracle.com>
OvmfPkg: TCG- and TPM2-related modules OvmfPkg: TCG- and TPM2-related modules
F: OvmfPkg/Include/IndustryStandard/QemuTpm.h F: OvmfPkg/Include/IndustryStandard/QemuTpm.h
@ -502,8 +495,8 @@ F: OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
F: OvmfPkg/Library/Tcg2PhysicalPresenceLib*/ F: OvmfPkg/Library/Tcg2PhysicalPresenceLib*/
F: OvmfPkg/PlatformPei/ClearCache.c F: OvmfPkg/PlatformPei/ClearCache.c
F: OvmfPkg/Tcg/ F: OvmfPkg/Tcg/
R: Marc-André Lureau <marcandre.lureau@redhat.com> R: Marc-André Lureau <marcandre.lureau@redhat.com> [elmarco]
R: Stefan Berger <stefanb@linux.ibm.com> R: Stefan Berger <stefanb@linux.ibm.com> [stefanberger]
OvmfPkg: Xen-related modules OvmfPkg: Xen-related modules
F: OvmfPkg/Include/Guid/XenBusRootDevice.h F: OvmfPkg/Include/Guid/XenBusRootDevice.h
@ -531,9 +524,8 @@ F: OvmfPkg/XenIoPvhDxe/
F: OvmfPkg/XenPlatformPei/ F: OvmfPkg/XenPlatformPei/
F: OvmfPkg/XenPvBlkDxe/ F: OvmfPkg/XenPvBlkDxe/
F: OvmfPkg/XenResetVector/ F: OvmfPkg/XenResetVector/
F: OvmfPkg/XenTimerDxe/
R: Anthony Perard <anthony.perard@citrix.com> [sheep] R: Anthony Perard <anthony.perard@citrix.com> [sheep]
R: Julien Grall <julien@xen.org> R: Julien Grall <julien@xen.org> [jgrall]
PcAtChipsetPkg PcAtChipsetPkg
F: PcAtChipsetPkg/ F: PcAtChipsetPkg/
@ -550,8 +542,8 @@ R: Ankit Sinha <ankit.sinha@intel.com> [ankit13s]
RedfishPkg: Redfish related modules RedfishPkg: Redfish related modules
F: RedfishPkg/ F: RedfishPkg/
M: Abner Chang <abner.chang@hpe.com> [changab] M: Abner Chang <abner.chang@amd.com> [changab]
R: Nickle Wang <nickle.wang@hpe.com> [nicklela] R: Nickle Wang <nickle@csie.io> [nicklela]
SecurityPkg SecurityPkg
F: SecurityPkg/ F: SecurityPkg/
@ -603,8 +595,7 @@ R: Rahul Kumar <rahul1.kumar@intel.com> [rahul1-kumar]
UefiCpuPkg: Sec related modules UefiCpuPkg: Sec related modules
F: UefiCpuPkg/SecCore/ F: UefiCpuPkg/SecCore/
F: UefiCpuPkg/ResetVector/ F: UefiCpuPkg/ResetVector/
R: Debkumar De <debkumar.de@intel.com> R: Debkumar De <debkumar.de@intel.com> [dde01]
R: Harry Han <harry.han@intel.com>
R: Catharine West <catharine.west@intel.com> [catharine-intl] R: Catharine West <catharine.west@intel.com> [catharine-intl]
UefiPayloadPkg UefiPayloadPkg
@ -612,9 +603,7 @@ F: UefiPayloadPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/UefiPayloadPkg W: https://github.com/tianocore/tianocore.github.io/wiki/UefiPayloadPkg
M: Guo Dong <guo.dong@intel.com> [gdong1] M: Guo Dong <guo.dong@intel.com> [gdong1]
M: Ray Ni <ray.ni@intel.com> [niruiyu] M: Ray Ni <ray.ni@intel.com> [niruiyu]
R: Maurice Ma <maurice.ma@intel.com> [mauricema] M: Sean Rhodes <sean@starlabs.systems> [Sean-StarLabs]
R: Benjamin You <benjamin.you@intel.com> [BenjaminYou]
R: Sean Rhodes <sean@starlabs.systems>
S: Maintained S: Maintained
UnitTestFrameworkPkg UnitTestFrameworkPkg

View File

@ -361,7 +361,7 @@ DumpPcdInfo (
Uint8 = mPiPcd->Get8 (TokenSpace, TokenNumber); Uint8 = mPiPcd->Get8 (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint8); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint8);
break; break;
case EFI_PCD_TYPE_16: case EFI_PCD_TYPE_16:
if (TokenSpace == NULL) { if (TokenSpace == NULL) {
@ -370,7 +370,7 @@ DumpPcdInfo (
Uint16 = mPiPcd->Get16 (TokenSpace, TokenNumber); Uint16 = mPiPcd->Get16 (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint16); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint16);
break; break;
case EFI_PCD_TYPE_32: case EFI_PCD_TYPE_32:
if (TokenSpace == NULL) { if (TokenSpace == NULL) {
@ -379,7 +379,7 @@ DumpPcdInfo (
Uint32 = mPiPcd->Get32 (TokenSpace, TokenNumber); Uint32 = mPiPcd->Get32 (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint32); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x - Value = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint32);
break; break;
case EFI_PCD_TYPE_64: case EFI_PCD_TYPE_64:
if (TokenSpace == NULL) { if (TokenSpace == NULL) {
@ -388,7 +388,7 @@ DumpPcdInfo (
Uint64 = mPiPcd->Get64 (TokenSpace, TokenNumber); Uint64 = mPiPcd->Get64 (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x - Value = 0x%lx\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint64); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x - Value = 0x%lx\n", TokenNumber, RetString, PcdInfo->PcdSize, Uint64);
break; break;
case EFI_PCD_TYPE_BOOL: case EFI_PCD_TYPE_BOOL:
if (TokenSpace == NULL) { if (TokenSpace == NULL) {
@ -397,7 +397,7 @@ DumpPcdInfo (
Boolean = mPiPcd->GetBool (TokenSpace, TokenNumber); Boolean = mPiPcd->GetBool (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x - Value = %a\n", TokenNumber, RetString, PcdInfo->PcdSize, Boolean ? "TRUE" : "FALSE"); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x - Value = %a\n", TokenNumber, RetString, PcdInfo->PcdSize, Boolean ? "TRUE" : "FALSE");
break; break;
case EFI_PCD_TYPE_PTR: case EFI_PCD_TYPE_PTR:
if (TokenSpace == NULL) { if (TokenSpace == NULL) {
@ -406,7 +406,7 @@ DumpPcdInfo (
PcdData = mPiPcd->GetPtr (TokenSpace, TokenNumber); PcdData = mPiPcd->GetPtr (TokenSpace, TokenNumber);
} }
Print (L" Token = 0x%08x - Type = %H%-17s%N - Size = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize); Print (L" Token = 0x%08x - Type = %-17s - Size = 0x%x\n", TokenNumber, RetString, PcdInfo->PcdSize);
DumpHex (2, 0, PcdInfo->PcdSize, PcdData); DumpHex (2, 0, PcdInfo->PcdSize, PcdData);
break; break;
default: default:
@ -509,7 +509,7 @@ ProcessPcd (
// //
// The specified PCD is not found, print error. // The specified PCD is not found, print error.
// //
Print (L"%EError. %NNo matching PCD found: %s.\n", InputPcdName); Print (L"Error. No matching PCD found: %s.\n", InputPcdName);
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@ -548,25 +548,25 @@ DumpDynPcdMain (
Status = gBS->LocateProtocol (&gEfiPcdProtocolGuid, NULL, (VOID **)&mPiPcd); Status = gBS->LocateProtocol (&gEfiPcdProtocolGuid, NULL, (VOID **)&mPiPcd);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Print (L"DumpDynPcd: %EError. %NPI PCD protocol is not present.\n"); Print (L"DumpDynPcd: Error. PI PCD protocol is not present.\n");
return Status; return Status;
} }
Status = gBS->LocateProtocol (&gEfiGetPcdInfoProtocolGuid, NULL, (VOID **)&mPiPcdInfo); Status = gBS->LocateProtocol (&gEfiGetPcdInfoProtocolGuid, NULL, (VOID **)&mPiPcdInfo);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Print (L"DumpDynPcd: %EError. %NPI PCD info protocol is not present.\n"); Print (L"DumpDynPcd: Error. PI PCD info protocol is not present.\n");
return Status; return Status;
} }
Status = gBS->LocateProtocol (&gPcdProtocolGuid, NULL, (VOID **)&mPcd); Status = gBS->LocateProtocol (&gPcdProtocolGuid, NULL, (VOID **)&mPcd);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Print (L"DumpDynPcd: %EError. %NPCD protocol is not present.\n"); Print (L"DumpDynPcd: Error. PCD protocol is not present.\n");
return Status; return Status;
} }
Status = gBS->LocateProtocol (&gGetPcdInfoProtocolGuid, NULL, (VOID **)&mPcdInfo); Status = gBS->LocateProtocol (&gGetPcdInfoProtocolGuid, NULL, (VOID **)&mPcdInfo);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Print (L"DumpDynPcd: %EError. %NPCD info protocol is not present.\n"); Print (L"DumpDynPcd: Error. PCD info protocol is not present.\n");
return Status; return Status;
} }
@ -575,13 +575,13 @@ DumpDynPcdMain (
// //
Status = GetArg (); Status = GetArg ();
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Print (L"DumpDynPcd: %EError. %NThe input parameters are not recognized.\n"); Print (L"DumpDynPcd: Error. The input parameters are not recognized.\n");
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
return Status; return Status;
} }
if (Argc > 2) { if (Argc > 2) {
Print (L"DumpDynPcd: %EError. %NToo many arguments specified.\n"); Print (L"DumpDynPcd: Error. Too many arguments specified.\n");
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
return Status; return Status;
} }
@ -600,7 +600,7 @@ DumpDynPcdMain (
goto Done; goto Done;
} else { } else {
if (StrStr (Argv[1], L"-") != NULL) { if (StrStr (Argv[1], L"-") != NULL) {
Print (L"DumpDynPcd: %EError. %NThe argument '%B%s%N' is invalid.\n", Argv[1]); Print (L"DumpDynPcd: Error. The argument '%s' is invalid.\n", Argv[1]);
goto Done; goto Done;
} }
} }

View File

@ -9,6 +9,9 @@
**/ **/
#include "AhciPei.h" #include "AhciPei.h"
#include <Ppi/PciDevice.h>
#include <Library/DevicePathLib.h>
#include <IndustryStandard/Pci.h>
EFI_PEI_PPI_DESCRIPTOR mAhciAtaPassThruPpiListTemplate = { EFI_PEI_PPI_DESCRIPTOR mAhciAtaPassThruPpiListTemplate = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
@ -40,6 +43,18 @@ EFI_PEI_NOTIFY_DESCRIPTOR mAhciEndOfPeiNotifyListTemplate = {
AhciPeimEndOfPei AhciPeimEndOfPei
}; };
EFI_PEI_NOTIFY_DESCRIPTOR mAtaAhciHostControllerNotify = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiPeiAtaAhciHostControllerPpiGuid,
AtaAhciHostControllerPpiInstallationCallback
};
EFI_PEI_NOTIFY_DESCRIPTOR mPciDevicePpiNotify = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiPeiPciDevicePpiGuid,
AtaAhciPciDevicePpiInstallationCallback
};
/** /**
Free the DMA resources allocated by an ATA AHCI controller. Free the DMA resources allocated by an ATA AHCI controller.
@ -111,33 +126,30 @@ AhciPeimEndOfPei (
} }
/** /**
Entry point of the PEIM. Initialize and install PrivateData PPIs.
@param[in] FileHandle Handle of the file being invoked. @param[in] MmioBase MMIO base address of specific AHCI controller
@param[in] PeiServices Describes the list of possible PEI Services. @param[in] DevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL
structure.
@retval EFI_SUCCESS PPI successfully installed. @param[in] DevicePathLength Length of the device path.
@retval EFI_SUCCESS AHCI controller initialized and PPIs installed
@retval others Failed to initialize AHCI controller
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI AtaAhciInitPrivateData (
AtaAhciPeimEntry ( IN UINTN MmioBase,
IN EFI_PEI_FILE_HANDLE FileHandle, IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
IN CONST EFI_PEI_SERVICES **PeiServices IN UINTN DevicePathLength
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_BOOT_MODE BootMode; UINT32 PortBitMap;
EDKII_ATA_AHCI_HOST_CONTROLLER_PPI *AhciHcPpi; UINT8 NumberOfPorts;
UINT8 Controller; PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private;
UINTN MmioBase; EFI_BOOT_MODE BootMode;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINT32 PortBitMap;
PEI_AHCI_CONTROLLER_PRIVATE_DATA *Private;
UINT8 NumberOfPorts;
DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__)); DEBUG ((DEBUG_INFO, "Initializing private data for ATA\n"));
// //
// Get the current boot mode. // Get the current boot mode.
@ -149,19 +161,149 @@ AtaAhciPeimEntry (
} }
// //
// Locate the ATA AHCI host controller PPI. // Check validity of the device path of the ATA AHCI controller.
// //
Status = PeiServicesLocatePpi ( Status = AhciIsHcDevicePathValid (DevicePath, DevicePathLength);
&gEdkiiPeiAtaAhciHostControllerPpiGuid,
0,
NULL,
(VOID **)&AhciHcPpi
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Failed to locate AtaAhciHostControllerPpi.\n", __FUNCTION__)); DEBUG ((
return EFI_UNSUPPORTED; DEBUG_ERROR,
"%a: The device path is invalid.\n",
__FUNCTION__
));
return Status;
} }
//
// For S3 resume performance consideration, not all ports on an ATA AHCI
// controller will be enumerated/initialized. The driver consumes the
// content within S3StorageDeviceInitList LockBox to get the ports that
// will be enumerated/initialized during S3 resume.
//
if (BootMode == BOOT_ON_S3_RESUME) {
NumberOfPorts = AhciS3GetEumeratePorts (DevicePath, DevicePathLength, &PortBitMap);
if (NumberOfPorts == 0) {
return EFI_SUCCESS;
}
} else {
PortBitMap = MAX_UINT32;
}
//
// Memory allocation for controller private data.
//
Private = AllocateZeroPool (sizeof (PEI_AHCI_CONTROLLER_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((
DEBUG_ERROR,
"%a: Fail to allocate private data.\n",
__FUNCTION__
));
return EFI_OUT_OF_RESOURCES;
}
//
// Initialize controller private data.
//
Private->Signature = AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->MmioBase = MmioBase;
Private->DevicePathLength = DevicePathLength;
Private->DevicePath = DevicePath;
Private->PortBitMap = PortBitMap;
InitializeListHead (&Private->DeviceList);
Status = AhciModeInitialization (Private);
if (EFI_ERROR (Status)) {
return Status;
}
Private->AtaPassThruMode.Attributes = EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL;
Private->AtaPassThruMode.IoAlign = sizeof (UINTN);
Private->AtaPassThruPpi.Revision = EDKII_PEI_ATA_PASS_THRU_PPI_REVISION;
Private->AtaPassThruPpi.Mode = &Private->AtaPassThruMode;
Private->AtaPassThruPpi.PassThru = AhciAtaPassThruPassThru;
Private->AtaPassThruPpi.GetNextPort = AhciAtaPassThruGetNextPort;
Private->AtaPassThruPpi.GetNextDevice = AhciAtaPassThruGetNextDevice;
Private->AtaPassThruPpi.GetDevicePath = AhciAtaPassThruGetDevicePath;
CopyMem (
&Private->AtaPassThruPpiList,
&mAhciAtaPassThruPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->AtaPassThruPpiList.Ppi = &Private->AtaPassThruPpi;
PeiServicesInstallPpi (&Private->AtaPassThruPpiList);
Private->BlkIoPpi.GetNumberOfBlockDevices = AhciBlockIoGetDeviceNo;
Private->BlkIoPpi.GetBlockDeviceMediaInfo = AhciBlockIoGetMediaInfo;
Private->BlkIoPpi.ReadBlocks = AhciBlockIoReadBlocks;
CopyMem (
&Private->BlkIoPpiList,
&mAhciBlkIoPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
PeiServicesInstallPpi (&Private->BlkIoPpiList);
Private->BlkIo2Ppi.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
Private->BlkIo2Ppi.GetNumberOfBlockDevices = AhciBlockIoGetDeviceNo2;
Private->BlkIo2Ppi.GetBlockDeviceMediaInfo = AhciBlockIoGetMediaInfo2;
Private->BlkIo2Ppi.ReadBlocks = AhciBlockIoReadBlocks2;
CopyMem (
&Private->BlkIo2PpiList,
&mAhciBlkIo2PpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
PeiServicesInstallPpi (&Private->BlkIo2PpiList);
if (Private->TrustComputingDevices != 0) {
DEBUG ((
DEBUG_INFO,
"%a: Security Security Command PPI will be produced.\n",
__FUNCTION__
));
Private->StorageSecurityPpi.Revision = EDKII_STORAGE_SECURITY_PPI_REVISION;
Private->StorageSecurityPpi.GetNumberofDevices = AhciStorageSecurityGetDeviceNo;
Private->StorageSecurityPpi.GetDevicePath = AhciStorageSecurityGetDevicePath;
Private->StorageSecurityPpi.ReceiveData = AhciStorageSecurityReceiveData;
Private->StorageSecurityPpi.SendData = AhciStorageSecuritySendData;
CopyMem (
&Private->StorageSecurityPpiList,
&mAhciStorageSecurityPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
PeiServicesInstallPpi (&Private->StorageSecurityPpiList);
}
CopyMem (
&Private->EndOfPeiNotifyList,
&mAhciEndOfPeiNotifyListTemplate,
sizeof (EFI_PEI_NOTIFY_DESCRIPTOR)
);
PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
return EFI_SUCCESS;
}
/**
Initialize AHCI controller from EDKII_ATA_AHCI_HOST_CONTROLLER_PPI instance.
@param[in] AhciHcPpi Pointer to the AHCI Host Controller PPI instance.
@retval EFI_SUCCESS PPI successfully installed.
**/
EFI_STATUS
AtaAhciInitPrivateDataFromHostControllerPpi (
IN EDKII_ATA_AHCI_HOST_CONTROLLER_PPI *AhciHcPpi
)
{
UINT8 Controller;
UINTN MmioBase;
UINTN DevicePathLength;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_STATUS Status;
Controller = 0; Controller = 0;
MmioBase = 0; MmioBase = 0;
while (TRUE) { while (TRUE) {
@ -193,65 +335,7 @@ AtaAhciPeimEntry (
return Status; return Status;
} }
// Status = AtaAhciInitPrivateData (MmioBase, DevicePath, DevicePathLength);
// Check validity of the device path of the ATA AHCI controller.
//
Status = AhciIsHcDevicePathValid (DevicePath, DevicePathLength);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_ERROR,
"%a: The device path is invalid for Controller %d.\n",
__FUNCTION__,
Controller
));
Controller++;
continue;
}
//
// For S3 resume performance consideration, not all ports on an ATA AHCI
// controller will be enumerated/initialized. The driver consumes the
// content within S3StorageDeviceInitList LockBox to get the ports that
// will be enumerated/initialized during S3 resume.
//
if (BootMode == BOOT_ON_S3_RESUME) {
NumberOfPorts = AhciS3GetEumeratePorts (DevicePath, DevicePathLength, &PortBitMap);
if (NumberOfPorts == 0) {
//
// No ports need to be enumerated for this controller.
//
Controller++;
continue;
}
} else {
PortBitMap = MAX_UINT32;
}
//
// Memory allocation for controller private data.
//
Private = AllocateZeroPool (sizeof (PEI_AHCI_CONTROLLER_PRIVATE_DATA));
if (Private == NULL) {
DEBUG ((
DEBUG_ERROR,
"%a: Fail to allocate private data for Controller %d.\n",
__FUNCTION__,
Controller
));
return EFI_OUT_OF_RESOURCES;
}
//
// Initialize controller private data.
//
Private->Signature = AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->MmioBase = MmioBase;
Private->DevicePathLength = DevicePathLength;
Private->DevicePath = DevicePath;
Private->PortBitMap = PortBitMap;
InitializeListHead (&Private->DeviceList);
Status = AhciModeInitialization (Private);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG (( DEBUG ((
DEBUG_ERROR, DEBUG_ERROR,
@ -260,86 +344,187 @@ AtaAhciPeimEntry (
Controller, Controller,
Status Status
)); ));
Controller++; } else {
continue;
}
Private->AtaPassThruMode.Attributes = EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL |
EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL;
Private->AtaPassThruMode.IoAlign = sizeof (UINTN);
Private->AtaPassThruPpi.Revision = EDKII_PEI_ATA_PASS_THRU_PPI_REVISION;
Private->AtaPassThruPpi.Mode = &Private->AtaPassThruMode;
Private->AtaPassThruPpi.PassThru = AhciAtaPassThruPassThru;
Private->AtaPassThruPpi.GetNextPort = AhciAtaPassThruGetNextPort;
Private->AtaPassThruPpi.GetNextDevice = AhciAtaPassThruGetNextDevice;
Private->AtaPassThruPpi.GetDevicePath = AhciAtaPassThruGetDevicePath;
CopyMem (
&Private->AtaPassThruPpiList,
&mAhciAtaPassThruPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->AtaPassThruPpiList.Ppi = &Private->AtaPassThruPpi;
PeiServicesInstallPpi (&Private->AtaPassThruPpiList);
Private->BlkIoPpi.GetNumberOfBlockDevices = AhciBlockIoGetDeviceNo;
Private->BlkIoPpi.GetBlockDeviceMediaInfo = AhciBlockIoGetMediaInfo;
Private->BlkIoPpi.ReadBlocks = AhciBlockIoReadBlocks;
CopyMem (
&Private->BlkIoPpiList,
&mAhciBlkIoPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIoPpiList.Ppi = &Private->BlkIoPpi;
PeiServicesInstallPpi (&Private->BlkIoPpiList);
Private->BlkIo2Ppi.Revision = EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION;
Private->BlkIo2Ppi.GetNumberOfBlockDevices = AhciBlockIoGetDeviceNo2;
Private->BlkIo2Ppi.GetBlockDeviceMediaInfo = AhciBlockIoGetMediaInfo2;
Private->BlkIo2Ppi.ReadBlocks = AhciBlockIoReadBlocks2;
CopyMem (
&Private->BlkIo2PpiList,
&mAhciBlkIo2PpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->BlkIo2PpiList.Ppi = &Private->BlkIo2Ppi;
PeiServicesInstallPpi (&Private->BlkIo2PpiList);
if (Private->TrustComputingDevices != 0) {
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: Security Security Command PPI will be produced for Controller %d.\n", "%a: Controller %d has been successfully initialized.\n",
__FUNCTION__, __FUNCTION__,
Controller Controller
)); ));
Private->StorageSecurityPpi.Revision = EDKII_STORAGE_SECURITY_PPI_REVISION;
Private->StorageSecurityPpi.GetNumberofDevices = AhciStorageSecurityGetDeviceNo;
Private->StorageSecurityPpi.GetDevicePath = AhciStorageSecurityGetDevicePath;
Private->StorageSecurityPpi.ReceiveData = AhciStorageSecurityReceiveData;
Private->StorageSecurityPpi.SendData = AhciStorageSecuritySendData;
CopyMem (
&Private->StorageSecurityPpiList,
&mAhciStorageSecurityPpiListTemplate,
sizeof (EFI_PEI_PPI_DESCRIPTOR)
);
Private->StorageSecurityPpiList.Ppi = &Private->StorageSecurityPpi;
PeiServicesInstallPpi (&Private->StorageSecurityPpiList);
} }
CopyMem (
&Private->EndOfPeiNotifyList,
&mAhciEndOfPeiNotifyListTemplate,
sizeof (EFI_PEI_NOTIFY_DESCRIPTOR)
);
PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
DEBUG ((
DEBUG_INFO,
"%a: Controller %d has been successfully initialized.\n",
__FUNCTION__,
Controller
));
Controller++; Controller++;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/**
Callback for EDKII_ATA_AHCI_HOST_CONTROLLER_PPI installation.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
event that caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_SUCCESS The function completes successfully
@retval Others Cannot initialize AHCI controller from given EDKII_ATA_AHCI_HOST_CONTROLLER_PPI
**/
EFI_STATUS
EFIAPI
AtaAhciHostControllerPpiInstallationCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
)
{
EDKII_ATA_AHCI_HOST_CONTROLLER_PPI *AhciHcPpi;
if (Ppi == NULL) {
return EFI_INVALID_PARAMETER;
}
AhciHcPpi = (EDKII_ATA_AHCI_HOST_CONTROLLER_PPI *)Ppi;
return AtaAhciInitPrivateDataFromHostControllerPpi (AhciHcPpi);
}
/**
Initialize AHCI controller from fiven PCI_DEVICE_PPI.
@param[in] PciDevice Pointer to the PCI Device PPI instance.
@retval EFI_SUCCESS The function completes successfully
@retval Others Cannot initialize AHCI controller for given device
**/
EFI_STATUS
AtaAhciInitPrivateDataFromPciDevice (
EDKII_PCI_DEVICE_PPI *PciDevice
)
{
EFI_STATUS Status;
PCI_TYPE00 PciData;
UINTN MmioBase;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN DevicePathLength;
UINT64 EnabledPciAttributes;
//
// Now further check the PCI header: Base Class (offset 0x0B) and
// Sub Class (offset 0x0A). This controller should be an SATA controller
//
Status = PciDevice->PciIo.Pci.Read (
&PciDevice->PciIo,
EfiPciIoWidthUint8,
PCI_CLASSCODE_OFFSET,
sizeof (PciData.Hdr.ClassCode),
PciData.Hdr.ClassCode
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
if (!IS_PCI_IDE (&PciData) && !IS_PCI_SATADPA (&PciData)) {
return EFI_UNSUPPORTED;
}
Status = PciDevice->PciIo.Attributes (
&PciDevice->PciIo,
EfiPciIoAttributeOperationSupported,
0,
&EnabledPciAttributes
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
} else {
EnabledPciAttributes &= (UINT64)EFI_PCI_DEVICE_ENABLE;
Status = PciDevice->PciIo.Attributes (
&PciDevice->PciIo,
EfiPciIoAttributeOperationEnable,
EnabledPciAttributes,
NULL
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
}
Status = PciDevice->PciIo.Pci.Read (
&PciDevice->PciIo,
EfiPciIoWidthUint32,
0x24,
sizeof (UINTN),
&MmioBase
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
DevicePathLength = GetDevicePathSize (PciDevice->DevicePath);
DevicePath = PciDevice->DevicePath;
Status = AtaAhciInitPrivateData (MmioBase, DevicePath, DevicePathLength);
if (EFI_ERROR (Status)) {
DEBUG ((
DEBUG_INFO,
"%a: Failed to init controller, with Status - %r\n",
__FUNCTION__,
Status
));
}
return EFI_SUCCESS;
}
/**
Callback for EDKII_PCI_DEVICE_PPI installation.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
event that caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_SUCCESS The function completes successfully
@retval Others Cannot initialize AHCI controller from given PCI_DEVICE_PPI
**/
EFI_STATUS
EFIAPI
AtaAhciPciDevicePpiInstallationCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
)
{
EDKII_PCI_DEVICE_PPI *PciDevice;
PciDevice = (EDKII_PCI_DEVICE_PPI *)Ppi;
return AtaAhciInitPrivateDataFromPciDevice (PciDevice);
}
/**
Entry point of the PEIM.
@param[in] FileHandle Handle of the file being invoked.
@param[in] PeiServices Describes the list of possible PEI Services.
@retval EFI_SUCCESS PPI successfully installed.
**/
EFI_STATUS
EFIAPI
AtaAhciPeimEntry (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
PeiServicesNotifyPpi (&mAtaAhciHostControllerNotify);
PeiServicesNotifyPpi (&mPciDevicePpiNotify);
return EFI_SUCCESS;
}

View File

@ -29,6 +29,7 @@
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/TimerLib.h> #include <Library/TimerLib.h>
#include <Library/DevicePathLib.h>
// //
// Structure forward declarations // Structure forward declarations
@ -354,6 +355,46 @@ extern UINT32 mMaxTransferBlockNumber[2];
// Internal functions // Internal functions
// //
/**
Callback for EDKII_ATA_AHCI_HOST_CONTROLLER_PPI installation.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
event that caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_SUCCESS The function completes successfully
@retval Others Cannot initialize AHCI controller from given EDKII_ATA_AHCI_HOST_CONTROLLER_PPI
**/
EFI_STATUS
EFIAPI
AtaAhciHostControllerPpiInstallationCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
/**
Callback for EDKII_PCI_DEVICE_PPI installation.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDescriptor Pointer to the descriptor for the Notification
event that caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_SUCCESS The function completes successfully
@retval Others Cannot initialize AHCI controller from given PCI_DEVICE_PPI
**/
EFI_STATUS
EFIAPI
AtaAhciPciDevicePpiInstallationCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
/** /**
Allocates pages that are suitable for an OperationBusMasterCommonBuffer or Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
OperationBusMasterCommonBuffer64 mapping. OperationBusMasterCommonBuffer64 mapping.
@ -631,22 +672,6 @@ TrustTransferAtaDevice (
OUT UINTN *TransferLengthOut OUT UINTN *TransferLengthOut
); );
/**
Returns a pointer to the next node in a device path.
If Node is NULL, then ASSERT().
@param Node A pointer to a device path node data structure.
@return a pointer to the device path node that follows the device path node
specified by Node.
**/
EFI_DEVICE_PATH_PROTOCOL *
NextDevicePathNode (
IN CONST VOID *Node
);
/** /**
Get the size of the current device path instance. Get the size of the current device path instance.

View File

@ -50,11 +50,13 @@
TimerLib TimerLib
LockBoxLib LockBoxLib
PeimEntryPoint PeimEntryPoint
DevicePathLib
[Ppis] [Ppis]
gEdkiiPeiAtaAhciHostControllerPpiGuid ## CONSUMES gEdkiiPeiAtaAhciHostControllerPpiGuid ## CONSUMES
gEdkiiIoMmuPpiGuid ## CONSUMES gEdkiiIoMmuPpiGuid ## CONSUMES
gEfiEndOfPeiSignalPpiGuid ## CONSUMES gEfiEndOfPeiSignalPpiGuid ## CONSUMES
gEdkiiPeiPciDevicePpiGuid ## CONSUMES
gEdkiiPeiAtaPassThruPpiGuid ## SOMETIMES_PRODUCES gEdkiiPeiAtaPassThruPpiGuid ## SOMETIMES_PRODUCES
gEfiPeiVirtualBlockIoPpiGuid ## SOMETIMES_PRODUCES gEfiPeiVirtualBlockIoPpiGuid ## SOMETIMES_PRODUCES
gEfiPeiVirtualBlockIo2PpiGuid ## SOMETIMES_PRODUCES gEfiPeiVirtualBlockIo2PpiGuid ## SOMETIMES_PRODUCES
@ -65,8 +67,7 @@
[Depex] [Depex]
gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiMemoryDiscoveredPpiGuid AND
gEfiPeiMasterBootModePpiGuid AND gEfiPeiMasterBootModePpiGuid
gEdkiiPeiAtaAhciHostControllerPpiGuid
[UserExtensions.TianoCore."ExtraFiles"] [UserExtensions.TianoCore."ExtraFiles"]
AhciPeiExtra.uni AhciPeiExtra.uni

View File

@ -38,50 +38,6 @@ EFI_DEVICE_PATH_PROTOCOL mAhciEndDevicePathNodeTemplate = {
} }
}; };
/**
Returns the 16-bit Length field of a device path node.
Returns the 16-bit Length field of the device path node specified by Node.
Node is not required to be aligned on a 16-bit boundary, so it is recommended
that a function such as ReadUnaligned16() be used to extract the contents of
the Length field.
If Node is NULL, then ASSERT().
@param Node A pointer to a device path node data structure.
@return The 16-bit Length field of the device path node specified by Node.
**/
UINTN
DevicePathNodeLength (
IN CONST VOID *Node
)
{
ASSERT (Node != NULL);
return ReadUnaligned16 ((UINT16 *)&((EFI_DEVICE_PATH_PROTOCOL *)(Node))->Length[0]);
}
/**
Returns a pointer to the next node in a device path.
If Node is NULL, then ASSERT().
@param Node A pointer to a device path node data structure.
@return a pointer to the device path node that follows the device path node
specified by Node.
**/
EFI_DEVICE_PATH_PROTOCOL *
NextDevicePathNode (
IN CONST VOID *Node
)
{
ASSERT (Node != NULL);
return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength (Node));
}
/** /**
Get the size of the current device path instance. Get the size of the current device path instance.

View File

@ -1,7 +1,7 @@
/** @file /** @file
Internal library implementation for PCI Bus module. Internal library implementation for PCI Bus module.
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR> (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
@ -1528,6 +1528,7 @@ PciHostBridgeEnumerator (
UINT8 StartBusNumber; UINT8 StartBusNumber;
LIST_ENTRY RootBridgeList; LIST_ENTRY RootBridgeList;
LIST_ENTRY *Link; LIST_ENTRY *Link;
EFI_STATUS RootBridgeEnumerationStatus;
if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) { if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
InitializeHotPlugSupport (); InitializeHotPlugSupport ();
@ -1545,7 +1546,8 @@ PciHostBridgeEnumerator (
} }
DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n")); DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));
RootBridgeHandle = NULL; RootBridgeHandle = NULL;
RootBridgeEnumerationStatus = EFI_SUCCESS;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) { while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
// //
// if a root bridge instance is found, create root bridge device for it // if a root bridge instance is found, create root bridge device for it
@ -1572,7 +1574,7 @@ PciHostBridgeEnumerator (
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; RootBridgeEnumerationStatus = Status;
} }
} }
@ -1581,6 +1583,10 @@ PciHostBridgeEnumerator (
// //
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation); NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
if (EFI_ERROR (RootBridgeEnumerationStatus)) {
return RootBridgeEnumerationStatus;
}
if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) { if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
// //
// Reset all assigned PCI bus number in all PPB // Reset all assigned PCI bus number in all PPB
@ -1659,7 +1665,7 @@ PciHostBridgeEnumerator (
DestroyRootBridge (RootBridgeDev); DestroyRootBridge (RootBridgeDev);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; RootBridgeEnumerationStatus = Status;
} }
} }
@ -1667,6 +1673,10 @@ PciHostBridgeEnumerator (
// Notify the bus allocation phase is to end for the 2nd time // Notify the bus allocation phase is to end for the 2nd time
// //
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation); NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
if (EFI_ERROR (RootBridgeEnumerationStatus)) {
return RootBridgeEnumerationStatus;
}
} }
// //

View File

@ -1,7 +1,7 @@
/** @file /** @file
The XHCI controller driver. The XHCI controller driver.
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -399,24 +399,31 @@ XhcGetRootHubPortStatus (
// //
// According to XHCI 1.1 spec November 2017, // According to XHCI 1.1 spec November 2017,
// bit 10~13 of the root port status register identifies the speed of the attached device. // Section 7.2 xHCI Support Protocol Capability
// //
switch ((State & XHC_PORTSC_PS) >> 10) { PortStatus->PortStatus = XhcCheckUsbPortSpeedUsedPsic (Xhc, ((State & XHC_PORTSC_PS) >> 10));
case 2: if (PortStatus->PortStatus == 0) {
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED; //
break; // According to XHCI 1.1 spec November 2017,
// bit 10~13 of the root port status register identifies the speed of the attached device.
//
switch ((State & XHC_PORTSC_PS) >> 10) {
case 2:
PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
break;
case 3: case 3:
PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED; PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
break; break;
case 4: case 4:
case 5: case 5:
PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED; PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
break; break;
default: default:
break; break;
}
} }
// //
@ -1813,13 +1820,21 @@ XhcCreateUsbHc (
// This xHC supports a page size of 2^(n+12) if bit n is Set. For example, // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
// if bit 0 is Set, the xHC supports 4k byte page sizes. // if bit 0 is Set, the xHC supports 4k byte page sizes.
// //
PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK; PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);
if ((PageSize & (~XHC_PAGESIZE_MASK)) != 0) {
DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for PageSize\n"));
goto ON_ERROR;
}
PageSize &= XHC_PAGESIZE_MASK;
Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12); Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg); ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
Xhc->ExtCapRegBase = ExtCapReg << 2; Xhc->ExtCapRegBase = ExtCapReg << 2;
Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY); Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG); Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
Xhc->Usb2SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2);
Xhc->Usb3SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3);
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
@ -1829,6 +1844,8 @@ XhcCreateUsbHc (
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset)); DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb2SupOffset 0x%x\n", Xhc->Usb2SupOffset));
DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb3SupOffset 0x%x\n", Xhc->Usb3SupOffset));
// //
// Create AsyncRequest Polling Timer // Create AsyncRequest Polling Timer

View File

@ -227,6 +227,8 @@ struct _USB_XHCI_INSTANCE {
UINT32 ExtCapRegBase; UINT32 ExtCapRegBase;
UINT32 UsbLegSupOffset; UINT32 UsbLegSupOffset;
UINT32 DebugCapSupOffset; UINT32 DebugCapSupOffset;
UINT32 Usb2SupOffset;
UINT32 Usb3SupOffset;
UINT64 *DCBAA; UINT64 *DCBAA;
VOID *DCBAAMap; VOID *DCBAAMap;
UINT32 MaxSlotsEn; UINT32 MaxSlotsEn;

View File

@ -575,6 +575,184 @@ XhcGetCapabilityAddr (
return 0xFFFFFFFF; return 0xFFFFFFFF;
} }
/**
Calculate the offset of the xHCI Supported Protocol Capability.
@param Xhc The XHCI Instance.
@param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
@return The offset of xHCI Supported Protocol capability register.
**/
UINT32
XhcGetSupportedProtocolCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 MajorVersion
)
{
UINT32 ExtCapOffset;
UINT8 NextExtCapReg;
UINT32 Data;
UINT32 NameString;
XHC_SUPPORTED_PROTOCOL_DW0 UsbSupportDw0;
if (Xhc == NULL) {
return 0;
}
ExtCapOffset = 0;
do {
//
// Check if the extended capability register's capability id is USB Legacy Support.
//
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
UsbSupportDw0.Dword = Data;
if ((Data & 0xFF) == XHC_CAP_USB_SUPPORTED_PROTOCOL) {
if (UsbSupportDw0.Data.RevMajor == MajorVersion) {
NameString = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET);
if (NameString == XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) {
//
// Ensure Name String field is xHCI supported protocols in xHCI Supported Protocol Capability Offset 04h
//
return ExtCapOffset;
}
}
}
//
// If not, then traverse all of the ext capability registers till finding out it.
//
NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
ExtCapOffset += (NextExtCapReg << 2);
} while (NextExtCapReg != 0);
return 0xFFFFFFFF;
}
/**
Find PortSpeed value match Protocol Speed ID Value (PSIV).
@param Xhc The XHCI Instance.
@param ExtCapOffset The USB Major Version in xHCI Support Protocol Capability Field
@param PortSpeed The Port Speed Field in USB PortSc register
@return The Protocol Speed ID (PSI) from xHCI Supported Protocol capability register.
**/
UINT32
XhciPsivGetPsid (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 ExtCapOffset,
IN UINT8 PortSpeed
)
{
XHC_SUPPORTED_PROTOCOL_DW2 PortId;
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Reg;
UINT32 Count;
if ((Xhc == NULL) || (ExtCapOffset == 0xFFFFFFFF)) {
return 0;
}
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2 xHCI Supported Protocol Capability
// 1. Get the PSIC(Protocol Speed ID Count) value.
// 2. The PSID register boundary should be Base address + PSIC * 0x04
//
PortId.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_DW2_OFFSET);
for (Count = 0; Count < PortId.Data.Psic; Count++) {
Reg.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_PSI_OFFSET + (Count << 2));
if (Reg.Data.Psiv == PortSpeed) {
return Reg.Dword;
}
}
return 0;
}
/**
Find PortSpeed value match case in XHCI Supported Protocol Capability
@param Xhc The XHCI Instance.
@param PortSpeed The Port Speed Field in USB PortSc register
@return The USB Port Speed.
**/
UINT16
XhcCheckUsbPortSpeedUsedPsic (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 PortSpeed
)
{
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID SpField;
UINT16 UsbSpeedIdMap;
if (Xhc == NULL) {
return 0;
}
SpField.Dword = 0;
UsbSpeedIdMap = 0;
//
// Check xHCI Supported Protocol Capability, find the PSIV field to match
// PortSpeed definition when the Major Revision is 03h.
//
if (Xhc->Usb3SupOffset != 0xFFFFFFFF) {
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);
if (SpField.Dword != 0) {
//
// Found the corresponding PORTSC value in PSIV field of USB3 offset.
//
UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;
}
}
//
// Check xHCI Supported Protocol Capability, find the PSIV field to match
// PortSpeed definition when the Major Revision is 02h.
//
if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed);
if (SpField.Dword != 0) {
//
// Found the corresponding PORTSC value in PSIV field of USB2 offset.
//
if (SpField.Data.Psie == 2) {
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 2 shall represent bit rate in Mb/s
//
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM) {
//
// PSIM shows as default High-speed protocol, apply to High-speed mapping
//
UsbSpeedIdMap = USB_PORT_STAT_HIGH_SPEED;
}
} else if (SpField.Data.Psie == 1) {
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 1 shall represent bit rate in Kb/s
//
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM) {
//
// PSIM shows as default Low-speed protocol, apply to Low-speed mapping
//
UsbSpeedIdMap = USB_PORT_STAT_LOW_SPEED;
}
}
}
}
return UsbSpeedIdMap;
}
/** /**
Whether the XHCI host controller is halted. Whether the XHCI host controller is halted.

View File

@ -25,8 +25,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define USB_HUB_CLASS_CODE 0x09 #define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00 #define USB_HUB_SUBCLASS_CODE 0x00
#define XHC_CAP_USB_LEGACY 0x01 #define XHC_CAP_USB_LEGACY 0x01
#define XHC_CAP_USB_DEBUG 0x0A #define XHC_CAP_USB_DEBUG 0x0A
#define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02
// ============================================// // ============================================//
// XHCI register offset // // XHCI register offset //
@ -74,6 +75,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
//
// xHCI Supported Protocol Capability
//
#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02
#define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03
#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04
#define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355
#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08
#define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10
#define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480
#define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500
#pragma pack (1) #pragma pack (1)
typedef struct { typedef struct {
UINT8 MaxSlots; // Number of Device Slots UINT8 MaxSlots; // Number of Device Slots
@ -130,6 +143,52 @@ typedef union {
HCCPARAMS Data; HCCPARAMS Data;
} XHC_HCCPARAMS; } XHC_HCCPARAMS;
//
// xHCI Supported Protocol Cabability
//
typedef struct {
UINT8 CapId;
UINT8 NextExtCapReg;
UINT8 RevMinor;
UINT8 RevMajor;
} SUPPORTED_PROTOCOL_DW0;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_DW0 Data;
} XHC_SUPPORTED_PROTOCOL_DW0;
typedef struct {
UINT32 NameString;
} XHC_SUPPORTED_PROTOCOL_DW1;
typedef struct {
UINT8 CompPortOffset;
UINT8 CompPortCount;
UINT16 ProtocolDef : 12;
UINT16 Psic : 4;
} SUPPORTED_PROTOCOL_DW2;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_DW2 Data;
} XHC_SUPPORTED_PROTOCOL_DW2;
typedef struct {
UINT16 Psiv : 4;
UINT16 Psie : 2;
UINT16 Plt : 2;
UINT16 Pfd : 1;
UINT16 RsvdP : 5;
UINT16 Lp : 2;
UINT16 Psim;
} SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
typedef union {
UINT32 Dword;
SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data;
} XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;
#pragma pack () #pragma pack ()
// //
@ -546,4 +605,34 @@ XhcGetCapabilityAddr (
IN UINT8 CapId IN UINT8 CapId
); );
/**
Calculate the offset of the xHCI Supported Protocol Capability.
@param Xhc The XHCI Instance.
@param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
@return The offset of xHCI Supported Protocol capability register.
**/
UINT32
XhcGetSupportedProtocolCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 MajorVersion
);
/**
Find SpeedField value match with Port Speed ID value.
@param Xhc The XHCI Instance.
@param Speed The Port Speed filed in USB PortSc register
@return The USB Port Speed.
**/
UINT16
XhcCheckUsbPortSpeedUsedPsic (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 Speed
);
#endif #endif

View File

@ -1,7 +1,7 @@
/** @file /** @file
DXE Core Main Entry Point DXE Core Main Entry Point
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -253,9 +253,17 @@ DxeMain (
VectorInfoList = (EFI_VECTOR_HANDOFF_INFO *)(GET_GUID_HOB_DATA (GuidHob)); VectorInfoList = (EFI_VECTOR_HANDOFF_INFO *)(GET_GUID_HOB_DATA (GuidHob));
} }
Status = InitializeCpuExceptionHandlersEx (VectorInfoList, NULL); Status = InitializeCpuExceptionHandlers (VectorInfoList);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
//
// Setup Stack Guard
//
if (PcdGetBool (PcdCpuStackGuard)) {
Status = InitializeSeparateExceptionStacks (NULL, NULL);
ASSERT_EFI_ERROR (Status);
}
// //
// Initialize Debug Agent to support source level debug in DXE phase // Initialize Debug Agent to support source level debug in DXE phase
// //

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