ShellBinPkg: Ia32/X64 Shell binary update.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> (cherry picked from commit 46e2632b4e)
MdeModulePkg/BMMUiLib: Fix incorrect variable name
2017-06-13 16:26:05 +08:00 · 2017-06-13 10:48:07 +08:00 · 2017-06-10 13:25:25 +08:00 · 2017-06-10 10:25:53 +08:00 · 2017-06-10 10:25:52 +08:00 · 2017-06-09 10:52:20 +08:00
2035 changed files with 95833 additions and 125414 deletions
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "CryptoPkg/Library/OpensslLib/openssl"]
-	path = CryptoPkg/Library/OpensslLib/openssl
-	url = https://github.com/openssl/openssl
--- a/AppPkg/Applications/Python/PyMod-2.7.2/Python/marshal.c
+++ b/AppPkg/Applications/Python/PyMod-2.7.2/Python/marshal.c
@@ -1289,7 +1289,7 @@ The file must be an open file object such as sys.stdout or returned by\n\
 open() or os.popen(). It must be opened in binary mode ('wb' or 'w+b').\n\
 \n\
 If the value has (or contains an object that has) an unsupported type, a\n\
-ValueError exception is raised - but garbage data will also be written\n\
+ValueError exception is raised — but garbage data will also be written\n\
 to the file. The object will not be properly read back by load()\n\
 \n\
 New in version 2.4: The version argument indicates the data format that\n\
@@ -1317,7 +1317,7 @@ PyDoc_STRVAR(load_doc,
 "load(file)\n\
 \n\
 Read one value from the open file and return it. If no valid value is\n\
-read (e.g. because the data has a different Python version's\n\
+read (e.g. because the data has a different Python version’s\n\
 incompatible marshal format), raise EOFError, ValueError or TypeError.\n\
 The file must be an open file object opened in binary mode ('rb' or\n\
 'r+b').\n\
--- a/AppPkg/Applications/Sockets/WebServer/Mtrr.c
+++ b/AppPkg/Applications/Sockets/WebServer/Mtrr.c
@@ -146,12 +146,12 @@ MemoryTypeRegistersPage (
 {
  UINT64 Addr;
  BOOLEAN bValid;
-  MSR_IA32_MTRRCAP_REGISTER Capabilities;
+  UINT64 Capabilities;
  UINTN Count;
-  MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+  UINT64 DefType;
  UINTN Index;
  UINT64 Mask;
-
+  UINT64 MaxMtrrs;
  CONST UINT64 mFixedAddresses [( 8 * MTRR_NUMBER_OF_FIXED_MTRR ) + 1 ] = {
           0ULL,
     0x10000ULL,
@@ -302,8 +302,8 @@ MemoryTypeRegistersPage (
      //
      //  Get the capabilities
      //
-      Capabilities.Uint64 = AsmReadMsr64 ( MSR_IA32_MTRRCAP );
-      DefType.Uint64 =  AsmReadMsr64 ( MSR_IA32_MTRR_DEF_TYPE );
+      Capabilities = AsmReadMsr64 ( MTRR_LIB_IA32_MTRR_CAP );
+      DefType =  AsmReadMsr64 ( MTRR_LIB_IA32_MTRR_DEF_TYPE );

      //
      //  Display the capabilities
@@ -316,7 +316,7 @@ MemoryTypeRegistersPage (
      }
      Status = HttpSendHexValue ( SocketFD,
                                  pPort,
-                                  Capabilities.Uint64 );
+                                  Capabilities );
      if ( EFI_ERROR ( Status )) {
        break;
      }
@@ -338,7 +338,7 @@ MemoryTypeRegistersPage (
      }
      Status = HttpSendHexValue ( SocketFD,
                                  pPort,
-                                  DefType.Uint64);
+                                  DefType );
      if ( EFI_ERROR ( Status )) {
        break;
      }
@@ -350,7 +350,7 @@ MemoryTypeRegistersPage (
      }
      Status = HttpSendAnsiString ( SocketFD,
                                    pPort,
-                                    ( 0 != DefType.Bits.E )
+                                    ( 0 != ( DefType & MTRR_LIB_CACHE_MTRR_ENABLED ))
                                    ? "Enabled"
                                    : "Disabled" );
      if ( EFI_ERROR ( Status )) {
@@ -364,7 +364,7 @@ MemoryTypeRegistersPage (
      }
      Status = HttpSendAnsiString ( SocketFD,
                                    pPort,
-                                    ( 0 != DefType.Bits.FE )
+                                    ( 0 != ( DefType & MTRR_LIB_CACHE_FIXED_MTRR_ENABLED ))
                                    ? "Enabled"
                                    : "Disabled" );
      if ( EFI_ERROR ( Status )) {
@@ -376,7 +376,7 @@ MemoryTypeRegistersPage (
      if ( EFI_ERROR ( Status )) {
        break;
      }
-      Type = DefType.Uint64 & 0xff;
+      Type = DefType & 0xff;
      Status = HttpSendAnsiString ( SocketFD,
                                    pPort,
                                    ( DIM ( mMemoryType ) > Type )
@@ -395,7 +395,7 @@ MemoryTypeRegistersPage (
      //
      //  Determine if MTRRs are enabled
      //
-      if ( 0 == DefType.Bits.E ) {
+      if ( 0 == ( DefType & MTRR_LIB_CACHE_MTRR_ENABLED )) {
        Status = HttpSendAnsiString ( SocketFD,
                                      pPort,
                                      "<p>All memory is uncached!</p>\r\n" );
@@ -412,8 +412,8 @@ MemoryTypeRegistersPage (
        //
        //  Determine if the fixed MTRRs are supported
        //
-        if (( 0 != Capabilities.Bits.FIX )
-          && ( 0 != DefType.Bits.FE)) {
+        if (( 0 != ( Capabilities & 0x100 ))
+          && ( 0 != ( DefType & MTRR_LIB_CACHE_FIXED_MTRR_ENABLED ))) {

          //
          //  Beginning of table
@@ -615,7 +615,8 @@ MemoryTypeRegistersPage (
        //
        //  Determine if the variable MTRRs are supported
        //
-        if ( 0 < Capabilities.Bits.VCNT ) {
+        MaxMtrrs = Capabilities & MTRR_LIB_IA32_MTRR_CAP_VCNT_MASK;
+        if ( 0 < MaxMtrrs ) {
          //
          //  Beginning of table
          //
@@ -631,7 +632,7 @@ MemoryTypeRegistersPage (
          //
          //  Display the variable MTRRs
          //
-          for ( Count = 0; Capabilities.Bits.VCNT > Count; Count++ ) {
+          for ( Count = 0; MaxMtrrs > Count; Count++ ) {
            //
            //  Start the row
            //
--- a/AppPkg/Applications/Sockets/WebServer/WebServer.h
+++ b/AppPkg/Applications/Sockets/WebServer/WebServer.h
@@ -20,7 +20,6 @@

 #include <Guid/EventGroup.h>

-#include <Register/Msr.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
 #include <Library/MemoryAllocationLib.h>
--- a/AppPkg/Contributions.txt
+++ b/AppPkg/Contributions.txt
@@ -1,3 +1,4 @@
+
 ======================
 = Code Contributions =
 ======================
@@ -11,7 +12,7 @@ To make a contribution to a TianoCore project, follow these steps.
   contribution is made under the terms of the specified
   contribution agreement.  Your "Contributed-under" message
   must include the name of contribution agreement and version.
-   For example: Contributed-under: TianoCore Contribution Agreement 1.1
+   For example: Contributed-under: TianoCore Contribution Agreement 1.0
   The "TianoCore Contribution Agreement" is included below in
   this document.
 4. Submit your code to the TianoCore project using the process
@@ -27,10 +28,6 @@ To make a contribution to a TianoCore project, follow these steps.
   * Python-2.0: http://opensource.org/licenses/Python-2.0
   * Zlib: http://opensource.org/licenses/Zlib

-   For documentation:
-   * FreeBSD Documentation License
-     https://www.freebsd.org/copyright/freebsd-doc-license.html
-
   Contributions of code put into the public domain can also be
   accepted.

@@ -50,11 +47,11 @@ and the "Contributed-under" message.
 === Start of sample patch email message ===

 From: Contributor Name <contributor@example.com>
-Subject: [Repository/Branch PATCH] Module: Brief-single-line-summary
+Subject: [PATCH] CodeModule: Brief-single-line-summary

 Full-commit-message

-Contributed-under: TianoCore Contribution Agreement 1.1
+Contributed-under: TianoCore Contribution Agreement 1.0
 Signed-off-by: Contributor Name <contributor@example.com>
 ---

@@ -68,63 +65,49 @@ Patch content inline or attached
 === Notes for sample patch email ===

 * The first line of commit message is taken from the email's subject
-  line following [Repository/Branch PATCH]. The remaining portion of the
-  commit message is the email's content until the '---' line.
+  line following [PATCH]. The remaining portion of the commit message
+  is the email's content until the '---' line.
 * git format-patch is one way to create this format

 === Definitions for sample patch email ===

-* "Repository" is the identifier of the repository the patch applies.
-  This identifier should only be provided for repositories other than
-  'edk2'. For example 'edk2-BuildSpecification' or 'staging'.
-* "Branch" is the identifier of the branch the patch applies. This
-  identifier should only be provided for branches other than 'edk2/master'.
-  For example 'edk2/UDK2015', 'edk2-BuildSpecification/release/1.27', or
-  'staging/edk2-test'.
-* "Module" is a short identifier for the affected code or documentation. For
-  example 'MdePkg', 'MdeModulePkg/UsbBusDxe', 'Introduction', or
-  'EDK II INF File Format'.
+* "CodeModule" is a short idenfier for the affected code.  For
+  example MdePkg, or MdeModulePkg UsbBusDxe.
 * "Brief-single-line-summary" is a short summary of the change.
 * The entire first line should be less than ~70 characters.
 * "Full-commit-message" a verbose multiple line comment describing
  the change.  Each line should be less than ~70 characters.
-* "Contributed-under" explicitly states that the contribution is
-  made under the terms of the contribution agreement. This
+* "Contributed-under" explicitely states that the contribution is
+  made under the terms of the contribtion agreement.  This
  agreement is included below in this document.
 * "Signed-off-by" is the contributor's signature identifying them
  by their real/legal name and their email address.

 ========================================
-= TianoCore Contribution Agreement 1.1 =
+= TianoCore Contribution Agreement 1.0 =
 ========================================

-INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION
-("DOCUMENTATION"), INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE
-TIANOCORE OPEN SOURCE PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT
-IS GOVERNED BY THE TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND
-INTEL AND/OR THE TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES
-INDICATED OR REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR
-USE OF THE CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND
-CONDITIONS OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR
-REFERENCED BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
 AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
 AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
 USE THE CONTENT.

-Unless otherwise indicated, all Content (except Documentation) made available
-on the TianoCore site is provided to you under the terms and conditions of the
-BSD License ("BSD"). A copy of the BSD License is available at
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
 http://opensource.org/licenses/bsd-license.php
 or when applicable, in the associated License.txt file.

-Unless otherwise indicated, all Documentation made available on the
-TianoCore site is provided to you under the terms and conditions of the
-FreeBSD Documentation License ("FreeBSD"). A copy of the license is
-available at https://www.freebsd.org/copyright/freebsd-doc-license.html or,
-when applicable, in the associated License.txt file.
-
 Certain other content may be made available under other licenses as
-indicated in or with such Content (for example, in a License.txt file).
+indicated in or with such Content. (For example, in a License.txt file.)

 You accept and agree to the following terms and conditions for Your
 present and future Contributions submitted to TianoCore site. Except
--- a/AppPkg/License.txt
+++ b/AppPkg/License.txt
@@ -0,0 +1,25 @@
+Copyright (c) 2012, Intel Corporation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -36,10 +36,10 @@
  ArmLib|Include/Library/ArmLib.h
  ArmMmuLib|Include/Library/ArmMmuLib.h
  SemihostLib|Include/Library/Semihosting.h
+  UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  ArmGicArchLib|Include/Library/ArmGicArchLib.h
-  ArmSvcLib|Include/Library/ArmSvcLib.h

 [Guids.common]
  gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
@@ -84,6 +84,9 @@
  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024

+  # This PCD will free the unallocated buffers if their size reach this threshold.
+  # We set the default value to 512MB.
+  gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005

@@ -113,6 +116,14 @@
  #
  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B

+  #
+  # BdsLib
+  #
+  # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
+  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
+  # Maximum file size for TFTP servers that do not support 'tsize' extension
+  gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
+
  #
  # ARM Normal (or Non Secure) Firmware PCDs
  #
@@ -216,8 +227,8 @@
 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]

  # System Memory (DRAM): These PCDs define the region of in-built system memory
-  # Some platforms can get DRAM extensions, these additional regions may be
-  # declared to UEFI using separate resource descriptor HOBs
+  # Some platforms can get DRAM extensions, these additional regions will be declared
+  # to UEFI by ArmPlatformLib
  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A

--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -33,6 +33,8 @@
 [BuildOptions]
  XCODE:*_*_ARM_PLATFORM_FLAGS  == -arch armv7
  GCC:*_*_ARM_PLATFORM_FLAGS    == -march=armv7-a -mfpu=neon
+  # We use A15 to get the Secure and Virtualization extensions
+  RVCT:*_*_ARM_PLATFORM_FLAGS  == --cpu Cortex-A15

  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
  *_*_*_CC_FLAGS  = -DDISABLE_NEW_DEPRECATED_INTERFACES
@@ -41,7 +43,6 @@
  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
-  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -61,6 +62,7 @@
  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf

  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
@@ -71,11 +73,13 @@
  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf

  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf

+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf

  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
@@ -103,6 +107,8 @@
 [Components.common]
  ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
  ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmPkg/Library/BdsLib/BdsLib.inf
  ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
  ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
  ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
@@ -111,6 +117,7 @@
  ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
  ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
  ArmPkg/Library/SemihostLib/SemihostLib.inf
+  ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
  ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
  ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
  ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
@@ -119,6 +126,7 @@
  ArmPkg/Drivers/CpuPei/CpuPei.inf
  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
  ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
  ArmPkg/Drivers/TimerDxe/TimerDxe.inf

@@ -128,7 +136,6 @@
  ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
  ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.inf
  ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
-  ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf

  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf

--- a/ArmPkg/Contributions.txt
+++ b/ArmPkg/Contributions.txt
@@ -0,0 +1,218 @@
+
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+   use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+   and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+   contribution is made under the terms of the specified
+   contribution agreement.  Your "Contributed-under" message
+   must include the name of contribution agreement and version.
+   For example: Contributed-under: TianoCore Contribution Agreement 1.0
+   The "TianoCore Contribution Agreement" is included below in
+   this document.
+4. Submit your code to the TianoCore project using the process
+   that the project documents on its web page.  If the process is
+   not documented, then submit the code on development email list
+   for the project.
+5. It is preferred that contributions are submitted using the same
+   copyright license as the base project. When that is not possible,
+   then contributions using the following licenses can be accepted:
+   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
+   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
+   * MIT: http://opensource.org/licenses/MIT
+   * Python-2.0: http://opensource.org/licenses/Python-2.0
+   * Zlib: http://opensource.org/licenses/Zlib
+
+   Contributions of code put into the public domain can also be
+   accepted.
+
+   Contributions using other licenses might be accepted, but further
+   review will be required.
+
+=====================================================
+= Change Description / Commit Message / Patch Email =
+=====================================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Start of sample patch email message ===
+
+From: Contributor Name <contributor@example.com>
+Subject: [PATCH] CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <contributor@example.com>
+---
+
+An extra message for the patch email which will not be considered part
+of the commit message can be added here.
+
+Patch content inline or attached
+
+=== End of sample patch email message ===
+
+=== Notes for sample patch email ===
+
+* The first line of commit message is taken from the email's subject
+  line following [PATCH]. The remaining portion of the commit message
+  is the email's content until the '---' line.
+* git format-patch is one way to create this format
+
+=== Definitions for sample patch email ===
+
+* "CodeModule" is a short idenfier for the affected code.  For
+  example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+  the change.  Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+  made under the terms of the contribtion agreement.  This
+  agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+  by their real/legal name and their email address.
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+  entity authorized by the copyright owner that is making a
+  Contribution hereunder. All other entities that control, are
+  controlled by, or are under common control with that entity are
+  considered to be a single Contributor. For the purposes of this
+  definition, "control" means (i) the power, direct or indirect, to
+  cause the direction or management of such entity, whether by
+  contract or otherwise, or (ii) ownership of fifty percent (50%)
+  or more of the outstanding shares, or (iii) beneficial ownership
+  of such entity.
+* "Contribution" shall mean any original work of authorship,
+  including any modifications or additions to an existing work,
+  that is intentionally submitted by You to the TinaoCore site for
+  inclusion in, or documentation of, any of the Content. For the
+  purposes of this definition, "submitted" means any form of
+  electronic, verbal, or written communication sent to the
+  TianoCore site or its representatives, including but not limited
+  to communication on electronic mailing lists, source code
+  control systems, and issue tracking systems that are managed by,
+  or on behalf of, the TianoCore site for the purpose of
+  discussing and improving the Content, but excluding
+  communication that is conspicuously marked or otherwise
+  designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+  Contribution in source and binary forms, with or without
+  modification, are permitted provided that the following
+  conditions are met:
+** Redistributions of source code must retain the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer.
+** Redistributions in binary form must reproduce the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided
+   with the distribution.
+* Disclaimer. None of the names of Contributor, Intel, or the names
+  of their respective contributors may be used to endorse or
+  promote products derived from this software without specific
+  prior written permission.
+* Contributor grants a license (with the right to sublicense) under
+  claims of Contributor's patents that Contributor can license that
+  are infringed by the Contribution (as delivered by Contributor) to
+  make, use, distribute, sell, offer for sale, and import the
+  Contribution and derivative works thereof solely to the minimum
+  extent necessary for licensee to exercise the granted copyright
+  license; this patent license applies solely to those portions of
+  the Contribution that are unmodified. No hardware per se is
+  licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+  DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+  license. If your employer(s) has rights to intellectual property
+  that You create that includes Your Contributions, You represent
+  that You have received permission to make Contributions on behalf
+  of that employer, that Your employer has waived such rights for
+  Your Contributions.
+* You represent that each of Your Contributions is Your original
+  creation (see Section 4 for submissions on behalf of others).
+  You represent that Your Contribution submissions include complete
+  details of any third-party license or other restriction
+  (including, but not limited to, related patents and trademarks)
+  of which You are personally aware and which are associated with
+  any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+  You may submit it to TianoCore site separately from any
+  Contribution, identifying the complete details of its source
+  and of any license or other restriction (including, but not
+  limited to, related patents, trademarks, and license agreements)
+  of which You are personally aware, and conspicuously marking the
+  work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+  Agreement shall be governed by the internal substantive laws of
+  the State of Delaware or federal courts located in Delaware,
+  without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+  language shall be controlling in all respects, and all versions
+  of this Agreement in any other language shall be for accommodation
+  only and shall not be binding. All communications and notices made
+  or given pursuant to this Agreement, and all documentation and
+  support to be provided, unless otherwise noted, shall be in the
+  English language.
+
--- a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c
+++ b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c
@@ -1,38 +0,0 @@
-/** @file
-
-  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-#include <Library/DebugLib.h>
-#include <Library/DefaultExceptionHandlerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Protocol/Cpu.h>
-
-STATIC EFI_CPU_ARCH_PROTOCOL      *mCpu;
-
-EFI_STATUS
-EFIAPI
-ArmCrashDumpDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS      Status;
-
-  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
-  ASSERT_EFI_ERROR(Status);
-
-  return mCpu->RegisterInterruptHandler (mCpu,
-                                         EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
-                                         &DefaultExceptionHandler);
-}
--- a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc
+++ b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc
@@ -1,56 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = ArmCrashDumpDxe
-  PLATFORM_GUID                  = 8dc3c2f8-988e-4e32-8fb7-0df43f6d0d8a
-  PLATFORM_VERSION               = 0.1
-  DSC_SPECIFICATION              = 0x00010019
-  OUTPUT_DIRECTORY               = Build/ArmCrashDumpDxe
-  SUPPORTED_ARCHITECTURES        = AARCH64
-  BUILD_TARGETS                  = DEBUG
-  SKUID_IDENTIFIER               = DEFAULT
-
-[PcdsFixedAtBuild]
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
-
-[LibraryClasses]
-  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
-  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
-  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-  DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
-  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
-  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
-  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
-  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
-  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
-  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
-
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-
-[Components.common]
-  ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
--- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c
@@ -1,6 +1,6 @@
 /*++

-Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>

 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
@@ -28,10 +28,14 @@ ExitBootServicesEvent (
  IN VOID       *Context
  );

+//
 // Making this global saves a few bytes in image size
+//
 EFI_HANDLE  gHardwareInterruptHandle = NULL;

+//
 // Notifications
+//
 EFI_EVENT EfiExitBootServicesEvent      = (EFI_EVENT)NULL;

 // Maximum Number of Interrupts
@@ -39,46 +43,6 @@ UINTN mGicNumInterrupts                 = 0;

 HARDWARE_INTERRUPT_HANDLER  *gRegisteredInterruptHandlers = NULL;

-
-/**
-  Calculate GICD_ICFGRn base address and corresponding bit
-  field Int_config[1] of the GIC distributor register.
-
-  @param Source       Hardware source of the interrupt.
-  @param RegAddress   Corresponding GICD_ICFGRn base address.
-  @param Config1Bit   Bit number of F Int_config[1] bit in the register.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-EFI_STATUS
-GicGetDistributorIcfgBaseAndBit (
-  IN HARDWARE_INTERRUPT_SOURCE             Source,
-  OUT UINTN                               *RegAddress,
-  OUT UINTN                               *Config1Bit
-  )
-{
-  UINTN                  RegIndex;
-  UINTN                  Field;
-
-  if (Source >= mGicNumInterrupts) {
-    ASSERT(Source < mGicNumInterrupts);
-    return EFI_UNSUPPORTED;
-  }
-
-  RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE;  // NOTE: truncation is significant
-  Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
-  *RegAddress = PcdGet64 (PcdGicDistributorBase)
-                + ARM_GIC_ICDICFR
-                + (ARM_GIC_ICDICFR_BYTES * RegIndex);
-  *Config1Bit = ((Field * ARM_GIC_ICDICFR_F_WIDTH)
-                 + ARM_GIC_ICDICFR_F_CONFIG1_BIT);
-
-  return EFI_SUCCESS;
-}
-
-
-
 /**
  Register Handler for the specified interrupt source.

@@ -124,64 +88,54 @@ RegisterInterruptSource (
 EFI_STATUS
 InstallAndRegisterInterruptService (
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL   *InterruptProtocol,
-  IN EFI_HARDWARE_INTERRUPT2_PROTOCOL  *Interrupt2Protocol,
  IN EFI_CPU_INTERRUPT_HANDLER          InterruptHandler,
  IN EFI_EVENT_NOTIFY                   ExitBootServicesEvent
  )
 {
  EFI_STATUS               Status;
  EFI_CPU_ARCH_PROTOCOL   *Cpu;
-  CONST UINTN              RihArraySize =
-    (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);

  // Initialize the array for the Interrupt Handlers
-  gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
+  gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
  if (gRegisteredInterruptHandlers == NULL) {
    return EFI_OUT_OF_RESOURCES;
  }

  Status = gBS->InstallMultipleProtocolInterfaces (
                  &gHardwareInterruptHandle,
-                  &gHardwareInterruptProtocolGuid,
-                  InterruptProtocol,
-                  &gHardwareInterrupt2ProtocolGuid,
-                  Interrupt2Protocol,
+                  &gHardwareInterruptProtocolGuid, InterruptProtocol,
                  NULL
                  );
  if (EFI_ERROR (Status)) {
    return Status;
  }

+  //
  // Get the CPU protocol that this driver requires.
+  //
  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
  if (EFI_ERROR (Status)) {
    return Status;
  }

+  //
  // Unregister the default exception handler.
+  //
  Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
  if (EFI_ERROR (Status)) {
    return Status;
  }

+  //
  // Register to receive interrupts
-  Status = Cpu->RegisterInterruptHandler (
-                  Cpu,
-                  ARM_ARCH_EXCEPTION_IRQ,
-                  InterruptHandler
-                  );
+  //
+  Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, InterruptHandler);
  if (EFI_ERROR (Status)) {
    return Status;
  }

  // Register for an ExitBootServicesEvent
-  Status = gBS->CreateEvent (
-                  EVT_SIGNAL_EXIT_BOOT_SERVICES,
-                  TPL_NOTIFY,
-                  ExitBootServicesEvent,
-                  NULL,
-                  &EfiExitBootServicesEvent
-                  );
+  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);

  return Status;
 }
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h
@@ -1,6 +1,6 @@
 /*++

-Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>

 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
@@ -24,16 +24,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 #include <Protocol/Cpu.h>
 #include <Protocol/HardwareInterrupt.h>
-#include <Protocol/HardwareInterrupt2.h>

 extern UINTN                        mGicNumInterrupts;
 extern HARDWARE_INTERRUPT_HANDLER  *gRegisteredInterruptHandlers;

+//
 // Common API
+//
 EFI_STATUS
 InstallAndRegisterInterruptService (
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL   *InterruptProtocol,
-  IN EFI_HARDWARE_INTERRUPT2_PROTOCOL  *Interrupt2Protocol,
  IN EFI_CPU_INTERRUPT_HANDLER          InterruptHandler,
  IN EFI_EVENT_NOTIFY                   ExitBootServicesEvent
  );
@@ -46,39 +46,22 @@ RegisterInterruptSource (
  IN HARDWARE_INTERRUPT_HANDLER         Handler
  );

+//
 // GicV2 API
+//
 EFI_STATUS
 GicV2DxeInitialize (
  IN EFI_HANDLE         ImageHandle,
  IN EFI_SYSTEM_TABLE   *SystemTable
  );

+//
 // GicV3 API
+//
 EFI_STATUS
 GicV3DxeInitialize (
  IN EFI_HANDLE         ImageHandle,
  IN EFI_SYSTEM_TABLE   *SystemTable
  );

-
-// Shared code
-
-/**
-  Calculate GICD_ICFGRn base address and corresponding bit
-  field Int_config[1] of the GIC distributor register.
-
-  @param Source       Hardware source of the interrupt.
-  @param RegAddress   Corresponding GICD_ICFGRn base address.
-  @param Config1Bit   Bit number of F Int_config[1] bit in the register.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-EFI_STATUS
-GicGetDistributorIcfgBaseAndBit (
-  IN HARDWARE_INTERRUPT_SOURCE             Source,
-  OUT UINTN                               *RegAddress,
-  OUT UINTN                               *Config1Bit
-  );
-
 #endif
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -1,7 +1,7 @@
 #/** @file
 #
 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  Copyright (c) 2012 - 2017, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -48,7 +48,6 @@

 [Protocols]
  gHardwareInterruptProtocolGuid
-  gHardwareInterrupt2ProtocolGuid
  gEfiCpuArchProtocolGuid

 [Pcd.common]
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -19,13 +19,6 @@
 #include <Library/IoLib.h>
 #include <Library/PcdLib.h>

-
-#define ISENABLER_ADDRESS(base,offset) ((base) + \
-          ARM_GICR_CTLR_FRAME_SIZE +  ARM_GICR_ISENABLER + (4 * offset))
-
-#define ICENABLER_ADDRESS(base,offset) ((base) + \
-          ARM_GICR_CTLR_FRAME_SIZE +  ARM_GICR_ICENABLER + (4 * offset))
-
 /**
 *
 * Return whether the Source interrupt index refers to a shared interrupt (SPI)
@@ -62,17 +55,13 @@ GicGetCpuRedistributorBase (
  UINTN GicCpuRedistributorBase;

  MpId = ArmReadMpidr ();
-  // Define CPU affinity as:
-  // Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
+  // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
  // whereas Affinity3 is defined at [32:39] in MPIDR
-  CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
-                ((MpId & ARM_CORE_AFF3) >> 8);
+  CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | ((MpId & ARM_CORE_AFF3) >> 8);

  if (Revision == ARM_GIC_ARCH_REVISION_3) {
-    // 2 x 64KB frame:
-    //   Redistributor control frame + SGI Control & Generation frame
-    GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE
-                                  + ARM_GICR_SGI_PPI_FRAME_SIZE;
+    // 2 x 64KB frame: Redistributor control frame + SGI Control & Generation frame
+    GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_SGI_PPI_FRAME_SIZE;
  } else {
    ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
    return 0;
@@ -123,10 +112,7 @@ ArmGicSendSgiTo (
  IN  INTN          SgiId
  )
 {
-  MmioWrite32 (
-    GicDistributorBase + ARM_GIC_ICDSGIR,
-    ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId
-    );
+  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
 }

 /*
@@ -137,8 +123,7 @@ ArmGicSendSgiTo (
 * in the GICv3 the register value is only the InterruptId.
 *
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
- * @param InterruptId                 InterruptId read from the Interrupt
- *                                    Acknowledge Register
+ * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register
 *
 * @retval value returned by the Interrupt Acknowledge Register
 *
@@ -215,25 +200,16 @@ ArmGicEnableInterrupt (
      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
      SourceIsSpi (Source)) {
    // Write set-enable register
-    MmioWrite32 (
-      GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
-      1 << RegShift
-      );
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
  } else {
-    GicCpuRedistributorBase = GicGetCpuRedistributorBase (
-                                GicRedistributorBase,
-                                Revision
-                                );
+    GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
    if (GicCpuRedistributorBase == 0) {
      ASSERT_EFI_ERROR (EFI_NOT_FOUND);
      return;
    }

    // Write set-enable register
-    MmioWrite32 (
-      ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
-      1 << RegShift
-      );
+    MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset), 1 << RegShift);
  }
 }

@@ -259,24 +235,15 @@ ArmGicDisableInterrupt (
      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
      SourceIsSpi (Source)) {
    // Write clear-enable register
-    MmioWrite32 (
-      GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
-      1 << RegShift
-      );
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
  } else {
-    GicCpuRedistributorBase = GicGetCpuRedistributorBase (
-      GicRedistributorBase,
-      Revision
-      );
+    GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
    if (GicCpuRedistributorBase == 0) {
      return;
    }

    // Write clear-enable register
-    MmioWrite32 (
-      ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
-      1 << RegShift
-      );
+    MmioWrite32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * RegOffset), 1 << RegShift);
  }
 }

@@ -302,23 +269,15 @@ ArmGicIsInterruptEnabled (
  if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
      FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
      SourceIsSpi (Source)) {
-    Interrupts = ((MmioRead32 (
-                     GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
-                     )
-                  & (1 << RegShift)) != 0);
+    Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
  } else {
-    GicCpuRedistributorBase = GicGetCpuRedistributorBase (
-                                GicRedistributorBase,
-                                Revision
-                                );
+    GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);
    if (GicCpuRedistributorBase == 0) {
      return 0;
    }

    // Read set-enable register
-    Interrupts = MmioRead32 (
-                   ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
-                   );
+    Interrupts = MmioRead32 (GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * RegOffset));
  }

  return ((Interrupts & (1 << RegShift)) != 0);
--- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
@@ -0,0 +1,52 @@
+#/* @file
+#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmGicSecLib
+  FILE_GUID                      = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmGicLib
+
+[Sources]
+  ArmGicLib.c
+  ArmGicSecLib.c
+
+  GicV2/ArmGicV2Lib.c
+  GicV2/ArmGicV2SecLib.c
+
+[Sources.ARM]
+  GicV3/Arm/ArmGicV3.S     | GCC
+  GicV3/Arm/ArmGicV3.asm   | RVCT
+
+[Sources.AARCH64]
+  GicV3/AArch64/ArmGicV3.S
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  IoLib
+  ArmGicArchLib
+
+[Pcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[FeaturePcd]
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c
@@ -2,7 +2,7 @@

 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
+Portions copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>

 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
@@ -29,7 +29,6 @@ Abstract:
 #define ARM_GIC_DEFAULT_PRIORITY  0x80

 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;

 STATIC UINT32 mGicInterruptInterfaceBase;
 STATIC UINT32 mGicDistributorBase;
@@ -44,7 +43,6 @@ STATIC UINT32 mGicDistributorBase;
  @retval EFI_UNSUPPORTED   Source interrupt is not supported

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV2EnableInterruptSource (
@@ -72,7 +70,6 @@ GicV2EnableInterruptSource (
  @retval EFI_UNSUPPORTED   Source interrupt is not supported

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV2DisableInterruptSource (
@@ -101,7 +98,6 @@ GicV2DisableInterruptSource (
  @retval EFI_UNSUPPORTED   Source interrupt is not supported

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV2GetInterruptSourceState (
@@ -131,7 +127,6 @@ GicV2GetInterruptSourceState (
  @retval EFI_UNSUPPORTED   Source interrupt is not supported

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV2EndOfInterrupt (
@@ -152,15 +147,13 @@ GicV2EndOfInterrupt (
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.

  @param  InterruptType    Defines the type of interrupt or exception that
-                           occurred on the processor.This parameter is
-                           processor architecture specific.
+                           occurred on the processor.This parameter is processor architecture specific.
  @param  SystemContext    A pointer to the processor context when
                           the interrupt occurred on the processor.

  @return None

 **/
-STATIC
 VOID
 EFIAPI
 GicV2IrqInterruptHandler (
@@ -173,10 +166,9 @@ GicV2IrqInterruptHandler (

  GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);

-  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
-  // number of interrupt (ie: Spurious interrupt).
+  // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
  if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
-    // The special interrupts do not need to be acknowledged
+    // The special interrupt do not need to be acknowledge
    return;
  }

@@ -185,12 +177,14 @@ GicV2IrqInterruptHandler (
    // Call the registered interrupt handler.
    InterruptHandler (GicInterrupt, SystemContext);
  } else {
-    DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
    GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
  }
 }

+//
 // The protocol instance produced by this driver
+//
 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
  RegisterInterruptSource,
  GicV2EnableInterruptSource,
@@ -199,151 +193,15 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
  GicV2EndOfInterrupt
 };

-/**
-  Get interrupt trigger type of an interrupt
-
-  @param This          Instance pointer for this protocol
-  @param Source        Hardware source of the interrupt.
-  @param TriggerType   Returns interrupt trigger type.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-GicV2GetTriggerType (
-  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,
-  IN  HARDWARE_INTERRUPT_SOURCE              Source,
-  OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  *TriggerType
-  )
-{
-  UINTN                   RegAddress;
-  UINTN                   Config1Bit;
-  EFI_STATUS              Status;
-
-  Status = GicGetDistributorIcfgBaseAndBit (
-              Source,
-              &RegAddress,
-              &Config1Bit
-              );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
-     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
-  } else {
-     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Set interrupt trigger type of an interrupt
-
-  @param This          Instance pointer for this protocol
-  @param Source        Hardware source of the interrupt.
-  @param TriggerType   Interrupt trigger type.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-GicV2SetTriggerType (
-  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,
-  IN  HARDWARE_INTERRUPT_SOURCE             Source,
-  IN  EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  TriggerType
-  )
-{
-  UINTN                   RegAddress;
-  UINTN                   Config1Bit;
-  UINT32                  Value;
-  EFI_STATUS              Status;
-  BOOLEAN                 SourceEnabled;
-
-  if (   (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
-      && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
-          DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
-                  TriggerType));
-          ASSERT (FALSE);
-          return EFI_UNSUPPORTED;
-  }
-
-  Status = GicGetDistributorIcfgBaseAndBit (
-             Source,
-             &RegAddress,
-             &Config1Bit
-             );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = GicV2GetInterruptSourceState (
-             (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-             Source,
-             &SourceEnabled
-             );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
-          ?  ARM_GIC_ICDICFR_EDGE_TRIGGERED
-          :  ARM_GIC_ICDICFR_LEVEL_TRIGGERED;
-
-  // Before changing the value, we must disable the interrupt,
-  // otherwise GIC behavior is UNPREDICTABLE.
-  if (SourceEnabled) {
-    GicV2DisableInterruptSource (
-      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-      Source
-      );
-  }
-
-  MmioAndThenOr32 (
-    RegAddress,
-    ~(0x1 << Config1Bit),
-    Value << Config1Bit
-    );
-
-  // Restore interrupt state
-  if (SourceEnabled) {
-    GicV2EnableInterruptSource (
-      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-      Source
-      );
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
-  (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
-  (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
-  (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
-  (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState,
-  (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt,
-  GicV2GetTriggerType,
-  GicV2SetTriggerType
-};
-
 /**
  Shutdown our hardware

-  DXE Core will disable interrupts and turn off the timer and disable
-  interrupts after all the event handlers have run.
+  DXE Core will disable interrupts and turn off the timer and disable interrupts
+  after all the event handlers have run.

  @param[in]  Event   The Event that is being processed
  @param[in]  Context Event Context
 **/
-STATIC
 VOID
 EFIAPI
 GicV2ExitBootServicesEvent (
@@ -398,8 +256,7 @@ GicV2DxeInitialize (
  UINTN                   RegShift;
  UINT32                  CpuTarget;

-  // Make sure the Interrupt Controller Protocol is not already installed in
-  // the system.
+  // Make sure the Interrupt Controller Protocol is not already installed in the system.
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);

  mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
@@ -419,27 +276,25 @@ GicV2DxeInitialize (
      );
  }

+  //
  // Targets the interrupts to the Primary Cpu
+  //

-  // Only Primary CPU will run this code. We can identify our GIC CPU ID by
-  // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn
-  // are banked to each connected CPU. These 8 registers hold the CPU targets
-  // fields for interrupts 0-31. More Info in the GIC Specification about
-  // "Interrupt Processor Targets Registers"
-
-  // Read the first Interrupt Processor Targets Register (that corresponds to
-  // the 4 first SGIs)
+  // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
+  // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
+  // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
+  // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
+  //
+  // Read the first Interrupt Processor Targets Register (that corresponds to the 4
+  // first SGIs)
  CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);

-  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
-  // This value is 0 when we run on a uniprocessor platform.
+  // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
+  // is 0 when we run on a uniprocessor platform.
  if (CpuTarget != 0) {
    // The 8 first Interrupt Processor Targets Registers are read-only
    for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
-      MmioWrite32 (
-        mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
-        CpuTarget
-        );
+      MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
    }
  }

@@ -456,11 +311,7 @@ GicV2DxeInitialize (
  ArmGicEnableDistributor (mGicDistributorBase);

  Status = InstallAndRegisterInterruptService (
-             &gHardwareInterruptV2Protocol,
-             &gHardwareInterrupt2V2Protocol,
-             GicV2IrqInterruptHandler,
-             GicV2ExitBootServicesEvent
-             );
+          &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);

  return Status;
 }
--- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
+++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2SecLib.c
@@ -0,0 +1,100 @@
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+/*
+ * This function configures the all interrupts to be Non-secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicV2SetupNonSecure (
+  IN  UINTN         MpId,
+  IN  INTN          GicDistributorBase,
+  IN  INTN          GicInterruptInterfaceBase
+  )
+{
+  UINTN InterruptId;
+  UINTN CachedPriorityMask;
+  UINTN Index;
+  UINTN MaxInterrupts;
+
+  CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
+
+  // Set priority Mask so that no interrupts get through to CPU
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
+
+  InterruptId   = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+  MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
+
+  // Only try to clear valid interrupts. Ignore spurious interrupts.
+  while ((InterruptId & 0x3FF) < MaxInterrupts) {
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+    ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId);
+
+    // Next
+    InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+  }
+
+  // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
+  if (ArmPlatformIsPrimaryCore (MpId)) {
+    // Ensure all GIC interrupts are Non-Secure
+    for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
+      MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
+    }
+  } else {
+    // The secondary cores only set the Non Secure bit to their banked PPIs
+    MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
+  }
+
+  // Ensure all interrupts can get through the priority mask
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
+}
+
+VOID
+EFIAPI
+ArmGicV2EnableInterruptInterface (
+  IN  INTN          GicInterruptInterfaceBase
+  )
+{
+  // Set Priority Mask to allow interrupts
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
+
+  // Enable CPU interface in Secure world
+  // Enable CPU interface in Non-secure World
+  // Signal Secure Interrupts to CPU using FIQ line *
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
+      ARM_GIC_ICCICR_ENABLE_SECURE |
+      ARM_GIC_ICCICR_ENABLE_NS |
+      ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
+}
+
+VOID
+EFIAPI
+ArmGicV2DisableInterruptInterface (
+  IN  INTN          GicInterruptInterfaceBase
+  )
+{
+  UINT32    ControlValue;
+
+  // Disable CPU interface in Secure world and Non-secure World
+  ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
+  MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
+}
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -19,7 +19,6 @@
 #define ARM_GIC_DEFAULT_PRIORITY  0x80

 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;

 STATIC UINTN mGicDistributorBase;
 STATIC UINTN mGicRedistributorsBase;
@@ -34,7 +33,6 @@ STATIC UINTN mGicRedistributorsBase;
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV3EnableInterruptSource (
@@ -62,7 +60,6 @@ GicV3EnableInterruptSource (
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV3DisableInterruptSource (
@@ -91,7 +88,6 @@ GicV3DisableInterruptSource (
  @retval EFI_DEVICE_ERROR  InterruptState is not valid

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV3GetInterruptSourceState (
@@ -105,11 +101,7 @@ GicV3GetInterruptSourceState (
    return EFI_UNSUPPORTED;
  }

-  *InterruptState = ArmGicIsInterruptEnabled (
-                      mGicDistributorBase,
-                      mGicRedistributorsBase,
-                      Source
-                      );
+  *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);

  return EFI_SUCCESS;
 }
@@ -125,7 +117,6 @@ GicV3GetInterruptSourceState (
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 **/
-STATIC
 EFI_STATUS
 EFIAPI
 GicV3EndOfInterrupt (
@@ -146,15 +137,13 @@ GicV3EndOfInterrupt (
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.

  @param  InterruptType    Defines the type of interrupt or exception that
-                           occurred on the processor. This parameter is
-                           processor architecture specific.
+                           occurred on the processor.This parameter is processor architecture specific.
  @param  SystemContext    A pointer to the processor context when
                           the interrupt occurred on the processor.

  @return None

 **/
-STATIC
 VOID
 EFIAPI
 GicV3IrqInterruptHandler (
@@ -179,12 +168,14 @@ GicV3IrqInterruptHandler (
    // Call the registered interrupt handler.
    InterruptHandler (GicInterrupt, SystemContext);
  } else {
-    DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
    GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);
  }
 }

+//
 // The protocol instance produced by this driver
+//
 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
  RegisterInterruptSource,
  GicV3EnableInterruptSource,
@@ -193,140 +184,6 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
  GicV3EndOfInterrupt
 };

-/**
-  Get interrupt trigger type of an interrupt
-
-  @param This          Instance pointer for this protocol
-  @param Source        Hardware source of the interrupt.
-  @param TriggerType   Returns interrupt trigger type.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-GicV3GetTriggerType (
-  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,
-  IN  HARDWARE_INTERRUPT_SOURCE             Source,
-  OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  *TriggerType
-  )
-{
-  UINTN                   RegAddress;
-  UINTN                   Config1Bit;
-  EFI_STATUS              Status;
-
-  Status = GicGetDistributorIcfgBaseAndBit (
-             Source,
-             &RegAddress,
-             &Config1Bit
-             );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
-     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
-  } else {
-     *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Set interrupt trigger type of an interrupt
-
-  @param This          Instance pointer for this protocol
-  @param Source        Hardware source of the interrupt.
-  @param TriggerType   Interrupt trigger type.
-
-  @retval EFI_SUCCESS       Source interrupt supported.
-  @retval EFI_UNSUPPORTED   Source interrupt is not supported.
-**/
-STATIC
-EFI_STATUS
-EFIAPI
-GicV3SetTriggerType (
-  IN  EFI_HARDWARE_INTERRUPT2_PROTOCOL      *This,
-  IN  HARDWARE_INTERRUPT_SOURCE             Source,
-  IN  EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE  TriggerType
-  )
-{
-  UINTN                   RegAddress;
-  UINTN                   Config1Bit;
-  UINT32                  Value;
-  EFI_STATUS              Status;
-  BOOLEAN                 SourceEnabled;
-
-  if (   (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
-      && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
-          DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
-                 TriggerType));
-          ASSERT (FALSE);
-          return EFI_UNSUPPORTED;
-  }
-
-  Status = GicGetDistributorIcfgBaseAndBit (
-             Source,
-             &RegAddress,
-             &Config1Bit
-             );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = GicV3GetInterruptSourceState (
-             (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-             Source,
-             &SourceEnabled
-             );
-
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
-          ?  ARM_GIC_ICDICFR_EDGE_TRIGGERED
-          :  ARM_GIC_ICDICFR_LEVEL_TRIGGERED;
-
-  // Before changing the value, we must disable the interrupt,
-  // otherwise GIC behavior is UNPREDICTABLE.
-  if (SourceEnabled) {
-    GicV3DisableInterruptSource (
-      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-      Source
-      );
-  }
-
-  MmioAndThenOr32 (
-    RegAddress,
-    ~(0x1 << Config1Bit),
-    Value << Config1Bit
-    );
-  // Restore interrupt state
-  if (SourceEnabled) {
-    GicV3EnableInterruptSource (
-      (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
-      Source
-      );
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
-  (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
-  (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
-  (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
-  (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState,
-  (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt,
-  GicV3GetTriggerType,
-  GicV3SetTriggerType
-};
-
 /**
  Shutdown our hardware

@@ -385,16 +242,17 @@ GicV3DxeInitialize (
  UINT64                  CpuTarget;
  UINT64                  MpId;

-  // Make sure the Interrupt Controller Protocol is not already installed in
-  // the system.
+  // Make sure the Interrupt Controller Protocol is not already installed in the system.
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);

  mGicDistributorBase    = PcdGet64 (PcdGicDistributorBase);
  mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase);
  mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);

+  //
  // We will be driving this GIC in native v3 mode, i.e., with Affinity
  // Routing enabled. So ensure that the ARE bit is set.
+  //
  if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
    MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
  }
@@ -412,65 +270,51 @@ GicV3DxeInitialize (
      );
  }

+  //
  // Targets the interrupts to the Primary Cpu
+  //

  if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
-    // Only Primary CPU will run this code. We can identify our GIC CPU ID by
-    // reading the GIC Distributor Target register. The 8 first
-    // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers
-    // hold the CPU targets fields for interrupts 0-31. More Info in the GIC
-    // Specification about "Interrupt Processor Targets Registers"
-
-    // Read the first Interrupt Processor Targets Register (that corresponds
-    // to the 4 first SGIs)
+    // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
+    // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
+    // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
+    // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
+    //
+    // Read the first Interrupt Processor Targets Register (that corresponds to the 4
+    // first SGIs)
    CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);

-    // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
-    // This value is 0 when we run on a uniprocessor platform.
+    // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
+    // is 0 when we run on a uniprocessor platform.
    if (CpuTarget != 0) {
      // The 8 first Interrupt Processor Targets Registers are read-only
      for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
-        MmioWrite32 (
-          mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
-          CpuTarget
-          );
+        MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
      }
    }
  } else {
    MpId = ArmReadMpidr ();
-    CpuTarget = MpId &
-      (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
-
-    if ((MmioRead32 (
-           mGicDistributorBase + ARM_GIC_ICDDCR
-         ) & ARM_GIC_ICDDCR_DS) != 0) {
+    CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);

+    if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {
+      //
      // If the Disable Security (DS) control bit is set, we are dealing with a
      // GIC that has only one security state. In this case, let's assume we are
      // executing in non-secure state (which is appropriate for DXE modules)
      // and that no other firmware has performed any configuration on the GIC.
      // This means we need to reconfigure all interrupts to non-secure Group 1
      // first.
-
-      MmioWrite32 (
-        mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR,
-        0xffffffff
-        );
+      //
+      MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);

      for (Index = 32; Index < mGicNumInterrupts; Index += 32) {
-        MmioWrite32 (
-          mGicDistributorBase + ARM_GIC_ICDISR + Index / 8,
-          0xffffffff
-          );
+        MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);
      }
    }

    // Route the SPIs to the primary CPU. SPIs start at the INTID 32
    for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
-      MmioWrite32 (
-        mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
-        CpuTarget | ARM_GICD_IROUTER_IRM
-        );
+      MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);
    }
  }

@@ -487,11 +331,7 @@ GicV3DxeInitialize (
  ArmGicEnableDistributor (mGicDistributorBase);

  Status = InstallAndRegisterInterruptService (
-             &gHardwareInterruptV3Protocol,
-             &gHardwareInterrupt2V3Protocol,
-             GicV3IrqInterruptHandler,
-             GicV3ExitBootServicesEvent
-             );
+          &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);

  return Status;
 }
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2013-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD
@@ -24,24 +24,24 @@
 #include <Library/UefiLib.h>
 #include <Library/ArmGenericTimerCounterLib.h>

-#include <Protocol/HardwareInterrupt2.h>
 #include <Protocol/WatchdogTimer.h>
+#include <Protocol/HardwareInterrupt.h>

 #include "GenericWatchdog.h"

-/* The number of 100ns periods (the unit of time passed to these functions)
-   in a second */
+// The number of 100ns periods (the unit of time passed to these functions)
+// in a second
 #define TIME_UNITS_PER_SECOND 10000000

-// Tick frequency of the generic timer basis of the generic watchdog.
+// Tick frequency of the generic timer that is the basis of the generic watchdog
 UINTN mTimerFrequencyHz = 0;

-/* In cases where the compare register was set manually, information about
-   how long the watchdog was asked to wait cannot be retrieved from hardware.
-   It is therefore stored here. 0 means the timer is not running. */
+// In cases where the compare register was set manually, information about
+// how long the watchdog was asked to wait cannot be retrieved from hardware.
+// It is therefore stored here. 0 means the timer is not running.
 UINT64 mNumTimerTicks = 0;

-EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
+EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol;

 EFI_STATUS
 WatchdogWriteOffsetRegister (
@@ -75,7 +75,8 @@ WatchdogDisable (
  return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);
 }

-/** On exiting boot services we must make sure the Watchdog Timer
+/**
+    On exiting boot services we must make sure the Watchdog Timer
    is stopped.
 **/
 VOID
@@ -89,8 +90,9 @@ WatchdogExitBootServicesEvent (
  mNumTimerTicks = 0;
 }

-/* This function is called when the watchdog's first signal (WS0) goes high.
-   It uses the ResetSystem Runtime Service to reset the board.
+/*
+  This function is called when the watchdog's first signal (WS0) goes high.
+  It uses the ResetSystem Runtime Service to reset the board.
 */
 VOID
 EFIAPI
@@ -99,7 +101,7 @@ WatchdogInterruptHandler (
  IN  EFI_SYSTEM_CONTEXT          SystemContext
  )
 {
-  STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";
+  STATIC CONST CHAR16      ResetString[] = L"The generic watchdog timer ran out.";

  WatchdogDisable ();

@@ -124,10 +126,10 @@ WatchdogInterruptHandler (
  then the new handler is registered and EFI_SUCCESS is returned.
  If NotifyFunction is NULL, and a handler is already registered,
  then that handler is unregistered.
-  If an attempt is made to register a handler when a handler is already
-  registered, then EFI_ALREADY_STARTED is returned.
-  If an attempt is made to unregister a handler when a handler is not
-  registered, then EFI_INVALID_PARAMETER is returned.
+  If an attempt is made to register a handler when a handler is already registered,
+  then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not registered,
+  then EFI_INVALID_PARAMETER is returned.

  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
  @param  NotifyFunction   The function to call when a timer interrupt fires.
@@ -137,7 +139,11 @@ WatchdogInterruptHandler (
                           information is used to signal timer based events.
                           NULL will unregister the handler.

-  @retval EFI_UNSUPPORTED       The code does not support NotifyFunction.
+  @retval EFI_SUCCESS           The watchdog timer handler was registered.
+  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is already
+                                registered.
+  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+                                previously registered.

 **/
 EFI_STATUS
@@ -154,18 +160,18 @@ WatchdogRegisterHandler (

 /**
  This function sets the amount of time to wait before firing the watchdog
-  timer to TimerPeriod 100ns units.  If TimerPeriod is 0, then the watchdog
+  timer to TimerPeriod 100 nS units.  If TimerPeriod is 0, then the watchdog
  timer is disabled.

  @param  This             The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
-  @param  TimerPeriod      The amount of time in 100ns units to wait before
-                           the watchdog timer is fired. If TimerPeriod is zero,
-                           then the watchdog timer is disabled.
+  @param  TimerPeriod      The amount of time in 100 nS units to wait before the watchdog
+                           timer is fired. If TimerPeriod is zero, then the watchdog
+                           timer is disabled.

-  @retval EFI_SUCCESS           The watchdog timer has been programmed to fire
-                                in Time  100ns units.
-  @retval EFI_DEVICE_ERROR      A watchdog timer could not be programmed due
-                                to a device error.
+  @retval EFI_SUCCESS           The watchdog timer has been programmed to fire in Time
+                                100 nS units.
+  @retval EFI_DEVICE_ERROR      A watchdog timer could not be programmed due to a device
+                                error.

 **/
 EFI_STATUS
@@ -178,7 +184,7 @@ WatchdogSetTimerPeriod (
  UINTN       SystemCount;
  EFI_STATUS  Status;

-  // if TimerPeriod is 0, this is a request to stop the watchdog.
+  // if TimerPerdiod is 0, this is a request to stop the watchdog.
  if (TimerPeriod == 0) {
    mNumTimerTicks = 0;
    return WatchdogDisable ();
@@ -187,14 +193,18 @@ WatchdogSetTimerPeriod (
  // Work out how many timer ticks will equate to TimerPeriod
  mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;

-  /* If the number of required ticks is greater than the max the watchdog's
-     offset register (WOR) can hold, we need to manually compute and set
-     the compare register (WCV) */
+  //
+  // If the number of required ticks is greater than the max number the
+  // watchdog's offset register (WOR) can hold, we need to manually compute and
+  // set the compare register (WCV)
+  //
  if (mNumTimerTicks > MAX_UINT32) {
-    /* We need to enable the watchdog *before* writing to the compare register,
-       because enabling the watchdog causes an "explicit refresh", which
-       clobbers the compare register (WCV). In order to make sure this doesn't
-       trigger an interrupt, set the offset to max. */
+    //
+    // We need to enable the watchdog *before* writing to the compare register,
+    // because enabling the watchdog causes an "explicit refresh", which
+    // clobbers the compare register (WCV). In order to make sure this doesn't
+    // trigger an interrupt, set the offset to max.
+    //
    Status = WatchdogWriteOffsetRegister (MAX_UINT32);
    if (EFI_ERROR (Status)) {
      return Status;
@@ -211,14 +221,14 @@ WatchdogSetTimerPeriod (
 }

 /**
-  This function retrieves the period of timer interrupts in 100ns units,
+  This function retrieves the period of timer interrupts in 100 ns units,
  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod
  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is
  returned, then the timer is currently disabled.

  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
-  @param  TimerPeriod      A pointer to the timer period to retrieve in
-                           100ns units. If 0 is returned, then the timer is
+  @param  TimerPeriod      A pointer to the timer period to retrieve in 100
+                           ns units. If 0 is returned, then the timer is
                           currently disabled.


@@ -265,19 +275,19 @@ WatchdogGetTimerPeriod (
        this function will not have any chance of executing.

  @param SetTimerPeriod
-  Sets the period of the timer interrupt in 100ns units.
+  Sets the period of the timer interrupt in 100 nS units.
  This function is optional, and may return EFI_UNSUPPORTED.
  If this function is supported, then the timer period will
  be rounded up to the nearest supported timer period.

  @param GetTimerPeriod
-  Retrieves the period of the timer interrupt in 100ns units.
+  Retrieves the period of the timer interrupt in 100 nS units.

 **/
 EFI_WATCHDOG_TIMER_ARCH_PROTOCOL    gWatchdogTimer = {
-  (EFI_WATCHDOG_TIMER_REGISTER_HANDLER)WatchdogRegisterHandler,
-  (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD)WatchdogSetTimerPeriod,
-  (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD)WatchdogGetTimerPeriod
+  (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler,
+  (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod,
+  (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod
 };

 EFI_EVENT                           EfiExitBootServicesEvent = (EFI_EVENT)NULL;
@@ -292,9 +302,11 @@ GenericWatchdogEntry (
  EFI_STATUS                      Status;
  EFI_HANDLE                      Handle;

-  /* Make sure the Watchdog Timer Architectural Protocol has not been installed
-     in the system yet.
-     This will avoid conflicts with the universal watchdog */
+  //
+  // Make sure the Watchdog Timer Architectural Protocol has not been installed
+  // in the system yet.
+  // This will avoid conflicts with the universal watchdog
+  //
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);

  mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();
@@ -302,46 +314,38 @@ GenericWatchdogEntry (

  // Register for an ExitBootServicesEvent
  Status = gBS->CreateEvent (
-                  EVT_SIGNAL_EXIT_BOOT_SERVICES,
-                  TPL_NOTIFY,
-                  WatchdogExitBootServicesEvent,
-                  NULL,
-                  &EfiExitBootServicesEvent
+                  EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+                  WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent
                  );
  if (!EFI_ERROR (Status)) {
    // Install interrupt handler
    Status = gBS->LocateProtocol (
-                    &gHardwareInterrupt2ProtocolGuid,
+                    &gHardwareInterruptProtocolGuid,
                    NULL,
                    (VOID **)&mInterruptProtocol
                    );
    if (!EFI_ERROR (Status)) {
      Status = mInterruptProtocol->RegisterInterruptSource (
-                 mInterruptProtocol,
-                 FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
-                 WatchdogInterruptHandler
-                 );
+                                    mInterruptProtocol,
+                                    FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+                                    WatchdogInterruptHandler
+                                    );
      if (!EFI_ERROR (Status)) {
-        Status = mInterruptProtocol->SetTriggerType (
-                   mInterruptProtocol,
-                   FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
-                   EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING
-                   );
-        if (!EFI_ERROR (Status)) {
-          // Install the Timer Architectural Protocol onto a new handle
-          Handle = NULL;
-          Status = gBS->InstallMultipleProtocolInterfaces (
-                          &Handle,
-                          &gEfiWatchdogTimerArchProtocolGuid,
-                          &gWatchdogTimer,
-                          NULL
-                          );
-        }
+        // Install the Timer Architectural Protocol onto a new handle
+        Handle = NULL;
+        Status = gBS->InstallMultipleProtocolInterfaces (
+                        &Handle,
+                        &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
+                        NULL
+                        );
      }
    }
  }

-  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    // The watchdog failed to initialize
+    ASSERT (FALSE);
+  }

  mNumTimerTicks = 0;
  WatchdogDisable ();
--- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2013-2017, ARM Limited. All rights reserved.
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -47,7 +47,7 @@

 [Protocols]
  gEfiWatchdogTimerArchProtocolGuid
-  gHardwareInterrupt2ProtocolGuid
+  gHardwareInterruptProtocolGuid

 [Depex]
-  gHardwareInterrupt2ProtocolGuid
+  gHardwareInterruptProtocolGuid
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -1,7 +1,7 @@
 /** @file

  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>

  This program and the accompanying materials
  are licensed and made available under the terms and conditions of the BSD License
@@ -235,14 +235,4 @@ ArmWriteCptr (
  IN  UINT64 Cptr
  );

-UINT32
-ArmReadCntHctl (
-  VOID
-  );
-
-VOID
-ArmWriteCntHctl (
-  IN UINT32 CntHctl
-  );
-
 #endif // __AARCH64_H__
--- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
@@ -1,43 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2012-2017, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __ARM_MM_SVC_H__
-#define __ARM_MM_SVC_H__
-
-/*
- * SVC IDs to allow the MM secure partition to initialise itself, handle
- * delegated events and request the Secure partition manager to perform
- * privileged operations on its behalf.
- */
-#define ARM_SVC_ID_SPM_VERSION_AARCH64             0xC4000060
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64       0xC4000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64   0xC4000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64   0xC4000065
-
-#define SET_MEM_ATTR_DATA_PERM_MASK       0x3
-#define SET_MEM_ATTR_DATA_PERM_SHIFT        0
-#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS    0
-#define SET_MEM_ATTR_DATA_PERM_RW           1
-#define SET_MEM_ATTR_DATA_PERM_RO           3
-
-#define SET_MEM_ATTR_CODE_PERM_MASK   0x1
-#define SET_MEM_ATTR_CODE_PERM_SHIFT    2
-#define SET_MEM_ATTR_CODE_PERM_X        0
-#define SET_MEM_ATTR_CODE_PERM_XN       1
-
-#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm)                            \
-    ((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
-    (( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
-
-#endif
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2012-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2012-2014, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -40,24 +40,6 @@
 #define ARM_SMC_STD_REVISION_MAJOR    0x0
 #define ARM_SMC_STD_REVISION_MINOR    0x1

-/*
- * Management Mode (MM) calls cover a subset of the Standard Service Call range.
- * The list below is not exhaustive.
- */
-#define ARM_SMC_ID_MM_VERSION_AARCH32              0x84000040
-#define ARM_SMC_ID_MM_VERSION_AARCH64              0xC4000040
-
-// Request service from secure standalone MM environment
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32          0x84000041
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64          0xC4000041
-
-/* MM return error codes */
-#define ARM_SMC_MM_RET_SUCCESS              0
-#define ARM_SMC_MM_RET_NOT_SUPPORTED       -1
-#define ARM_SMC_MM_RET_INVALID_PARAMS      -2
-#define ARM_SMC_MM_RET_DENIED              -3
-#define ARM_SMC_MM_RET_NO_MEMORY           -4
-
 /*
 * Power State Coordination Interface (PSCI) calls cover a subset of the
 * Standard Service Call range.
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -17,7 +17,9 @@

 #include <Library/ArmGicArchLib.h>

+//
 // GIC Distributor
+//
 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
@@ -49,17 +51,10 @@
 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)
 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)

-// GICD_ICDICFR bits
-#define ARM_GIC_ICDICFR_WIDTH            32   // ICDICFR is a 32 bit register
-#define ARM_GIC_ICDICFR_BYTES            (ARM_GIC_ICDICFR_WIDTH / 8)
-#define ARM_GIC_ICDICFR_F_WIDTH          2    // Each F field is 2 bits
-#define ARM_GIC_ICDICFR_F_STRIDE         16   // (32/2) F fields per register
-#define ARM_GIC_ICDICFR_F_CONFIG1_BIT    1    // Bit number within F field
-#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED  0x0  // Level triggered interrupt
-#define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1  // Edge triggered interrupt
-
-
+//
 // GIC Redistributor
+//
+
 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB
 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB

@@ -70,7 +65,9 @@
 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers

+//
 // GIC Cpu interface
+//
 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
@@ -107,7 +104,9 @@ ArmGicGetInterfaceIdentification (
  IN  INTN          GicInterruptInterfaceBase
  );

+//
 // GIC Secure interfaces
+//
 VOID
 EFIAPI
 ArmGicSetupNonSecure (
@@ -171,8 +170,7 @@ ArmGicSendSgiTo (
 * in the GICv3 the register value is only the InterruptId.
 *
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
- * @param InterruptId                 InterruptId read from the Interrupt
- *                                    Acknowledge Register
+ * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register
 *
 * @retval value returned by the Interrupt Acknowledge Register
 *
@@ -222,12 +220,12 @@ ArmGicIsInterruptEnabled (
  IN UINTN                  Source
  );

+//
 // GIC revision 2 specific declarations
+//

-// Interrupts from 1020 to 1023 are considered as special interrupts
-// (eg: spurious interrupts)
-#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
-          (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
+// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))

 VOID
 EFIAPI
@@ -262,7 +260,9 @@ ArmGicV2EndOfInterrupt (
  IN UINTN                  Source
  );

+//
 // GIC revision 3 specific declarations
+//

 #define ICC_SRE_EL2_SRE         (1 << 0)

--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -41,14 +41,6 @@ typedef enum {
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
-
-  // On some platforms, memory mapped flash region is designed as not supporting
-  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
-  // need.
-  // Do NOT use below two attributes if you are not sure.
-  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
-  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
-
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
--- a/ArmPkg/Include/Library/ArmSvcLib.h
+++ b/ArmPkg/Include/Library/ArmSvcLib.h
@@ -1,46 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __ARM_SVC_LIB__
-#define __ARM_SVC_LIB__
-
-/**
- * The size of the SVC arguments are different between AArch64 and AArch32.
- * The native size is used for the arguments.
- */
-typedef struct {
-  UINTN  Arg0;
-  UINTN  Arg1;
-  UINTN  Arg2;
-  UINTN  Arg3;
-  UINTN  Arg4;
-  UINTN  Arg5;
-  UINTN  Arg6;
-  UINTN  Arg7;
-} ARM_SVC_ARGS;
-
-/**
-  Trigger an SVC call
-
-  SVC calls can take up to 7 arguments and return up to 4 return values.
-  Therefore, the 4 first fields in the ARM_SVC_ARGS structure are used
-  for both input and output values.
-
-**/
-VOID
-ArmCallSvc (
-  IN OUT ARM_SVC_ARGS *Args
-  );
-
-#endif
--- a/ArmPkg/Include/Library/BdsLib.h
+++ b/ArmPkg/Include/Library/BdsLib.h
@@ -15,9 +15,6 @@
 #ifndef __BDS_ENTRY_H__
 #define __BDS_ENTRY_H__

-#define IS_DEVICE_PATH_NODE(node,type,subtype)    \
-        (((node)->Type == (type)) && ((node)->SubType == (subtype)))
-
 /**
  This is defined by the UEFI specs, don't change it
 **/
--- a/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
+++ b/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
@@ -0,0 +1,665 @@
+/** @file
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+#define __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+
+/**
+  Converts a cached or uncached address to a physical address suitable for use in SoC registers.
+
+  @param  VirtualAddress                 The pointer to convert.
+
+  @return The physical address of the supplied virtual pointer.
+
+**/
+EFI_PHYSICAL_ADDRESS
+ConvertToPhysicalAddress (
+  IN VOID *VirtualAddress
+  );
+
+/**
+  Converts a cached or uncached address to a cached address.
+
+  @param  Address                 The pointer to convert.
+
+  @return The address of the cached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToCachedAddress (
+  IN VOID *Address
+  );
+
+/**
+  Converts a cached or uncached address to an uncached address.
+
+  @param  Address                 The pointer to convert.
+
+  @return The address of the uncached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToUncachedAddress (
+  IN VOID *Address
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiBootServicesData.
+
+  Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePages (
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiRuntimeServicesData.
+
+  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePages (
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiReservedMemoryType.
+
+  Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPages (
+  IN UINTN  Pages
+  );
+
+/**
+  Frees one or more 4KB pages that were previously allocated with one of the page allocation
+  functions in the Memory Allocation Library.
+
+  Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer.  Buffer
+  must have been allocated on a previous call to the page allocation services of the Memory
+  Allocation Library.
+  If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
+  then ASSERT().
+  If Pages is zero, then ASSERT().
+
+  @param  Buffer                Pointer to the buffer of pages to free.
+  @param  Pages                 The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Frees one or more 4KB pages that were previously allocated with one of the aligned page
+  allocation functions in the Memory Allocation Library.
+
+  Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer.  Buffer
+  must have been allocated on a previous call to the aligned page allocation services of the Memory
+  Allocation Library.
+  If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
+  Library, then ASSERT().
+  If Pages is zero, then ASSERT().
+
+  @param  Buffer                Pointer to the buffer of pages to free.
+  @param  Pages                 The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates a buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a
+  pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates a buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns
+  a pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates a buffer of type EfieservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType and returns
+  a pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiReservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiReservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Frees a buffer that was previously allocated with one of the pool allocation functions in the
+  Memory Allocation Library.
+
+  Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the
+  pool allocation services of the Memory Allocation Library.
+  If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
+  then ASSERT().
+
+  @param  Buffer                Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePool (
+  IN VOID   *Buffer
+  );
+
+/**
+  Allocates a buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates a buffer of type EfieservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfieservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiReservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Frees a buffer that was previously allocated with one of the aligned pool allocation functions
+  in the Memory Allocation Library.
+
+  Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the
+  aligned pool allocation services of the Memory Allocation Library.
+  If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation
+  Library, then ASSERT().
+
+  @param  Buffer                Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPool (
+  IN VOID   *Buffer
+  );
+
+VOID
+EFIAPI
+UncachedSafeFreePool (
+  IN VOID   *Buffer
+  );
+
+#endif // __UNCACHED_MEMORY_ALLOCATION_LIB_H__
--- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
+++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
@@ -0,0 +1,342 @@
+/** @file
+  Generic ARM implementation of DmaLib.h
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Protocol/Cpu.h>
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS      HostAddress;
+  VOID                      *BufferAddress;
+  UINTN                     NumberOfBytes;
+  DMA_MAP_OPERATION         Operation;
+  BOOLEAN                   DoubleBuffer;
+} MAP_INFO_INSTANCE;
+
+
+
+STATIC EFI_CPU_ARCH_PROTOCOL      *mCpu;
+
+STATIC
+PHYSICAL_ADDRESS
+HostToDeviceAddress (
+  IN  PHYSICAL_ADDRESS  HostAddress
+  )
+{
+  return HostAddress + PcdGet64 (PcdArmDmaDeviceOffset);
+}
+
+/**
+  Provides the DMA controller-specific addresses needed to access system memory.
+
+  Operation is relative to the DMA bus master.
+
+  @param  Operation             Indicates if the bus master is going to read or write to system memory.
+  @param  HostAddress           The system memory address to map to the DMA controller.
+  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
+                                that were mapped.
+  @param  DeviceAddress         The resulting map address for the bus master controller to use to
+                                access the hosts HostAddress.
+  @param  Mapping               A resulting value to pass to Unmap().
+
+  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
+
+**/
+EFI_STATUS
+EFIAPI
+DmaMap (
+  IN     DMA_MAP_OPERATION              Operation,
+  IN     VOID                           *HostAddress,
+  IN OUT UINTN                          *NumberOfBytes,
+  OUT    PHYSICAL_ADDRESS               *DeviceAddress,
+  OUT    VOID                           **Mapping
+  )
+{
+  EFI_STATUS                      Status;
+  MAP_INFO_INSTANCE               *Map;
+  VOID                            *Buffer;
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
+
+  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL ) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Operation >= MapOperationMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // The debug implementation of UncachedMemoryAllocationLib in ArmPkg returns
+  // a virtual uncached alias, and unmaps the cached ID mapping of the buffer,
+  // in order to catch inadvertent references to the cached mapping.
+  // Since HostToDeviceAddress () expects ID mapped input addresses, convert
+  // the host address to an ID mapped address first.
+  //
+  *DeviceAddress = HostToDeviceAddress (ConvertToPhysicalAddress (HostAddress));
+
+  // Remember range so we can flush on the other side
+  Map = AllocatePool (sizeof (MAP_INFO_INSTANCE));
+  if (Map == NULL) {
+    return  EFI_OUT_OF_RESOURCES;
+  }
+
+  if ((((UINTN)HostAddress & (mCpu->DmaBufferAlignment - 1)) != 0) ||
+      ((*NumberOfBytes & (mCpu->DmaBufferAlignment - 1)) != 0)) {
+
+    // Get the cacheability of the region
+    Status = gDS->GetMemorySpaceDescriptor ((UINTN)HostAddress, &GcdDescriptor);
+    if (EFI_ERROR(Status)) {
+      goto FreeMapInfo;
+    }
+
+    // If the mapped buffer is not an uncached buffer
+    if ((GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) != 0) {
+      //
+      // Operations of type MapOperationBusMasterCommonBuffer are only allowed
+      // on uncached buffers.
+      //
+      if (Operation == MapOperationBusMasterCommonBuffer) {
+        DEBUG ((EFI_D_ERROR,
+          "%a: Operation type 'MapOperationBusMasterCommonBuffer' is only supported\n"
+          "on memory regions that were allocated using DmaAllocateBuffer ()\n",
+          __FUNCTION__));
+        Status = EFI_UNSUPPORTED;
+        goto FreeMapInfo;
+      }
+
+      //
+      // If the buffer does not fill entire cache lines we must double buffer into
+      // uncached memory. Device (PCI) address becomes uncached page.
+      //
+      Map->DoubleBuffer  = TRUE;
+      Status = DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (*NumberOfBytes), &Buffer);
+      if (EFI_ERROR (Status)) {
+        goto FreeMapInfo;
+      }
+
+      if (Operation == MapOperationBusMasterRead) {
+        CopyMem (Buffer, HostAddress, *NumberOfBytes);
+      }
+
+      *DeviceAddress = HostToDeviceAddress (ConvertToPhysicalAddress (Buffer));
+      Map->BufferAddress = Buffer;
+    } else {
+      Map->DoubleBuffer  = FALSE;
+    }
+  } else {
+    Map->DoubleBuffer  = FALSE;
+
+    DEBUG_CODE_BEGIN ();
+
+    //
+    // The operation type check above only executes if the buffer happens to be
+    // misaligned with respect to CWG, but even if it is aligned, we should not
+    // allow arbitrary buffers to be used for creating consistent mappings.
+    // So duplicate the check here when running in DEBUG mode, just to assert
+    // that we are not trying to create a consistent mapping for cached memory.
+    //
+    Status = gDS->GetMemorySpaceDescriptor ((UINTN)HostAddress, &GcdDescriptor);
+    ASSERT_EFI_ERROR(Status);
+
+    ASSERT (Operation != MapOperationBusMasterCommonBuffer ||
+            (GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) == 0);
+
+    DEBUG_CODE_END ();
+
+    // Flush the Data Cache (should not have any effect if the memory region is uncached)
+    mCpu->FlushDataCache (mCpu, (UINTN)HostAddress, *NumberOfBytes,
+            EfiCpuFlushTypeWriteBackInvalidate);
+  }
+
+  Map->HostAddress   = (UINTN)HostAddress;
+  Map->NumberOfBytes = *NumberOfBytes;
+  Map->Operation     = Operation;
+
+  *Mapping = Map;
+
+  return EFI_SUCCESS;
+
+FreeMapInfo:
+  FreePool (Map);
+
+  return Status;
+}
+
+
+/**
+  Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
+  operation and releases any corresponding resources.
+
+  @param  Mapping               The mapping value returned from DmaMap*().
+
+  @retval EFI_SUCCESS           The range was unmapped.
+  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
+  @retval EFI_INVALID_PARAMETER An inconsistency was detected between the mapping type
+                                and the DoubleBuffer field
+
+**/
+EFI_STATUS
+EFIAPI
+DmaUnmap (
+  IN  VOID                         *Mapping
+  )
+{
+  MAP_INFO_INSTANCE *Map;
+  EFI_STATUS        Status;
+
+  if (Mapping == NULL) {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Map = (MAP_INFO_INSTANCE *)Mapping;
+
+  Status = EFI_SUCCESS;
+  if (Map->DoubleBuffer) {
+    ASSERT (Map->Operation != MapOperationBusMasterCommonBuffer);
+
+    if (Map->Operation == MapOperationBusMasterCommonBuffer) {
+      Status = EFI_INVALID_PARAMETER;
+    } else if (Map->Operation == MapOperationBusMasterWrite) {
+      CopyMem ((VOID *)(UINTN)Map->HostAddress, Map->BufferAddress,
+        Map->NumberOfBytes);
+    }
+
+    DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), Map->BufferAddress);
+
+  } else {
+    if (Map->Operation == MapOperationBusMasterWrite) {
+      //
+      // Make sure we read buffer from uncached memory and not the cache
+      //
+      mCpu->FlushDataCache (mCpu, Map->HostAddress, Map->NumberOfBytes,
+              EfiCpuFlushTypeInvalidate);
+    }
+  }
+
+  FreePool (Map);
+
+  return Status;
+}
+
+/**
+  Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
+  mapping.
+
+  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
+  @param  HostAddress           A pointer to store the base system memory address of the
+                                allocated range.
+
+                                @retval EFI_SUCCESS           The requested memory pages were allocated.
+  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+DmaAllocateBuffer (
+  IN  EFI_MEMORY_TYPE              MemoryType,
+  IN  UINTN                        Pages,
+  OUT VOID                         **HostAddress
+  )
+{
+  VOID    *Allocation;
+
+  if (HostAddress == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
+  //
+  // We used uncached memory to keep coherency
+  //
+  if (MemoryType == EfiBootServicesData) {
+    Allocation = UncachedAllocatePages (Pages);
+  } else if (MemoryType == EfiRuntimeServicesData) {
+    Allocation = UncachedAllocateRuntimePages (Pages);
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Allocation == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  *HostAddress = Allocation;
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Frees memory that was allocated with DmaAllocateBuffer().
+
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
+  @retval EFI_SUCCESS           The requested memory pages were freed.
+  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+                                was not allocated with DmaAllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+DmaFreeBuffer (
+  IN  UINTN                        Pages,
+  IN  VOID                         *HostAddress
+  )
+{
+  if (HostAddress == NULL) {
+     return EFI_INVALID_PARAMETER;
+  }
+
+  UncachedFreePages (HostAddress, Pages);
+  return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+ArmDmaLibConstructor (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS              Status;
+
+  // Get the Cpu protocol for later use
+  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+  ASSERT_EFI_ERROR(Status);
+
+  return Status;
+}
+
--- a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
+++ b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
@@ -1,7 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
-#
+#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -13,28 +12,39 @@
 #**/

 [Defines]
-  INF_VERSION                    = 0x00010018
-  BASE_NAME                      = ArmCrashDumpDxe
-  FILE_GUID                      = 0bda00b0-05d6-4bb8-bfc7-058ad13615cf
-  MODULE_TYPE                    = DXE_DRIVER
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmDmaLib
+  FILE_GUID                      = F1BD6B36-B705-43aa-8A28-33F58ED85EFB
+  MODULE_TYPE                    = UEFI_DRIVER
  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = ArmCrashDumpDxeInitialize
+  LIBRARY_CLASS                  = DmaLib
+  CONSTRUCTOR                    = ArmDmaLibConstructor

-[Sources]
-  ArmCrashDumpDxe.c
+[Sources.common]
+  ArmDmaLib.c

 [Packages]
-  ArmPkg/ArmPkg.dec
  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+

 [LibraryClasses]
  DebugLib
-  DefaultExceptionHandlerLib
+  DxeServicesTableLib
  UefiBootServicesTableLib
-  UefiDriverEntryPoint
+  MemoryAllocationLib
+  UncachedMemoryAllocationLib
+  IoLib
+  BaseMemoryLib

 [Protocols]
  gEfiCpuArchProtocolGuid

+[Guids]
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmDmaDeviceOffset
+
 [Depex]
  gEfiCpuArchProtocolGuid
--- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
+++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
@@ -320,36 +320,3 @@ CommonCExceptionHandler(

  DefaultExceptionHandler(ExceptionType, SystemContext);
 }
-
-/**
-  Initializes all CPU exceptions entries with optional extra initializations.
-
-  By default, this method should include all functionalities implemented by
-  InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
-  This could be done by calling InitializeCpuExceptionHandlers() directly
-  in this method besides the extra works.
-
-  InitData is optional and its use and content are processor arch dependent.
-  The typical usage of it is to convey resources which have to be reserved
-  elsewhere and are necessary for the extra initializations of exception.
-
-  @param[in]  VectorInfo    Pointer to reserved vector list.
-  @param[in]  InitData      Pointer to data optional for extra initializations
-                            of exception.
-
-  @retval EFI_SUCCESS             The exceptions have been successfully
-                                  initialized.
-  @retval EFI_INVALID_PARAMETER   VectorInfo or InitData contains invalid
-                                  content.
-
-**/
-EFI_STATUS
-EFIAPI
-InitializeCpuExceptionHandlersEx (
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL
-  )
-{
-  return InitializeCpuExceptionHandlers (VectorInfo);
-}
-
--- a/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.S
+++ b/ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.S
@@ -12,7 +12,7 @@
 //
 //

-#include <AsmMacroIoLib.h>
+#include <AsmMacroIoLibV8.h>

 .arch_extension virt

--- a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+++ b/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
@@ -30,6 +30,3 @@
 [Packages]
  MdePkg/MdePkg.dec
  ArmPkg/ArmPkg.dec
-
-[BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -1,7 +1,7 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
 # Copyright (c) 2016, Linaro Limited. All rights reserved.
 #
 # This program and the accompanying materials
@@ -403,11 +403,9 @@ ASM_FUNC(ArmEnableVFP)
  mov   x1, x30                 // Save LR
  bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
  mov   x30, x1                 // Restore LR
-  ubfx  x0, x0, #16, #4         // Extract the FP bits 16:19
-  cmp   x0, #0xF                // Check if FP bits are '1111b',
-                                // i.e. Floating Point not implemented
-  b.eq  4f                      // Exit when VFP is not implemented.
-
+  ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
+  cmp   x0, #0                  // VFP is implemented if '0'.
+  b.ne  4f                      // Exit if VFP not implemented.
  // FVP is implemented.
  // Make sure VFP exceptions are not trapped (to any exception level).
  mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
@@ -482,14 +480,4 @@ ASM_FUNC(ArmReadCurrentEL)
  mrs   x0, CurrentEL
  ret

-// UINT32 ArmReadCntHctl(VOID)
-ASM_FUNC(ArmReadCntHctl)
-  mrs   x0, cnthctl_el2
-  ret
-
-// VOID ArmWriteCntHctl(UINT32 CntHctl)
-ASM_FUNC(ArmWriteCntHctl)
-  msr   cnthctl_el2, x0
-  ret
-
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -35,10 +35,6 @@ ArmMemoryAttributeToPageAttribute (
  )
 {
  switch (Attributes) {
-  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
-    return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-
  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
    return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -128,7 +128,6 @@ PopulateLevel2PageTable (
  UINT32  SectionDescriptor;
  UINT32  TranslationTable;
  UINT32  BaseSectionAddress;
-  UINT32  FirstPageOffset;

  switch (Attributes) {
    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
@@ -200,12 +199,9 @@ PopulateLevel2PageTable (
        TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
  }

-  FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
-  PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
+  PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));
  Pages     = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;

-  ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
-
  for (Index = 0; Index < Pages; Index++) {
    *PageEntry++     =  TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
    PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
@@ -224,7 +220,6 @@ FillTranslationTable (
  UINT32  Attributes;
  UINT32  PhysicalBase;
  UINT64  RemainLength;
-  UINT32  PageMapLength;

  ASSERT(MemoryRegion->Length > 0);

@@ -273,31 +268,30 @@ FillTranslationTable (
  SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);

  while (RemainLength != 0) {
-    if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&
-        RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
-      // Case: Physical address aligned on the Section Size (1MB) && the length
-      // is greater than the Section Size
-      *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
-      PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
-      RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
-    } else {
-      PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE) -
-                      (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE);
+    if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {
+      if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
+        // Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size
+        *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+        PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+      } else {
+        // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
+        PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);

-      // Case: Physical address aligned on the Section Size (1MB) && the length
-      //       does not fill a section
+        // It must be the last entry
+        break;
+      }
+    } else {
      // Case: Physical address NOT aligned on the Section Size (1MB)
-      PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,
-        MemoryRegion->Attributes);
+      PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
+      // Aligned the address
+      PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);

      // If it is the last entry
      if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
        break;
      }
-
-      PhysicalBase += PageMapLength;
-      RemainLength -= PageMapLength;
    }
+    RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
  }
 }

--- a/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.S
+++ b/ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.S
@@ -11,7 +11,7 @@
 //
 //

-#include <AsmMacroIoLib.h>
+#include <AsmMacroIoLibV8.h>

 .arch_extension sec

--- a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+++ b/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
@@ -29,6 +29,3 @@
 [Packages]
  MdePkg/MdePkg.dec
  ArmPkg/ArmPkg.dec
-
-[BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu 7-A.security
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
@@ -1,115 +0,0 @@
-/** @file
-  ResetSystemLib implementation using PSCI calls
-
-  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/ResetSystemLib.h>
-#include <Library/ArmSmcLib.h>
-
-#include <IndustryStandard/ArmStdSmc.h>
-
-/**
-  This function causes a system-wide reset (cold reset), in which
-  all circuitry within the system returns to its initial state. This type of reset
-  is asynchronous to system operation and operates without regard to
-  cycle boundaries.
-
-  If this function returns, it means that the system does not support cold reset.
-**/
-VOID
-EFIAPI
-ResetCold (
-  VOID
-  )
-{
-  ARM_SMC_ARGS ArmSmcArgs;
-
-  // Send a PSCI 0.2 SYSTEM_RESET command
-  ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
-  ArmCallSmc (&ArmSmcArgs);
-}
-
-/**
-  This function causes a system-wide initialization (warm reset), in which all processors
-  are set to their initial state. Pending cycles are not corrupted.
-
-  If this function returns, it means that the system does not support warm reset.
-**/
-VOID
-EFIAPI
-ResetWarm (
-  VOID
-  )
-{
-  // Map a warm reset into a cold reset
-  ResetCold ();
-}
-
-/**
-  This function causes the system to enter a power state equivalent
-  to the ACPI G2/S5 or G3 states.
-
-  If this function returns, it means that the system does not support shutdown reset.
-**/
-VOID
-EFIAPI
-ResetShutdown (
-  VOID
-  )
-{
-  ARM_SMC_ARGS ArmSmcArgs;
-
-  // Send a PSCI 0.2 SYSTEM_OFF command
-  ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
-  ArmCallSmc (&ArmSmcArgs);
-}
-
-/**
-  This function causes the system to enter S3 and then wake up immediately.
-
-  If this function returns, it means that the system does not support S3 feature.
-**/
-VOID
-EFIAPI
-EnterS3WithImmediateWake (
-  VOID
-  )
-{
-  // Not implemented
-}
-
-/**
-  This function causes a systemwide reset. The exact type of the reset is
-  defined by the EFI_GUID that follows the Null-terminated Unicode string passed
-  into ResetData. If the platform does not recognize the EFI_GUID in ResetData
-  the platform must pick a supported reset type to perform.The platform may
-  optionally log the parameters from any non-normal reset that occurs.
-
-  @param[in]  DataSize   The size, in bytes, of ResetData.
-  @param[in]  ResetData  The data buffer starts with a Null-terminated string,
-                         followed by the EFI_GUID.
-**/
-VOID
-EFIAPI
-ResetPlatformSpecific (
-  IN UINTN   DataSize,
-  IN VOID    *ResetData
-  )
-{
-  // Map the platform specific reset as reboot
-  ResetCold ();
-}
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
@@ -1,35 +0,0 @@
-#/** @file
-#  ResetSystemLib implementation using PSCI calls
-#
-#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010019
-  BASE_NAME                      = ArmSmcPsciResetSystemLib
-  FILE_GUID                      = 18B12C83-7718-4D83-ADA4-87F2FE698DD4
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ResetSystemLib
-
-[Sources]
-  ArmSmcPsciResetSystemLib.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  ArmSmcLib
-  BaseLib
-  DebugLib
--- a/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S
+++ b/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S
@@ -1,46 +0,0 @@
-//
-//  Copyright (c) 2012 - 2017, ARM Limited. All rights reserved.
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ArmCallSvc)
-
-ASM_PFX(ArmCallSvc):
-  // Push frame pointer and return address on the stack
-  stp   x29, x30, [sp, #-32]!
-  mov   x29, sp
-
-  // Push x0 on the stack - The stack must always be quad-word aligned
-  str   x0, [sp, #16]
-
-  // Load the SVC arguments values into the appropriate registers
-  ldp   x6, x7, [x0, #48]
-  ldp   x4, x5, [x0, #32]
-  ldp   x2, x3, [x0, #16]
-  ldp   x0, x1, [x0, #0]
-
-  svc   #0
-
-  // Pop the ARM_SVC_ARGS structure address from the stack into x9
-  ldr   x9, [sp, #16]
-
-  // Store the SVC returned values into the ARM_SVC_ARGS structure.
-  // A SVC call can return up to 4 values - we do not need to store back x4-x7.
-  stp   x0, x1, [x9, #0]
-  stp   x2, x3, [x9, #16]
-
-  mov   x0, x9
-
-  ldp   x29, x30, [sp], #32
-  ret
--- a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S
+++ b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S
@@ -1,39 +0,0 @@
-//
-//  Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ArmCallSvc)
-
-ASM_PFX(ArmCallSvc):
-    // r0 will be popped just after the SVC call
-    push    {r0, r4-r8}
-
-    // Load the SVC arguments values into the appropriate registers
-    ldm     r0, {r0-r7}
-
-    svc     #0
-
-    // Load the ARM_SVC_ARGS structure address from the stack into r8
-    ldr     r8, [sp]
-
-    // Load the SVC returned values into the appropriate registers
-    // A SVC call can return up to 4 values - we do not need to store back r4-r7.
-    stm     r8, {r0-r3}
-
-    mov     r0, r8
-
-    // Restore the registers r4-r8
-    pop     {r1, r4-r8}
-    bx      lr
--- a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm
+++ b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm
@@ -1,39 +0,0 @@
-//
-//  Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-
-    INCLUDE AsmMacroExport.inc
-
- RVCT_ASM_EXPORT ArmCallSvc
-    // r0 will be popped just after the SVC call
-    push     {r0, r4-r8}
-
-    // Load the SVC arguments values into the appropriate registers
-    ldm     r0, {r0-r7}
-
-    svc     #0
-
-    // Load the ARM_SVC_ARGS structure address from the stack into r8
-    ldr     r8, [sp]
-
-    // Load the SVC returned values into the appropriate registers
-    // A SVC call can return up to 4 values - we do not need to store back r4-r7.
-    stm     r8, {r0-r3}
-
-    mov     r0, r8
-
-    // Restore the registers r4-r8
-    pop     {r1, r4-r8}
-    bx      lr
-
-    END
--- a/ArmPkg/Library/BdsLib/BdsAppLoader.c
+++ b/ArmPkg/Library/BdsLib/BdsAppLoader.c
@@ -0,0 +1,253 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+/**
+  Locate an EFI application in a the Firmware Volumes by its Name
+
+  @param  EfiAppGuid            Guid of the EFI Application into the Firmware Volume
+  @param  DevicePath            EFI Device Path of the EFI application
+
+  @return EFI_SUCCESS           The function completed successfully.
+  @return EFI_NOT_FOUND         The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateEfiApplicationInFvByName (
+  IN  CONST CHAR16*             EfiAppName,
+  OUT EFI_DEVICE_PATH           **DevicePath
+  )
+{
+  VOID                          *Key;
+  EFI_STATUS                    Status, FileStatus;
+  EFI_GUID                      NameGuid;
+  EFI_FV_FILETYPE               FileType;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINTN                         Size;
+  UINTN                         UiStringLen;
+  CHAR16                        *UiSection;
+  UINT32                        Authentication;
+  EFI_DEVICE_PATH               *FvDevicePath;
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH    FileDevicePath;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         NumberOfHandles;
+  UINTN                         Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+  ASSERT (DevicePath != NULL);
+
+  // Length of FilePath
+  UiStringLen = StrLen (EfiAppName);
+
+  // Locate all the Firmware Volume protocols.
+  Status = gBS->LocateHandleBuffer (
+                   ByProtocol,
+                   &gEfiFirmwareVolume2ProtocolGuid,
+                   NULL,
+                   &NumberOfHandles,
+                   &HandleBuffer
+                   );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  *DevicePath = NULL;
+
+  // Looking for FV with ACPI storage file
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+    //
+    // Get the protocol on this handle
+    // This should not fail because of LocateHandleBuffer
+    //
+    Status = gBS->HandleProtocol (
+                     HandleBuffer[Index],
+                     &gEfiFirmwareVolume2ProtocolGuid,
+                     (VOID**) &FvInstance
+                     );
+    if (EFI_ERROR (Status)) {
+      goto FREE_HANDLE_BUFFER;
+    }
+
+    // Allocate Key
+    Key = AllocatePool (FvInstance->KeySize);
+    ASSERT (Key != NULL);
+    ZeroMem (Key, FvInstance->KeySize);
+
+    do {
+      // Search in all files
+      FileType = EFI_FV_FILETYPE_ALL;
+
+      Status = FvInstance->GetNextFile (FvInstance, Key, &FileType, &NameGuid, &Attributes, &Size);
+      if (!EFI_ERROR (Status)) {
+        UiSection = NULL;
+        FileStatus = FvInstance->ReadSection (
+                      FvInstance,
+                      &NameGuid,
+                      EFI_SECTION_USER_INTERFACE,
+                      0,
+                      (VOID **)&UiSection,
+                      &Size,
+                      &Authentication
+                      );
+        if (!EFI_ERROR (FileStatus)) {
+          if (StrnCmp (EfiAppName, UiSection, UiStringLen) == 0) {
+            //
+            // We found a UiString match.
+            //
+            Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&FvDevicePath);
+
+            // Generate the Device Path for the file
+            EfiInitializeFwVolDevicepathNode (&FileDevicePath, &NameGuid);
+            *DevicePath = AppendDevicePathNode (FvDevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&FileDevicePath);
+            ASSERT (*DevicePath != NULL);
+
+            FreePool (Key);
+            FreePool (UiSection);
+            FreePool (HandleBuffer);
+            return FileStatus;
+          }
+          FreePool (UiSection);
+        }
+      }
+    } while (!EFI_ERROR (Status));
+
+    FreePool (Key);
+  }
+
+FREE_HANDLE_BUFFER:
+  FreePool (HandleBuffer);
+  return EFI_NOT_FOUND;
+}
+
+/**
+  Locate an EFI application in a the Firmware Volumes by its GUID
+
+  @param  EfiAppGuid            Guid of the EFI Application into the Firmware Volume
+  @param  DevicePath            EFI Device Path of the EFI application
+
+  @return EFI_SUCCESS           The function completed successfully.
+  @return EFI_NOT_FOUND         The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateEfiApplicationInFvByGuid (
+  IN  CONST EFI_GUID            *EfiAppGuid,
+  OUT EFI_DEVICE_PATH           **DevicePath
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_DEVICE_PATH               *FvDevicePath;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         NumberOfHandles;
+  UINTN                         Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINT32                        AuthenticationStatus;
+  EFI_FV_FILETYPE               Type;
+  UINTN                         Size;
+  CHAR16                        *UiSection;
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FvFileDevicePath;
+
+  ASSERT (DevicePath != NULL);
+
+  // Locate all the Firmware Volume protocols.
+  Status = gBS->LocateHandleBuffer (
+                   ByProtocol,
+                   &gEfiFirmwareVolume2ProtocolGuid,
+                   NULL,
+                   &NumberOfHandles,
+                   &HandleBuffer
+                   );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  *DevicePath = NULL;
+
+  // Looking for FV with ACPI storage file
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+    //
+    // Get the protocol on this handle
+    // This should not fail because of LocateHandleBuffer
+    //
+    Status = gBS->HandleProtocol (
+                     HandleBuffer[Index],
+                     &gEfiFirmwareVolume2ProtocolGuid,
+                     (VOID**) &FvInstance
+                     );
+    if (EFI_ERROR (Status)) {
+      goto FREE_HANDLE_BUFFER;
+    }
+
+    Status = FvInstance->ReadFile (
+                  FvInstance,
+                  EfiAppGuid,
+                  NULL,
+                  &Size,
+                  &Type,
+                  &Attributes,
+                  &AuthenticationStatus
+                  );
+    if (EFI_ERROR (Status)) {
+      //
+      // Skip if no EFI application file in the FV
+      //
+      continue;
+    } else {
+      UiSection = NULL;
+      Status = FvInstance->ReadSection (
+                    FvInstance,
+                    EfiAppGuid,
+                    EFI_SECTION_USER_INTERFACE,
+                    0,
+                    (VOID **)&UiSection,
+                    &Size,
+                    &AuthenticationStatus
+                    );
+      if (!EFI_ERROR (Status)) {
+        //
+        // Create the EFI Device Path for the application using the Filename of the application
+        //
+        *DevicePath = FileDevicePath (HandleBuffer[Index], UiSection);
+      } else {
+        Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID**)&FvDevicePath);
+        ASSERT_EFI_ERROR (Status);
+
+        //
+        // Create the EFI Device Path for the application using the EFI GUID of the application
+        //
+        EfiInitializeFwVolDevicepathNode (&FvFileDevicePath, EfiAppGuid);
+
+        *DevicePath = AppendDevicePathNode (FvDevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&FvFileDevicePath);
+        ASSERT (*DevicePath != NULL);
+      }
+      break;
+    }
+  }
+
+FREE_HANDLE_BUFFER:
+  //
+  // Free any allocated buffers
+  //
+  FreePool (HandleBuffer);
+
+  if (*DevicePath == NULL) {
+    return EFI_NOT_FOUND;
+  } else {
+    return EFI_SUCCESS;
+  }
+}
--- a/ArmPkg/Library/BdsLib/BdsFilePath.c
+++ b/ArmPkg/Library/BdsLib/BdsFilePath.c
--- a/ArmPkg/Library/BdsLib/BdsHelper.c
+++ b/ArmPkg/Library/BdsLib/BdsHelper.c
@@ -0,0 +1,183 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+EFI_STATUS
+ShutdownUefiBootServices (
+  VOID
+  )
+{
+  EFI_STATUS              Status;
+  UINTN                   MemoryMapSize;
+  EFI_MEMORY_DESCRIPTOR   *MemoryMap;
+  UINTN                   MapKey;
+  UINTN                   DescriptorSize;
+  UINT32                  DescriptorVersion;
+  UINTN                   Pages;
+
+  MemoryMap = NULL;
+  MemoryMapSize = 0;
+  Pages = 0;
+
+  do {
+    Status = gBS->GetMemoryMap (
+                    &MemoryMapSize,
+                    MemoryMap,
+                    &MapKey,
+                    &DescriptorSize,
+                    &DescriptorVersion
+                    );
+    if (Status == EFI_BUFFER_TOO_SMALL) {
+
+      Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+      MemoryMap = AllocatePages (Pages);
+
+      //
+      // Get System MemoryMap
+      //
+      Status = gBS->GetMemoryMap (
+                      &MemoryMapSize,
+                      MemoryMap,
+                      &MapKey,
+                      &DescriptorSize,
+                      &DescriptorVersion
+                      );
+    }
+
+    // Don't do anything between the GetMemoryMap() and ExitBootServices()
+    if (!EFI_ERROR(Status)) {
+      Status = gBS->ExitBootServices (gImageHandle, MapKey);
+      if (EFI_ERROR(Status)) {
+        FreePages (MemoryMap, Pages);
+        MemoryMap = NULL;
+        MemoryMapSize = 0;
+      }
+    }
+  } while (EFI_ERROR(Status));
+
+  return Status;
+}
+
+/**
+  Connect all DXE drivers
+
+  @retval EFI_SUCCESS           All drivers have been connected
+  @retval EFI_NOT_FOUND         No handles match the search.
+  @retval EFI_OUT_OF_RESOURCES  There is not resource pool memory to store the matching results.
+
+**/
+EFI_STATUS
+BdsConnectAllDrivers (
+  VOID
+  )
+{
+  UINTN                     HandleCount, Index;
+  EFI_HANDLE                *HandleBuffer;
+  EFI_STATUS                Status;
+
+  do {
+    // Locate all the driver handles
+    Status = gBS->LocateHandleBuffer (
+                AllHandles,
+                NULL,
+                NULL,
+                &HandleCount,
+                &HandleBuffer
+                );
+    if (EFI_ERROR (Status)) {
+      break;
+    }
+
+    // Connect every handles
+    for (Index = 0; Index < HandleCount; Index++) {
+      gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
+    }
+
+    if (HandleBuffer != NULL) {
+      FreePool (HandleBuffer);
+    }
+
+    // Check if new handles have been created after the start of the previous handles
+    Status = gDS->Dispatch ();
+  } while (!EFI_ERROR(Status));
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetGlobalEnvironmentVariable (
+  IN     CONST CHAR16*   VariableName,
+  IN     VOID*           DefaultValue,
+  IN OUT UINTN*          Size,
+  OUT    VOID**          Value
+  )
+{
+  return GetEnvironmentVariable (VariableName, &gEfiGlobalVariableGuid,
+           DefaultValue, Size, Value);
+}
+
+EFI_STATUS
+GetEnvironmentVariable (
+  IN     CONST CHAR16*   VariableName,
+  IN     EFI_GUID*       VendorGuid,
+  IN     VOID*           DefaultValue,
+  IN OUT UINTN*          Size,
+  OUT    VOID**          Value
+  )
+{
+  EFI_STATUS  Status;
+  UINTN       VariableSize;
+
+  // Try to get the variable size.
+  *Value = NULL;
+  VariableSize = 0;
+  Status = gRT->GetVariable ((CHAR16 *) VariableName, VendorGuid, NULL, &VariableSize, *Value);
+  if (Status == EFI_NOT_FOUND) {
+    if ((DefaultValue != NULL) && (Size != NULL) && (*Size != 0)) {
+      // If the environment variable does not exist yet then set it with the default value
+      Status = gRT->SetVariable (
+                    (CHAR16*)VariableName,
+                    VendorGuid,
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+                    *Size,
+                    DefaultValue
+                    );
+      *Value = AllocateCopyPool (*Size, DefaultValue);
+    } else {
+      return EFI_NOT_FOUND;
+    }
+  } else if (Status == EFI_BUFFER_TOO_SMALL) {
+    // Get the environment variable value
+    *Value = AllocatePool (VariableSize);
+    if (*Value == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    Status = gRT->GetVariable ((CHAR16 *)VariableName, VendorGuid, NULL, &VariableSize, *Value);
+    if (EFI_ERROR (Status)) {
+      FreePool(*Value);
+      return EFI_INVALID_PARAMETER;
+    }
+
+    if (Size) {
+      *Size = VariableSize;
+    }
+  } else {
+    *Value = AllocateCopyPool (*Size, DefaultValue);
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
--- a/ArmPkg/Library/BdsLib/BdsInternal.h
+++ b/ArmPkg/Library/BdsLib/BdsInternal.h
@@ -0,0 +1,111 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __BDS_INTERNAL_H__
+#define __BDS_INTERNAL_H__
+
+#include <PiDxe.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BdsLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include <Guid/GlobalVariable.h>
+#include <Guid/FileInfo.h>
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/DevicePathFromText.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/LoadFile.h>
+#include <Protocol/PxeBaseCode.h>
+
+#include <Uefi.h>
+
+/**
+ * Check if the file loader can support this device path.
+ *
+ * @param DevicePath    EFI Device Path of the image to load.
+ *                      This device path generally comes from the boot entry (ie: Boot####).
+ * @param Handle        Handle of the driver supporting the device path
+ * @param RemainingDevicePath   Part of the EFI Device Path that has not been resolved during
+ *                      the Device Path discovery
+ */
+typedef BOOLEAN (*BDS_FILE_LOADER_SUPPORT) (
+  IN EFI_DEVICE_PATH            *DevicePath,
+  IN EFI_HANDLE                 Handle,
+  IN EFI_DEVICE_PATH            *RemainingDevicePath
+  );
+
+/**
+ * Function to load an image from a given Device Path for a
+ * specific support (FileSystem, TFTP, PXE, ...)
+ *
+ * @param DevicePath    EFI Device Path of the image to load.
+ *                      This device path generally comes from the boot entry (ie: Boot####).
+ *                      This path is also defined as 'OUT' as there are some device paths that
+ *                      might not be completed such as EFI path for removable device. In these
+ *                      cases, it is expected the loader to add \EFI\BOOT\BOOT(ARM|AA64).EFI
+ * @param Handle        Handle of the driver supporting the device path
+ * @param RemainingDevicePath   Part of the EFI Device Path that has not been resolved during
+ *                      the Device Path discovery
+ * @param Type          Define where the image should be loaded (see EFI_ALLOCATE_TYPE definition)
+ * @param Image         Base Address of the image has been loaded
+ * @param ImageSize     Size of the image that has been loaded
+ */
+typedef EFI_STATUS (*BDS_FILE_LOADER_LOAD_IMAGE) (
+  IN OUT EFI_DEVICE_PATH        **DevicePath,
+  IN     EFI_HANDLE             Handle,
+  IN     EFI_DEVICE_PATH        *RemainingDevicePath,
+  IN     EFI_ALLOCATE_TYPE      Type,
+  IN OUT EFI_PHYSICAL_ADDRESS*  Image,
+  OUT    UINTN                  *ImageSize
+  );
+
+typedef struct {
+  BDS_FILE_LOADER_SUPPORT     Support;
+  BDS_FILE_LOADER_LOAD_IMAGE  LoadImage;
+} BDS_FILE_LOADER;
+
+typedef struct _BDS_SYSTEM_MEMORY_RESOURCE {
+  LIST_ENTRY                  Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
+  EFI_PHYSICAL_ADDRESS        PhysicalStart;
+  UINT64                      ResourceLength;
+} BDS_SYSTEM_MEMORY_RESOURCE;
+
+typedef struct {
+  UINT64  FileSize;
+  UINT64  DownloadedNbOfBytes;
+  UINT64  LastReportedNbOfBytes;
+} BDS_TFTP_CONTEXT;
+
+EFI_STATUS
+BdsLoadImage (
+  IN     EFI_DEVICE_PATH       *DevicePath,
+  IN     EFI_ALLOCATE_TYPE     Type,
+  IN OUT EFI_PHYSICAL_ADDRESS* Image,
+  OUT    UINTN                 *FileSize
+  );
+
+#endif
--- a/ArmPkg/Library/BdsLib/BdsLib.inf
+++ b/ArmPkg/Library/BdsLib/BdsLib.inf
@@ -0,0 +1,69 @@
+#/* @file
+#
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = BdsLib
+  FILE_GUID                      = ddbf73a0-bb25-11df-8e4e-0002a5d5c51b
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = BdsLib
+
+[Sources.common]
+  BdsFilePath.c
+  BdsAppLoader.c
+  BdsHelper.c
+  BdsLoadOption.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseLib
+  DebugLib
+  DevicePathLib
+  HobLib
+  PcdLib
+  NetLib
+
+[Guids]
+  gEfiFileInfoGuid
+
+[Protocols]
+  gEfiBdsArchProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiDevicePathFromTextProtocolGuid
+  gEfiSimpleFileSystemProtocolGuid
+  gEfiFirmwareVolume2ProtocolGuid
+  gEfiLoadFileProtocolGuid
+  gEfiPxeBaseCodeProtocolGuid
+  gEfiDiskIoProtocolGuid
+  gEfiUsbIoProtocolGuid
+  gEfiLoadedImageProtocolGuid
+  gEfiSimpleNetworkProtocolGuid
+  gEfiDhcp4ServiceBindingProtocolGuid
+  gEfiDhcp4ProtocolGuid
+  gEfiMtftp4ServiceBindingProtocolGuid
+  gEfiMtftp4ProtocolGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdMaxTftpFileSize
+
+[Depex]
+  TRUE
--- a/ArmPkg/Library/BdsLib/BdsLoadOption.c
+++ b/ArmPkg/Library/BdsLib/BdsLoadOption.c
@@ -0,0 +1,272 @@
+/** @file
+*
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+EFI_STATUS
+BootOptionParseLoadOption (
+  IN     EFI_LOAD_OPTION *EfiLoadOption,
+  IN     UINTN           EfiLoadOptionSize,
+  IN OUT BDS_LOAD_OPTION **BdsLoadOption
+  )
+{
+  BDS_LOAD_OPTION *LoadOption;
+  UINTN           DescriptionLength;
+  UINTN           EfiLoadOptionPtr;
+
+  if (EfiLoadOption == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (EfiLoadOptionSize < sizeof(UINT32) + sizeof(UINT16) + sizeof(CHAR16) + sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
+    return EFI_BAD_BUFFER_SIZE;
+  }
+
+  if (*BdsLoadOption == NULL) {
+    LoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
+    if (LoadOption == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+  } else {
+    LoadOption = *BdsLoadOption;
+  }
+
+  EfiLoadOptionPtr           = (UINTN)EfiLoadOption;
+  LoadOption->LoadOption     = EfiLoadOption;
+  LoadOption->LoadOptionSize = EfiLoadOptionSize;
+
+  LoadOption->Attributes         = *(UINT32*)EfiLoadOptionPtr;
+  LoadOption->FilePathListLength = *(UINT16*)(EfiLoadOptionPtr + sizeof(UINT32));
+  LoadOption->Description        = (CHAR16*)(EfiLoadOptionPtr + sizeof(UINT32) + sizeof(UINT16));
+  DescriptionLength              = StrSize (LoadOption->Description);
+  LoadOption->FilePathList       = (EFI_DEVICE_PATH_PROTOCOL*)(EfiLoadOptionPtr + sizeof(UINT32) + sizeof(UINT16) + DescriptionLength);
+
+  // If ((End of EfiLoadOptiony - Start of EfiLoadOption) == EfiLoadOptionSize) then No Optional Data
+  if ((UINTN)((UINTN)LoadOption->FilePathList + LoadOption->FilePathListLength - EfiLoadOptionPtr) == EfiLoadOptionSize) {
+    LoadOption->OptionalData     = NULL;
+    LoadOption->OptionalDataSize = 0;
+  } else {
+    LoadOption->OptionalData     = (VOID*)((UINTN)(LoadOption->FilePathList) + LoadOption->FilePathListLength);
+    LoadOption->OptionalDataSize = EfiLoadOptionSize - ((UINTN)LoadOption->OptionalData - EfiLoadOptionPtr);
+  }
+
+  if (*BdsLoadOption == NULL) {
+    *BdsLoadOption = LoadOption;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootOptionFromLoadOptionVariable (
+  IN  CHAR16*           BootVariableName,
+  OUT BDS_LOAD_OPTION** BdsLoadOption
+  )
+{
+  EFI_STATUS            Status;
+  EFI_LOAD_OPTION       *EfiLoadOption;
+  UINTN                 EfiLoadOptionSize;
+
+  Status = GetGlobalEnvironmentVariable (BootVariableName, NULL, &EfiLoadOptionSize, (VOID**)&EfiLoadOption);
+  if (!EFI_ERROR(Status)) {
+    *BdsLoadOption = NULL;
+    Status = BootOptionParseLoadOption (EfiLoadOption, EfiLoadOptionSize, BdsLoadOption);
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+BootOptionFromLoadOptionIndex (
+  IN  UINT16            LoadOptionIndex,
+  OUT BDS_LOAD_OPTION **BdsLoadOption
+  )
+{
+  CHAR16        BootVariableName[9];
+  EFI_STATUS    Status;
+
+  UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", LoadOptionIndex);
+
+  Status = BootOptionFromLoadOptionVariable (BootVariableName, BdsLoadOption);
+  if (!EFI_ERROR(Status)) {
+    (*BdsLoadOption)->LoadOptionIndex = LoadOptionIndex;
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+BootOptionToLoadOptionVariable (
+  IN BDS_LOAD_OPTION*   BdsLoadOption
+  )
+{
+  EFI_STATUS                    Status;
+  UINTN                         DescriptionSize;
+  //UINT16                        FilePathListLength;
+  EFI_DEVICE_PATH_PROTOCOL*     DevicePathNode;
+  UINTN                         NodeLength;
+  UINT8*                        EfiLoadOptionPtr;
+  VOID*                         OldLoadOption;
+  CHAR16                        BootVariableName[9];
+  UINTN                         BootOrderSize;
+  UINT16*                       BootOrder;
+
+  // If we are overwriting an existent Boot Option then we have to free previously allocated memory
+  if (BdsLoadOption->LoadOptionSize > 0) {
+    OldLoadOption = BdsLoadOption->LoadOption;
+  } else {
+    OldLoadOption = NULL;
+
+    // If this function is called at the creation of the Boot Device entry (not at the update) the
+    // BootOption->LoadOptionSize must be zero then we get a new BootIndex for this entry
+    BdsLoadOption->LoadOptionIndex = BootOptionAllocateBootIndex ();
+
+    //TODO: Add to the the Boot Entry List
+  }
+
+  DescriptionSize = StrSize(BdsLoadOption->Description);
+
+  // Ensure the FilePathListLength information is correct
+  ASSERT (GetDevicePathSize (BdsLoadOption->FilePathList) == BdsLoadOption->FilePathListLength);
+
+  // Allocate the memory for the EFI Load Option
+  BdsLoadOption->LoadOptionSize = sizeof(UINT32) + sizeof(UINT16) + DescriptionSize + BdsLoadOption->FilePathListLength + BdsLoadOption->OptionalDataSize;
+
+  BdsLoadOption->LoadOption = (EFI_LOAD_OPTION *)AllocateZeroPool (BdsLoadOption->LoadOptionSize);
+  if (BdsLoadOption->LoadOption == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  EfiLoadOptionPtr = (UINT8 *) BdsLoadOption->LoadOption;
+
+  //
+  // Populate the EFI Load Option and BDS Boot Option structures
+  //
+
+  // Attributes fields
+  *(UINT32*)EfiLoadOptionPtr = BdsLoadOption->Attributes;
+  EfiLoadOptionPtr += sizeof(UINT32);
+
+  // FilePath List fields
+  *(UINT16*)EfiLoadOptionPtr = BdsLoadOption->FilePathListLength;
+  EfiLoadOptionPtr += sizeof(UINT16);
+
+  // Boot description fields
+  CopyMem (EfiLoadOptionPtr, BdsLoadOption->Description, DescriptionSize);
+  EfiLoadOptionPtr += DescriptionSize;
+
+  // File path fields
+  DevicePathNode = BdsLoadOption->FilePathList;
+  while (!IsDevicePathEndType (DevicePathNode)) {
+    NodeLength = DevicePathNodeLength(DevicePathNode);
+    CopyMem (EfiLoadOptionPtr, DevicePathNode, NodeLength);
+    EfiLoadOptionPtr += NodeLength;
+    DevicePathNode = NextDevicePathNode (DevicePathNode);
+  }
+
+  // Set the End Device Path Type
+  SetDevicePathEndNode (EfiLoadOptionPtr);
+  EfiLoadOptionPtr += sizeof(EFI_DEVICE_PATH);
+
+  // Fill the Optional Data
+  if (BdsLoadOption->OptionalDataSize > 0) {
+    CopyMem (EfiLoadOptionPtr, BdsLoadOption->OptionalData, BdsLoadOption->OptionalDataSize);
+  }
+
+  // Case where the fields have been updated
+  if (OldLoadOption) {
+    // Now, the old data has been copied to the new allocated packed structure, we need to update the pointers of BdsLoadOption
+    BootOptionParseLoadOption (BdsLoadOption->LoadOption, BdsLoadOption->LoadOptionSize, &BdsLoadOption);
+    // Free the old packed structure
+    FreePool (OldLoadOption);
+  }
+
+  // Create/Update Boot#### environment variable
+  UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BdsLoadOption->LoadOptionIndex);
+  Status = gRT->SetVariable (
+      BootVariableName,
+      &gEfiGlobalVariableGuid,
+      EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+      BdsLoadOption->LoadOptionSize,
+      BdsLoadOption->LoadOption
+      );
+
+  // When it is a new entry we must add the entry to the BootOrder
+  if (OldLoadOption == NULL) {
+    // Add the new Boot Index to the list
+    Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+    if (!EFI_ERROR(Status)) {
+      BootOrder = ReallocatePool (BootOrderSize, BootOrderSize + sizeof(UINT16), BootOrder);
+      // Add the new index at the end
+      BootOrder[BootOrderSize / sizeof(UINT16)] = BdsLoadOption->LoadOptionIndex;
+      BootOrderSize += sizeof(UINT16);
+    } else {
+      // BootOrder does not exist. Create it
+      BootOrderSize = sizeof(UINT16);
+      BootOrder = &(BdsLoadOption->LoadOptionIndex);
+    }
+
+    // Update (or Create) the BootOrder environment variable
+    gRT->SetVariable (
+        L"BootOrder",
+        &gEfiGlobalVariableGuid,
+        EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+        BootOrderSize,
+        BootOrder
+        );
+    DEBUG((EFI_D_ERROR,"Create %s\n",BootVariableName));
+
+    // Free memory allocated by GetGlobalEnvironmentVariable
+    if (!EFI_ERROR(Status)) {
+      FreePool (BootOrder);
+    }
+  } else {
+    DEBUG((EFI_D_ERROR,"Update %s\n",BootVariableName));
+  }
+
+  return EFI_SUCCESS;
+}
+
+UINT16
+BootOptionAllocateBootIndex (
+  VOID
+  )
+{
+  EFI_STATUS        Status;
+  UINTN             Index;
+  UINT32            BootIndex;
+  UINT16            *BootOrder;
+  UINTN             BootOrderSize;
+  BOOLEAN           Found;
+
+  // Get the Boot Option Order from the environment variable
+  Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+  if (!EFI_ERROR(Status)) {
+    for (BootIndex = 0; BootIndex <= 0xFFFF; BootIndex++) {
+      Found = FALSE;
+      for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
+        if (BootOrder[Index] == BootIndex) {
+          Found = TRUE;
+          break;
+        }
+      }
+      if (!Found) {
+        return BootIndex;
+      }
+    }
+    FreePool (BootOrder);
+  }
+  // Return the first index
+  return 0;
+}
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -18,14 +18,11 @@

 #include <IndustryStandard/Pci22.h>
 #include <Library/BootLogoLib.h>
-#include <Library/CapsuleLib.h>
 #include <Library/DevicePathLib.h>
-#include <Library/HobLib.h>
 #include <Library/PcdLib.h>
 #include <Library/UefiBootManagerLib.h>
 #include <Library/UefiLib.h>
 #include <Protocol/DevicePath.h>
-#include <Protocol/EsrtManagement.h>
 #include <Protocol/GraphicsOutput.h>
 #include <Protocol/LoadedImage.h>
 #include <Protocol/PciIo.h>
@@ -450,21 +447,6 @@ PlatformBootManagerBeforeConsole (
  VOID
  )
 {
-  EFI_STATUS                    Status;
-  ESRT_MANAGEMENT_PROTOCOL      *EsrtManagement;
-
-  if (GetBootModeHob() == BOOT_ON_FLASH_UPDATE) {
-    DEBUG ((DEBUG_INFO, "ProcessCapsules Before EndOfDxe ......\n"));
-    Status = ProcessCapsules ();
-    DEBUG ((DEBUG_INFO, "ProcessCapsules returned %r\n", Status));
-  } else {
-    Status = gBS->LocateProtocol (&gEsrtManagementProtocolGuid, NULL,
-                    (VOID **)&EsrtManagement);
-    if (!EFI_ERROR (Status)) {
-      EsrtManagement->SyncEsrtFmp ();
-    }
-  }
-
  //
  // Signal EndOfDxe PI Event
  //
@@ -515,8 +497,6 @@ PlatformBootManagerBeforeConsole (
  PlatformRegisterOptionsAndKeys ();
 }

-#define VERSION_STRING_PREFIX    L"Tianocore/EDK2 firmware version "
-
 /**
  Do the platform specific action after the console is ready
  Possible things that can be done in PlatformBootManagerAfterConsole:
@@ -534,56 +514,20 @@ PlatformBootManagerAfterConsole (
  VOID
  )
 {
-  ESRT_MANAGEMENT_PROTOCOL      *EsrtManagement;
-  EFI_STATUS                    Status;
-  EFI_GRAPHICS_OUTPUT_PROTOCOL  *GraphicsOutput;
-  UINTN                         FirmwareVerLength;
-  UINTN                         PosX;
-  UINTN                         PosY;
-
-  FirmwareVerLength = StrLen (PcdGetPtr (PcdFirmwareVersionString));
+  EFI_STATUS      Status;

  //
  // Show the splash screen.
  //
  Status = BootLogoEnableLogo ();
  if (EFI_ERROR (Status)) {
-    if (FirmwareVerLength > 0) {
-      Print (VERSION_STRING_PREFIX L"%s\n",
-        PcdGetPtr (PcdFirmwareVersionString));
-    }
    Print (L"Press ESCAPE for boot options ");
-  } else if (FirmwareVerLength > 0) {
-    Status = gBS->HandleProtocol (gST->ConsoleOutHandle,
-                    &gEfiGraphicsOutputProtocolGuid, (VOID **)&GraphicsOutput);
-    if (!EFI_ERROR (Status)) {
-      PosX = (GraphicsOutput->Mode->Info->HorizontalResolution -
-              (StrLen (VERSION_STRING_PREFIX) + FirmwareVerLength) *
-              EFI_GLYPH_WIDTH) / 2;
-      PosY = 0;
-
-      PrintXY (PosX, PosY, NULL, NULL, VERSION_STRING_PREFIX L"%s",
-        PcdGetPtr (PcdFirmwareVersionString));
-    }
  }
-
  //
  // Connect the rest of the devices.
  //
  EfiBootManagerConnectAll ();

-  Status = gBS->LocateProtocol (&gEsrtManagementProtocolGuid, NULL,
-                  (VOID **)&EsrtManagement);
-  if (!EFI_ERROR (Status)) {
-    EsrtManagement->SyncEsrtFmp ();
-  }
-
-  if (GetBootModeHob() == BOOT_ON_FLASH_UPDATE) {
-    DEBUG((DEBUG_INFO, "ProcessCapsules After EndOfDxe ......\n"));
-    Status = ProcessCapsules ();
-    DEBUG((DEBUG_INFO, "ProcessCapsules returned %r\n", Status));
-  }
-
  //
  // Enumerate all possible boot options.
  //
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -43,11 +43,9 @@
  BaseLib
  BaseMemoryLib
  BootLogoLib
-  CapsuleLib
  DebugLib
  DevicePathLib
  DxeServicesLib
-  HobLib
  MemoryAllocationLib
  PcdLib
  PrintLib
@@ -59,7 +57,6 @@
  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport

 [FixedPcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
@@ -83,4 +80,3 @@
  gEfiLoadedImageProtocolGuid
  gEfiPciRootBridgeIoProtocolGuid
  gEfiSimpleFileSystemProtocolGuid
-  gEsrtManagementProtocolGuid
--- a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
+++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
@@ -0,0 +1,719 @@
+/** @file
+  UncachedMemoryAllocation lib that uses DXE Service to change cachability for
+  a buffer.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2014, AMR Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/ArmLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <Protocol/Cpu.h>
+
+STATIC EFI_CPU_ARCH_PROTOCOL    *mCpu;
+
+VOID *
+UncachedInternalAllocatePages (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages
+  );
+
+VOID *
+UncachedInternalAllocateAlignedPages (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages,
+  IN UINTN            Alignment
+  );
+
+
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS  Base;
+  VOID                  *Allocation;
+  UINTN                 Pages;
+  EFI_MEMORY_TYPE       MemoryType;
+  BOOLEAN               Allocated;
+  LIST_ENTRY            Link;
+  UINT64                Attributes;
+} FREE_PAGE_NODE;
+
+STATIC LIST_ENTRY  mPageList = INITIALIZE_LIST_HEAD_VARIABLE (mPageList);
+// Track the size of the non-allocated buffer in the linked-list
+STATIC UINTN   mFreedBufferSize = 0;
+
+/**
+ * This function firstly checks if the requested allocation can fit into one
+ * of the previously allocated buffer.
+ * If the requested allocation does not fit in the existing pool then
+ * the function makes a new allocation.
+ *
+ * @param MemoryType    Type of memory requested for the new allocation
+ * @param Pages         Number of requested page
+ * @param Alignment     Required alignment
+ * @param Allocation    Address of the newly allocated buffer
+ *
+ * @return EFI_SUCCESS  If the function manage to allocate a buffer
+ * @return !EFI_SUCCESS If the function did not manage to allocate a buffer
+ */
+STATIC
+EFI_STATUS
+AllocatePagesFromList (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages,
+  IN UINTN            Alignment,
+  OUT VOID            **Allocation
+  )
+{
+  EFI_STATUS       Status;
+  LIST_ENTRY      *Link;
+  FREE_PAGE_NODE  *Node;
+  FREE_PAGE_NODE  *NewNode;
+  UINTN            AlignmentMask;
+  EFI_PHYSICAL_ADDRESS Memory;
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+
+  // Alignment must be a power of two or zero.
+  ASSERT ((Alignment & (Alignment - 1)) == 0);
+
+  //
+  // Look in our list for the smallest page that could satisfy the new allocation
+  //
+  Node = NULL;
+  NewNode = NULL;
+  for (Link = mPageList.ForwardLink; Link != &mPageList; Link = Link->ForwardLink) {
+    Node = BASE_CR (Link, FREE_PAGE_NODE, Link);
+    if ((Node->Allocated == FALSE) && (Node->MemoryType == MemoryType)) {
+      // We have a node that fits our requirements
+      if (((UINTN)Node->Base & (Alignment - 1)) == 0) {
+        // We found a page that matches the page size
+        if (Node->Pages == Pages) {
+          Node->Allocated  = TRUE;
+          Node->Allocation = (VOID*)(UINTN)Node->Base;
+          *Allocation      = Node->Allocation;
+
+          // Update the size of the freed buffer
+          mFreedBufferSize  -= Pages * EFI_PAGE_SIZE;
+          return EFI_SUCCESS;
+        } else if (Node->Pages > Pages) {
+          if (NewNode == NULL) {
+            // It is the first node that could contain our new allocation
+            NewNode = Node;
+          } else if (NewNode->Pages > Node->Pages) {
+            // This node offers a smaller number of page.
+            NewNode = Node;
+          }
+        }
+      }
+    }
+  }
+  // Check if we have found a node that could contain our new allocation
+  if (NewNode != NULL) {
+    NewNode->Allocated  = TRUE;
+    NewNode->Allocation = (VOID*)(UINTN)NewNode->Base;
+    *Allocation         = NewNode->Allocation;
+    mFreedBufferSize    -= NewNode->Pages * EFI_PAGE_SIZE;
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Otherwise, we need to allocate a new buffer
+  //
+
+  // We do not want to over-allocate in case the alignment requirement does not
+  // require extra pages
+  if (Alignment > EFI_PAGE_SIZE) {
+    AlignmentMask  = Alignment - 1;
+    Pages          += EFI_SIZE_TO_PAGES (Alignment);
+  } else {
+    AlignmentMask  = 0;
+  }
+
+  Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, Pages, &Memory);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gDS->GetMemorySpaceDescriptor (Memory, &Descriptor);
+  if (EFI_ERROR (Status)) {
+    goto FreePages;
+  }
+
+  Status = gDS->SetMemorySpaceAttributes (Memory, EFI_PAGES_TO_SIZE (Pages),
+                  EFI_MEMORY_WC);
+  if (EFI_ERROR (Status)) {
+    goto FreePages;
+  }
+
+  //
+  // EFI_CPU_ARCH_PROTOCOL::SetMemoryAttributes() will preserve the original
+  // memory type attribute if no memory type is passed. Permission attributes
+  // will be replaced, so EFI_MEMORY_RO will be removed if present (although
+  // it would be a bug if that were the case for an AllocatePages() allocation)
+  //
+  Status = mCpu->SetMemoryAttributes (mCpu, Memory, EFI_PAGES_TO_SIZE (Pages),
+                   EFI_MEMORY_XP);
+  if (EFI_ERROR (Status)) {
+    goto FreePages;
+  }
+
+  InvalidateDataCacheRange ((VOID *)(UINTN)Memory, EFI_PAGES_TO_SIZE (Pages));
+
+  NewNode = AllocatePool (sizeof (FREE_PAGE_NODE));
+  if (NewNode == NULL) {
+    ASSERT (FALSE);
+    Status = EFI_OUT_OF_RESOURCES;
+    goto FreePages;
+  }
+
+  NewNode->Base       = Memory;
+  NewNode->Allocation = (VOID*)(((UINTN)Memory + AlignmentMask) & ~AlignmentMask);
+  NewNode->Pages      = Pages;
+  NewNode->Allocated  = TRUE;
+  NewNode->MemoryType = MemoryType;
+  NewNode->Attributes = Descriptor.Attributes;
+
+  InsertTailList (&mPageList, &NewNode->Link);
+
+  *Allocation = NewNode->Allocation;
+  return EFI_SUCCESS;
+
+FreePages:
+  gBS->FreePages (Memory, Pages);
+  return Status;
+}
+
+/**
+ * Free the memory allocation
+ *
+ * This function will actually try to find the allocation in the linked list.
+ * And it will then mark the entry as freed.
+ *
+ * @param  Allocation  Base address of the buffer to free
+ *
+ * @return EFI_SUCCESS            The allocation has been freed
+ * @return EFI_NOT_FOUND          The allocation was not found in the pool.
+ * @return EFI_INVALID_PARAMETER  If Allocation is NULL
+ *
+ */
+STATIC
+EFI_STATUS
+FreePagesFromList (
+  IN  VOID  *Allocation
+  )
+{
+  LIST_ENTRY      *Link;
+  FREE_PAGE_NODE  *Node;
+
+  if (Allocation == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (Link = mPageList.ForwardLink; Link != &mPageList; Link = Link->ForwardLink) {
+    Node = BASE_CR (Link, FREE_PAGE_NODE, Link);
+    if ((UINTN)Node->Allocation == (UINTN)Allocation) {
+      Node->Allocated = FALSE;
+
+      // Update the size of the freed buffer
+      mFreedBufferSize  += Node->Pages * EFI_PAGE_SIZE;
+
+      // If the size of the non-allocated reaches the threshold we raise a warning.
+      // It might be an expected behaviour in some cases.
+      // We might device to free some of these buffers later on.
+      if (mFreedBufferSize > PcdGet64 (PcdArmFreeUncachedMemorySizeThreshold)) {
+        DEBUG ((EFI_D_WARN, "Warning: The list of non-allocated buffer has reach the threshold.\n"));
+      }
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/**
+ * This function is automatically invoked when the driver exits
+ * It frees all the non-allocated memory buffer.
+ * This function is not responsible to free allocated buffer (eg: case of memory leak,
+ * runtime allocation).
+ */
+EFI_STATUS
+EFIAPI
+UncachedMemoryAllocationLibConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  return gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+}
+
+EFI_STATUS
+EFIAPI
+UncachedMemoryAllocationLibDestructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  LIST_ENTRY      *Link;
+  FREE_PAGE_NODE  *OldNode;
+
+  // Test if the list is empty
+  Link = mPageList.ForwardLink;
+  if (Link == &mPageList) {
+    return EFI_SUCCESS;
+  }
+
+  // Free all the pages and nodes
+  do {
+    OldNode = BASE_CR (Link, FREE_PAGE_NODE, Link);
+    // Point to the next entry
+    Link = Link->ForwardLink;
+
+    // We only free the non-allocated buffer
+    if (OldNode->Allocated == FALSE) {
+      gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)OldNode->Base, OldNode->Pages);
+
+      gDS->SetMemorySpaceAttributes ((EFI_PHYSICAL_ADDRESS)(UINTN)OldNode->Base,
+             EFI_PAGES_TO_SIZE (OldNode->Pages), OldNode->Attributes);
+
+      RemoveEntryList (&OldNode->Link);
+      FreePool (OldNode);
+    }
+  } while (Link != &mPageList);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Converts a cached or uncached address to a physical address suitable for use in SoC registers.
+
+  @param  VirtualAddress                 The pointer to convert.
+
+  @return The physical address of the supplied virtual pointer.
+
+**/
+EFI_PHYSICAL_ADDRESS
+ConvertToPhysicalAddress (
+  IN VOID *VirtualAddress
+  )
+{
+  return (EFI_PHYSICAL_ADDRESS)(UINTN)VirtualAddress;
+}
+
+
+VOID *
+UncachedInternalAllocatePages (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages
+  )
+{
+  return UncachedInternalAllocateAlignedPages (MemoryType, Pages, EFI_PAGE_SIZE);
+}
+
+
+VOID *
+EFIAPI
+UncachedAllocatePages (
+  IN UINTN  Pages
+  )
+{
+  return UncachedInternalAllocatePages (EfiBootServicesData, Pages);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimePages (
+  IN UINTN  Pages
+  )
+{
+  return UncachedInternalAllocatePages (EfiRuntimeServicesData, Pages);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedPages (
+  IN UINTN  Pages
+  )
+{
+  return UncachedInternalAllocatePages (EfiReservedMemoryType, Pages);
+}
+
+
+
+VOID
+EFIAPI
+UncachedFreePages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  )
+{
+  UncachedFreeAlignedPages (Buffer, Pages);
+  return;
+}
+
+
+VOID *
+UncachedInternalAllocateAlignedPages (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages,
+  IN UINTN            Alignment
+  )
+{
+  EFI_STATUS Status;
+  VOID   *Allocation;
+
+  if (Pages == 0) {
+    return NULL;
+  }
+
+  Allocation = NULL;
+  Status = AllocatePagesFromList (MemoryType, Pages, Alignment, &Allocation);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return NULL;
+  } else {
+    return Allocation;
+  }
+}
+
+
+VOID
+EFIAPI
+UncachedFreeAlignedPages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  )
+{
+  FreePagesFromList (Buffer);
+}
+
+
+VOID *
+UncachedInternalAllocateAlignedPool (
+  IN EFI_MEMORY_TYPE  PoolType,
+  IN UINTN            AllocationSize,
+  IN UINTN            Alignment
+  )
+{
+  VOID      *AlignedAddress;
+
+  //
+  // Alignment must be a power of two or zero.
+  //
+  ASSERT ((Alignment & (Alignment - 1)) == 0);
+
+  if (Alignment < EFI_PAGE_SIZE) {
+    Alignment = EFI_PAGE_SIZE;
+  }
+
+  AlignedAddress = UncachedInternalAllocateAlignedPages (PoolType, EFI_SIZE_TO_PAGES (AllocationSize), Alignment);
+  if (AlignedAddress == NULL) {
+    return NULL;
+  }
+
+  return (VOID *) AlignedAddress;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedPool (EfiBootServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedPool (EfiRuntimeServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedPool (EfiReservedMemoryType, AllocationSize, Alignment);
+}
+
+VOID *
+UncachedInternalAllocateAlignedZeroPool (
+  IN EFI_MEMORY_TYPE  PoolType,
+  IN UINTN            AllocationSize,
+  IN UINTN            Alignment
+  )
+{
+  VOID    *Memory;
+  Memory = UncachedInternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
+  if (Memory != NULL) {
+    Memory = ZeroMem (Memory, AllocationSize);
+  }
+  return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedZeroPool (EfiBootServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedZeroPool (EfiRuntimeServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedZeroPool (EfiReservedMemoryType, AllocationSize, Alignment);
+}
+
+VOID *
+UncachedInternalAllocateAlignedCopyPool (
+  IN EFI_MEMORY_TYPE  PoolType,
+  IN UINTN            AllocationSize,
+  IN CONST VOID       *Buffer,
+  IN UINTN            Alignment
+  )
+{
+  VOID  *Memory;
+
+  ASSERT (Buffer != NULL);
+  ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));
+
+  Memory = UncachedInternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
+  if (Memory != NULL) {
+    Memory = CopyMem (Memory, Buffer, AllocationSize);
+  }
+  return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedCopyPool (EfiBootServicesData, AllocationSize, Buffer, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedCopyPool (EfiRuntimeServicesData, AllocationSize, Buffer, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  )
+{
+  return UncachedInternalAllocateAlignedCopyPool (EfiReservedMemoryType, AllocationSize, Buffer, Alignment);
+}
+
+VOID
+EFIAPI
+UncachedFreeAlignedPool (
+  IN VOID   *Allocation
+  )
+{
+  UncachedFreePages (Allocation, 0);
+}
+
+VOID *
+UncachedInternalAllocatePool (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            AllocationSize
+  )
+{
+  UINTN CacheLineLength = ArmCacheWritebackGranule ();
+  return UncachedInternalAllocateAlignedPool (MemoryType, AllocationSize, CacheLineLength);
+}
+
+VOID *
+EFIAPI
+UncachedAllocatePool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocatePool (EfiBootServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimePool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocatePool (EfiRuntimeServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedPool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocatePool (EfiReservedMemoryType, AllocationSize);
+}
+
+VOID *
+UncachedInternalAllocateZeroPool (
+  IN EFI_MEMORY_TYPE  PoolType,
+  IN UINTN            AllocationSize
+  )
+{
+  VOID  *Memory;
+
+  Memory = UncachedInternalAllocatePool (PoolType, AllocationSize);
+  if (Memory != NULL) {
+    Memory = ZeroMem (Memory, AllocationSize);
+  }
+  return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateZeroPool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocateZeroPool (EfiBootServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimeZeroPool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocateZeroPool (EfiRuntimeServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedZeroPool (
+  IN UINTN  AllocationSize
+  )
+{
+  return UncachedInternalAllocateZeroPool (EfiReservedMemoryType, AllocationSize);
+}
+
+VOID *
+UncachedInternalAllocateCopyPool (
+  IN EFI_MEMORY_TYPE  PoolType,
+  IN UINTN            AllocationSize,
+  IN CONST VOID       *Buffer
+  )
+{
+  VOID  *Memory;
+
+  ASSERT (Buffer != NULL);
+  ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));
+
+  Memory = UncachedInternalAllocatePool (PoolType, AllocationSize);
+  if (Memory != NULL) {
+     Memory = CopyMem (Memory, Buffer, AllocationSize);
+  }
+  return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  )
+{
+  return UncachedInternalAllocateCopyPool (EfiBootServicesData, AllocationSize, Buffer);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  )
+{
+  return UncachedInternalAllocateCopyPool (EfiRuntimeServicesData, AllocationSize, Buffer);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  )
+{
+  return UncachedInternalAllocateCopyPool (EfiReservedMemoryType, AllocationSize, Buffer);
+}
+
+VOID
+EFIAPI
+UncachedFreePool (
+  IN VOID   *Buffer
+  )
+{
+  UncachedFreeAlignedPool (Buffer);
+}
+
+VOID
+EFIAPI
+UncachedSafeFreePool (
+  IN VOID   *Buffer
+  )
+{
+  if (Buffer != NULL) {
+    UncachedFreePool (Buffer);
+    Buffer = NULL;
+  }
+}
+
--- a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#  UncachedMemoryAllocation lib that uses DXE Service to change cachability for
+#  a buffer.
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = UncachedMemoryAllocationLib
+  FILE_GUID                      = DC101A1A-7525-429B-84AF-EEAA630E576C
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = UncachedMemoryAllocationLib
+  CONSTRUCTOR                    = UncachedMemoryAllocationLibConstructor
+  DESTRUCTOR                     = UncachedMemoryAllocationLibDestructor
+
+[Sources.common]
+  UncachedMemoryAllocationLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  ArmLib
+  MemoryAllocationLib
+  PcdLib
+  DxeServicesTableLib
+  CacheMaintenanceLib
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold
+
+[Protocols]
+  gEfiCpuArchProtocolGuid
+
+[Depex]
+  gEfiCpuArchProtocolGuid
--- a/ArmPkg/License.txt
+++ b/ArmPkg/License.txt
@@ -0,0 +1,26 @@
+Copyright (c) 2009-2010, Apple Inc. All rights reserved.
+Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
--- a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
@@ -0,0 +1,47 @@
+#
+#  Copyright (c) 2013-2015, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = ArmJunoPkg
+  PACKAGE_GUID                   = a1147a20-3144-4f8d-8295-b48311c8e4a4
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmJunoTokenSpaceGuid    =  { 0xa1147a20, 0x3144, 0x4f8d, { 0x82, 0x95, 0xb4, 0x83, 0x11, 0xc8, 0xe4, 0xa4 } }
+
+[PcdsFeatureFlag.common]
+  gArmJunoTokenSpaceGuid.PcdPciMaxPayloadFixup|FALSE|BOOLEAN|0x00000013
+
+[PcdsFixedAtBuild.common]
+  gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress|0x7FF20000|UINT64|0x0000000B
+  gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress|0x7FF30000|UINT64|0x0000000C
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress|0x40000000|UINT64|0x00000011
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x10000000|UINT64|0x00000012
+
+  gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB0000|UINT32|0x00000004
+  gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC0000|UINT32|0x00000005
+
+  # Juno Device Trees are loaded from NOR Flash
+  gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/board.dtb"|VOID*|0x00000008
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c
@@ -0,0 +1,78 @@
+/** @file
+
+  This file contains support for ACPI Tables that are generated at boot time.
+
+  Copyright (c) 2015, ARM Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmPlatform.h"
+#include "ArmJunoDxeInternal.h"
+
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+/*
+ * Memory Mapped Configuration Space Access Table (MCFG)
+ */
+typedef struct {
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER                        Header;
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Entry;
+} MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE;
+
+MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE mAcpiMcfgTable = {
+    {
+        ARM_ACPI_HEADER (
+          EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+          MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE,
+          EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
+        ),
+        0, // Reserved
+    }, {
+        FixedPcdGet32 (PcdPciConfigurationSpaceBaseAddress),
+        0, // PciSegmentGroupNumber
+        FixedPcdGet32 (PcdPciBusMin),
+        FixedPcdGet32 (PcdPciBusMax),
+        0 // Reserved;
+    }
+};
+
+/**
+ * Callback called when ACPI Protocol is installed
+ */
+VOID
+AcpiPciNotificationEvent (
+  IN  EFI_EVENT                Event,
+  IN  VOID                     *Context
+  )
+{
+  EFI_STATUS                Status;
+  EFI_ACPI_TABLE_PROTOCOL   *AcpiTableProtocol;
+  UINTN                     AcpiTableKey;
+
+  //
+  // Ensure the ACPI protocol is installed
+  //
+  Status = gBS->LocateProtocol (
+                  &gEfiAcpiTableProtocolGuid,
+                  NULL,
+                  (VOID**)&AcpiTableProtocol
+                  );
+  if (EFI_ERROR (Status)) {
+    return;
+  }
+
+  //
+  // Install MCFG Table
+  //
+  AcpiTableKey = 0;
+  Status = AcpiTableProtocol->InstallAcpiTable (AcpiTableProtocol, &mAcpiMcfgTable, sizeof (mAcpiMcfgTable), &AcpiTableKey);
+  ASSERT_EFI_ERROR (Status);
+}
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c
@@ -0,0 +1,549 @@
+/** @file
+*
+*  Copyright (c) 2013-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmJunoDxeInternal.h"
+#include <ArmPlatform.h>
+
+#include <IndustryStandard/Pci.h>
+#include <Protocol/DevicePathFromText.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#include <Guid/EventGroup.h>
+#include <Guid/GlobalVariable.h>
+
+#include <Library/ArmShellCmdLib.h>
+#include <Library/AcpiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/PrintLib.h>
+
+
+// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
+STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } };
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH      AcpiDevicePath;
+  PCI_DEVICE_PATH           PciDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mPciRootComplexDevicePath = {
+    {
+      { ACPI_DEVICE_PATH,
+        ACPI_DP,
+        { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
+          (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) }
+      },
+      EISA_PNP_ID (0x0A03),
+      0
+    },
+    {
+      { HARDWARE_DEVICE_PATH,
+        HW_PCI_DP,
+        { (UINT8) (sizeof (PCI_DEVICE_PATH)),
+          (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) }
+      },
+      0,
+      0
+    },
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      { END_DEVICE_PATH_LENGTH, 0 }
+    }
+};
+
+EFI_EVENT mAcpiRegistration = NULL;
+
+/**
+  This function reads PCI ID of the controller.
+
+  @param[in]  PciIo   PCI IO protocol handle
+  @param[in]  PciId   Looking for specified PCI ID Vendor/Device
+**/
+STATIC
+EFI_STATUS
+ReadMarvellYoukonPciId (
+  IN EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN UINT32               PciId
+  )
+{
+  UINT32      DevicePciId;
+  EFI_STATUS  Status;
+
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint32,
+                        PCI_VENDOR_ID_OFFSET,
+                        1,
+                        &DevicePciId);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (DevicePciId != PciId) {
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function searches for Marvell Yukon NIC on the Juno
+  platform and returns PCI IO protocol handle for the controller.
+
+  @param[out]  PciIo   PCI IO protocol handle
+**/
+STATIC
+EFI_STATUS
+GetMarvellYukonPciIoProtocol (
+  OUT EFI_PCI_IO_PROTOCOL  **PciIo
+  )
+{
+  UINTN       HandleCount;
+  EFI_HANDLE  *HandleBuffer;
+  UINTN       HIndex;
+  EFI_STATUS  Status;
+
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiPciIoProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    return (Status);
+  }
+
+  for (HIndex = 0; HIndex < HandleCount; ++HIndex) {
+    // If PciIo opened with EFI_OPEN_PROTOCOL_GET_PROTOCOL, the CloseProtocol() is not required
+    Status = gBS->OpenProtocol (
+                    HandleBuffer[HIndex],
+                    &gEfiPciIoProtocolGuid,
+                    (VOID **) PciIo,
+                    NULL,
+                    NULL,
+                    EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+
+    Status = ReadMarvellYoukonPciId (*PciIo, JUNO_MARVELL_YUKON_ID);
+    if (EFI_ERROR (Status)) {
+      continue;
+    } else {
+      break;
+    }
+  }
+
+  gBS->FreePool (HandleBuffer);
+
+  return Status;
+}
+
+/**
+ This function restore the original controller attributes
+
+   @param[in]   PciIo               PCI IO protocol handle
+   @param[in]   PciAttr             PCI controller attributes.
+   @param[in]   AcpiResDescriptor   ACPI 2.0 resource descriptors for the BAR
+**/
+STATIC
+VOID
+RestorePciDev (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN UINT64                             PciAttr
+  )
+{
+  PciIo->Attributes (
+           PciIo,
+           EfiPciIoAttributeOperationSet,
+           PciAttr,
+           NULL
+           );
+}
+
+/**
+ This function returns PCI MMIO base address for a controller
+
+   @param[in]   PciIo               PCI IO protocol handle
+   @param[out]  PciRegBase          PCI base MMIO address
+**/
+STATIC
+EFI_STATUS
+BarIsDeviceMemory (
+  IN   EFI_PCI_IO_PROTOCOL *PciIo,
+  OUT  UINT32              *PciRegBase
+  )
+{
+  EFI_STATUS                         Status;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *AcpiResDescriptor;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *AcpiCurrentDescriptor;
+
+  // Marvell Yukon's Bar0 provides base memory address for control registers
+  Status = PciIo->GetBarAttributes (PciIo, PCI_BAR_IDX0, NULL, (VOID**)&AcpiResDescriptor);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  AcpiCurrentDescriptor = AcpiResDescriptor;
+
+  // Search for a memory type descriptor
+  while (AcpiCurrentDescriptor->Desc != ACPI_END_TAG_DESCRIPTOR) {
+
+    // Check if Bar is memory type one and fetch a base address
+    if (AcpiCurrentDescriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR &&
+        AcpiCurrentDescriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM &&
+        !(AcpiCurrentDescriptor->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) {
+      *PciRegBase = AcpiCurrentDescriptor->AddrRangeMin;
+      break;
+    } else {
+      Status = EFI_UNSUPPORTED;
+    }
+
+    AcpiCurrentDescriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (AcpiCurrentDescriptor + 1);
+  }
+
+  gBS->FreePool (AcpiResDescriptor);
+
+  return Status;
+}
+
+/**
+ This function provides PCI MMIO base address, old PCI controller attributes.
+
+   @param[in]   PciIo               PCI IO protocol handle
+   @param[out]  PciRegBase          PCI base MMIO address
+   @param[out]  OldPciAttr          Old PCI controller attributes.
+**/
+STATIC
+EFI_STATUS
+InitPciDev (
+  IN EFI_PCI_IO_PROTOCOL                 *PciIo,
+  OUT UINT32                             *PciRegBase,
+  OUT UINT64                             *OldPciAttr
+  )
+{
+  UINT64      AttrSupports;
+  EFI_STATUS  Status;
+
+  // Get controller's current attributes
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationGet,
+                    0,
+                    OldPciAttr);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Fetch supported attributes
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSupported,
+                    0,
+                    &AttrSupports);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Enable EFI_PCI_IO_ATTRIBUTE_IO, EFI_PCI_IO_ATTRIBUTE_MEMORY and
+  // EFI_PCI_IO_ATTRIBUTE_BUS_MASTER bits in the PCI Config Header
+  AttrSupports &= EFI_PCI_DEVICE_ENABLE;
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationEnable,
+                    AttrSupports,
+                    NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = BarIsDeviceMemory (PciIo, PciRegBase);
+  if (EFI_ERROR (Status)) {
+    RestorePciDev (PciIo, *OldPciAttr);
+  }
+
+  return Status;
+}
+
+/**
+ This function reads MAC address from IOFPGA and writes it to Marvell Yukon NIC
+
+   @param[in]   PciRegBase   PCI base MMIO address
+**/
+STATIC
+EFI_STATUS
+WriteMacAddress (
+  IN UINT32  PciRegBase
+  )
+{
+  UINT32  MacHigh;
+  UINT32  MacLow;
+
+  // Read MAC address from IOFPGA
+  MacHigh= MmioRead32 (ARM_JUNO_SYS_PCIGBE_H);
+  MacLow = MmioRead32 (ARM_JUNO_SYS_PCIGBE_L);
+
+  // Set software reset control register to protect from deactivation
+  // the config write state
+  MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);
+
+  // Convert to Marvell MAC Address register format
+  MacHigh = SwapBytes32 ((MacHigh & 0xFFFF) << 16 |
+                         (MacLow & 0xFFFF0000) >> 16);
+  MacLow = SwapBytes32 (MacLow) >> 16;
+
+  // Set MAC Address
+  MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_ENABLE);
+  MmioWrite32 (PciRegBase + R_MAC, MacHigh);
+  MmioWrite32 (PciRegBase + R_MAC_MAINT, MacHigh);
+  MmioWrite32 (PciRegBase + R_MAC + R_MAC_LOW, MacLow);
+  MmioWrite32 (PciRegBase + R_MAC_MAINT + R_MAC_LOW, MacLow);
+  MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_DISABLE);
+
+  // Initiate device reset
+  MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_SET);
+  MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  The function reads MAC address from Juno IOFPGA registers and writes it
+  into Marvell Yukon NIC.
+**/
+STATIC
+EFI_STATUS
+ArmJunoSetNicMacAddress ()
+{
+  UINT64                              OldPciAttr;
+  EFI_PCI_IO_PROTOCOL*                PciIo;
+  UINT32                              PciRegBase;
+  EFI_STATUS                          Status;
+
+  Status = GetMarvellYukonPciIoProtocol (&PciIo);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = InitPciDev (PciIo, &PciRegBase, &OldPciAttr);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = WriteMacAddress (PciRegBase);
+
+  RestorePciDev (PciIo, OldPciAttr);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Notification function of the event defined as belonging to the
+  EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in
+  the entry point of the driver.
+
+  This function is called when an event belonging to the
+  EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an
+  event is signalled once at the end of the dispatching of all
+  drivers (end of the so called DXE phase).
+
+  @param[in]  Event    Event declared in the entry point of the driver whose
+                       notification function is being invoked.
+  @param[in]  Context  NULL
+**/
+STATIC
+VOID
+OnEndOfDxe (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL* PciRootComplexDevicePath;
+  EFI_HANDLE                Handle;
+  EFI_STATUS                Status;
+
+  //
+  // PCI Root Complex initialization
+  // At the end of the DXE phase, we should get all the driver dispatched.
+  // Force the PCI Root Complex to be initialized. It allows the OS to skip
+  // this step.
+  //
+  PciRootComplexDevicePath = (EFI_DEVICE_PATH_PROTOCOL*) &mPciRootComplexDevicePath;
+  Status = gBS->LocateDevicePath (&gEfiPciRootBridgeIoProtocolGuid,
+                                  &PciRootComplexDevicePath,
+                                  &Handle);
+
+  Status = gBS->ConnectController (Handle, NULL, PciRootComplexDevicePath, FALSE);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ArmJunoSetNicMacAddress ();
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ArmJunoDxe: Failed to set Marvell Yukon NIC MAC address\n"));
+  }
+}
+
+EFI_STATUS
+EFIAPI
+ArmJunoEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  HypBase;
+  CHAR16                *TextDevicePath;
+  UINTN                 TextDevicePathSize;
+  VOID                  *Buffer;
+  UINT32                JunoRevision;
+  EFI_EVENT             EndOfDxeEvent;
+
+  //
+  // Register the OHCI and EHCI controllers as non-coherent
+  // non-discoverable devices.
+  //
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeOhci,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress),
+             SIZE_64KB
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeEhci,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress),
+             SIZE_64KB
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // If a hypervisor has been declared then we need to make sure its region is protected at runtime
+  //
+  // Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/)
+  //       that does not set up (yet) the stage 2 translation table to hide its own memory to EL1.
+  //
+  if (FixedPcdGet32 (PcdHypFvSize) != 0) {
+    // Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region.
+    // The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself.
+    // A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded
+    // to this size then there is a risk some non-runtime memory could be visible to the OS view.
+    if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) {
+      // The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space
+      // as it contains the Firmware.
+      Status = gDS->AddMemorySpace (
+          EfiGcdMemoryTypeSystemMemory,
+          FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize),
+          EFI_MEMORY_WB | EFI_MEMORY_RUNTIME
+          );
+      if (!EFI_ERROR (Status)) {
+        // We allocate the memory to ensure it is marked as runtime memory
+        HypBase = FixedPcdGet32 (PcdHypFvBaseAddress);
+        Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode,
+                                     EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase);
+      }
+    } else {
+      // The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned
+      // on a EFI_PAGE_SIZE boundary (ie: 4KB).
+      Status = EFI_UNSUPPORTED;
+      ASSERT_EFI_ERROR (Status);
+    }
+
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  // Install dynamic Shell command to run baremetal binaries.
+  Status = ShellDynCmdRunAxfInstall (ImageHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n"));
+  }
+
+  GetJunoRevision(JunoRevision);
+
+  //
+  // Try to install the ACPI Tables
+  //
+  Status = LocateAndInstallAcpiFromFv (&mJunoAcpiTableFile);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Setup R1/R2 options if not already done.
+  //
+  if (JunoRevision != JUNO_REVISION_R0) {
+    // Enable PCI enumeration
+    PcdSetBool (PcdPciDisableBusEnumeration, FALSE);
+
+    //
+    // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group.
+    // The "OnEndOfDxe()" function is declared as the call back function.
+    // It will be called at the end of the DXE phase when an event of the
+    // same group is signalled to inform about the end of the DXE phase.
+    // Install the INSTALL_FDT_PROTOCOL protocol.
+    //
+    Status = gBS->CreateEventEx (
+                    EVT_NOTIFY_SIGNAL,
+                    TPL_CALLBACK,
+                    OnEndOfDxe,
+                    NULL,
+                    &gEfiEndOfDxeEventGroupGuid,
+                    &EndOfDxeEvent
+                    );
+
+    // Declare the related ACPI Tables
+    EfiCreateProtocolNotifyEvent (
+        &gEfiAcpiTableProtocolGuid,
+        TPL_CALLBACK,
+        AcpiPciNotificationEvent,
+        NULL,
+        &mAcpiRegistration
+        );
+  }
+
+  //
+  // Set up the device path to the FDT.
+  //
+  TextDevicePath = (CHAR16*)FixedPcdGetPtr (PcdJunoFdtDevicePath);
+  if (TextDevicePath != NULL) {
+    TextDevicePathSize = StrSize (TextDevicePath);
+    Buffer = PcdSetPtr (PcdFdtDevicePaths, &TextDevicePathSize, TextDevicePath);
+    Status = (Buffer != NULL) ? EFI_SUCCESS : EFI_BUFFER_TOO_SMALL;
+  } else {
+    Status = EFI_NOT_FOUND;
+  }
+
+  if (EFI_ERROR (Status)) {
+    DEBUG (
+      (EFI_D_ERROR,
+      "ArmJunoDxe: Setting of FDT device path in PcdFdtDevicePaths failed - %r\n", Status)
+      );
+    return Status;
+  }
+
+  return Status;
+}
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
@@ -0,0 +1,90 @@
+#
+#  Copyright (c) 2013-2015, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmJunoDxe
+  FILE_GUID                      = 1484ebe8-2681-45f1-a2e5-12ecad893b62
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = ArmJunoEntryPoint
+
+[Sources.common]
+  AcpiTables.c
+  ArmJunoDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+  ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  AcpiLib
+  ArmLib
+  ArmShellCmdRunAxfLib
+  BaseMemoryLib
+  DebugLib
+  DmaLib
+  DxeServicesTableLib
+  IoLib
+  NonDiscoverableDeviceRegistrationLib
+  PcdLib
+  PrintLib
+  SerialPortLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  UefiLib
+  UefiDriverEntryPoint
+
+[Guids]
+  gEfiEndOfDxeEventGroupGuid
+  gEfiFileInfoGuid
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathFromTextProtocolGuid
+  gEfiPciIoProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+  gEfiSimpleFileSystemProtocolGuid
+  gEfiAcpiTableProtocolGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  gArmTokenSpaceGuid.PcdHypFvBaseAddress
+  gArmTokenSpaceGuid.PcdHypFvSize
+
+  gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress
+  gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress
+
+  gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath
+
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument
+
+  # PCI Root complex specific PCDs
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gArmTokenSpaceGuid.PcdPciBusMin
+  gArmTokenSpaceGuid.PcdPciBusMax
+
+[Pcd]
+  gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
+
+[Depex]
+  # We depend on these protocols to create the default boot entries
+  gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h
@@ -0,0 +1,54 @@
+/** @file
+*
+*  Copyright (c) 2013-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_JUNO_DXE_INTERNAL_H__
+#define __ARM_JUNO_DXE_INTERNAL_H__
+
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/ArmLib.h>
+#include <Library/AcpiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/AcpiTable.h>
+
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_SPECFLAG_PREFETCHABLE    0x06
+#define JUNO_MARVELL_YUKON_ID         0x438011AB /* Juno Marvell PCI Dev ID */
+#define TST_CFG_WRITE_ENABLE          0x02       /* Enable Config Write */
+#define TST_CFG_WRITE_DISABLE         0x00       /* Disable Config Write */
+#define CS_RESET_CLR                  0x02       /* SW Reset Clear */
+#define CS_RESET_SET                  0x00       /* SW Reset Set */
+#define R_CONTROL_STATUS              0x0004     /* Control/Status Register */
+#define R_MAC                         0x0100     /* MAC Address */
+#define R_MAC_MAINT                   0x0110     /* MAC Address Maintenance */
+#define R_MAC_LOW                     0x04       /* MAC Address Low Register Offset */
+#define R_TST_CTRL_1                  0x0158     /* Test Control Register 1 */
+
+
+/**
+ * Callback called when ACPI Protocol is installed
+ */
+VOID
+AcpiPciNotificationEvent (
+  IN  EFI_EVENT                Event,
+  IN  VOID                     *Context
+  );
+
+#endif // __ARM_JUNO_DXE_INTERNAL_H__
--- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
@@ -0,0 +1,124 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_JUNO_H__
+#define __ARM_JUNO_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE              0x1C010000
+#define ARM_VE_BOARD_SYS_ID                   0x0000
+#define ARM_VE_BOARD_SYS_PCIE_GBE_L           0x0074
+#define ARM_VE_BOARD_SYS_PCIE_GBE_H           0x0078
+
+#define ARM_VE_BOARD_SYS_ID_REV(word)         ((word >> 28) & 0xff)
+
+// NOR Flash 0
+#define ARM_VE_SMB_NOR0_BASE                  0x08000000
+#define ARM_VE_SMB_NOR0_SZ                    SIZE_64MB
+
+// Off-Chip peripherals (USB, Ethernet, VRAM)
+#define ARM_VE_SMB_PERIPH_BASE                0x18000000
+#define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_2MB)
+
+// On-Chip non-secure ROM
+#define ARM_JUNO_NON_SECURE_ROM_BASE          0x1F000000
+#define ARM_JUNO_NON_SECURE_ROM_SZ            SIZE_16MB
+
+// On-Chip Peripherals
+#define ARM_JUNO_PERIPHERALS_BASE             0x20000000
+#define ARM_JUNO_PERIPHERALS_SZ               0x0E000000
+
+// PCIe MSI address window
+#define ARM_JUNO_GIV2M_MSI_BASE               0x2c1c0000
+#define ARM_JUNO_GIV2M_MSI_SZ                 SIZE_256KB
+
+// PCIe MSI to SPI mapping range
+#define ARM_JUNO_GIV2M_MSI_SPI_BASE           224
+#define ARM_JUNO_GIV2M_MSI_SPI_COUNT          127 //TRM says last SPI is 351, 351-224=127
+
+// On-Chip non-secure SRAM
+#define ARM_JUNO_NON_SECURE_SRAM_BASE         0x2E000000
+#define ARM_JUNO_NON_SECURE_SRAM_SZ           SIZE_16MB
+
+// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
+#define ARM_JUNO_SOC_PERIPHERALS_BASE         0x7FF50000
+#define ARM_JUNO_SOC_PERIPHERALS_SZ           (SIZE_64KB * 9)
+
+// 6GB of DRAM from the 64bit address space
+#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE     0x0880000000
+#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ       (SIZE_2GB + SIZE_4GB)
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'A','R','M','L','T','D'   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x20140727
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('A','R','M',' ')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+//
+// Hardware platform identifiers
+//
+#define JUNO_REVISION_PROTOTYPE 0
+#define JUNO_REVISION_R0        1
+#define JUNO_REVISION_R1        2
+#define JUNO_REVISION_R2        3
+#define JUNO_REVISION_UKNOWN    0xFF
+
+//
+// We detect whether we are running on a Juno r0, r1 or r2
+// board at runtime by checking the value of board SYS_ID
+//
+#define GetJunoRevision(JunoRevision)                                  \
+{                                                                      \
+  UINT32    SysId;                                                     \
+  SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID);   \
+  JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId );                     \
+}
+
+#define JUNO_WATCHDOG_COUNT  2
+
+// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
+//#define ARM_JUNO_ACPI_5_0
+
+//
+// Address of the system registers that contain the MAC address
+// assigned to the PCI Gigabyte Ethernet device.
+//
+
+#define ARM_JUNO_SYS_PCIGBE_L  (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)
+#define ARM_JUNO_SYS_PCIGBE_H  (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)
+
+#endif
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/AArch64/ArmJunoHelper.S
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/AArch64/ArmJunoHelper.S
@@ -0,0 +1,58 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #7
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  ldr   w0, PrimaryCoreMpid
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+
+  ldr   w1, PrimaryCoreMpid
+
+  cmp   w0, w1
+  cset  x0, eq
+  ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  // The trusted firmware passes the primary CPU MPID through x0 register.
+  // Save it in a variable.
+  adr  x1, PrimaryCoreMpid
+  str  w0, [x1]
+  ret
+
+PrimaryCoreMpid:  .word    0x0
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/Arm/ArmJunoHelper.S
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/Arm/ArmJunoHelper.S
@@ -0,0 +1,91 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns the core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  LDRL  (r0, PrimaryCoreMpid)
+  bx    lr
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// The primary core is the core responsible to initialize the hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+//  @return   Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   r0, r0, r1
+
+  LDRL  (r1, PrimaryCoreMpid)
+
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_FUNC(ArmPlatformPeiBootAction)
+  // The trusted firmware passes the primary CPU MPID through r0 register.
+  // Save it in a variable.
+  adr  r1, PrimaryCoreMpid
+  str  r0, [r1]
+  bx   lr
+
+PrimaryCoreMpid:  .word    0x0
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJuno.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJuno.c
@@ -0,0 +1,193 @@
+/** @file
+*
+*  Copyright (c) 2013-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Drivers/PL011Uart.h>
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+ARM_CORE_INFO mJunoInfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 0
+    0x1, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 1
+    0x1, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 2
+    0x1, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 3
+    0x1, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  RETURN_STATUS       Status;
+  UINT64              BaudRate;
+  UINT32              ReceiveFifoDepth;
+  EFI_PARITY_TYPE     Parity;
+  UINT8               DataBits;
+  EFI_STOP_BITS_TYPE  StopBits;
+
+  Status = RETURN_SUCCESS;
+
+  //
+  // Initialize the Serial Debug UART
+  //
+  if (FixedPcdGet64 (PcdSerialDbgRegisterBase)) {
+    ReceiveFifoDepth = 0; // Use the default value for FIFO depth
+    Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+    DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+    StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
+
+    BaudRate = (UINTN)FixedPcdGet64 (PcdSerialDbgUartBaudRate);
+    Status = PL011UartInitializePort (
+               (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),
+               FixedPcdGet32 (PcdSerialDbgUartClkInHz),
+               &BaudRate,
+               &ReceiveFifoDepth,
+               &Parity,
+               &DataBits,
+               &StopBits
+               );
+  }
+
+  return Status;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  // Only support one cluster
+  *CoreCount    = sizeof(mJunoInfoTable) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mJunoInfoTable;
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
@@ -0,0 +1,80 @@
+#
+#  Copyright (c) 2013-2016, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmJunoLib
+  FILE_GUID                      = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  HobLib
+  MemoryAllocationLib
+  SerialPortLib
+
+[Sources.common]
+  ArmJuno.c
+  ArmJunoMem.c
+
+[Sources.AARCH64]
+  AArch64/ArmJunoHelper.S
+
+[Sources.ARM]
+  Arm/ArmJunoHelper.S     | GCC
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+  gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize
+
+
+  #
+  # PL011 Serial Debug UART
+  #
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdPciMmio32Base
+  gArmTokenSpaceGuid.PcdPciMmio32Size
+  gArmTokenSpaceGuid.PcdPciMmio64Base
+  gArmTokenSpaceGuid.PcdPciMmio64Size
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c
@@ -0,0 +1,173 @@
+/** @file
+*
+*  Copyright (c) 2013-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <ArmPlatform.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  //
+  // Declared the additional 6GB of memory
+  //
+  ResourceAttributes =
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    ResourceAttributes,
+    ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE,
+    ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  // SMB CS0 - NOR0 Flash
+  VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].Length          = SIZE_256KB * 255;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  // Environment Variables region
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].Length          = SIZE_64KB * 4;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SMB CS2 & CS3 - Off-chip (motherboard) peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_SMB_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // Juno OnChip non-secure ROM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_JUNO_NON_SECURE_ROM_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_JUNO_NON_SECURE_ROM_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_JUNO_NON_SECURE_ROM_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // Juno OnChip peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_JUNO_PERIPHERALS_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_JUNO_PERIPHERALS_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_JUNO_PERIPHERALS_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // Juno OnChip non-secure SRAM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_JUNO_NON_SECURE_SRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_JUNO_NON_SECURE_SRAM_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_JUNO_NON_SECURE_SRAM_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // PCI Root Complex
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPcieControlBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPcieControlBaseAddress);
+  VirtualMemoryTable[Index].Length          = SIZE_128KB;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  //
+  // PCI Configuration Space
+  //
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdPciConfigurationSpaceSize);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  //
+  // PCI Memory Space
+  //
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet32 (PcdPciMmio32Base);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet32 (PcdPciMmio32Base);
+  VirtualMemoryTable[Index].Length          = PcdGet32 (PcdPciMmio32Size);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  //
+  // 64-bit PCI Memory Space
+  //
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciMmio64Base);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciMmio64Base);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdPciMmio64Size);
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // Juno SOC peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_JUNO_SOC_PERIPHERALS_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_JUNO_SOC_PERIPHERALS_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_JUNO_SOC_PERIPHERALS_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DDR - 2GB
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // DDR - 6GB
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
+  VirtualMemoryTable[Index].Length          = 0;
+  VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
--- a/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c
@@ -0,0 +1,68 @@
+/** @file
+
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution.  The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NorFlashPlatformLib.h>
+#include <ArmPlatform.h>
+
+NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
+  {
+    ARM_VE_SMB_NOR0_BASE,
+    ARM_VE_SMB_NOR0_BASE,
+    SIZE_256KB * 255,
+    SIZE_256KB,
+    {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59} }
+  },
+  {
+    ARM_VE_SMB_NOR0_BASE,
+    ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,
+    SIZE_64KB * 4,
+    SIZE_64KB,
+    {0x02118005, 0x9DA7, 0x443A, { 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB } }
+  },
+};
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+  VOID
+  )
+{
+  // Everything seems ok so far, so now we need to disable the platform-specific
+  // flash write protection for Versatile Express
+  if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {
+    // Writing to NOR FLASH is disabled, so enable it
+    MmioWrite32 (ARM_VE_SYS_FLASH, 1);
+    DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" ));
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DESCRIPTION   **NorFlashDevices,
+  OUT UINT32                  *Count
+  )
+{
+  if ((NorFlashDevices == NULL) || (Count == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *NorFlashDevices = mNorFlashDevices;
+  *Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION);
+
+  return EFI_SUCCESS;
+}
--- a/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.inf
+++ b/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.inf
@@ -1,9 +1,6 @@
 #/** @file
 #
-#  Component description file for NorFlashPlatformNullLib module
-#
-#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
-#
+#  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -16,15 +13,20 @@

 [Defines]
  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = NorFlashPlatformNullLib
-  FILE_GUID                      = 29b733ad-d066-4df6-8a89-b9df1beb818a
+  BASE_NAME                      = NorFlashJunoLib
+  FILE_GUID                      = 3eb6cbc4-ce95-11e2-b1bd-00241d0c1ba8
  MODULE_TYPE                    = DXE_DRIVER
  VERSION_STRING                 = 1.0
  LIBRARY_CLASS                  = NorFlashPlatformLib

 [Sources.common]
-  NorFlashPlatformNullLib.c
+  NorFlashJuno.c

 [Packages]
  MdePkg/MdePkg.dec
  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -1,6 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
 #  Copyright (c) 2015, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
@@ -31,13 +31,6 @@
 [Includes.common]
  Include                        # Root include for the package

-[LibraryClasses]
-  ArmPlatformLib|Include/Library/ArmPlatformLib.h
-  LcdHwLib|Include/Library/LcdHwLib.h
-  LcdPlatformLib|Include/Library/LcdPlatformLib.h
-  NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
-  PL011UartLib|Include/Library/PL011UartLib.h
-
 [Guids.common]
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
  #
@@ -45,7 +38,14 @@
  #
  gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }

+  gArmBootMonFsFileInfoGuid   = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
+
 [PcdsFeatureFlag.common]
+  # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
+
+  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004

  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
@@ -54,10 +54,18 @@
  # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D

+  # Enable Legacy Linux support in the BDS
+  gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E
+
 [PcdsFixedAtBuild.common]
  gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038

+  # Stack for CPU Cores in Secure Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
+
  # Stack for CPU Cores in Non Secure Mode
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
@@ -66,10 +74,20 @@
  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015

+  # Boot Monitor FileSystem
+  gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
+
  #
  # ARM Primecells
  #

+  ## SP804 DualTimer
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
+
  ## SP805 Watchdog
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
@@ -79,7 +97,6 @@
  gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
  gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
-  gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E

  ## PL011 Serial Debug UART
  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
@@ -97,9 +114,31 @@
  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029

+  #
+  # BDS - Boot Manager
+  #
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
+
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
+
 [PcdsFixedAtBuild.common,PcdsDynamic.common]
  ## PL031 RealTimeClock
  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
  gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022

-  gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033
+[PcdsFixedAtBuild.ARM]
+  # Stack for CPU Cores in Secure Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
+
+[PcdsFixedAtBuild.AARCH64]
+  # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
+  # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
+  # and PcdCPUCoreSecSecondaryStackSize
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
+
--- a/ArmPlatformPkg/ArmPlatformPkg.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg.dsc
@@ -1,122 +0,0 @@
-#/** @file
-# ARM platform package.
-#
-# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
-# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
-#
-#    This program and the accompanying materials
-#    are licensed and made available under the terms and conditions of the BSD License
-#    which accompanies this distribution. The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = ArmPlatformPkg
-  PLATFORM_GUID                  = 9ce08891-ac9c-476d-ab04-0c04d3a97544
-  PLATFORM_VERSION               = 0.1
-  DSC_SPECIFICATION              = 0x0001001A
-  OUTPUT_DIRECTORY               = Build/ArmPlatform
-  SUPPORTED_ARCHITECTURES        = ARM|AARCH64
-  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
-  SKUID_IDENTIFIER               = DEFAULT
-
-[BuildOptions]
-  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
-  *_*_*_CC_FLAGS  = -DDISABLE_NEW_DEPRECATED_INTERFACES
-
-[PcdsFixedAtBuild]
-  gArmTokenSpaceGuid.PcdFdBaseAddress|0x0
-  gArmTokenSpaceGuid.PcdFdSize|0x1000
-
-[LibraryClasses.common]
-  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
-  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
-  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
-  ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
-  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
-  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
-  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
-  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
-  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
-  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
-  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  LcdHwLib|ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf
-  LcdPlatformLib|ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.inf
-  LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
-  NorFlashPlatformLib|ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.inf
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
-  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
-  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
-  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
-  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
-  TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
-  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
-  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
-  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
-  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
-  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
-
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-
-[LibraryClasses.common.PEIM]
-  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
-  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
-  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
-  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
-  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
-
-[LibraryClasses.common.SEC]
-  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
-  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
-  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
-  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
-
-[Components.common]
-  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
-  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
-  ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
-  ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
-
-  ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
-  ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
-  ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.inf
-  ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.inf
-  ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.inf
-  ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
-  ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
-  ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
-  ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
-
-  ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
-  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
-
-  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
-  ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
-
-  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
-  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
-
-  ArmPlatformPkg/PrePi/PeiMPCore.inf
-  ArmPlatformPkg/PrePi/PeiUniCore.inf
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/AArch64/ArmFvpDxeAArch64.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/AArch64/ArmFvpDxeAArch64.c
@@ -0,0 +1,113 @@
+/** @file
+
+  Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmVExpressInternal.h"
+#include <Library/ArmGicLib.h>
+
+//
+// Description of the AARCH64 model platforms :
+// Platform ids are defined in ArmVExpressInternal.h for
+// all "ArmVExpress-like" platforms (AARCH64 or ARM architecture,
+// model or hardware platforms).
+//
+CONST ARM_VEXPRESS_PLATFORM ArmVExpressPlatforms[] = {
+  { ARM_FVP_VEXPRESS_AEMv8x4,                  FixedPcdGetPtr (PcdFdtFvpVExpressAEMv8x4),        L"rtsm_ve-aemv8a.dtb"                  },
+  { ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2,        FixedPcdGetPtr (PcdFdtFvpBaseAEMv8x4GicV2),       L"fvp-base-gicv2-psci.dtb"             },
+  { ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2_LEGACY, FixedPcdGetPtr (PcdFdtFvpBaseAEMv8x4GicV2Legacy), L"fvp-base-gicv2legacy-psci.dtb"       },
+  { ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV3,        FixedPcdGetPtr (PcdFdtFvpBaseAEMv8x4GicV3),       L"fvp-base-gicv3-psci.dtb"             },
+  { ARM_FVP_FOUNDATION_GICV2,                  FixedPcdGetPtr (PcdFdtFvpFoundationGicV2),        L"fvp-foundation-gicv2-psci.dtb"       },
+  { ARM_FVP_FOUNDATION_GICV2_LEGACY,           FixedPcdGetPtr (PcdFdtFvpFoundationGicV2Legacy),  L"fvp-foundation-gicv2legacy-psci.dtb" },
+  { ARM_FVP_FOUNDATION_GICV3,                  FixedPcdGetPtr (PcdFdtFvpFoundationGicV3),        L"fvp-foundation-gicv3-psci.dtb"       },
+  { ARM_FVP_VEXPRESS_UNKNOWN }
+};
+
+/**
+  Get information about the VExpress platform the firmware is running on.
+
+  @param[out]  Platform   Address where the pointer to the platform information
+                          (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                          The returned pointer does not point to an allocated
+                          memory area.
+
+  @retval  EFI_SUCCESS    The platform information was returned.
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatform (
+  OUT CONST ARM_VEXPRESS_PLATFORM** Platform
+  )
+{
+  EFI_STATUS            Status;
+  UINT32                SysId;
+  UINT32                FvpSysId;
+  UINT32                VariantSysId;
+  ARM_GIC_ARCH_REVISION GicRevision;
+
+  ASSERT (Platform != NULL);
+
+  Status = EFI_NOT_FOUND;
+
+  SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
+  if (SysId != ARM_RTSM_SYS_ID) {
+    // Remove the GIC variant to identify if we are running on the FVP Base or
+    // Foundation models
+    FvpSysId     = SysId & (ARM_FVP_SYS_ID_HBI_MASK |
+                            ARM_FVP_SYS_ID_PLAT_MASK );
+    // Extract the variant from the SysId
+    VariantSysId = SysId & ARM_FVP_SYS_ID_VARIANT_MASK;
+
+    if (FvpSysId == ARM_FVP_BASE_BOARD_SYS_ID) {
+      if (VariantSysId == ARM_FVP_GIC_VE_MMAP) {
+        // FVP Base Model with legacy GIC memory map
+        Status = ArmVExpressGetPlatformFromId (ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2_LEGACY, Platform);
+      } else {
+        GicRevision = ArmGicGetSupportedArchRevision ();
+
+        if (GicRevision == ARM_GIC_ARCH_REVISION_2) {
+          // FVP Base Model with GICv2 support
+          Status = ArmVExpressGetPlatformFromId (ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2, Platform);
+        } else {
+          // FVP Base Model with GICv3 support
+          Status = ArmVExpressGetPlatformFromId (ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV3, Platform);
+        }
+      }
+    } else if (FvpSysId == ARM_FVP_FOUNDATION_BOARD_SYS_ID) {
+      if (VariantSysId == ARM_FVP_GIC_VE_MMAP) {
+        // FVP Foundation Model with legacy GIC memory map
+        Status = ArmVExpressGetPlatformFromId (ARM_FVP_FOUNDATION_GICV2_LEGACY, Platform);
+      } else {
+        GicRevision = ArmGicGetSupportedArchRevision ();
+
+        if (GicRevision == ARM_GIC_ARCH_REVISION_2) {
+          // FVP Foundation Model with GICv2
+          Status = ArmVExpressGetPlatformFromId (ARM_FVP_FOUNDATION_GICV2, Platform);
+        } else {
+          // FVP Foundation Model with GICv3
+          Status = ArmVExpressGetPlatformFromId (ARM_FVP_FOUNDATION_GICV3, Platform);
+        }
+      }
+    }
+  } else {
+    // FVP Versatile Express AEMv8
+    Status = ArmVExpressGetPlatformFromId (ARM_FVP_VEXPRESS_AEMv8x4, Platform);
+  }
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Unsupported AArch64 RTSM (SysId:0x%X).\n", SysId));
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  return Status;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/Arm/ArmFvpDxeArm.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/Arm/ArmFvpDxeArm.c
@@ -0,0 +1,84 @@
+/** @file
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmVExpressInternal.h"
+#include <Library/ArmPlatformLib.h>  // To get Core Count
+
+//
+// Description of the four ARM model platforms :
+// Platform ids are defined in ArmVExpressInternal.h for
+// all "ArmVExpress-like" platforms (AARCH64 or ARM architecture,
+// model or hardware platforms).
+//
+CONST ARM_VEXPRESS_PLATFORM ArmVExpressPlatforms[] = {
+  { ARM_FVP_VEXPRESS_A9x4,  FixedPcdGetPtr (PcdFdtVExpressFvpA9x4),  L"rtsm_ve-cortex_a9x4.dtb"  },
+  { ARM_FVP_VEXPRESS_A15x1, FixedPcdGetPtr (PcdFdtVExpressFvpA15x1), L"rtsm_ve-cortex_a15x1.dtb" },
+  { ARM_FVP_VEXPRESS_A15x2, FixedPcdGetPtr (PcdFdtVExpressFvpA15x2), L"rtsm_ve-cortex_a15x2.dtb" },
+  { ARM_FVP_VEXPRESS_A15x4, FixedPcdGetPtr (PcdFdtVExpressFvpA15x4), L"rtsm_ve-cortex_a15x4.dtb" },
+  { ARM_FVP_VEXPRESS_UNKNOWN, }
+};
+
+/**
+  Get information about the VExpress platform the firmware is running on.
+
+  @param[out]  Platform   Address where the pointer to the platform information
+                          (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                          The returned pointer does not point to an allocated
+                          memory area.
+
+  @retval  EFI_SUCCESS    The platform information was returned.
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatform (
+  OUT CONST ARM_VEXPRESS_PLATFORM** Platform
+  )
+{
+  UINT32                SysId;
+  UINTN                 CpuType;
+  EFI_STATUS            Status;
+  UINTN                 CoreCount;
+
+  ASSERT (Platform != NULL);
+
+  CpuType   = 0;
+  Status    = EFI_NOT_FOUND;
+  *Platform = NULL;
+
+  SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
+  if (SysId == ARM_RTSM_SYS_ID) {
+    // Get the Cortex-A version
+    CpuType = (ArmReadMidr () >> 4) & ARM_CPU_TYPE_MASK;
+    if (CpuType == ARM_CPU_TYPE_A9) {
+      Status = ArmVExpressGetPlatformFromId (ARM_FVP_VEXPRESS_A9x4, Platform);
+    } else if (CpuType == ARM_CPU_TYPE_A15) {
+      CoreCount = ArmGetCpuCountPerCluster ();
+      if (CoreCount == 1) {
+        Status = ArmVExpressGetPlatformFromId (ARM_FVP_VEXPRESS_A15x1, Platform);
+      } else if (CoreCount == 2) {
+        Status = ArmVExpressGetPlatformFromId (ARM_FVP_VEXPRESS_A15x2, Platform);
+      } else if (CoreCount == 4) {
+        Status = ArmVExpressGetPlatformFromId (ARM_FVP_VEXPRESS_A15x4, Platform);
+      }
+    }
+  }
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Unsupported platform (SysId:0x%X, CpuType:0x%X)\n", SysId, CpuType));
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  return Status;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.c
@@ -0,0 +1,217 @@
+/** @file
+
+  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmVExpressInternal.h"
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/VirtioMmioDeviceLib.h>
+#include <Library/ArmShellCmdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DevicePathLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+
+#define ARM_FVP_BASE_VIRTIO_BLOCK_BASE    0x1c130000
+
+#pragma pack(1)
+typedef struct {
+  VENDOR_DEVICE_PATH                  Vendor;
+  EFI_DEVICE_PATH_PROTOCOL            End;
+} VIRTIO_BLK_DEVICE_PATH;
+#pragma pack()
+
+VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath =
+{
+  {
+    {
+      HARDWARE_DEVICE_PATH,
+      HW_VENDOR_DP,
+      {
+        (UINT8)( sizeof(VENDOR_DEVICE_PATH) ),
+        (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)
+      }
+    },
+    EFI_CALLER_ID_GUID,
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    {
+      sizeof (EFI_DEVICE_PATH_PROTOCOL),
+      0
+    }
+  }
+};
+
+STATIC
+EFI_STATUS
+InternalFindFdtByGuid (
+  IN OUT   EFI_DEVICE_PATH  **FdtDevicePath,
+  IN CONST EFI_GUID         *FdtGuid
+  )
+{
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH    FileDevicePath;
+  EFI_HANDLE                           *HandleBuffer;
+  UINTN                                HandleCount;
+  UINTN                                Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL        *FvProtocol;
+  EFI_GUID                             NameGuid;
+  UINTN                                Size;
+  VOID                                 *Key;
+  EFI_FV_FILETYPE                      FileType;
+  EFI_FV_FILE_ATTRIBUTES               Attributes;
+  EFI_DEVICE_PATH                      *FvDevicePath;
+  EFI_STATUS                           Status;
+
+  if (FdtGuid == NULL) {
+    return EFI_NOT_FOUND;
+  }
+
+  EfiInitializeFwVolDevicepathNode (&FileDevicePath, FdtGuid);
+
+  HandleBuffer = NULL;
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolume2ProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  for (Index = 0; Index < HandleCount; Index++) {
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    &gEfiFirmwareVolume2ProtocolGuid,
+                    (VOID **) &FvProtocol
+                    );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    // Allocate Key
+    Key = AllocatePool (FvProtocol->KeySize);
+    ASSERT (Key != NULL);
+    ZeroMem (Key, FvProtocol->KeySize);
+
+    do {
+      FileType = EFI_FV_FILETYPE_RAW;
+      Status = FvProtocol->GetNextFile (FvProtocol, Key, &FileType, &NameGuid, &Attributes, &Size);
+      if (Status == EFI_NOT_FOUND) {
+        break;
+      }
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+
+      //
+      // Check whether this file is the one we are looking for. If so,
+      // create a device path for it and return it to the caller.
+      //
+      if (CompareGuid (&NameGuid, FdtGuid)) {
+          Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&FvDevicePath);
+          if (!EFI_ERROR (Status)) {
+            *FdtDevicePath = AppendDevicePathNode (FvDevicePath,
+                               (EFI_DEVICE_PATH_PROTOCOL *)&FileDevicePath);
+          }
+          goto Done;
+      }
+    } while (TRUE);
+    FreePool (Key);
+  }
+
+  if (Index == HandleCount) {
+    Status = EFI_NOT_FOUND;
+  }
+  return Status;
+
+Done:
+  FreePool (Key);
+  return Status;
+}
+
+/**
+ * Generic UEFI Entrypoint for 'ArmFvpDxe' driver
+ * See UEFI specification for the details of the parameters
+ */
+EFI_STATUS
+EFIAPI
+ArmFvpInitialise (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  CONST ARM_VEXPRESS_PLATFORM* Platform;
+  EFI_STATUS                   Status;
+  CHAR16                       *TextDevicePath;
+  UINTN                        TextDevicePathSize;
+  VOID                         *Buffer;
+  EFI_DEVICE_PATH              *FdtDevicePath;
+
+  Status = gBS->InstallProtocolInterface (&ImageHandle,
+                 &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,
+                 &mVirtioBlockDevicePath);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = ArmVExpressGetPlatform (&Platform);
+  if (!EFI_ERROR (Status)) {
+    FdtDevicePath = NULL;
+    Status = InternalFindFdtByGuid (&FdtDevicePath, Platform->FdtGuid);
+    if (!EFI_ERROR (Status)) {
+      TextDevicePath = ConvertDevicePathToText (FdtDevicePath, FALSE, FALSE);
+      if (TextDevicePath != NULL) {
+        TextDevicePathSize = StrSize (TextDevicePath);
+      }
+      FreePool (FdtDevicePath);
+    } else {
+      TextDevicePathSize  = StrSize ((CHAR16*)PcdGetPtr (PcdFvpFdtDevicePathsBase)) - sizeof (CHAR16);
+      TextDevicePathSize += StrSize (Platform->FdtName);
+
+      TextDevicePath = AllocatePool (TextDevicePathSize);
+      if (TextDevicePath != NULL) {
+        StrCpy (TextDevicePath, ((CHAR16*)PcdGetPtr (PcdFvpFdtDevicePathsBase)));
+        StrCat (TextDevicePath, Platform->FdtName);
+      }
+    }
+    if (TextDevicePath != NULL) {
+      Buffer = PcdSetPtr (PcdFdtDevicePaths, &TextDevicePathSize, TextDevicePath);
+      if (Buffer == NULL) {
+        DEBUG ((
+          EFI_D_ERROR,
+          "ArmFvpDxe: Setting of FDT device path in PcdFdtDevicePaths failed - %r\n", EFI_BUFFER_TOO_SMALL
+          ));
+      }
+      FreePool (TextDevicePath);
+    }
+  }
+
+  // Declare the Virtio BlockIo device
+  Status = VirtioMmioInstallDevice (ARM_FVP_BASE_VIRTIO_BLOCK_BASE, ImageHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install Virtio block device\n"));
+  }
+
+  // Install dynamic Shell command to run baremetal binaries.
+  Status = ShellDynCmdRunAxfInstall (ImageHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n"));
+  }
+
+  return Status;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
@@ -0,0 +1,80 @@
+#/** @file
+#
+#  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010006
+  BASE_NAME                      = ArmFvpDxe
+  FILE_GUID                      = 405b2307-6839-4d52-aeb9-bece64252800
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = ArmFvpInitialise
+
+[Sources.common]
+  ArmFvpDxe.c
+  ArmVExpressCommon.c
+
+[Sources.ARM]
+  Arm/ArmFvpDxeArm.c
+
+[Sources.AARCH64]
+  AArch64/ArmFvpDxeAArch64.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  ArmShellCmdRunAxfLib
+  ArmLib
+  ArmPlatformLib
+  BaseMemoryLib
+  DxeServicesTableLib
+  MemoryAllocationLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  VirtioMmioDeviceLib
+  DevicePathLib
+
+[LibraryClasses.AARCH64]
+  ArmGicLib
+
+[Protocols]
+  gEfiFirmwareVolume2ProtocolGuid
+  gEfiDevicePathProtocolGuid
+
+[FixedPcd]
+  gArmVExpressTokenSpaceGuid.PcdFvpFdtDevicePathsBase
+
+[FixedPcd.ARM]
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA9x4
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x1
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x2
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x4
+
+[FixedPcd.AARCH64]
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpVExpressAEMv8x4
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2Legacy
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV3
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2Legacy
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV3
+
+[Pcd]
+  gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.c
@@ -0,0 +1,79 @@
+/** @file
+
+  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmVExpressInternal.h"
+#include <Library/ArmShellCmdLib.h>
+
+CONST EFI_GUID ArmHwA9x4Guid = { 0x2fd21cf6, 0xe6e8, 0x4ff2, { 0xa9, 0xca, 0x3b, 0x9f, 0x00, 0xe9, 0x28, 0x89 } };
+CONST EFI_GUID ArmHwA15x2A7x3Guid = { 0xd5e606eb, 0x83df, 0x4e90, { 0x81, 0xe8, 0xc3, 0xdb, 0x2f, 0x77, 0x17, 0x9a } };
+CONST EFI_GUID ArmHwA15Guid = { 0x6b8947c2, 0x4287, 0x4d91, { 0x8f, 0xe0, 0xa3, 0x81, 0xea, 0x5b, 0x56, 0x8f } };
+CONST EFI_GUID ArmHwA5Guid = { 0xa2cc7663, 0x4d7c, 0x448a, { 0xaa, 0xb5, 0x4c, 0x03, 0x4b, 0x6f, 0xda, 0xb7 } };
+CONST EFI_GUID NullGuid = { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } };
+
+//
+// Description of the four hardware platforms :
+// just the platform id for the time being.
+// Platform ids are defined in ArmVExpressInternal.h for
+// all "ArmVExpress-like" platforms (AARCH64 or ARM architecture,
+// model or hardware platforms).
+//
+//Note: File extensions are stripped with the VExpress NOR Flash FileSystem
+CONST ARM_VEXPRESS_PLATFORM ArmVExpressPlatforms[] = {
+  { ARM_HW_A9x4, &ArmHwA9x4Guid, L"ca9" },
+  { ARM_HW_A15x2_A7x3, &ArmHwA15x2A7x3Guid, L"ca15a7" },
+  { ARM_HW_A15, &ArmHwA15Guid, L"ca15a7" },
+  { ARM_HW_A5, &ArmHwA5Guid, L"ca5s" },
+  { ARM_FVP_VEXPRESS_UNKNOWN, &NullGuid, NULL }
+};
+
+/**
+  Get information about the VExpress platform the firmware is running on.
+
+  @param[out]  Platform   Address where the pointer to the platform information
+                          (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                          The returned pointer does not point to an allocated
+                          memory area. Not used here.
+
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatform (
+  OUT CONST ARM_VEXPRESS_PLATFORM** Platform
+  )
+{
+  return EFI_NOT_FOUND;
+}
+
+/**
+ * Generic UEFI Entrypoint for 'ArmHwDxe' driver
+ * See UEFI specification for the details of the parameters
+ */
+EFI_STATUS
+EFIAPI
+ArmHwInitialise (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  // Install dynamic Shell command to run baremetal binaries.
+  Status = ShellDynCmdRunAxfInstall (ImageHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "ArmHwDxe: Failed to install ShellDynCmdRunAxf\n"));
+  }
+
+  return Status;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf
@@ -0,0 +1,40 @@
+#/** @file
+#
+#  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010006
+  BASE_NAME                      = ArmHwDxe
+  FILE_GUID                      = fe61bb5f-1b67-4c24-b346-73db42e873e5
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = ArmHwInitialise
+
+[Sources.common]
+  ArmHwDxe.c
+  ArmVExpressCommon.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmShellCmdRunAxfLib
+  DxeServicesTableLib
+  MemoryAllocationLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiDevicePathProtocolGuid
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmVExpressCommon.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmVExpressCommon.c
@@ -0,0 +1,48 @@
+/** @file
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ArmVExpressInternal.h"
+
+/**
+  Get information about the VExpress platform the firmware is running on given its Id.
+
+  @param[in]   PlatformId  Id of the VExpress platform.
+  @param[out]  Platform    Address where the pointer to the platform information
+                           (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                           The returned pointer does not point to an allocated
+                           memory area.
+
+  @retval  EFI_SUCCESS    The platform information was returned.
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatformFromId (
+  IN  CONST ARM_VEXPRESS_PLATFORM_ID PlatformId,
+  OUT CONST ARM_VEXPRESS_PLATFORM**  Platform
+  )
+{
+  UINTN Index;
+
+  ASSERT (Platform != NULL);
+
+  for (Index = 0; ArmVExpressPlatforms[Index].Id != ARM_FVP_VEXPRESS_UNKNOWN; Index++) {
+    if (ArmVExpressPlatforms[Index].Id == PlatformId) {
+      *Platform = &ArmVExpressPlatforms[Index];
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmVExpressInternal.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmVExpressInternal.h
@@ -0,0 +1,99 @@
+/** @file
+
+  Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_VEXPRESS_INTERNAL_H__
+#define __ARM_VEXPRESS_INTERNAL_H__
+
+#include <Uefi.h>
+
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <VExpressMotherBoard.h>
+
+// This 'enum' is needed as variations based on existing platform exist
+typedef enum {
+  ARM_FVP_VEXPRESS_UNKNOWN = 0,
+  ARM_FVP_VEXPRESS_A9x4,
+  ARM_FVP_VEXPRESS_A15x1,
+  ARM_FVP_VEXPRESS_A15x2,
+  ARM_FVP_VEXPRESS_A15x4,
+  ARM_FVP_VEXPRESS_A15x1_A7x1,
+  ARM_FVP_VEXPRESS_A15x4_A7x4,
+  ARM_FVP_VEXPRESS_AEMv8x4,
+  ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2,
+  ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2_LEGACY,
+  ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV3,
+  ARM_FVP_FOUNDATION_GICV2,
+  ARM_FVP_FOUNDATION_GICV2_LEGACY,
+  ARM_FVP_FOUNDATION_GICV3,
+  ARM_HW_A9x4,
+  ARM_HW_A15x2_A7x3,
+  ARM_HW_A15,
+  ARM_HW_A5
+} ARM_VEXPRESS_PLATFORM_ID;
+
+typedef struct {
+  ARM_VEXPRESS_PLATFORM_ID  Id;
+
+  // Flattened Device Tree (FDT) File
+  CONST EFI_GUID            *FdtGuid; /// Name of the FDT when present into the FV
+  CONST CHAR16              *FdtName; /// Name of the FDT when present into a File System
+} ARM_VEXPRESS_PLATFORM;
+
+// Array that contains the list of the VExpress based platform supported by this DXE driver
+extern CONST ARM_VEXPRESS_PLATFORM ArmVExpressPlatforms[];
+
+/**
+  Get information about the VExpress platform the firmware is running on given its Id.
+
+  @param[in]   PlatformId  Id of the VExpress platform.
+  @param[out]  Platform    Address where the pointer to the platform information
+                           (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                           The returned pointer does not point to an allocated
+                           memory area.
+
+  @retval  EFI_SUCCESS    The platform information was returned.
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatformFromId (
+  IN  CONST ARM_VEXPRESS_PLATFORM_ID PlatformId,
+  OUT CONST ARM_VEXPRESS_PLATFORM**  Platform
+  );
+
+/**
+
+  Get information about the VExpress platform the firmware is running on.
+
+  @param[out]  Platform   Address where the pointer to the platform information
+                          (type ARM_VEXPRESS_PLATFORM*) should be stored.
+                          The returned pointer does not point to an allocated
+                          memory area.
+
+  @retval  EFI_SUCCESS    The platform information was returned.
+  @retval  EFI_NOT_FOUND  The platform was not recognised.
+
+**/
+EFI_STATUS
+ArmVExpressGetPlatform (
+  OUT CONST ARM_VEXPRESS_PLATFORM** Platform
+  );
+
+#endif // __ARM_VEXPRESS_INTERNAL_H__
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBoot.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBoot.c
@@ -0,0 +1,519 @@
+/** @file
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*
+  Implementation of the Android Fastboot Platform protocol, to be used by the
+  Fastboot UEFI application, for ARM Versatile Express platforms.
+*/
+
+#include <Protocol/AndroidFastbootPlatform.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/DiskIo.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define FLASH_DEVICE_PATH_SIZE(DevPath) ( GetDevicePathSize (DevPath) - \
+                                            sizeof (EFI_DEVICE_PATH_PROTOCOL))
+
+#define PARTITION_NAME_MAX_LENGTH 72/2
+
+#define IS_ALPHA(Char) (((Char) <= L'z' && (Char) >= L'a') || \
+                        ((Char) <= L'Z' && (Char) >= L'Z'))
+
+typedef struct _FASTBOOT_PARTITION_LIST {
+  LIST_ENTRY  Link;
+  CHAR16      PartitionName[PARTITION_NAME_MAX_LENGTH];
+  EFI_HANDLE  PartitionHandle;
+} FASTBOOT_PARTITION_LIST;
+
+STATIC LIST_ENTRY mPartitionListHead;
+
+/*
+  Helper to free the partition list
+*/
+STATIC
+VOID
+FreePartitionList (
+  VOID
+  )
+{
+  FASTBOOT_PARTITION_LIST *Entry;
+  FASTBOOT_PARTITION_LIST *NextEntry;
+
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
+
+    RemoveEntryList (&Entry->Link);
+    FreePool (Entry);
+
+    Entry = NextEntry;
+  }
+}
+/*
+  Read the PartitionName fields from the GPT partition entries, putting them
+  into an allocated array that should later be freed.
+*/
+STATIC
+EFI_STATUS
+ReadPartitionEntries (
+  IN  EFI_BLOCK_IO_PROTOCOL *BlockIo,
+  OUT EFI_PARTITION_ENTRY  **PartitionEntries
+  )
+{
+  UINTN                       EntrySize;
+  UINTN                       NumEntries;
+  UINTN                       BufferSize;
+  UINT32                      MediaId;
+  EFI_PARTITION_TABLE_HEADER *GptHeader;
+  EFI_STATUS                  Status;
+
+  MediaId = BlockIo->Media->MediaId;
+
+  //
+  // Read size of Partition entry and number of entries from GPT header
+  //
+
+  GptHeader = AllocatePool (BlockIo->Media->BlockSize);
+  if (GptHeader == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 1, BlockIo->Media->BlockSize, (VOID *) GptHeader);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Check there is a GPT on the media
+  if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||
+      GptHeader->MyLBA != 1) {
+    DEBUG ((EFI_D_ERROR,
+      "Fastboot platform: No GPT on flash. "
+      "Fastboot on Versatile Express does not support MBR.\n"
+      ));
+    return EFI_DEVICE_ERROR;
+  }
+
+  EntrySize = GptHeader->SizeOfPartitionEntry;
+  NumEntries = GptHeader->NumberOfPartitionEntries;
+
+  FreePool (GptHeader);
+
+  ASSERT (EntrySize != 0);
+  ASSERT (NumEntries != 0);
+
+  BufferSize = ALIGN_VALUE (EntrySize * NumEntries, BlockIo->Media->BlockSize);
+  *PartitionEntries = AllocatePool (BufferSize);
+  if (PartitionEntries == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 2, BufferSize, (VOID *) *PartitionEntries);
+  if (EFI_ERROR (Status)) {
+    FreePool (PartitionEntries);
+    return Status;
+  }
+
+  return Status;
+}
+
+
+/*
+  Do any initialisation that needs to be done in order to be able to respond to
+  commands.
+
+  @retval EFI_SUCCESS   Initialised successfully.
+  @retval !EFI_SUCCESS  Error in initialisation.
+*/
+STATIC
+EFI_STATUS
+ArmFastbootPlatformInit (
+  VOID
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePathDup;
+  EFI_DEVICE_PATH_PROTOCOL           *DevicePath;
+  EFI_DEVICE_PATH_PROTOCOL           *NextNode;
+  HARDDRIVE_DEVICE_PATH              *PartitionNode;
+  UINTN                               NumHandles;
+  EFI_HANDLE                         *AllHandles;
+  UINTN                               LoopIndex;
+  EFI_HANDLE                          FlashHandle;
+  EFI_BLOCK_IO_PROTOCOL              *FlashBlockIo;
+  EFI_PARTITION_ENTRY                *PartitionEntries;
+  FASTBOOT_PARTITION_LIST            *Entry;
+
+  InitializeListHead (&mPartitionListHead);
+
+  //
+  // Get EFI_HANDLES for all the partitions on the block devices pointed to by
+  // PcdFastbootFlashDevicePath, also saving their GPT partition labels.
+  // We will use these labels as the key in ArmFastbootPlatformFlashPartition.
+  // There's no way to find all of a device's children, so we get every handle
+  // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones
+  // that don't represent partitions on the flash device.
+  //
+
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+
+  //
+  // Open the Disk IO protocol on the flash device - this will be used to read
+  // partition names out of the GPT entries
+  //
+  // Create another device path pointer because LocateDevicePath will modify it.
+  FlashDevicePathDup = FlashDevicePath;
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &FlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+
+  Status = gBS->OpenProtocol (
+                  FlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &FlashBlockIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Read the GPT partition entry array into memory so we can get the partition names
+  Status = ReadPartitionEntries (FlashBlockIo, &PartitionEntries);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+
+  // Get every Block IO protocol instance installed in the system
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiBlockIoProtocolGuid,
+                  NULL,
+                  &NumHandles,
+                  &AllHandles
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  // Filter out handles that aren't children of the flash device
+  for (LoopIndex = 0; LoopIndex < NumHandles; LoopIndex++) {
+    // Get the device path for the handle
+    Status = gBS->OpenProtocol (
+                    AllHandles[LoopIndex],
+                    &gEfiDevicePathProtocolGuid,
+                    (VOID **) &DevicePath,
+                    gImageHandle,
+                    NULL,
+                    EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                    );
+    ASSERT_EFI_ERROR (Status);
+
+    // Check if it is a sub-device of the flash device
+    if (!CompareMem (DevicePath, FlashDevicePath, FLASH_DEVICE_PATH_SIZE (FlashDevicePath))) {
+      // Device path starts with path of flash device. Check it isn't the flash
+      // device itself.
+      NextNode = NextDevicePathNode (DevicePath);
+      if (IsDevicePathEndType (NextNode)) {
+        continue;
+      }
+
+      // Assert that this device path node represents a partition.
+      ASSERT (NextNode->Type == MEDIA_DEVICE_PATH &&
+              NextNode->SubType == MEDIA_HARDDRIVE_DP);
+
+      PartitionNode = (HARDDRIVE_DEVICE_PATH *) NextNode;
+
+      // Assert that the partition type is GPT. ReadPartitionEntries checks for
+      // presence of a GPT, so we should never find MBR partitions.
+      // ("MBRType" is a misnomer - this field is actually called "Partition
+      //  Format")
+      ASSERT (PartitionNode->MBRType == MBR_TYPE_EFI_PARTITION_TABLE_HEADER);
+
+      // The firmware may install a handle for "partition 0", representing the
+      // whole device. Ignore it.
+      if (PartitionNode->PartitionNumber == 0) {
+        continue;
+      }
+
+      //
+      // Add the partition handle to the list
+      //
+
+      // Create entry
+      Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
+      if (Entry == NULL) {
+        Status = EFI_OUT_OF_RESOURCES;
+        FreePartitionList ();
+        goto Exit;
+      }
+
+      // Copy handle and partition name
+      Entry->PartitionHandle = AllHandles[LoopIndex];
+      CopyMem (
+        Entry->PartitionName,
+        PartitionEntries[PartitionNode->PartitionNumber - 1].PartitionName, // Partition numbers start from 1.
+        PARTITION_NAME_MAX_LENGTH
+        );
+      InsertTailList (&mPartitionListHead, &Entry->Link);
+
+      // Print a debug message if the partition label is empty or looks like
+      // garbage.
+      if (!IS_ALPHA (Entry->PartitionName[0])) {
+        DEBUG ((EFI_D_ERROR,
+          "Warning: Partition %d doesn't seem to have a GPT partition label. "
+          "You won't be able to flash it with Fastboot.\n",
+          PartitionNode->PartitionNumber
+          ));
+      }
+    }
+  }
+
+Exit:
+  FreePool (PartitionEntries);
+  FreePool (FlashDevicePath);
+  FreePool (AllHandles);
+  return Status;
+
+}
+
+/*
+  To be called when Fastboot is finished and we aren't rebooting or booting an
+  image. Undo initialisation, free resrouces.
+*/
+STATIC
+VOID
+ArmFastbootPlatformUnInit (
+  VOID
+  )
+{
+  FreePartitionList ();
+}
+
+/*
+  Flash the partition named (according to a platform-specific scheme)
+  PartitionName, with the image pointed to by Buffer, whose size is BufferSize.
+
+  @param[in] PartitionName  Null-terminated name of partition to write.
+  @param[in] BufferSize     Size of Buffer in byets.
+  @param[in] Buffer         Data to write to partition.
+
+  @retval EFI_NOT_FOUND     No such partition.
+  @retval EFI_DEVICE_ERROR  Flashing failed.
+*/
+STATIC
+EFI_STATUS
+ArmFastbootPlatformFlashPartition (
+  IN CHAR8  *PartitionName,
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  EFI_BLOCK_IO_PROTOCOL   *BlockIo;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+  UINT32                   MediaId;
+  UINTN                    PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+
+  AsciiStrToUnicodeStrS (PartitionName, PartitionNameUnicode,
+    ARRAY_SIZE (PartitionNameUnicode));
+
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+
+   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = gBS->OpenProtocol (
+                  Entry->PartitionHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));
+    return EFI_NOT_FOUND;
+  }
+
+  // Check image will fit on device
+  PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
+  if (PartitionSize < Size) {
+    DEBUG ((EFI_D_ERROR, "Partition not big enough.\n"));
+    DEBUG ((EFI_D_ERROR, "Partition Size:\t%d\nImage Size:\t%d\n", PartitionSize, Size));
+
+    return EFI_VOLUME_FULL;
+  }
+
+  MediaId = BlockIo->Media->MediaId;
+
+  Status = gBS->OpenProtocol (
+                  Entry->PartitionHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  BlockIo->FlushBlocks(BlockIo);
+
+  return Status;
+}
+
+/*
+  Erase the partition named PartitionName.
+
+  @param[in] PartitionName  Null-terminated name of partition to erase.
+
+  @retval EFI_NOT_FOUND     No such partition.
+  @retval EFI_DEVICE_ERROR  Erasing failed.
+*/
+STATIC
+EFI_STATUS
+ArmFastbootPlatformErasePartition (
+  IN CHAR8 *Partition
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/*
+  If the variable referred to by Name exists, copy it (as a null-terminated
+  string) into Value. If it doesn't exist, put the Empty string in Value.
+
+  Variable names and values may not be larger than 60 bytes, excluding the
+  terminal null character. This is a limitation of the Fastboot protocol.
+
+  The Fastboot application will handle platform-nonspecific variables
+  (Currently "version" is the only one of these.)
+
+  @param[in]  Name   Null-terminated name of Fastboot variable to retrieve.
+  @param[out] Value  Caller-allocated buffer for null-terminated value of
+                     variable.
+
+  @retval EFI_SUCCESS       The variable was retrieved, or it doesn't exist.
+  @retval EFI_DEVICE_ERROR  There was an error looking up the variable. This
+                            does _not_ include the variable not existing.
+*/
+STATIC
+EFI_STATUS
+ArmFastbootPlatformGetVar (
+  IN  CHAR8   *Name,
+  OUT CHAR8   *Value
+  )
+{
+  if (AsciiStrCmp (Name, "product")) {
+    AsciiStrCpyS (Value, 61, FixedPcdGetPtr (PcdFirmwareVendor));
+  } else {
+    *Value = '\0';
+  }
+  return EFI_SUCCESS;
+}
+
+/*
+  React to an OEM-specific command.
+
+  Future versions of this function might want to allow the platform to do some
+  extra communication with the host. A way to do this would be to add a function
+  to the FASTBOOT_TRANSPORT_PROTOCOL that allows the implementation of
+  DoOemCommand to replace the ReceiveEvent with its own, and to restore the old
+  one when it's finished.
+
+  However at the moment although the specification allows it, the AOSP fastboot
+  host application doesn't handle receiving any data from the client, and it
+  doesn't support a data phase for OEM commands.
+
+  @param[in] Command    Null-terminated command string.
+
+  @retval EFI_SUCCESS       The command executed successfully.
+  @retval EFI_NOT_FOUND     The command wasn't recognised.
+  @retval EFI_DEVICE_ERROR  There was an error executing the command.
+*/
+STATIC
+EFI_STATUS
+ArmFastbootPlatformOemCommand (
+  IN  CHAR8   *Command
+  )
+{
+  CHAR16 CommandUnicode[65];
+
+  AsciiStrToUnicodeStrS (Command, CommandUnicode, ARRAY_SIZE (CommandUnicode));
+
+  if (AsciiStrCmp (Command, "Demonstrate") == 0) {
+    DEBUG ((EFI_D_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));
+    return EFI_SUCCESS;
+  } else {
+    DEBUG ((EFI_D_ERROR,
+      "VExpress: Unrecognised Fastboot OEM command: %s\n",
+      CommandUnicode
+      ));
+    return EFI_NOT_FOUND;
+  }
+}
+
+STATIC FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {
+  ArmFastbootPlatformInit,
+  ArmFastbootPlatformUnInit,
+  ArmFastbootPlatformFlashPartition,
+  ArmFastbootPlatformErasePartition,
+  ArmFastbootPlatformGetVar,
+  ArmFastbootPlatformOemCommand
+};
+
+EFI_STATUS
+EFIAPI
+ArmAndroidFastbootPlatformEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  return gBS->InstallProtocolInterface (
+                &ImageHandle,
+                &gAndroidFastbootPlatformProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &mPlatformProtocol
+                );
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf
@@ -1,7 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2017, Linaro. All rights reserved.
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -14,50 +13,39 @@
 #**/

 [Defines]
-  INF_VERSION                    = 0x00010019
-  BASE_NAME                      = AndroidBootApp
-  FILE_GUID                      = 3a738b36-b9c5-4763-abbd-6cbd4b25f9ff
-  MODULE_TYPE                    = UEFI_APPLICATION
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmVExpressFastBootDxe
+  FILE_GUID                      = 4004e454-89a0-11e3-89aa-97ef9d942abc
+  MODULE_TYPE                    = UEFI_DRIVER
  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = AndroidBootAppEntryPoint
+  ENTRY_POINT                    = ArmAndroidFastbootPlatformEntryPoint

 [Sources.common]
-  AndroidBootApp.c
+  ArmVExpressFastBoot.c

 [LibraryClasses]
-  AndroidBootImgLib
  BaseLib
  BaseMemoryLib
  DebugLib
  DevicePathLib
-  DxeServicesTableLib
-  FdtLib
  MemoryAllocationLib
  PcdLib
-  PrintLib
-  UefiApplicationEntryPoint
  UefiBootServicesTableLib
-  UefiLib
-  UefiRuntimeServicesTableLib
+  UefiDriverEntryPoint

 [Protocols]
  gAndroidFastbootPlatformProtocolGuid
  gEfiBlockIoProtocolGuid
-  gEfiDevicePathFromTextProtocolGuid
-  gEfiSimpleTextOutProtocolGuid
-  gEfiSimpleTextInProtocolGuid
+  gEfiDiskIoProtocolGuid

 [Packages]
  EmbeddedPkg/EmbeddedPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
  MdePkg/MdePkg.dec
-
-[Packages.ARM, Packages.AARCH64]
-  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
  ArmPlatformPkg/ArmPlatformPkg.dec
-
-[Guids]
-  gFdtTableGuid
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+  ArmPkg/ArmPkg.dec

 [Pcd]
-  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath
+  gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
@@ -0,0 +1,81 @@
+#/** @file
+# Arm Versatile Express package.
+#
+#  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = ArmVExpressPkg
+  PACKAGE_GUID                   = 9c0aaed4-74c5-4043-b417-a3223814ce76
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmVExpressTokenSpaceGuid    =  { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
+  #
+  # MaxMode must be one number higher than the actual max mode,
+  # i.e. for actual maximum mode 2, set the value to 3.
+  #
+  # For a list of mode numbers look in LcdArmVExpress.c
+  #
+  gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000001
+  gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000002
+  gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000003
+
+  #
+  # Device path of block device on which Fastboot will flash partitions
+  #
+  gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|""|VOID*|0x00000004
+
+  # FVP platforms : install FDT from SemiHosting
+  gArmVExpressTokenSpaceGuid.PcdFvpFdtDevicePathsBase|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/"|VOID*|0x00000005
+  # HW platforms : install FDT from NOR Flash
+  gArmVExpressTokenSpaceGuid.PcdHwFdtDevicePathsBase|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/"|VOID*|0x00000006
+
+  #
+  # ARM Versatile Express FDT Guids
+  #
+  # FVP platforms
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA9x4|{ 0x12, 0x7b, 0xdf, 0xa1, 0x60, 0x11, 0xcf, 0x16, 0xb8, 0xc6, 0x98, 0xde, 0xdf, 0xe2, 0xce, 0xae }|VOID*|0x00000007
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x1|{ 0xe5, 0x1b, 0xc0, 0x96, 0xeb, 0xd7, 0x1a, 0x42, 0xc8, 0xe8, 0x6a, 0xfd, 0x5a, 0x86, 0x1d, 0x84 }|VOID*|0x00000008
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x2|{ 0x84, 0x43, 0x70, 0x4d, 0x19, 0xf1, 0x29, 0xe3, 0xef, 0xcd, 0xa5, 0x9b, 0x3d, 0x0a, 0x5a, 0x5f }|VOID*|0x00000009
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x4|{ 0x72, 0x3b, 0x28, 0x27, 0x90, 0x2f, 0xca, 0x4d, 0x9a, 0xb5, 0x98, 0x48, 0xfb, 0xc2, 0xd4, 0xed }|VOID*|0x0000000A
+  # HW platforms
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA9x4|{ 0xf6, 0x1c, 0xd2, 0x2f, 0xe8, 0xe6, 0xf2, 0x4f, 0xa9, 0xca, 0x3b, 0x9f, 0x00, 0xe9, 0x28, 0x89 }|VOID*|0x0000000B
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A7x3|{ 0xeb, 0x06, 0xe6, 0xd5, 0xdf, 0x83, 0x90, 0x4e, 0x81, 0xe8, 0xc3, 0xdb, 0x2f, 0x77, 0x17, 0x9a }|VOID*|0x0000000C
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15|{ 0xc2, 0x47, 0x89, 0x6b, 0x87, 0x42, 0x91, 0x4d, 0x8f, 0xe0, 0xa3, 0x81, 0xea, 0x5b, 0x56, 0x8f }|VOID*|0x0000000D
+  gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA5|{ 0x63, 0x76, 0xcc, 0xa2, 0x7c, 0x4d, 0x8a, 0x44, 0xaa, 0xb5, 0x4c, 0x03, 0x4b, 0x6f, 0xda, 0xb7 }|VOID*|0x0000000E
+
+  # AArch64 FVP platforms
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpVExpressAEMv8x4|{ 0xa8, 0x95, 0x5f, 0xf6, 0x32, 0x7b, 0xf3, 0x16, 0x12, 0x32, 0x45, 0x50, 0xbd, 0x54, 0xca, 0xe5 }|VOID*|0x00000010
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2|{ 0x66, 0xcf, 0x57, 0xa4, 0xac, 0x7e, 0x7f, 0x3d, 0x21, 0x88, 0x3a, 0x58, 0x3c, 0x27, 0xd7, 0xe8 }|VOID*|0x00000011
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2Legacy|{ 0x8b, 0xcb, 0xe0, 0x14, 0xd1, 0x46, 0x79, 0xae, 0x7f, 0x20, 0xcf, 0x84, 0x22, 0xc7, 0x94, 0x4a }|VOID*|0x00000012
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV3|{ 0x4d, 0x03, 0xb8, 0x77, 0x63, 0x25, 0x0a, 0x7f, 0xe9, 0x72, 0xfa, 0x68, 0x74, 0xc7, 0x5e, 0xb5 }|VOID*|0x00000013
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2|{ 0x36, 0x4f, 0x61, 0x92, 0x86, 0xb1, 0xa2, 0x16, 0x32, 0x65, 0x35, 0x3f, 0x01, 0xf3, 0x3b, 0x64 }|VOID*|0x00000014
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2Legacy|{ 0xf6, 0xcb, 0x9d, 0x86, 0x38, 0x74, 0x8a, 0xb0, 0xfe, 0x40, 0x08, 0x0f, 0x3f, 0xb3, 0x50, 0x7c }|VOID*|0x00000015
+  gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV3|{ 0x51, 0xd0, 0x75, 0x6b, 0x9d, 0x35, 0x1b, 0x1b, 0xa6, 0xc6, 0xab, 0xa0, 0x90, 0xf9, 0xf0, 0x0a }|VOID*|0x00000016
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h
@@ -0,0 +1,154 @@
+/** @file
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+*  Copyright (c) 2012, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_CTA15A7_H__
+#define __ARM_VEXPRESS_CTA15A7_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE              0x1C010000
+
+#ifdef ARM_BIGLITTLE_TC2
+
+// Secure NOR Flash
+#define ARM_VE_SEC_NOR0_BASE                  0x00000000
+#define ARM_VE_SEC_NOR0_SZ                    SIZE_64MB
+
+// Secure RAM
+#define ARM_VE_SEC_RAM0_BASE                  0x04000000
+#define ARM_VE_SEC_RAM0_SZ                    SIZE_64MB
+
+#endif
+
+// NOR Flash 0
+#define ARM_VE_SMB_NOR0_BASE                  0x08000000
+#define ARM_VE_SMB_NOR0_SZ                    SIZE_64MB
+// NOR Flash 1
+#define ARM_VE_SMB_NOR1_BASE                  0x0C000000
+#define ARM_VE_SMB_NOR1_SZ                    SIZE_64MB
+
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE                  0x14000000
+#define ARM_VE_SMB_SRAM_SZ                    SIZE_32MB
+
+// USB, Ethernet, VRAM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_SMB_PERIPH_BASE                0x18000000
+#define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_32MB + SIZE_16MB)
+#else
+#define ARM_VE_SMB_PERIPH_BASE                0x1C000000
+#define ARM_VE_SMB_PERIPH_SZ                  (SIZE_64MB + SIZE_16MB)
+#endif
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE      ARM_VE_SMB_PERIPH_BASE
+
+// On-Chip non-secure ROM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_TC2_NON_SECURE_ROM_BASE        0x1F000000
+#define ARM_VE_TC2_NON_SECURE_ROM_SZ          SIZE_16MB
+#endif
+
+// On-Chip Peripherals
+#define ARM_VE_ONCHIP_PERIPH_BASE             0x20000000
+#define ARM_VE_ONCHIP_PERIPH_SZ               0x10000000
+
+// On-Chip non-secure SRAM
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_TC2_NON_SECURE_SRAM_BASE       0x2E000000
+#define ARM_VE_TC2_NON_SECURE_SRAM_SZ         SIZE_64KB
+#endif
+
+// Allocate a section for the VRAM (Video RAM)
+// If 0 then allow random memory allocation
+#define LCD_VRAM_CORE_TILE_BASE               0
+
+// Define SEC phase sync point
+#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE   (ARM_SEC_EVENT_MAX + 1)
+
+/***********************************************************************************
+   Core Tile memory-mapped Peripherals
+************************************************************************************/
+
+// PL354 Static Memory Controller Base
+#ifdef ARM_BIGLITTLE_TC2
+#define ARM_VE_SMC_CTRL_BASE                    0x7FFD0000
+#else
+#define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
+#endif
+
+#define ARM_CTA15A7_SCC_BASE                    0x7FFF0000
+#define ARM_CTA15A7_SCC_CFGREG48                (ARM_CTA15A7_SCC_BASE + 0x700)
+
+#define ARM_CTA15A7_SCC_SYSINFO                 ARM_CTA15A7_SCC_CFGREG48
+
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val)         (((val) >> 20) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val)        (((val) >> 16) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15              (1 << 0)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7               (1 << 1)
+#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH   (1 << 4)
+
+#define ARM_CTA15A7_SPC_BASE                    0x7FFF0B00
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK           (ARM_CTA15A7_SPC_BASE + 0x24)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT         (ARM_CTA15A7_SPC_BASE + 0x3C)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR0            (ARM_CTA15A7_SPC_BASE + 0x68)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR1            (ARM_CTA15A7_SPC_BASE + 0x6C)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR2            (ARM_CTA15A7_SPC_BASE + 0x70)
+#define ARM_CTA15A7_SPC_A15_BX_ADDR3            (ARM_CTA15A7_SPC_BASE + 0x74)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR0             (ARM_CTA15A7_SPC_BASE + 0x78)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR1             (ARM_CTA15A7_SPC_BASE + 0x7C)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR2             (ARM_CTA15A7_SPC_BASE + 0x80)
+#define ARM_CTA15A7_SPC_A7_BX_ADDR3             (ARM_CTA15A7_SPC_BASE + 0x84)
+
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0  (1 << 0)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1  (1 << 1)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0  (1 << 2)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1  (1 << 3)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0   (1 << 4)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1   (1 << 5)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2   (1 << 6)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0   (1 << 7)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1   (1 << 8)
+#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2   (1 << 9)
+
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0   (1 << 0)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1   (1 << 1)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2  (1 << 2)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0    (1 << 3)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1    (1 << 4)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2    (1 << 5)
+#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2   (1 << 6)
+
+
+/***********************************************************************************
+// Memory-mapped peripherals
+************************************************************************************/
+
+/*// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE                         0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE                         ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)*/
+
+#endif
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h
@@ -0,0 +1,121 @@
+/** @file
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_H__
+#define __ARM_VEXPRESS_H__
+
+#include <Base.h>
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Can be NOR0, NOR1, DRAM
+#define ARM_VE_REMAP_BASE                       0x00000000
+#define ARM_VE_REMAP_SZ                         SIZE_64MB
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         SIZE_256MB
+#define ARM_VE_BOARD_PERIPH_BASE                0x10000000
+#define ARM_VE_CHIP_PERIPH_BASE                 0x10020000
+
+// SMC
+#define ARM_VE_SMC_BASE                         0x40000000
+#define ARM_VE_SMC_SZ                           0x1C000000
+
+// NOR Flash 1
+#define ARM_VE_SMB_NOR0_BASE                    0x40000000
+#define ARM_VE_SMB_NOR0_SZ                      SIZE_64MB
+// NOR Flash 2
+#define ARM_VE_SMB_NOR1_BASE                    0x44000000
+#define ARM_VE_SMB_NOR1_SZ                      SIZE_64MB
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE                    0x48000000
+#define ARM_VE_SMB_SRAM_SZ                      SIZE_32MB
+// USB, Ethernet, VRAM
+#define ARM_VE_SMB_PERIPH_BASE                  0x4C000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        ARM_VE_SMB_PERIPH_BASE
+#define ARM_VE_SMB_PERIPH_SZ                    SIZE_64MB
+
+// DRAM
+#define ARM_VE_DRAM_BASE                        PcdGet64 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ                          PcdGet64 (PcdSystemMemorySize)
+// Inside the DRAM we allocate a section for the VRAM (Video RAM)
+#define LCD_VRAM_CORE_TILE_BASE                     0x64000000
+
+// External AXI between daughterboards (Logic Tile)
+#define ARM_VE_EXT_AXI_BASE                     0xE0000000
+#define ARM_VE_EXT_AXI_SZ                       0x20000000  /* 512 MB */
+
+
+/***********************************************************************************
+   Core Tile memory-mapped Peripherals
+************************************************************************************/
+
+// PL111 Colour LCD Controller - core tile
+#define PL111_CLCD_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
+#define PL111_CLCD_SITE                         ARM_VE_DAUGHTERBOARD_1_SITE
+
+// PL341 Dynamic Memory Controller Base
+#define ARM_VE_DMC_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
+
+// PL354 Static Memory Controller Base
+#define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
+
+// System Configuration Controller register Base addresses
+#define ARM_VE_SYS_CFG_CTRL_BASE                (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
+#define ARM_VE_SCC_BASE                         ARM_VE_SYS_CFG_CTRL_BASE
+#define ARM_VE_SYS_CFGRW0_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
+#define ARM_VE_SYS_CFGRW1_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
+#define ARM_VE_SYS_CFGRW2_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
+
+// SP805 Watchdog on Cortex A9 core tile
+#define SP805_WDOG_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
+
+// BP147 TZPC Base Address
+#define ARM_VE_TZPC_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)
+
+// PL301 Fast AXI Base Address
+#define ARM_VE_FAXI_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)
+
+// TZASC Trust Zone Address Space Controller Base Address
+#define ARM_VE_TZASC_BASE                       (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)
+
+// PL310 L2x0 Cache Controller Base Address
+//#define ARM_VE_L2x0_CTLR_BASE                 0x1E00A000
+
+/***********************************************************************************
+   Peripherals' misc settings
+************************************************************************************/
+
+#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000
+#define ARM_VE_CFGRW1_REMAP_NOR0                0
+#define ARM_VE_CFGRW1_REMAP_NOR1                (1 << 28)
+#define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)
+#define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)
+
+// TZASC - Other settings
+#define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)
+#define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)
+#define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)
+#define ARM_VE_DECPROT_BIT_SMC_TZASC            (1 << 13)
+#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ          (1)
+#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK       (1 << 3)
+#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)
+#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)
+
+#endif
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
@@ -0,0 +1,79 @@
+/** @file
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_H__
+#define __ARM_VEXPRESS_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Can be NOR0, NOR1, DRAM
+#define ARM_VE_REMAP_BASE                       0x00000000
+#define ARM_VE_REMAP_SZ                         SIZE_64MB
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE                0x1C010000
+
+// NOR Flash 1
+// There is typo in the reference manual for the Base address of NOR Flash 1
+#define ARM_VE_SMB_NOR0_BASE                    0x08000000
+#define ARM_VE_SMB_NOR0_SZ                      SIZE_64MB
+// NOR Flash 2
+#define ARM_VE_SMB_NOR1_BASE                    0x0C000000
+#define ARM_VE_SMB_NOR1_SZ                      SIZE_64MB
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE                    0x2E000000
+#define ARM_VE_SMB_SRAM_SZ                      SIZE_64KB
+// USB, Ethernet, VRAM
+#define ARM_VE_SMB_PERIPH_BASE                  0x18800000
+#define ARM_VE_SMB_PERIPH_SZ                    (SIZE_64MB - SIZE_8MB)
+
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        0x18000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE        0x800000
+
+// DRAM
+#define ARM_VE_DRAM_BASE                        PcdGet64 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ                          PcdGet64 (PcdSystemMemorySize)
+
+// This can be any value since we only support motherboard PL111
+#define LCD_VRAM_CORE_TILE_BASE                 0x00000000
+
+// On-chip peripherals (Snoop Control Unit etc...)
+#define ARM_VE_ON_CHIP_PERIPH_BASE              0x2C000000
+// Note: The TRM says not all the peripherals are implemented
+#define ARM_VE_ON_CHIP_PERIPH_SZ                SIZE_256MB
+
+
+// External AXI between daughterboards (Logic Tile)
+#define ARM_VE_EXT_AXI_BASE                     0x2E010000 // Not modelled
+#define ARM_VE_EXT_AXI_SZ                       0x20000000  /* 512 MB */
+
+/***********************************************************************************
+// Memory-mapped peripherals
+************************************************************************************/
+
+// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE                         0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE                         ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1
+
+#endif
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
@@ -0,0 +1,140 @@
+/** @file
+*  Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __VEXPRESSMOTHERBOARD_H_
+#define __VEXPRESSMOTHERBOARD_H_
+
+#include <ArmPlatform.h>
+
+/***********************************************************************************
+// Motherboard memory-mapped peripherals
+************************************************************************************/
+
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
+#define ARM_VE_SYS_ID_REG                         (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
+#define ARM_VE_SYS_SW_REG                         (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
+#define ARM_VE_SYS_LED_REG                        (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
+#define ARM_VE_SYS_FLAGS_REG                      (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_SET_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_CLR_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
+#define ARM_VE_SYS_FLAGS_NV_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_SET_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
+#define ARM_VE_SYS_FLASH                          (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
+#define ARM_VE_SYS_CFGSWR_REG                     (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
+#define ARM_VE_SYS_MISC                           (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
+#define ARM_VE_SYS_PROCID0_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
+#define ARM_VE_SYS_PROCID1_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
+#define ARM_VE_SYS_CFGDATA_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
+#define ARM_VE_SYS_CFGCTRL_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
+#define ARM_VE_SYS_CFGSTAT_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
+
+// SP810 Controller
+#ifndef SP810_CTRL_BASE
+#define SP810_CTRL_BASE                           (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
+#endif
+
+// PL111 Colour LCD Controller - motherboard
+#define PL111_CLCD_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)
+
+#define ARM_VE_SYS_PROC_ID_HBI                    0xFFF
+#define ARM_VE_SYS_PROC_ID_MASK                   (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_UNSUPPORTED            (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A9              (UINT32)(0x0CU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A5              (UINT32)(0x12U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A15             (UINT32)(0x14U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A7              (UINT32)(0x18U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A12             (UINT32)(0x1CU << 24)
+
+// Boot Master Select:
+// 0 = Site 1 boot master
+// 1 = Site 2 boot master
+#define ARM_VE_SYS_MISC_MASTERSITE                (1 << 14)
+//
+// Sites where the peripheral is fitted
+//
+#define ARM_VE_UNSUPPORTED                        ~0
+#define ARM_VE_MOTHERBOARD_SITE                   0
+#define ARM_VE_DAUGHTERBOARD_1_SITE               1
+#define ARM_VE_DAUGHTERBOARD_2_SITE               2
+
+#define VIRTUAL_SYS_CFG(site,func)                (((site) << 24) | (func))
+
+//
+// System Configuration Control Functions
+//
+#define SYS_CFG_OSC                               1
+#define SYS_CFG_VOLT                              2
+#define SYS_CFG_AMP                               3
+#define SYS_CFG_TEMP                              4
+#define SYS_CFG_RESET                             5
+#define SYS_CFG_SCC                               6
+#define SYS_CFG_MUXFPGA                           7
+#define SYS_CFG_SHUTDOWN                          8
+#define SYS_CFG_REBOOT                            9
+#define SYS_CFG_DVIMODE                           11
+#define SYS_CFG_POWER                             12
+// Oscillator for Site 1
+#define SYS_CFG_OSC_SITE1                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)
+// Oscillator for Site 2
+#define SYS_CFG_OSC_SITE2                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)
+// Can not access the battery backed-up hardware clock on the Versatile Express motherboard
+#define SYS_CFG_RTC                               VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
+
+//
+// System ID
+//
+// All RTSM VE models have the same System ID : 0x225F500
+//
+// FVP models have a different System ID.
+// Default Base model System ID : 0x00201100
+// [31:28] Rev     - Board revision:          0x0     = Rev A
+// [27:16] HBI     - HBI board number in BCD: 0x020   = v8 Base Platform
+// [15:12] Variant - Build variant of board:  0x1     = Variant B. (GIC 64k map)
+// [11:8]  Plat    - Platform type:           0x1     = Model
+// [7:0]   FPGA    - FPGA build, BCD coded:   0x00
+//
+//HBI = 010 = Foundation Model
+//HBI = 020 = Base Platform
+//
+// And specifically, the GIC register banks start at the following
+// addresses:
+//              Variant = 0             Variant = 1
+//GICD          0x2c001000              0x2f000000
+//GICC          0x2c002000              0x2c000000
+//GICH          0x2c004000              0x2c010000
+//GICV          0x2c006000              0x2c020000
+
+#define ARM_FVP_BASE_BOARD_SYS_ID       (0x00200100)
+#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)
+
+#define ARM_FVP_SYS_ID_REV_MASK        (UINT32)(0xFUL   << 28)
+#define ARM_FVP_SYS_ID_HBI_MASK        (UINT32)(0xFFFUL << 16)
+#define ARM_FVP_SYS_ID_VARIANT_MASK    (UINT32)(0xFUL   << 12)
+#define ARM_FVP_SYS_ID_PLAT_MASK       (UINT32)(0xFUL   << 8 )
+#define ARM_FVP_SYS_ID_FPGA_MASK       (UINT32)(0xFFUL  << 0 )
+#define ARM_FVP_GIC_VE_MMAP            0x0
+#define ARM_FVP_GIC_BASE_MMAP          (UINT32)(1 << 12)
+
+// The default SYS_IDs. These can be changed when starting the model.
+#define ARM_RTSM_SYS_ID                (0x225F500)
+#define ARM_FVP_BASE_SYS_ID            (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
+#define ARM_FVP_FOUNDATION_SYS_ID      (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
+
+#endif /* VEXPRESSMOTHERBOARD_H_ */
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
@@ -0,0 +1,53 @@
+#/* @file
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA15A7ArmVExpressLib
+  FILE_GUID                      = b98a6cb7-d472-4128-ad62-a7347f85ce13
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  MemoryAllocationLib
+  SerialPortLib
+
+[Sources.common]
+  CTA15-A7.c
+  CTA15-A7Mem.c
+  CTA15-A7Helper.asm | RVCT
+  CTA15-A7Helper.S   | GCC
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c
@@ -0,0 +1,195 @@
+/** @file
+*
+*  Copyright (c) 2012, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
+    (UINT64)0
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
+    (UINT64)0
+  },
+#ifndef ARM_BIGLITTLE_TC2
+  {
+    // Cluster 0, Core 2
+    0x0, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
+    (UINT64)0
+  },
+  {
+    // Cluster 0, Core 3
+    0x0, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
+    (UINT64)0
+  },
+#endif
+  {
+    // Cluster 1, Core 0
+    0x1, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
+    (UINT64)0
+  },
+  {
+    // Cluster 1, Core 1
+    0x1, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
+    (UINT64)0
+  },
+  {
+    // Cluster 1, Core 2
+    0x1, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
+    (UINT64)0
+  }
+#ifndef ARM_BIGLITTLE_TC2
+  ,{
+    // Cluster 1, Core 3
+    0x1, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
+    (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
+    (UINT64)0
+  }
+#endif
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH) {
+    return BOOT_WITH_DEFAULT_SETTINGS;
+  } else {
+    return BOOT_WITH_FULL_CONFIGURATION;
+  }
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  if (!ArmPlatformIsPrimaryCore (MpId)) {
+    return RETURN_SUCCESS;
+  }
+
+  // Nothing to do here
+
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  // Only support one cluster
+  *CoreCount    = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mVersatileExpressCTA15A7InfoTable;
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
@@ -0,0 +1,81 @@
+//
+//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+#include <ArmPlatform.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  bx    lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48)
+  ldr   r1, [r1]
+  lsr   r1, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r2, r1, #4
+  and   r2, r2, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r1, r1, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r1, r1, r2
+
+  // Keep the Cluster ID and Core ID from the MPID
+  MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK)
+  and   r0, r0, r2
+
+  // Compare mpid and boot cpu from ARM_SCC_CFGREG48
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48)
+  ldr   r0, [r0]
+  lsr   r0, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r1, r0, #4
+  and   r1, r1, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r0, r0, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r0, r0, r1
+  bx    lr
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm
@@ -0,0 +1,96 @@
+//
+//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <Library/ArmLib.h>
+
+#include <ArmPlatform.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+  EXPORT  ArmPlatformPeiBootAction
+  EXPORT  ArmPlatformGetCorePosition
+  EXPORT  ArmPlatformIsPrimaryCore
+  EXPORT  ArmPlatformGetPrimaryCoreMpId
+
+  PRESERVE8
+  AREA    CTA15A7Helper, CODE, READONLY
+
+ArmPlatformPeiBootAction FUNCTION
+  bx    lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ArmPlatformGetCorePosition FUNCTION
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ArmPlatformIsPrimaryCore FUNCTION
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  mov32 r1, ARM_CTA15A7_SCC_CFGREG48
+  ldr   r1, [r1]
+  lsr   r1, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r2, r1, #4
+  and   r2, r2, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r1, r1, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r1, r1, r2
+
+  // Keep the Cluster ID and Core ID from the MPID
+  mov32 r2, ARM_CLUSTER_MASK :OR: ARM_CORE_MASK
+  and   r0, r0, r2
+
+  // Compare mpid and boot cpu from ARM_SCC_CFGREG48
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+  // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
+  // with cpu_id[0:3] and cluster_id[4:7]
+  mov32 r0, ARM_CTA15A7_SCC_CFGREG48
+  ldr   r0, [r0]
+  lsr   r0, #24
+
+  // Shift the SCC value to get the cluster ID at the offset #8
+  lsl   r1, r0, #4
+  and   r1, r1, #0xF00
+
+  // Keep only the cpu ID from the original SCC
+  and   r0, r0, #0x0F
+  // Add the Cluster ID to the Cpu ID
+  orr   r0, r0, r1
+  bx    lr
+  ENDFUNC
+
+  END
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
@@ -0,0 +1,182 @@
+/** @file
+*
+*  Copyright (c) 2012, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <ArmPlatform.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+    return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+    CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+#ifdef ARM_BIGLITTLE_TC2
+  // Secure NOR0 Flash
+  VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SEC_NOR0_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SEC_NOR0_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_SEC_NOR0_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  // Secure RAM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SEC_RAM0_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SEC_RAM0_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_SEC_RAM0_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+#endif
+
+  // SMB CS0 - NOR0 Flash
+  VirtualMemoryTable[Index].PhysicalBase    = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].Length          = SIZE_256KB * 255;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  // Environment Variables region
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].Length          = SIZE_64KB * 4;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SMB CS1 or CS4 - NOR1 Flash
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR1_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR1_BASE;
+  VirtualMemoryTable[Index].Length          = SIZE_256KB * 255;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  // Environment Variables region
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
+  VirtualMemoryTable[Index].Length          = SIZE_64KB * 4;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SMB CS3 or CS1 - PSRAM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_SMB_SRAM_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // Motherboard peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_SMB_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+#ifdef ARM_BIGLITTLE_TC2
+  // Non-secure ROM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_TC2_NON_SECURE_ROM_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_TC2_NON_SECURE_ROM_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_TC2_NON_SECURE_ROM_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+#endif
+
+  // OnChip peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_ONCHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_ONCHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_ONCHIP_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SCC Region
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_CTA15A7_SCC_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_CTA15A7_SCC_BASE;
+  VirtualMemoryTable[Index].Length          = SIZE_64KB;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+#ifdef ARM_BIGLITTLE_TC2
+  // TC2 OnChip non-secure SRAM
+  VirtualMemoryTable[++Index].PhysicalBase  = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
+  VirtualMemoryTable[Index].Length          = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+#endif
+
+#ifndef ARM_BIGLITTLE_TC2
+  // Workaround for SRAM bug in RTSM
+  if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {
+    VirtualMemoryTable[++Index].PhysicalBase  = 0x80000000;
+    VirtualMemoryTable[Index].VirtualBase     = 0x80000000;
+    VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;
+    VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+  }
+#endif
+
+  // DDR
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // Detect if it is a 1GB or 2GB Test Chip
+  //   [16:19]: 0=1GB TC2, 1=2GB TC2
+  if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
+    DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
+    BuildResourceDescriptorHob (
+        EFI_RESOURCE_SYSTEM_MEMORY,
+        EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+          EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+          EFI_RESOURCE_ATTRIBUTE_TESTED,
+        PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),
+        SIZE_1GB
+    );
+
+    // Map the additional 1GB into the MMU
+    VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
+    VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
+    VirtualMemoryTable[Index].Length          = SIZE_1GB;
+    VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
+  VirtualMemoryTable[Index].Length          = 0;
+  VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
@@ -0,0 +1,57 @@
+#/* @file
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA9x4ArmVExpressLib
+  FILE_GUID                      = b16c63a0-f417-11df-b3af-0002a5d5c51b
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  ArmTrustZoneLib
+  MemoryAllocationLib
+  PL341DmcLib
+  PL301AxiLib
+
+[Sources.common]
+  CTA9x4Helper.asm    | RVCT
+  CTA9x4Helper.S      | GCC
+  CTA9x4.c
+  CTA9x4Mem.c
+  CTA9x4Helper.S   | GCC
+  CTA9x4Helper.asm | RVCT
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLibSec.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLibSec.inf
@@ -0,0 +1,54 @@
+#/* @file
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CTA9x4ArmVExpressLibSec
+  FILE_GUID                      = 8d25ef2c-2015-416e-b8aa-2369fecd4bda
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  ArmTrustZoneLib
+  PL341DmcLib
+  PL301AxiLib
+  SerialPortLib
+
+[Sources.common]
+  CTA9x4.c
+  CTA9x4Helper.S   | GCC
+  CTA9x4Helper.asm | RVCT
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
@@ -0,0 +1,198 @@
+/** @file
+*
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Drivers/PL341Dmc.h>
+#include <Drivers/PL301Axi.h>
+#include <Drivers/SP804Timer.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 2
+    0x0, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 3
+    0x0, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+// DDR2 timings
+PL341_DMC_CONFIG DDRTimings = {
+  .MaxChip   = 1,
+  .IsUserCfg = TRUE,
+  .User0Cfg = 0x7C924924,
+  .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
+  .HasQos    = TRUE,
+  .RefreshPeriod  = 0x3D0,
+  .CasLatency  = 0x8,
+  .WriteLatency  = 0x3,
+  .t_mrd    = 0x2,
+  .t_ras    = 0xA,
+  .t_rc   = 0xE,
+  .t_rcd    = 0x104,
+  .t_rfc    = 0x2f32,
+  .t_rp   = 0x14,
+  .t_rrd    = 0x2,
+  .t_wr   = 0x4,
+  .t_wtr    = 0x2,
+  .t_xp   = 0x2,
+  .t_xsr    = 0xC8,
+  .t_esr    = 0x14,
+  .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
+                        DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
+  .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
+            DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
+  .MemoryCfg3  = 0x00000001,
+  .ChipCfg0    = 0x00010000,
+  .t_faw    = 0x00000A0D,
+  .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
+  .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
+    return BOOT_WITH_FULL_CONFIGURATION;
+  } else {
+    return BOOT_ON_S2_RESUME;
+  }
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  if (!ArmPlatformIsPrimaryCore (MpId)) {
+    return RETURN_SUCCESS;
+  }
+
+  // Configure periodic timer (TIMER0) for 1MHz operation
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+  // Configure 1MHz clock
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+  // configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+  PL341DmcInit (ARM_VE_DMC_BASE, &DDRTimings);
+  PL301AxiInit (ARM_VE_FAXI_BASE);
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
@@ -0,0 +1,49 @@
+#
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32  (r0, FixedPcdGet32 (PcdArmPrimaryCore))
+  bx    lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32  (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   r0, r0, r1
+  MOV32  (r1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   r0, r0, #ARM_CORE_MASK
+  bx    lr
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  bx    lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
@@ -0,0 +1,63 @@
+//
+//  Copyright (c) 2013, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <Library/ArmLib.h>
+
+#include <AutoGen.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+  EXPORT  ArmPlatformPeiBootAction
+  EXPORT  ArmPlatformIsPrimaryCore
+  EXPORT  ArmPlatformGetPrimaryCoreMpId
+  EXPORT  ArmPlatformGetCorePosition
+
+  AREA CTA9x4Helper, CODE, READONLY
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+  mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
+  bx      lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ArmPlatformIsPrimaryCore FUNCTION
+  mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)
+  and   r0, r0, r1
+  mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ArmPlatformGetCorePosition FUNCTION
+  and   r0, r0, #ARM_CORE_MASK
+  bx    lr
+  ENDFUNC
+
+ArmPlatformPeiBootAction FUNCTION
+  bx    lr
+  ENDFUNC
+
+  END
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
@@ -0,0 +1,119 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <ArmPlatform.h>
+
+// Number of Virtual Memory Map Descriptors without a Logic Tile
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+  ASSERT(VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
+    // ReMap (Either NOR Flash or DRAM)
+    VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
+    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;
+    VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;
+    VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+  }
+
+  // DDR
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // SMC CS7
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SMB CS0-CS1 - NOR Flash 1 & 2
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // SMB CS2 - SRAM
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;
+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
+
+  // SMB CS3-CS6 - Motherboard Peripherals
+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // If a Logic Tile is connected to The ARM Versatile Express Motherboard
+  if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
+      VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
+      VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;
+      VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;
+      VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+      ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
+  } else {
+    ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase  = 0;
+  VirtualMemoryTable[Index].Length       = 0;
+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S
@@ -0,0 +1,61 @@
+#
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+  ret
+
+# IN None
+# OUT x0 = number of cores present in the system
+ASM_FUNC(ArmGetCpuCountPerCluster)
+  MOV32  (w0, FixedPcdGet32 (PcdCoreCount))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32  (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   w0, w1
+  b.ne  1f
+  mov   x0, #1
+  ret
+1:
+  mov   x0, #0
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S
@@ -0,0 +1,97 @@
+#
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+#include <Chipset/ArmCortexA9.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  bx    lr
+
+# IN None
+# OUT r0 = SCU Base Address
+ASM_FUNC(ArmGetScuBaseAddress)
+  # Read Configuration Base Address Register. ArmCBar cannot be called to get
+  # the Configuration BAR as a stack is not necessary setup. The SCU is at the
+  # offset 0x0000 from the Private Memory Region.
+  mrc   p15, 4, r0, c15, c0, 0
+  bx    lr
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32  (r0, FixedPcdGet32 (PcdArmPrimaryCore))
+  bx    lr
+
+# IN None
+# OUT r0 = number of cores present in the system
+ASM_FUNC(ArmGetCpuCountPerCluster)
+  stmfd SP!, {r1-r2}
+
+  # Read CP15 MIDR
+  mrc   p15, 0, r1, c0, c0, 0
+
+  # Check if the CPU is A15
+  mov   r1, r1, LSR #4
+  MOV32 (r0, ARM_CPU_TYPE_MASK)
+  and   r1, r1, r0
+
+  MOV32 (r0, ARM_CPU_TYPE_A15)
+  cmp   r1, r0
+  beq   _Read_cp15_reg
+
+_CPU_is_not_A15:
+  mov   r2, lr                           @ Save link register
+  bl    ArmGetScuBaseAddress             @ Read SCU Base Address
+  mov   lr, r2                           @ Restore link register val
+  ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count
+  b     _Return
+
+_Read_cp15_reg:
+  mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count
+  lsr   r0, #24
+
+_Return:
+  and   r0, r0, #3
+  # Add '1' to the number of CPU on the Cluster
+  add   r0, r0, #1
+  ldmfd SP!, {r1-r2}
+  bx lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32  (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+  and   r0, r0, r1
+  MOV32  (r1, FixedPcdGet32 (PcdArmPrimaryCore))
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm
@@ -0,0 +1,118 @@
+//
+//  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include <Chipset/ArmCortexA9.h>
+
+#include <AutoGen.h>
+
+  INCLUDE AsmMacroIoLib.inc
+
+  EXPORT    ArmPlatformPeiBootAction
+  EXPORT    ArmGetCpuCountPerCluster
+  EXPORT    ArmPlatformIsPrimaryCore
+  EXPORT    ArmPlatformGetPrimaryCoreMpId
+  EXPORT    ArmPlatformGetCorePosition
+
+  AREA RTSMHelper, CODE, READONLY
+
+ArmPlatformPeiBootAction FUNCTION
+  bx    lr
+  ENDFUNC
+
+// IN None
+// OUT r0 = SCU Base Address
+ArmGetScuBaseAddress FUNCTION
+  // Read Configuration Base Address Register. ArmCBar cannot be called to get
+  // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+  // offset 0x0000 from the Private Memory Region.
+  mrc   p15, 4, r0, c15, c0, 0
+  bx  lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+  mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
+  bx    lr
+  ENDFUNC
+
+// IN None
+// OUT r0 = number of cores present in the system
+ArmGetCpuCountPerCluster FUNCTION
+  stmfd SP!, {r1-r2}
+
+  // Read CP15 MIDR
+  mrc   p15, 0, r1, c0, c0, 0
+
+  // Check if the CPU is A15
+  mov   r1, r1, LSR #4
+  mov   r0, #ARM_CPU_TYPE_MASK
+  and   r1, r1, r0
+
+  mov   r0, #ARM_CPU_TYPE_A15
+  cmp   r1, r0
+  beq   _Read_cp15_reg
+
+_CPU_is_not_A15
+  mov   r2, lr                              ; Save link register
+  bl    ArmGetScuBaseAddress                ; Read SCU Base Address
+  mov   lr, r2                              ; Restore link register val
+  ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     ; Read SCU Config reg to get CPU count
+  b     _Return
+
+_Read_cp15_reg
+  mrc   p15, 1, r0, c9, c0, 2            ; Read C9 register of CP15 to get CPU count
+  lsr   r0, #24
+
+
+_Return
+  and   r0, r0, #3
+  // Add '1' to the number of CPU on the Cluster
+  add   r0, r0, #1
+  ldmfd SP!, {r1-r2}
+  bx lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ArmPlatformIsPrimaryCore FUNCTION
+  mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)
+  and   r0, r0, r1
+  mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)
+  ldr   r1, [r1]
+  cmp   r0, r1
+  moveq r0, #1
+  movne r0, #0
+  bx    lr
+  ENDFUNC
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+ArmPlatformGetCorePosition FUNCTION
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+  ENDFUNC
+
+  END
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -0,0 +1,62 @@
+#/* @file
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = RTSMArmVExpressLib
+  FILE_GUID                      = b98a6cb7-d472-4128-ad62-a7347f85ce13
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  MemoryAllocationLib
+  SerialPortLib
+  HobLib
+
+[Sources.common]
+  RTSM.c
+  RTSMMem.c
+
+[Sources.ARM]
+  Arm/RTSMHelper.asm    | RVCT
+  Arm/RTSMHelper.S      | GCC
+
+[Sources.AARCH64]
+  AArch64/RTSMHelper.S
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
--- a/Show More
+++ b/Show More