5b78f30d81
https://bugzilla.tianocore.org/show_bug.cgi?id=556 NASM requires read-only data sections to use the section name .rodata. This fix changes .rdata to .rodata. The build failure from use of .rdata is seen when using the XCODE5 tool chain. Section "7.8.1 macho extensions to the SECTION Directive" of the NASM documentation at http://www.nasm.us/doc/ describes the section name requirements. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Andrew Fish <afish@apple.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
75 lines
2.0 KiB
NASM
75 lines
2.0 KiB
NASM
;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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;* This program and the accompanying materials
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;* are licensed and made available under the terms and conditions of the BSD License
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;* which accompanies this distribution. The full text of the license may be found at
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;* http://opensource.org/licenses/bsd-license.php
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;*
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;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;*
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;*
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;------------------------------------------------------------------------------
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SECTION .rodata
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;
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; Float control word initial value:
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; all exceptions masked, double-precision, round-to-nearest
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;
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mFpuControlWord: DW 0x27F
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;
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; Multimedia-extensions control word:
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; all exceptions masked, round-to-nearest, flush to zero for masked underflow
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;
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mMmxControlWord: DD 0x1F80
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SECTION .text
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;
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; Initializes floating point units for requirement of UEFI specification.
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;
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; This function initializes floating-point control word to 0x027F (all exceptions
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; masked,double-precision, round-to-nearest) and multimedia-extensions control word
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; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
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; for masked underflow).
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;
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global ASM_PFX(InitializeFloatingPointUnits)
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ASM_PFX(InitializeFloatingPointUnits):
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push ebx
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;
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; Initialize floating point units
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;
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finit
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fldcw [mFpuControlWord]
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;
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; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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mov eax, 1
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cpuid
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bt edx, 25
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jnc Done
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;
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; Set OSFXSR bit 9 in CR4
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;
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mov eax, cr4
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or eax, BIT9
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mov cr4, eax
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;
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; The processor should support SSE instruction and we can use
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; ldmxcsr instruction
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;
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ldmxcsr [mMmxControlWord]
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Done:
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pop ebx
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ret
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