0f73cca02b
Given that we only support ARMv7 and up in Tianocore (due to the fact that the PI spec mandates that the PEI services table pointer be stored in the TPIDRURW register, which is not available on earlier CPUs), we can assume that any code executing with the MMU on may perform unaligned accesses (since the AArch32 bindings in the UEFI spec stipulate that unaligned accesses should be allowed if supported by the CPU) So relax the alignment restrictions to XIP modules only, i.e., BASE, SEC, PEI_CORE and PEIM type modules, exactly like we do for AARCH64 already. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>