9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
302 lines
11 KiB
C
302 lines
11 KiB
C
/** @file
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Include file matches things in PI.
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Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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PI Version 1.3
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**/
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#ifndef __PI_I2C_H__
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#define __PI_I2C_H__
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///
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/// A 10-bit slave address is or'ed with the following value enabling the
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/// I2C protocol stack to address the duplicated address space between 0
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// and 127 in 10-bit mode.
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///
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#define I2C_ADDRESSING_10_BIT 0x80000000
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///
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/// I2C controller capabilities
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///
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/// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the
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/// I2C host controller. The StructureSizeInBytes enables variations of
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/// this structure to be identified if there is need to extend this
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/// structure in the future.
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///
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typedef struct {
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///
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/// Length of this data structure in bytes
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///
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UINT32 StructureSizeInBytes;
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///
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/// The maximum number of bytes the I2C host controller is able to
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/// receive from the I2C bus.
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///
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UINT32 MaximumReceiveBytes;
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///
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/// The maximum number of bytes the I2C host controller is able to send
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/// on the I2C bus.
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///
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UINT32 MaximumTransmitBytes;
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///
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/// The maximum number of bytes in the I2C bus transaction.
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///
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UINT32 MaximumTotalBytes;
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} EFI_I2C_CONTROLLER_CAPABILITIES;
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///
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/// I2C device description
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///
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/// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe
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/// the platform specific details associated with an I2C device. This
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/// description is passed to the I2C bus driver during enumeration where
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/// it is made available to the third party I2C device driver via the
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/// EFI_I2C_IO_PROTOCOL.
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///
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typedef struct {
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///
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/// Unique value assigned by the silicon manufacture or the third
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/// party I2C driver writer for the I2C part. This value logically
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/// combines both the manufacture name and the I2C part number into
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/// a single value specified as a GUID.
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///
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CONST EFI_GUID *DeviceGuid;
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///
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/// Unique ID of the I2C part within the system
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///
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UINT32 DeviceIndex;
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///
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/// Hardware revision - ACPI _HRV value. See the Advanced
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/// Configuration and Power Interface Specification, Revision 5.0
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/// for the field format and the Plug and play support for I2C
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/// web-page for restriction on values.
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///
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/// http://www.acpi.info/spec.htm
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/// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx
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///
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UINT32 HardwareRevision;
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///
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/// I2C bus configuration for the I2C device
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///
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UINT32 I2cBusConfiguration;
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///
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/// Number of slave addresses for the I2C device.
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///
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UINT32 SlaveAddressCount;
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///
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/// Pointer to the array of slave addresses for the I2C device.
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///
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CONST UINT32 *SlaveAddressArray;
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} EFI_I2C_DEVICE;
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///
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/// Define the I2C flags
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///
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/// I2C read operation when set
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#define I2C_FLAG_READ 0x00000001
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///
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/// Define the flags for SMBus operation
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///
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/// The following flags are also present in only the first I2C operation
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/// and are ignored when present in other operations. These flags
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/// describe a particular SMB transaction as shown in the following table.
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///
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/// SMBus operation
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#define I2C_FLAG_SMBUS_OPERATION 0x00010000
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/// SMBus block operation
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/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update
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/// the LengthInBytes field of the operation in the request packet with
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/// the actual number of bytes read or written. These values are only
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/// valid when the entire I2C transaction is successful.
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/// This flag also changes the LengthInBytes meaning to be: A maximum
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/// of LengthInBytes is to be read from the device. The first byte
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/// read contains the number of bytes remaining to be read, plus an
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/// optional PEC value.
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#define I2C_FLAG_SMBUS_BLOCK 0x00020000
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/// SMBus process call operation
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#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000
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/// SMBus use packet error code (PEC)
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/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit
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/// to indicate that the PEC value was checked by the hardware and is
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/// not appended to the returned read data.
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///
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#define I2C_FLAG_SMBUS_PEC 0x00080000
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//----------------------------------------------------------------------
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///
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/// QuickRead: OperationCount=1,
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/// LengthInBytes=0, Flags=I2C_FLAG_READ
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/// QuickWrite: OperationCount=1,
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/// LengthInBytes=0, Flags=0
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///
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///
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/// ReceiveByte: OperationCount=1,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_READ
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/// ReceiveByte+PEC: OperationCount=1,
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/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_READ
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/// | I2C_FLAG_SMBUS_PEC
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///
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///
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/// SendByte: OperationCount=1,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// SendByte+PEC: OperationCount=1,
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/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PEC
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///
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///
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/// ReadDataByte: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// LengthInBytes=1, Flags=I2C_FLAG_READ
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/// ReadDataByte+PEC: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PEC
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/// LengthInBytes=2, Flags=I2C_FLAG_READ
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///
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///
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/// WriteDataByte: OperationCount=1,
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/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// WriteDataByte+PEC: OperationCount=1,
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/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PEC
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///
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///
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/// ReadDataWord: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// LengthInBytes=2, Flags=I2C_FLAG_READ
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/// ReadDataWord+PEC: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PEC
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/// LengthInBytes=3, Flags=I2C_FLAG_READ
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///
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///
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/// WriteDataWord: OperationCount=1,
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/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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/// WriteDataWord+PEC: OperationCount=1,
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/// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PEC
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///
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///
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/// ReadBlock: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_BLOCK
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/// LengthInBytes=33, Flags=I2C_FLAG_READ
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/// ReadBlock+PEC: OperationCount=2,
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/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_BLOCK
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/// | I2C_FLAG_SMBUS_PEC
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/// LengthInBytes=34, Flags=I2C_FLAG_READ
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///
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///
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/// WriteBlock: OperationCount=1,
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/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_BLOCK
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/// WriteBlock+PEC: OperationCount=1,
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/// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_BLOCK
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/// | I2C_FLAG_SMBUS_PEC
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///
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///
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/// ProcessCall: OperationCount=2,
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/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PROCESS_CALL
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/// LengthInBytes=2, Flags=I2C_FLAG_READ
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/// ProcessCall+PEC: OperationCount=2,
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/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PROCESS_CALL
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/// | I2C_FLAG_SMBUS_PEC
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/// LengthInBytes=3, Flags=I2C_FLAG_READ
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///
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///
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/// BlkProcessCall: OperationCount=2,
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/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PROCESS_CALL
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/// | I2C_FLAG_SMBUS_BLOCK
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/// LengthInBytes=33, Flags=I2C_FLAG_READ
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/// BlkProcessCall+PEC: OperationCount=2,
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/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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/// | I2C_FLAG_SMBUS_PROCESS_CALL
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/// | I2C_FLAG_SMBUS_BLOCK
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/// | I2C_FLAG_SMBUS_PEC
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/// LengthInBytes=34, Flags=I2C_FLAG_READ
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///
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//----------------------------------------------------------------------
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///
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/// I2C device operation
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///
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/// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which
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/// the I2C controller is either sending or receiving bytes from the bus.
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/// Some transactions will consist of a single operation while others will
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/// be two or more.
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///
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/// Note: Some I2C controllers do not support read or write ping (address
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/// only) operation and will return EFI_UNSUPPORTED status when these
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/// operations are requested.
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///
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/// Note: I2C controllers which do not support complex transactions requiring
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/// multiple repeated start bits return EFI_UNSUPPORTED without processing
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/// any of the transaction.
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///
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typedef struct {
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///
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/// Flags to qualify the I2C operation.
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///
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UINT32 Flags;
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///
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/// Number of bytes to send to or receive from the I2C device. A ping
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/// (address only byte/bytes) is indicated by setting the LengthInBytes
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/// to zero.
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///
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UINT32 LengthInBytes;
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///
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/// Pointer to a buffer containing the data to send or to receive from
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/// the I2C device. The Buffer must be at least LengthInBytes in size.
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///
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UINT8 *Buffer;
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} EFI_I2C_OPERATION;
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///
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/// I2C device request
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///
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/// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The
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/// transaction starts with a start bit followed by the first operation
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/// in the operation array. Subsequent operations are separated with
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/// repeated start bits and the last operation is followed by a stop bit
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/// which concludes the transaction. Each operation is described by one
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/// of the elements in the Operation array.
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///
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typedef struct {
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///
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/// Number of elements in the operation array
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///
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UINTN OperationCount;
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///
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/// Description of the I2C operation
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///
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EFI_I2C_OPERATION Operation [1];
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} EFI_I2C_REQUEST_PACKET;
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#endif // __PI_I2C_H__
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