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Commita4626006bb("EmbeddedPkg/Lan9118Dxe: use MemoryFence") replaced some stalls with memory fences, on the presumption that these were erroneously being used to order memory accesses. However, this was not the case. LAN9118 devices require a timing delay between state-changing reads/writes and subsequent reads, as updates to the register file are asynchronous and the effects of state-changes are not immediately visible to subsequent reads. This delay cannot be ensured through the use of memory barriers, which only enforce observable ordering, and not timing. Thus, converting these stalls to memory fences was erroneous, and may result in stale values being read. This reverts commita4626006bb. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>