56ad09ba75
Some security features depend on the page table enabling. So, This patch is to enable paging if it is not enabled (32bit mode)" Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
612 lines
17 KiB
C
612 lines
17 KiB
C
/** @file
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Basic paging support for the CPU to enable Stack Guard.
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Register/Intel/Cpuid.h>
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#include <Register/Intel/Msr.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/CpuLib.h>
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#include <Library/BaseLib.h>
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#include <Guid/MigratedFvInfo.h>
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#include "CpuMpPei.h"
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_U BIT2
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#define IA32_PG_A BIT5
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#define IA32_PG_D BIT6
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#define IA32_PG_PS BIT7
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#define IA32_PG_NX BIT63
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#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
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#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \
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PAGE_ATTRIBUTE_BITS)
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#define PAGING_PAE_INDEX_MASK 0x1FF
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull
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typedef enum {
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PageNone = 0,
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PageMin = 1,
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Page4K = PageMin,
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Page2M = 2,
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Page1G = 3,
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Page512G = 4,
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PageMax = Page512G
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} PAGE_ATTRIBUTE;
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typedef struct {
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PAGE_ATTRIBUTE Attribute;
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UINT64 Length;
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UINT64 AddressMask;
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UINTN AddressBitOffset;
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UINTN AddressBitLength;
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} PAGE_ATTRIBUTE_TABLE;
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PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
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{ PageNone, 0, 0, 0, 0 },
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{ Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 },
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{ Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 },
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{ Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 },
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{ Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },
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};
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EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = {
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{
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiMemoryDiscoveredPpiGuid,
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MemoryDiscoveredPpiNotifyCallback
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}
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};
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/**
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The function will check if IA32 PAE is supported.
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@retval TRUE IA32 PAE is supported.
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@retval FALSE IA32 PAE is not supported.
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**/
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BOOLEAN
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IsIa32PaeSupported (
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VOID
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)
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{
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UINT32 RegEax;
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CPUID_VERSION_INFO_EDX RegEdx;
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AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
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if (RegEax >= CPUID_VERSION_INFO) {
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AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
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if (RegEdx.Bits.PAE != 0) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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This API provides a way to allocate memory for page table.
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@param Pages The number of 4 KB pages to allocate.
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@return A pointer to the allocated buffer or NULL if allocation fails.
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**/
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VOID *
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AllocatePageTableMemory (
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IN UINTN Pages
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)
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{
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VOID *Address;
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Address = AllocatePages (Pages);
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if (Address != NULL) {
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ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));
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}
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return Address;
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}
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/**
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Get the type of top level page table.
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@retval Page512G PML4 paging.
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@retval Page1G PAE paging.
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**/
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PAGE_ATTRIBUTE
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GetPageTableTopLevelType (
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VOID
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)
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{
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MSR_IA32_EFER_REGISTER MsrEfer;
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MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
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return (MsrEfer.Bits.LMA == 1) ? Page512G : Page1G;
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}
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/**
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Return page table entry matching the address.
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@param[in] Address The address to be checked.
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@param[out] PageAttributes The page attribute of the page entry.
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@return The page entry.
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**/
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VOID *
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GetPageTableEntry (
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IN PHYSICAL_ADDRESS Address,
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OUT PAGE_ATTRIBUTE *PageAttribute
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)
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{
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INTN Level;
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UINTN Index;
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UINT64 *PageTable;
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UINT64 AddressEncMask;
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
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PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
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for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {
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Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);
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Index &= PAGING_PAE_INDEX_MASK;
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//
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// No mapping?
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//
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if (PageTable[Index] == 0) {
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*PageAttribute = PageNone;
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return NULL;
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}
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//
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// Page memory?
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//
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if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
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*PageAttribute = (PAGE_ATTRIBUTE)Level;
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return &PageTable[Index];
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}
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//
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// Page directory or table
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//
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PageTable = (UINT64 *)(UINTN)(PageTable[Index] &
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~AddressEncMask &
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PAGING_4K_ADDRESS_MASK_64);
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}
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*PageAttribute = PageNone;
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return NULL;
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}
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/**
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This function splits one page entry to smaller page entries.
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@param[in] PageEntry The page entry to be splitted.
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@param[in] PageAttribute The page attribute of the page entry.
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@param[in] SplitAttribute How to split the page entry.
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@param[in] Recursively Do the split recursively or not.
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@retval RETURN_SUCCESS The page entry is splitted.
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@retval RETURN_INVALID_PARAMETER If target page attribute is invalid
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@retval RETURN_OUT_OF_RESOURCES No resource to split page entry.
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**/
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RETURN_STATUS
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SplitPage (
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IN UINT64 *PageEntry,
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IN PAGE_ATTRIBUTE PageAttribute,
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IN PAGE_ATTRIBUTE SplitAttribute,
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IN BOOLEAN Recursively
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)
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{
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UINT64 BaseAddress;
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UINT64 *NewPageEntry;
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UINTN Index;
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UINT64 AddressEncMask;
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PAGE_ATTRIBUTE SplitTo;
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if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
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ASSERT (SplitAttribute != PageNone);
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ASSERT (SplitAttribute < PageAttribute);
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return RETURN_INVALID_PARAMETER;
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}
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NewPageEntry = AllocatePageTableMemory (1);
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if (NewPageEntry == NULL) {
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ASSERT (NewPageEntry != NULL);
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return RETURN_OUT_OF_RESOURCES;
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}
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//
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// One level down each step to achieve more compact page table.
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//
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SplitTo = PageAttribute - 1;
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
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mPageAttributeTable[SplitTo].AddressMask;
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BaseAddress = *PageEntry &
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~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
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mPageAttributeTable[PageAttribute].AddressMask;
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for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
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NewPageEntry[Index] = BaseAddress | AddressEncMask |
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((*PageEntry) & PAGE_PROGATE_BITS);
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if (SplitTo != PageMin) {
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NewPageEntry[Index] |= IA32_PG_PS;
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}
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if (Recursively && (SplitTo > SplitAttribute)) {
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SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
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}
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BaseAddress += mPageAttributeTable[SplitTo].Length;
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}
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(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS;
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return RETURN_SUCCESS;
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}
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/**
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This function modifies the page attributes for the memory region specified
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by BaseAddress and Length from their current attributes to the attributes
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specified by Attributes.
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Caller should make sure BaseAddress and Length is at page boundary.
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@param[in] BaseAddress Start address of a memory region.
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@param[in] Length Size in bytes of the memory region.
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@param[in] Attributes Bit mask of attributes to modify.
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@retval RETURN_SUCCESS The attributes were modified for the memory
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region.
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@retval RETURN_INVALID_PARAMETER Length is zero; or,
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Attributes specified an illegal combination
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of attributes that cannot be set together; or
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Addressis not 4KB aligned.
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@retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify
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the attributes.
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@retval RETURN_UNSUPPORTED Cannot modify the attributes of given memory.
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**/
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RETURN_STATUS
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EFIAPI
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ConvertMemoryPageAttributes (
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IN PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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)
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{
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UINT64 *PageEntry;
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PAGE_ATTRIBUTE PageAttribute;
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RETURN_STATUS Status;
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EFI_PHYSICAL_ADDRESS MaximumAddress;
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if ((Length == 0) ||
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((BaseAddress & (SIZE_4KB - 1)) != 0) ||
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((Length & (SIZE_4KB - 1)) != 0))
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{
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ASSERT (Length > 0);
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ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
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ASSERT ((Length & (SIZE_4KB - 1)) == 0);
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return RETURN_INVALID_PARAMETER;
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}
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MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
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if ((BaseAddress > MaximumAddress) ||
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(Length > MaximumAddress) ||
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(BaseAddress > MaximumAddress - (Length - 1)))
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{
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return RETURN_UNSUPPORTED;
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}
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//
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// Below logic is to check 2M/4K page to make sure we do not waste memory.
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//
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while (Length != 0) {
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PageEntry = GetPageTableEntry (BaseAddress, &PageAttribute);
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if (PageEntry == NULL) {
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return RETURN_UNSUPPORTED;
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}
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if (PageAttribute != Page4K) {
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Status = SplitPage (PageEntry, PageAttribute, Page4K, FALSE);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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//
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// Do it again until the page is 4K.
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//
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continue;
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}
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//
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// Just take care of 'present' bit for Stack Guard.
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//
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if ((Attributes & IA32_PG_P) != 0) {
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*PageEntry |= (UINT64)IA32_PG_P;
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} else {
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*PageEntry &= ~((UINT64)IA32_PG_P);
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}
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//
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// Convert success, move to next
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//
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BaseAddress += SIZE_4KB;
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Length -= SIZE_4KB;
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}
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return RETURN_SUCCESS;
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}
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/**
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Enable PAE Page Table.
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@retval EFI_SUCCESS The PAE Page Table was enabled successfully.
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@retval EFI_OUT_OF_RESOURCES The PAE Page Table could not be enabled due to lack of available memory.
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**/
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EFI_STATUS
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EnablePaePageTable (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN PageTable;
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VOID *Buffer;
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UINTN BufferSize;
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IA32_MAP_ATTRIBUTE MapAttribute;
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IA32_MAP_ATTRIBUTE MapMask;
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PageTable = 0;
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Buffer = NULL;
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BufferSize = 0;
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MapAttribute.Uint64 = 0;
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MapMask.Uint64 = MAX_UINT64;
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MapAttribute.Bits.Present = 1;
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MapAttribute.Bits.ReadWrite = 1;
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//
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// 1:1 map 4GB in 32bit mode
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//
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Status = PageTableMap (&PageTable, PagingPae, 0, &BufferSize, 0, SIZE_4GB, &MapAttribute, &MapMask, NULL);
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ASSERT (Status == EFI_BUFFER_TOO_SMALL);
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if (Status != EFI_BUFFER_TOO_SMALL) {
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return Status;
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}
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//
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// Allocate required Buffer.
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//
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Buffer = AllocatePageTableMemory (EFI_SIZE_TO_PAGES (BufferSize));
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ASSERT (Buffer != NULL);
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if (Buffer == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = PageTableMap (&PageTable, PagingPae, Buffer, &BufferSize, 0, SIZE_4GB, &MapAttribute, &MapMask, NULL);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status) || (PageTable == 0)) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Write the Pagetable to CR3.
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//
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AsmWriteCr3 (PageTable);
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//
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// Enable CR4.PAE
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//
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AsmWriteCr4 (AsmReadCr4 () | BIT5);
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//
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// Enable CR0.PG
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//
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AsmWriteCr0 (AsmReadCr0 () | BIT31);
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DEBUG ((
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DEBUG_INFO,
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"EnablePaePageTable: Created PageTable = 0x%x, BufferSize = %x\n",
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PageTable,
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BufferSize
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));
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return Status;
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}
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/**
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Get the base address of current AP's stack.
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This function is called in AP's context and assumes that whole calling stacks
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(till this function) consumed by AP's wakeup procedure will not exceed 4KB.
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PcdCpuApStackSize must be configured with value taking the Guard page into
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account.
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@param[in,out] Buffer The pointer to private data buffer.
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**/
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VOID
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EFIAPI
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GetStackBase (
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IN OUT VOID *Buffer
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)
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{
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EFI_PHYSICAL_ADDRESS StackBase;
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StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
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StackBase += BASE_4KB;
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StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
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StackBase -= PcdGet32 (PcdCpuApStackSize);
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*(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
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}
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/**
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Setup stack Guard page at the stack base of each processor. BSP and APs have
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different way to get stack base address.
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**/
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VOID
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SetupStackGuardPage (
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VOID
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)
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{
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EFI_PEI_HOB_POINTERS Hob;
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EFI_PHYSICAL_ADDRESS StackBase;
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UINTN NumberOfProcessors;
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UINTN Bsp;
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UINTN Index;
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EFI_STATUS Status;
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//
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// One extra page at the bottom of the stack is needed for Guard page.
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//
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if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
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DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
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ASSERT (FALSE);
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}
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Status = MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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NumberOfProcessors = 1;
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}
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MpInitLibWhoAmI (&Bsp);
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for (Index = 0; Index < NumberOfProcessors; ++Index) {
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StackBase = 0;
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if (Index == Bsp) {
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Hob.Raw = GetHobList ();
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while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
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if (CompareGuid (
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&gEfiHobMemoryAllocStackGuid,
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&(Hob.MemoryAllocationStack->AllocDescriptor.Name)
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))
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{
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StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
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break;
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}
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Hob.Raw = GET_NEXT_HOB (Hob);
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}
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} else {
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//
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// Ask AP to return is stack base address.
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//
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MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
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}
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ASSERT (StackBase != 0);
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//
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// Set Guard page at stack base address.
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//
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ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
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DEBUG ((
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DEBUG_INFO,
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"Stack Guard set at %lx [cpu%lu]!\n",
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(UINT64)StackBase,
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(UINT64)Index
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));
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}
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//
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// Publish the changes of page table.
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//
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CpuFlushTlb ();
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}
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/**
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Enable/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.
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Doing this in the memory-discovered callback is to make sure the Stack Guard
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feature to cover as most PEI code as possible.
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@param[in] PeiServices General purpose services available to every PEIM.
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@param[in] NotifyDescriptor The notification structure this PEIM registered on install.
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@param[in] Ppi The memory discovered PPI. Not used.
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@retval EFI_SUCCESS The function completed successfully.
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@retval others There's error in MP initialization.
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**/
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EFI_STATUS
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EFIAPI
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MemoryDiscoveredPpiNotifyCallback (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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EFI_STATUS Status;
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BOOLEAN InitStackGuard;
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EDKII_MIGRATED_FV_INFO *MigratedFvInfo;
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EFI_PEI_HOB_POINTERS Hob;
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IA32_CR0 Cr0;
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//
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// Paging must be setup first. Otherwise the exception TSS setup during MP
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// initialization later will not contain paging information and then fail
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// the task switch (for the sake of stack switch).
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//
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InitStackGuard = FALSE;
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Hob.Raw = NULL;
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if (IsIa32PaeSupported ()) {
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Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);
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InitStackGuard = PcdGetBool (PcdCpuStackGuard);
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}
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//
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// Some security features depend on the page table enabling. So, here
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// is to enable paging if it is not enabled (only in 32bit mode).
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//
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Cr0.UintN = AsmReadCr0 ();
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if ((Cr0.Bits.PG == 0) && (InitStackGuard || (Hob.Raw != NULL))) {
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ASSERT (sizeof (UINTN) == sizeof (UINT32));
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Status = EnablePaePageTable ();
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "MemoryDiscoveredPpiNotifyCallback: Failed to enable PAE page table: %r.\n", Status));
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CpuDeadLoop ();
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}
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}
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Status = InitializeCpuMpWorker ((CONST EFI_PEI_SERVICES **)PeiServices);
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ASSERT_EFI_ERROR (Status);
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if (InitStackGuard) {
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SetupStackGuardPage ();
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}
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while (Hob.Raw != NULL) {
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MigratedFvInfo = GET_GUID_HOB_DATA (Hob);
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//
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// Enable #PF exception, so if the code access SPI after disable NEM, it will generate
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// the exception to avoid potential vulnerability.
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//
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ConvertMemoryPageAttributes (MigratedFvInfo->FvOrgBase, MigratedFvInfo->FvLength, 0);
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Hob.Raw = GET_NEXT_HOB (Hob);
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Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
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}
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CpuFlushTlb ();
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return Status;
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}
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