47d183db53
This register is A5x specific. It is the reason why the code moved from ArmLib to ArmCpuLib/ArmCortexA5xLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
51 lines
975 B
C
51 lines
975 B
C
/** @file
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Copyright (c) 2012-2014, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __ARM_CORTEX_A5x_H__
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#define __ARM_CORTEX_A5x_H__
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//
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// Cortex A5x feature bit definitions
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//
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#define A5X_FEATURE_SMP (1 << 6)
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//
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// Helper functions to access CPU Extended Control Register
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//
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UINT64
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EFIAPI
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ArmReadCpuExCr (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCpuExCr (
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IN UINT64 Val
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);
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VOID
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EFIAPI
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ArmSetCpuExCrBit (
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IN UINT64 Bits
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);
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VOID
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EFIAPI
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ArmUnsetCpuExCrBit (
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IN UINT64 Bits
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);
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#endif
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